drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include <net/ip6_checksum.h>
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "eswitch.h"
  43 #include "en_rep.h"
  44 #include "ipoib/ipoib.h"
  45 #include "en_accel/ipsec_rxtx.h"
  46
  47 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
  48 {
  49         return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
  50 }
  51
  52 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  53                                        void *data)
  54 {
  55         u32 ci = cqcc & cq->wq.sz_m1;
  56
  57         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  58 }
  59
  60 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  61                                          struct mlx5e_cq *cq, u32 cqcc)
  62 {
  63         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  64         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  65         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  66         rq->stats.cqe_compress_blks++;
  67 }
  68
  69 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  70 {
  71         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  72         cq->mini_arr_idx = 0;
  73 }
  74
  75 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  76 {
  77         u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
  78         u32 wq_sz = 1 << cq->wq.log_sz;
  79         u32 ci = cqcc & cq->wq.sz_m1;
  80         u32 ci_top = min_t(u32, wq_sz, ci + n);
  81
  82         for (; ci < ci_top; ci++, n--) {
  83                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  84
  85                 cqe->op_own = op_own;
  86         }
  87
  88         if (unlikely(ci == wq_sz)) {
  89                 op_own = !op_own;
  90                 for (ci = 0; ci < n; ci++) {
  91                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  92
  93                         cqe->op_own = op_own;
  94                 }
  95         }
  96 }
  97
  98 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
  99                                         struct mlx5e_cq *cq, u32 cqcc)
 100 {
 101         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 102         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 103         cq->title.op_own      &= 0xf0;
 104         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.log_sz);
 105         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 106
 107         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 108                 cq->decmprs_wqe_counter +=
 109                         mpwrq_get_cqe_consumed_strides(&cq->title);
 110         else
 111                 cq->decmprs_wqe_counter =
 112                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
 113 }
 114
 115 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 116                                                 struct mlx5e_cq *cq, u32 cqcc)
 117 {
 118         mlx5e_decompress_cqe(rq, cq, cqcc);
 119         cq->title.rss_hash_type   = 0;
 120         cq->title.rss_hash_result = 0;
 121 }
 122
 123 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 124                                              struct mlx5e_cq *cq,
 125                                              int update_owner_only,
 126                                              int budget_rem)
 127 {
 128         u32 cqcc = cq->wq.cc + update_owner_only;
 129         u32 cqe_count;
 130         u32 i;
 131
 132         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 133
 134         for (i = update_owner_only; i < cqe_count;
 135              i++, cq->mini_arr_idx++, cqcc++) {
 136                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 137                         mlx5e_read_mini_arr_slot(cq, cqcc);
 138
 139                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 140                 rq->handle_rx_cqe(rq, &cq->title);
 141         }
 142         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 143         cq->wq.cc = cqcc;
 144         cq->decmprs_left -= cqe_count;
 145         rq->stats.cqe_compress_pkts += cqe_count;
 146
 147         return cqe_count;
 148 }
 149
 150 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 151                                               struct mlx5e_cq *cq,
 152                                               int budget_rem)
 153 {
 154         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 155         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 156         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 157         rq->handle_rx_cqe(rq, &cq->title);
 158         cq->mini_arr_idx++;
 159
 160         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 161 }
 162
 163 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 164
 165 static inline bool mlx5e_page_is_reserved(struct page *page)
 166 {
 167         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 168 }
 169
 170 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 171                                       struct mlx5e_dma_info *dma_info)
 172 {
 173         struct mlx5e_page_cache *cache = &rq->page_cache;
 174         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 175
 176         if (tail_next == cache->head) {
 177                 rq->stats.cache_full++;
 178                 return false;
 179         }
 180
 181         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 182                 rq->stats.cache_waive++;
 183                 return false;
 184         }
 185
 186         cache->page_cache[cache->tail] = *dma_info;
 187         cache->tail = tail_next;
 188         return true;
 189 }
 190
 191 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 192                                       struct mlx5e_dma_info *dma_info)
 193 {
 194         struct mlx5e_page_cache *cache = &rq->page_cache;
 195
 196         if (unlikely(cache->head == cache->tail)) {
 197                 rq->stats.cache_empty++;
 198                 return false;
 199         }
 200
 201         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 202                 rq->stats.cache_busy++;
 203                 return false;
 204         }
 205
 206         *dma_info = cache->page_cache[cache->head];
 207         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 208         rq->stats.cache_reuse++;
 209
 210         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 211                                    RQ_PAGE_SIZE(rq),
 212                                    DMA_FROM_DEVICE);
 213         return true;
 214 }
 215
 216 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 217                                           struct mlx5e_dma_info *dma_info)
 218 {
 219         if (mlx5e_rx_cache_get(rq, dma_info))
 220                 return 0;
 221
 222         dma_info->page = dev_alloc_pages(rq->buff.page_order);
 223         if (unlikely(!dma_info->page))
 224                 return -ENOMEM;
 225
 226         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 227                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 228         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 229                 put_page(dma_info->page);
 230                 dma_info->page = NULL;
 231                 return -ENOMEM;
 232         }
 233
 234         return 0;
 235 }
 236
 237 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 238                         bool recycle)
 239 {
 240         if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
 241                 return;
 242
 243         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 244                        rq->buff.map_dir);
 245         put_page(dma_info->page);
 246 }
 247
 248 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 249                                     struct mlx5e_wqe_frag_info *wi)
 250 {
 251         return rq->wqe.page_reuse && wi->di.page &&
 252                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 253                 !mlx5e_page_is_reserved(wi->di.page);
 254 }
 255
 256 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 257 {
 258         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 259
 260         /* check if page exists, hence can be reused */
 261         if (!wi->di.page) {
 262                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 263                         return -ENOMEM;
 264                 wi->offset = 0;
 265         }
 266
 267         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 268         return 0;
 269 }
 270
 271 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 272                                      struct mlx5e_wqe_frag_info *wi)
 273 {
 274         mlx5e_page_release(rq, &wi->di, true);
 275         wi->di.page = NULL;
 276 }
 277
 278 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 279                                            struct mlx5e_wqe_frag_info *wi)
 280 {
 281         if (mlx5e_page_reuse(rq, wi)) {
 282                 rq->stats.page_reuse++;
 283                 return;
 284         }
 285
 286         mlx5e_free_rx_wqe(rq, wi);
 287 }
 288
 289 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 290 {
 291         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 292
 293         if (wi->di.page)
 294                 mlx5e_free_rx_wqe(rq, wi);
 295 }
 296
 297 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
 298 {
 299         return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
 300 }
 301
 302 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 303                                             struct sk_buff *skb,
 304                                             struct mlx5e_mpw_info *wi,
 305                                             u32 page_idx, u32 frag_offset,
 306                                             u32 len)
 307 {
 308         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 309
 310         dma_sync_single_for_cpu(rq->pdev,
 311                                 wi->umr.dma_info[page_idx].addr + frag_offset,
 312                                 len, DMA_FROM_DEVICE);
 313         wi->skbs_frags[page_idx]++;
 314         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 315                         wi->umr.dma_info[page_idx].page, frag_offset,
 316                         len, truesize);
 317 }
 318
 319 static inline void
 320 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 321                             struct sk_buff *skb,
 322                             struct mlx5e_mpw_info *wi,
 323                             u32 page_idx, u32 offset,
 324                             u32 headlen)
 325 {
 326         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 327         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
 328         unsigned int len;
 329
 330          /* Aligning len to sizeof(long) optimizes memcpy performance */
 331         len = ALIGN(headlen_pg, sizeof(long));
 332         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 333                                 DMA_FROM_DEVICE);
 334         skb_copy_to_linear_data_offset(skb, 0,
 335                                        page_address(dma_info->page) + offset,
 336                                        len);
 337         if (unlikely(offset + headlen > PAGE_SIZE)) {
 338                 dma_info++;
 339                 headlen_pg = len;
 340                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 341                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 342                                         DMA_FROM_DEVICE);
 343                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 344                                                page_address(dma_info->page),
 345                                                len);
 346         }
 347 }
 348
 349 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
 350 {
 351         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 352         struct mlx5e_icosq *sq = &rq->channel->icosq;
 353         struct mlx5_wq_cyc *wq = &sq->wq;
 354         struct mlx5e_umr_wqe *wqe;
 355         u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
 356         u16 pi;
 357
 358         /* fill sq edge with nops to avoid wqe wrap around */
 359         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 360                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 361                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 362         }
 363
 364         wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 365         memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
 366         wqe->ctrl.opmod_idx_opcode =
 367                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 368                             MLX5_OPCODE_UMR);
 369
 370         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 371         sq->pc += num_wqebbs;
 372         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
 373 }
 374
 375 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
 376                                     u16 ix)
 377 {
 378         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 379         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 380         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 381         int err;
 382         int i;
 383
 384         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 385                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 386                 if (unlikely(err))
 387                         goto err_unmap;
 388                 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 389                 page_ref_add(dma_info->page, pg_strides);
 390         }
 391
 392         memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE);
 393         wi->consumed_strides = 0;
 394
 395         return 0;
 396
 397 err_unmap:
 398         while (--i >= 0) {
 399                 dma_info--;
 400                 page_ref_sub(dma_info->page, pg_strides);
 401                 mlx5e_page_release(rq, dma_info, true);
 402         }
 403
 404         return err;
 405 }
 406
 407 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 408 {
 409         int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
 410         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 411         int i;
 412
 413         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 414                 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
 415                 mlx5e_page_release(rq, dma_info, true);
 416         }
 417 }
 418
 419 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 420 {
 421         struct mlx5_wq_ll *wq = &rq->wq;
 422         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 423
 424         rq->mpwqe.umr_in_progress = false;
 425
 426         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 427
 428         /* ensure wqes are visible to device before updating doorbell record */
 429         dma_wmb();
 430
 431         mlx5_wq_ll_update_db_record(wq);
 432 }
 433
 434 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 435 {
 436         int err;
 437
 438         err = mlx5e_alloc_rx_umr_mpwqe(rq, ix);
 439         if (unlikely(err)) {
 440                 rq->stats.buff_alloc_err++;
 441                 return err;
 442         }
 443         rq->mpwqe.umr_in_progress = true;
 444         mlx5e_post_umr_wqe(rq, ix);
 445         return 0;
 446 }
 447
 448 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 449 {
 450         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 451
 452         mlx5e_free_rx_mpwqe(rq, wi);
 453 }
 454
 455 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 456 {
 457         struct mlx5_wq_ll *wq = &rq->wq;
 458         int err;
 459
 460         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 461                 return false;
 462
 463         if (mlx5_wq_ll_is_full(wq))
 464                 return false;
 465
 466         do {
 467                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 468
 469                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 470                 if (unlikely(err)) {
 471                         rq->stats.buff_alloc_err++;
 472                         break;
 473                 }
 474
 475                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 476         } while (!mlx5_wq_ll_is_full(wq));
 477
 478         /* ensure wqes are visible to device before updating doorbell record */
 479         dma_wmb();
 480
 481         mlx5_wq_ll_update_db_record(wq);
 482
 483         return !!err;
 484 }
 485
 486 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 487                                              struct mlx5e_icosq *sq,
 488                                              struct mlx5e_rq *rq,
 489                                              struct mlx5_cqe64 *cqe)
 490 {
 491         struct mlx5_wq_cyc *wq = &sq->wq;
 492         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
 493         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 494
 495         mlx5_cqwq_pop(&cq->wq);
 496
 497         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 498                 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
 499                           cqe->op_own);
 500                 return;
 501         }
 502
 503         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 504                 mlx5e_post_rx_mpwqe(rq);
 505                 return;
 506         }
 507
 508         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 509                 WARN_ONCE(true,
 510                           "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
 511                           icowi->opcode);
 512 }
 513
 514 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 515 {
 516         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 517         struct mlx5_cqe64 *cqe;
 518
 519         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
 520                 return;
 521
 522         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 523         if (likely(!cqe))
 524                 return;
 525
 526         /* by design, there's only a single cqe */
 527         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 528
 529         mlx5_cqwq_update_db_record(&cq->wq);
 530 }
 531
 532 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 533 {
 534         struct mlx5_wq_ll *wq = &rq->wq;
 535
 536         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 537                 return false;
 538
 539         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 540
 541         if (mlx5_wq_ll_is_full(wq))
 542                 return false;
 543
 544         if (!rq->mpwqe.umr_in_progress)
 545                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 546
 547         return true;
 548 }
 549
 550 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 551 {
 552         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 553         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 554                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 555
 556         tcp->check                      = 0;
 557         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 558
 559         if (tcp_ack) {
 560                 tcp->ack                = 1;
 561                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 562                 tcp->window             = cqe->lro_tcp_win;
 563         }
 564 }
 565
 566 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 567                                  u32 cqe_bcnt)
 568 {
 569         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 570         struct tcphdr   *tcp;
 571         int network_depth = 0;
 572         __wsum check;
 573         __be16 proto;
 574         u16 tot_len;
 575         void *ip_p;
 576
 577         skb->mac_len = ETH_HLEN;
 578         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 579
 580         tot_len = cqe_bcnt - network_depth;
 581         ip_p = skb->data + network_depth;
 582
 583         if (proto == htons(ETH_P_IP)) {
 584                 struct iphdr *ipv4 = ip_p;
 585
 586                 tcp = ip_p + sizeof(struct iphdr);
 587                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 588
 589                 ipv4->ttl               = cqe->lro_min_ttl;
 590                 ipv4->tot_len           = cpu_to_be16(tot_len);
 591                 ipv4->check             = 0;
 592                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 593                                                        ipv4->ihl);
 594
 595                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 596                 check = csum_partial(tcp, tcp->doff * 4,
 597                                      csum_unfold((__force __sum16)cqe->check_sum));
 598                 /* Almost done, don't forget the pseudo header */
 599                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 600                                                tot_len - sizeof(struct iphdr),
 601                                                IPPROTO_TCP, check);
 602         } else {
 603                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 604                 struct ipv6hdr *ipv6 = ip_p;
 605
 606                 tcp = ip_p + sizeof(struct ipv6hdr);
 607                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 608
 609                 ipv6->hop_limit         = cqe->lro_min_ttl;
 610                 ipv6->payload_len       = cpu_to_be16(payload_len);
 611
 612                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 613                 check = csum_partial(tcp, tcp->doff * 4,
 614                                      csum_unfold((__force __sum16)cqe->check_sum));
 615                 /* Almost done, don't forget the pseudo header */
 616                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 617                                              IPPROTO_TCP, check);
 618         }
 619 }
 620
 621 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 622                                       struct sk_buff *skb)
 623 {
 624         u8 cht = cqe->rss_hash_type;
 625         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 626                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 627                                             PKT_HASH_TYPE_NONE;
 628         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 629 }
 630
 631 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
 632 {
 633         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 634
 635         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 636 }
 637
 638 static u32 mlx5e_get_fcs(const struct sk_buff *skb)
 639 {
 640         const void *fcs_bytes;
 641         u32 _fcs_bytes;
 642
 643         fcs_bytes = skb_header_pointer(skb, skb->len - ETH_FCS_LEN,
 644                                        ETH_FCS_LEN, &_fcs_bytes);
 645
 646         return __get_unaligned_cpu32(fcs_bytes);
 647 }
 648
 649 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 650
 651 static inline void mlx5e_handle_csum(struct net_device *netdev,
 652                                      struct mlx5_cqe64 *cqe,
 653                                      struct mlx5e_rq *rq,
 654                                      struct sk_buff *skb,
 655                                      bool   lro)
 656 {
 657         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 658                 goto csum_none;
 659
 660         if (lro) {
 661                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 662                 rq->stats.csum_unnecessary++;
 663                 return;
 664         }
 665
 666         /* CQE csum doesn't cover padding octets in short ethernet
 667          * frames. And the pad field is appended prior to calculating
 668          * and appending the FCS field.
 669          *
 670          * Detecting these padded frames requires to verify and parse
 671          * IP headers, so we simply force all those small frames to be
 672          * CHECKSUM_UNNECESSARY even if they are not padded.
 673          */
 674         if (short_frame(skb->len))
 675                 goto csum_unnecessary;
 676
 677         if (is_first_ethertype_ip(skb)) {
 678                 skb->ip_summed = CHECKSUM_COMPLETE;
 679                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 680                 if (unlikely(netdev->features & NETIF_F_RXFCS))
 681                         skb->csum = csum_block_add(skb->csum,
 682                                                    (__force __wsum)mlx5e_get_fcs(skb),
 683                                                    skb->len - ETH_FCS_LEN);
 684                 rq->stats.csum_complete++;
 685                 return;
 686         }
 687
 688 csum_unnecessary:
 689         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 690                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 691                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 692                 if (cqe_is_tunneled(cqe)) {
 693                         skb->csum_level = 1;
 694                         skb->encapsulation = 1;
 695                         rq->stats.csum_unnecessary_inner++;
 696                         return;
 697                 }
 698                 rq->stats.csum_unnecessary++;
 699                 return;
 700         }
 701 csum_none:
 702         skb->ip_summed = CHECKSUM_NONE;
 703         rq->stats.csum_none++;
 704 }
 705
 706 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 707                                       u32 cqe_bcnt,
 708                                       struct mlx5e_rq *rq,
 709                                       struct sk_buff *skb)
 710 {
 711         struct net_device *netdev = rq->netdev;
 712         struct mlx5e_tstamp *tstamp = rq->tstamp;
 713         int lro_num_seg;
 714
 715         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 716         if (lro_num_seg > 1) {
 717                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 718                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 719                 /* Subtract one since we already counted this as one
 720                  * "regular" packet in mlx5e_complete_rx_cqe()
 721                  */
 722                 rq->stats.packets += lro_num_seg - 1;
 723                 rq->stats.lro_packets++;
 724                 rq->stats.lro_bytes += cqe_bcnt;
 725         }
 726
 727         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
 728                 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
 729
 730         skb_record_rx_queue(skb, rq->ix);
 731
 732         if (likely(netdev->features & NETIF_F_RXHASH))
 733                 mlx5e_skb_set_hash(cqe, skb);
 734
 735         if (cqe_has_vlan(cqe))
 736                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 737                                        be16_to_cpu(cqe->vlan_info));
 738
 739         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 740
 741         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 742         skb->protocol = eth_type_trans(skb, netdev);
 743 }
 744
 745 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 746                                          struct mlx5_cqe64 *cqe,
 747                                          u32 cqe_bcnt,
 748                                          struct sk_buff *skb)
 749 {
 750         rq->stats.packets++;
 751         rq->stats.bytes += cqe_bcnt;
 752         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 753 }
 754
 755 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 756 {
 757         struct mlx5_wq_cyc *wq = &sq->wq;
 758         struct mlx5e_tx_wqe *wqe;
 759         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
 760
 761         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 762
 763         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 764 }
 765
 766 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 767                                         struct mlx5e_dma_info *di,
 768                                         const struct xdp_buff *xdp)
 769 {
 770         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 771         struct mlx5_wq_cyc       *wq   = &sq->wq;
 772         u16                       pi   = sq->pc & wq->sz_m1;
 773         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 774
 775         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 776         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 777         struct mlx5_wqe_data_seg *dseg;
 778
 779         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 780         dma_addr_t dma_addr  = di->addr + data_offset;
 781         unsigned int dma_len = xdp->data_end - xdp->data;
 782
 783         prefetchw(wqe);
 784
 785         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE ||
 786                      MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) {
 787                 rq->stats.xdp_drop++;
 788                 return false;
 789         }
 790
 791         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 792                 if (sq->db.doorbell) {
 793                         /* SQ is full, ring doorbell */
 794                         mlx5e_xmit_xdp_doorbell(sq);
 795                         sq->db.doorbell = false;
 796                 }
 797                 rq->stats.xdp_tx_full++;
 798                 return false;
 799         }
 800
 801         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 802
 803         cseg->fm_ce_se = 0;
 804
 805         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 806
 807         /* copy the inline part if required */
 808         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 809                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 810                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 811                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 812                 dma_addr += MLX5E_XDP_MIN_INLINE;
 813                 dseg++;
 814         }
 815
 816         /* write the dma part */
 817         dseg->addr       = cpu_to_be64(dma_addr);
 818         dseg->byte_count = cpu_to_be32(dma_len);
 819
 820         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 821
 822         /* move page to reference to sq responsibility,
 823          * and mark so it's not put back in page-cache.
 824          */
 825         rq->wqe.xdp_xmit = true;
 826         sq->db.di[pi] = *di;
 827         sq->pc++;
 828
 829         sq->db.doorbell = true;
 830
 831         rq->stats.xdp_tx++;
 832         return true;
 833 }
 834
 835 /* returns true if packet was consumed by xdp */
 836 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 837                                    struct mlx5e_dma_info *di,
 838                                    void *va, u16 *rx_headroom, u32 *len)
 839 {
 840         const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 841         struct xdp_buff xdp;
 842         u32 act;
 843
 844         if (!prog)
 845                 return false;
 846
 847         xdp.data = va + *rx_headroom;
 848         xdp.data_end = xdp.data + *len;
 849         xdp.data_hard_start = va;
 850
 851         act = bpf_prog_run_xdp(prog, &xdp);
 852         switch (act) {
 853         case XDP_PASS:
 854                 *rx_headroom = xdp.data - xdp.data_hard_start;
 855                 *len = xdp.data_end - xdp.data;
 856                 return false;
 857         case XDP_TX:
 858                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 859                         trace_xdp_exception(rq->netdev, prog, act);
 860                 return true;
 861         default:
 862                 bpf_warn_invalid_xdp_action(act);
 863         case XDP_ABORTED:
 864                 trace_xdp_exception(rq->netdev, prog, act);
 865         case XDP_DROP:
 866                 rq->stats.xdp_drop++;
 867                 return true;
 868         }
 869 }
 870
 871 static inline
 872 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 873                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 874 {
 875         struct mlx5e_dma_info *di = &wi->di;
 876         u16 rx_headroom = rq->buff.headroom;
 877         struct sk_buff *skb;
 878         void *va, *data;
 879         bool consumed;
 880         u32 frag_size;
 881
 882         va             = page_address(di->page) + wi->offset;
 883         data           = va + rx_headroom;
 884         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 885
 886         dma_sync_single_range_for_cpu(rq->pdev,
 887                                       di->addr + wi->offset,
 888                                       0, frag_size,
 889                                       DMA_FROM_DEVICE);
 890         prefetch(data);
 891         wi->offset += frag_size;
 892
 893         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 894                 rq->stats.wqe_err++;
 895                 return NULL;
 896         }
 897
 898         rcu_read_lock();
 899         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 900         rcu_read_unlock();
 901         if (consumed)
 902                 return NULL; /* page/packet was consumed by XDP */
 903
 904         skb = build_skb(va, frag_size);
 905         if (unlikely(!skb)) {
 906                 rq->stats.buff_alloc_err++;
 907                 return NULL;
 908         }
 909
 910         /* queue up for recycling/reuse */
 911         page_ref_inc(di->page);
 912
 913         skb_reserve(skb, rx_headroom);
 914         skb_put(skb, cqe_bcnt);
 915
 916         return skb;
 917 }
 918
 919 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 920 {
 921         struct mlx5e_wqe_frag_info *wi;
 922         struct mlx5e_rx_wqe *wqe;
 923         __be16 wqe_counter_be;
 924         struct sk_buff *skb;
 925         u16 wqe_counter;
 926         u32 cqe_bcnt;
 927
 928         wqe_counter_be = cqe->wqe_counter;
 929         wqe_counter    = be16_to_cpu(wqe_counter_be);
 930         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 931         wi             = &rq->wqe.frag_info[wqe_counter];
 932         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 933
 934         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 935         if (!skb) {
 936                 /* probably for XDP */
 937                 if (rq->wqe.xdp_xmit) {
 938                         wi->di.page = NULL;
 939                         rq->wqe.xdp_xmit = false;
 940                         /* do not return page to cache, it will be returned on XDP_TX completion */
 941                         goto wq_ll_pop;
 942                 }
 943                 /* probably an XDP_DROP, save the page-reuse checks */
 944                 mlx5e_free_rx_wqe(rq, wi);
 945                 goto wq_ll_pop;
 946         }
 947
 948         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 949         napi_gro_receive(rq->cq.napi, skb);
 950
 951         mlx5e_free_rx_wqe_reuse(rq, wi);
 952 wq_ll_pop:
 953         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 954                        &wqe->next.next_wqe_index);
 955 }
 956
 957 #ifdef CONFIG_MLX5_ESWITCH
 958 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 959 {
 960         struct net_device *netdev = rq->netdev;
 961         struct mlx5e_priv *priv = netdev_priv(netdev);
 962         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
 963         struct mlx5_eswitch_rep *rep = rpriv->rep;
 964         struct mlx5e_wqe_frag_info *wi;
 965         struct mlx5e_rx_wqe *wqe;
 966         struct sk_buff *skb;
 967         __be16 wqe_counter_be;
 968         u16 wqe_counter;
 969         u32 cqe_bcnt;
 970
 971         wqe_counter_be = cqe->wqe_counter;
 972         wqe_counter    = be16_to_cpu(wqe_counter_be);
 973         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 974         wi             = &rq->wqe.frag_info[wqe_counter];
 975         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 976
 977         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 978         if (!skb) {
 979                 if (rq->wqe.xdp_xmit) {
 980                         wi->di.page = NULL;
 981                         rq->wqe.xdp_xmit = false;
 982                         /* do not return page to cache, it will be returned on XDP_TX completion */
 983                         goto wq_ll_pop;
 984                 }
 985                 /* probably an XDP_DROP, save the page-reuse checks */
 986                 mlx5e_free_rx_wqe(rq, wi);
 987                 goto wq_ll_pop;
 988         }
 989
 990         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 991
 992         if (rep->vlan && skb_vlan_tag_present(skb))
 993                 skb_vlan_pop(skb);
 994
 995         napi_gro_receive(rq->cq.napi, skb);
 996
 997         mlx5e_free_rx_wqe_reuse(rq, wi);
 998 wq_ll_pop:
 999         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1000                        &wqe->next.next_wqe_index);
1001 }
1002 #endif
1003
1004 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
1005                                            struct mlx5_cqe64 *cqe,
1006                                            struct mlx5e_mpw_info *wi,
1007                                            u32 cqe_bcnt,
1008                                            struct sk_buff *skb)
1009 {
1010         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1011         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1012         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1013         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1014         u32 head_page_idx  = page_idx;
1015         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
1016         u32 frag_offset    = head_offset + headlen;
1017         u16 byte_cnt       = cqe_bcnt - headlen;
1018
1019         if (unlikely(frag_offset >= PAGE_SIZE)) {
1020                 page_idx++;
1021                 frag_offset -= PAGE_SIZE;
1022         }
1023
1024         while (byte_cnt) {
1025                 u32 pg_consumed_bytes =
1026                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1027
1028                 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
1029                                          pg_consumed_bytes);
1030                 byte_cnt -= pg_consumed_bytes;
1031                 frag_offset = 0;
1032                 page_idx++;
1033         }
1034         /* copy header */
1035         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
1036                                     head_offset, headlen);
1037         /* skb linear part was allocated with headlen and aligned to long */
1038         skb->tail += headlen;
1039         skb->len  += headlen;
1040 }
1041
1042 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1043 {
1044         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1045         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1046         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1047         struct mlx5e_rx_wqe  *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1048         struct sk_buff *skb;
1049         u16 cqe_bcnt;
1050
1051         wi->consumed_strides += cstrides;
1052
1053         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1054                 rq->stats.wqe_err++;
1055                 goto mpwrq_cqe_out;
1056         }
1057
1058         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1059                 rq->stats.mpwqe_filler++;
1060                 goto mpwrq_cqe_out;
1061         }
1062
1063         skb = napi_alloc_skb(rq->cq.napi,
1064                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
1065                                    sizeof(long)));
1066         if (unlikely(!skb)) {
1067                 rq->stats.buff_alloc_err++;
1068                 goto mpwrq_cqe_out;
1069         }
1070
1071         prefetchw(skb->data);
1072         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1073
1074         mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
1075         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1076         napi_gro_receive(rq->cq.napi, skb);
1077
1078 mpwrq_cqe_out:
1079         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1080                 return;
1081
1082         mlx5e_free_rx_mpwqe(rq, wi);
1083         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1084 }
1085
1086 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1087 {
1088         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1089         struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
1090         struct mlx5_cqe64 *cqe;
1091         int work_done = 0;
1092
1093         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1094                 return 0;
1095
1096         if (cq->decmprs_left) {
1097                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1098                 if (cq->decmprs_left || work_done >= budget)
1099                         goto out;
1100         }
1101
1102         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1103         if (!cqe) {
1104                 if (unlikely(work_done))
1105                         goto out;
1106                 return 0;
1107         }
1108
1109         do {
1110                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1111                         work_done +=
1112                                 mlx5e_decompress_cqes_start(rq, cq,
1113                                                             budget - work_done);
1114                         continue;
1115                 }
1116
1117                 mlx5_cqwq_pop(&cq->wq);
1118
1119                 rq->handle_rx_cqe(rq, cqe);
1120         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1121
1122 out:
1123         if (xdpsq->db.doorbell) {
1124                 mlx5e_xmit_xdp_doorbell(xdpsq);
1125                 xdpsq->db.doorbell = false;
1126         }
1127
1128         mlx5_cqwq_update_db_record(&cq->wq);
1129
1130         /* ensure cq space is freed before enabling more cqes */
1131         wmb();
1132
1133         return work_done;
1134 }
1135
1136 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1137 {
1138         struct mlx5e_xdpsq *sq;
1139         struct mlx5_cqe64 *cqe;
1140         struct mlx5e_rq *rq;
1141         u16 sqcc;
1142         int i;
1143
1144         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1145
1146         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1147                 return false;
1148
1149         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1150         if (!cqe)
1151                 return false;
1152
1153         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1154
1155         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1156          * otherwise a cq overrun may occur
1157          */
1158         sqcc = sq->cc;
1159
1160         i = 0;
1161         do {
1162                 u16 wqe_counter;
1163                 bool last_wqe;
1164
1165                 mlx5_cqwq_pop(&cq->wq);
1166
1167                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1168
1169                 do {
1170                         struct mlx5e_dma_info *di;
1171                         u16 ci;
1172
1173                         last_wqe = (sqcc == wqe_counter);
1174
1175                         ci = sqcc & sq->wq.sz_m1;
1176                         di = &sq->db.di[ci];
1177
1178                         sqcc++;
1179                         /* Recycle RX page */
1180                         mlx5e_page_release(rq, di, true);
1181                 } while (!last_wqe);
1182         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1183
1184         mlx5_cqwq_update_db_record(&cq->wq);
1185
1186         /* ensure cq space is freed before enabling more cqes */
1187         wmb();
1188
1189         sq->cc = sqcc;
1190         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1191 }
1192
1193 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1194 {
1195         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1196         struct mlx5e_dma_info *di;
1197         u16 ci;
1198
1199         while (sq->cc != sq->pc) {
1200                 ci = sq->cc & sq->wq.sz_m1;
1201                 di = &sq->db.di[ci];
1202                 sq->cc++;
1203
1204                 mlx5e_page_release(rq, di, false);
1205         }
1206 }
1207
1208 #ifdef CONFIG_MLX5_CORE_IPOIB
1209
1210 #define MLX5_IB_GRH_DGID_OFFSET 24
1211 #define MLX5_GID_SIZE           16
1212
1213 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1214                                          struct mlx5_cqe64 *cqe,
1215                                          u32 cqe_bcnt,
1216                                          struct sk_buff *skb)
1217 {
1218         struct net_device *netdev = rq->netdev;
1219         struct mlx5e_tstamp *tstamp = rq->tstamp;
1220         char *pseudo_header;
1221         u8 *dgid;
1222         u8 g;
1223
1224         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1225         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1226         if ((!g) || dgid[0] != 0xff)
1227                 skb->pkt_type = PACKET_HOST;
1228         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1229                 skb->pkt_type = PACKET_BROADCAST;
1230         else
1231                 skb->pkt_type = PACKET_MULTICAST;
1232
1233         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1234          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1235          */
1236
1237         skb_pull(skb, MLX5_IB_GRH_BYTES);
1238
1239         skb->protocol = *((__be16 *)(skb->data));
1240
1241         skb->ip_summed = CHECKSUM_COMPLETE;
1242         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1243
1244         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1245                 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
1246
1247         skb_record_rx_queue(skb, rq->ix);
1248
1249         if (likely(netdev->features & NETIF_F_RXHASH))
1250                 mlx5e_skb_set_hash(cqe, skb);
1251
1252         /* 20 bytes of ipoib header and 4 for encap existing */
1253         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1254         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1255         skb_reset_mac_header(skb);
1256         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1257
1258         skb->dev = netdev;
1259
1260         rq->stats.csum_complete++;
1261         rq->stats.packets++;
1262         rq->stats.bytes += cqe_bcnt;
1263 }
1264
1265 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1266 {
1267         struct mlx5e_wqe_frag_info *wi;
1268         struct mlx5e_rx_wqe *wqe;
1269         __be16 wqe_counter_be;
1270         struct sk_buff *skb;
1271         u16 wqe_counter;
1272         u32 cqe_bcnt;
1273
1274         wqe_counter_be = cqe->wqe_counter;
1275         wqe_counter    = be16_to_cpu(wqe_counter_be);
1276         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1277         wi             = &rq->wqe.frag_info[wqe_counter];
1278         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1279
1280         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1281         if (!skb)
1282                 goto wq_free_wqe;
1283
1284         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1285         napi_gro_receive(rq->cq.napi, skb);
1286
1287 wq_free_wqe:
1288         mlx5e_free_rx_wqe_reuse(rq, wi);
1289         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1290                        &wqe->next.next_wqe_index);
1291 }
1292
1293 #endif /* CONFIG_MLX5_CORE_IPOIB */
1294
1295 #ifdef CONFIG_MLX5_EN_IPSEC
1296
1297 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1298 {
1299         struct mlx5e_wqe_frag_info *wi;
1300         struct mlx5e_rx_wqe *wqe;
1301         __be16 wqe_counter_be;
1302         struct sk_buff *skb;
1303         u16 wqe_counter;
1304         u32 cqe_bcnt;
1305
1306         wqe_counter_be = cqe->wqe_counter;
1307         wqe_counter    = be16_to_cpu(wqe_counter_be);
1308         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1309         wi             = &rq->wqe.frag_info[wqe_counter];
1310         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1311
1312         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1313         if (unlikely(!skb)) {
1314                 /* a DROP, save the page-reuse checks */
1315                 mlx5e_free_rx_wqe(rq, wi);
1316                 goto wq_ll_pop;
1317         }
1318         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1319         if (unlikely(!skb)) {
1320                 mlx5e_free_rx_wqe(rq, wi);
1321                 goto wq_ll_pop;
1322         }
1323
1324         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1325         napi_gro_receive(rq->cq.napi, skb);
1326
1327         mlx5e_free_rx_wqe_reuse(rq, wi);
1328 wq_ll_pop:
1329         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1330                        &wqe->next.next_wqe_index);
1331 }
1332
1333 #endif /* CONFIG_MLX5_EN_IPSEC */