2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <net/busy_poll.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
40 #include <net/inet_ecn.h>
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/tls_rxtx.h"
48 #include "lib/clock.h"
51 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
53 return config->rx_filter == HWTSTAMP_FILTER_ALL;
56 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
59 u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
61 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
64 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
65 struct mlx5e_cq *cq, u32 cqcc)
67 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
68 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
69 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
70 rq->stats->cqe_compress_blks++;
73 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
75 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
79 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
81 struct mlx5_cqwq *wq = &cq->wq;
83 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
84 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
85 u32 wq_sz = mlx5_cqwq_get_size(wq);
86 u32 ci_top = min_t(u32, wq_sz, ci + n);
88 for (; ci < ci_top; ci++, n--) {
89 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
94 if (unlikely(ci == wq_sz)) {
96 for (ci = 0; ci < n; ci++) {
97 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
104 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
105 struct mlx5e_cq *cq, u32 cqcc)
107 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
108 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
109 cq->title.op_own &= 0xf0;
110 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
111 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
113 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
114 cq->decmprs_wqe_counter +=
115 mpwrq_get_cqe_consumed_strides(&cq->title);
117 cq->decmprs_wqe_counter =
118 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
121 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
122 struct mlx5e_cq *cq, u32 cqcc)
124 mlx5e_decompress_cqe(rq, cq, cqcc);
125 cq->title.rss_hash_type = 0;
126 cq->title.rss_hash_result = 0;
129 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
131 int update_owner_only,
134 u32 cqcc = cq->wq.cc + update_owner_only;
138 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
140 for (i = update_owner_only; i < cqe_count;
141 i++, cq->mini_arr_idx++, cqcc++) {
142 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
143 mlx5e_read_mini_arr_slot(cq, cqcc);
145 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
146 rq->handle_rx_cqe(rq, &cq->title);
148 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
150 cq->decmprs_left -= cqe_count;
151 rq->stats->cqe_compress_pkts += cqe_count;
156 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
160 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
161 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
162 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
163 rq->handle_rx_cqe(rq, &cq->title);
166 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
169 static inline bool mlx5e_page_is_reserved(struct page *page)
171 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
174 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
175 struct mlx5e_dma_info *dma_info)
177 struct mlx5e_page_cache *cache = &rq->page_cache;
178 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
179 struct mlx5e_rq_stats *stats = rq->stats;
181 if (tail_next == cache->head) {
186 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
187 stats->cache_waive++;
191 cache->page_cache[cache->tail] = *dma_info;
192 cache->tail = tail_next;
196 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
197 struct mlx5e_dma_info *dma_info)
199 struct mlx5e_page_cache *cache = &rq->page_cache;
200 struct mlx5e_rq_stats *stats = rq->stats;
202 if (unlikely(cache->head == cache->tail)) {
203 stats->cache_empty++;
207 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
212 *dma_info = cache->page_cache[cache->head];
213 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
214 stats->cache_reuse++;
216 dma_sync_single_for_device(rq->pdev, dma_info->addr,
222 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
223 struct mlx5e_dma_info *dma_info)
225 if (mlx5e_rx_cache_get(rq, dma_info))
228 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
229 if (unlikely(!dma_info->page))
232 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
233 PAGE_SIZE, rq->buff.map_dir);
234 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
235 put_page(dma_info->page);
236 dma_info->page = NULL;
243 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
245 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
251 if (likely(recycle)) {
252 if (mlx5e_rx_cache_put(rq, dma_info))
255 mlx5e_page_dma_unmap(rq, dma_info);
256 page_pool_recycle_direct(rq->page_pool, dma_info->page);
258 mlx5e_page_dma_unmap(rq, dma_info);
259 put_page(dma_info->page);
263 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
264 struct mlx5e_wqe_frag_info *frag)
269 /* On first frag (offset == 0), replenish page (dma_info actually).
270 * Other frags that point to the same dma_info (with a different
271 * offset) should just use the new one without replenishing again
274 err = mlx5e_page_alloc_mapped(rq, frag->di);
279 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
280 struct mlx5e_wqe_frag_info *frag,
283 if (frag->last_in_page)
284 mlx5e_page_release(rq, frag->di, recycle);
287 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
289 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
292 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
295 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
299 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
300 err = mlx5e_get_rx_frag(rq, frag);
304 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
305 frag->offset + rq->buff.headroom);
312 mlx5e_put_rx_frag(rq, --frag, true);
317 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
318 struct mlx5e_wqe_frag_info *wi,
323 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
324 mlx5e_put_rx_frag(rq, wi, recycle);
327 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
329 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
331 mlx5e_free_rx_wqe(rq, wi, false);
334 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
336 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
340 for (i = 0; i < wqe_bulk; i++) {
341 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
343 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
352 mlx5e_dealloc_rx_wqe(rq, ix + i);
358 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
359 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
360 unsigned int truesize)
362 dma_sync_single_for_cpu(rq->pdev,
363 di->addr + frag_offset,
364 len, DMA_FROM_DEVICE);
365 page_ref_inc(di->page);
366 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
367 di->page, frag_offset, len, truesize);
371 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
372 struct mlx5e_dma_info *dma_info,
373 int offset_from, int offset_to, u32 headlen)
375 const void *from = page_address(dma_info->page) + offset_from;
376 /* Aligning len to sizeof(long) optimizes memcpy performance */
377 unsigned int len = ALIGN(headlen, sizeof(long));
379 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
381 skb_copy_to_linear_data_offset(skb, offset_to, from, len);
385 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
387 struct mlx5e_dma_info *dma_info,
388 u32 offset, u32 headlen)
390 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
392 mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
394 if (unlikely(offset + headlen > PAGE_SIZE)) {
396 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
397 headlen - headlen_pg);
402 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
404 const bool no_xdp_xmit =
405 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
406 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
409 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
410 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
411 mlx5e_page_release(rq, &dma_info[i], recycle);
414 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
416 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
417 struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
419 rq->mpwqe.umr_in_progress = false;
421 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
423 /* ensure wqes are visible to device before updating doorbell record */
426 mlx5_wq_ll_update_db_record(wq);
429 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
431 return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
434 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
435 struct mlx5_wq_cyc *wq,
438 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
440 edge_wi = wi + nnops;
442 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
443 for (; wi < edge_wi; wi++) {
444 wi->opcode = MLX5_OPCODE_NOP;
445 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
449 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
452 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
453 struct mlx5e_icosq *sq = &rq->channel->icosq;
454 struct mlx5_wq_cyc *wq = &sq->wq;
455 struct mlx5e_umr_wqe *umr_wqe;
456 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
457 u16 pi, contig_wqebbs_room;
461 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
462 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
463 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
464 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
465 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
468 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
469 if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
470 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
471 offsetof(struct mlx5e_umr_wqe, inline_mtts));
473 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
474 err = mlx5e_page_alloc_mapped(rq, dma_info);
477 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
480 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
481 wi->consumed_strides = 0;
483 rq->mpwqe.umr_in_progress = true;
485 umr_wqe->ctrl.opmod_idx_opcode =
486 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
488 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
490 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
491 sq->pc += MLX5E_UMR_WQEBBS;
492 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
499 mlx5e_page_release(rq, dma_info, true);
501 rq->stats->buff_alloc_err++;
506 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
508 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
509 /* Don't recycle, this function is called on rq/netdev close */
510 mlx5e_free_rx_mpwqe(rq, wi, false);
513 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
515 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
519 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
522 wqe_bulk = rq->wqe.info.wqe_bulk;
524 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
528 u16 head = mlx5_wq_cyc_get_head(wq);
530 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
532 rq->stats->buff_alloc_err++;
536 mlx5_wq_cyc_push_n(wq, wqe_bulk);
537 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
539 /* ensure wqes are visible to device before updating doorbell record */
542 mlx5_wq_cyc_update_db_record(wq);
547 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
548 struct mlx5e_icosq *sq,
550 struct mlx5_cqe64 *cqe)
552 struct mlx5_wq_cyc *wq = &sq->wq;
553 u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
554 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
556 mlx5_cqwq_pop(&cq->wq);
558 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
559 netdev_WARN_ONCE(cq->channel->netdev,
560 "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
564 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
565 mlx5e_post_rx_mpwqe(rq);
569 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
570 netdev_WARN_ONCE(cq->channel->netdev,
571 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
574 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
576 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
577 struct mlx5_cqe64 *cqe;
579 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
582 cqe = mlx5_cqwq_get_cqe(&cq->wq);
586 /* by design, there's only a single cqe */
587 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
589 mlx5_cqwq_update_db_record(&cq->wq);
592 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
594 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
596 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
599 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
601 if (mlx5_wq_ll_is_full(wq))
604 if (!rq->mpwqe.umr_in_progress)
605 mlx5e_alloc_rx_mpwqe(rq, wq->head);
607 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
612 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
614 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
615 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
616 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
619 tcp->psh = get_cqe_lro_tcppsh(cqe);
623 tcp->ack_seq = cqe->lro_ack_seq_num;
624 tcp->window = cqe->lro_tcp_win;
628 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
631 struct ethhdr *eth = (struct ethhdr *)(skb->data);
633 int network_depth = 0;
639 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
641 tot_len = cqe_bcnt - network_depth;
642 ip_p = skb->data + network_depth;
644 if (proto == htons(ETH_P_IP)) {
645 struct iphdr *ipv4 = ip_p;
647 tcp = ip_p + sizeof(struct iphdr);
648 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
650 ipv4->ttl = cqe->lro_min_ttl;
651 ipv4->tot_len = cpu_to_be16(tot_len);
653 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
656 mlx5e_lro_update_tcp_hdr(cqe, tcp);
657 check = csum_partial(tcp, tcp->doff * 4,
658 csum_unfold((__force __sum16)cqe->check_sum));
659 /* Almost done, don't forget the pseudo header */
660 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
661 tot_len - sizeof(struct iphdr),
664 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
665 struct ipv6hdr *ipv6 = ip_p;
667 tcp = ip_p + sizeof(struct ipv6hdr);
668 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
670 ipv6->hop_limit = cqe->lro_min_ttl;
671 ipv6->payload_len = cpu_to_be16(payload_len);
673 mlx5e_lro_update_tcp_hdr(cqe, tcp);
674 check = csum_partial(tcp, tcp->doff * 4,
675 csum_unfold((__force __sum16)cqe->check_sum));
676 /* Almost done, don't forget the pseudo header */
677 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
682 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
685 u8 cht = cqe->rss_hash_type;
686 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
687 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
689 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
692 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
695 *proto = ((struct ethhdr *)skb->data)->h_proto;
696 *proto = __vlan_get_protocol(skb, *proto, network_depth);
698 if (*proto == htons(ETH_P_IP))
699 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
701 if (*proto == htons(ETH_P_IPV6))
702 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
707 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
709 int network_depth = 0;
714 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
717 ip = skb->data + network_depth;
718 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
719 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
721 rq->stats->ecn_mark += !!rc;
724 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
726 void *ip_p = skb->data + network_depth;
728 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
729 ((struct ipv6hdr *)ip_p)->nexthdr;
732 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
734 #define MAX_PADDING 8
737 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
738 struct mlx5e_rq_stats *stats)
740 stats->csum_complete_tail_slow++;
741 skb->csum = csum_block_add(skb->csum,
742 skb_checksum(skb, offset, len, 0),
747 tail_padding_csum(struct sk_buff *skb, int offset,
748 struct mlx5e_rq_stats *stats)
750 u8 tail_padding[MAX_PADDING];
751 int len = skb->len - offset;
754 if (unlikely(len > MAX_PADDING)) {
755 tail_padding_csum_slow(skb, offset, len, stats);
759 tail = skb_header_pointer(skb, offset, len, tail_padding);
760 if (unlikely(!tail)) {
761 tail_padding_csum_slow(skb, offset, len, stats);
765 stats->csum_complete_tail++;
766 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
770 mlx5e_skb_padding_csum(struct sk_buff *skb, int network_depth, __be16 proto,
771 struct mlx5e_rq_stats *stats)
778 case htons(ETH_P_IP):
779 ip4 = (struct iphdr *)(skb->data + network_depth);
780 pkt_len = network_depth + ntohs(ip4->tot_len);
782 case htons(ETH_P_IPV6):
783 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
784 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
790 if (likely(pkt_len >= skb->len))
793 tail_padding_csum(skb, pkt_len, stats);
796 static inline void mlx5e_handle_csum(struct net_device *netdev,
797 struct mlx5_cqe64 *cqe,
802 struct mlx5e_rq_stats *stats = rq->stats;
803 int network_depth = 0;
806 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
810 skb->ip_summed = CHECKSUM_UNNECESSARY;
811 stats->csum_unnecessary++;
815 /* True when explicitly set via priv flag, or XDP prog is loaded */
816 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
817 goto csum_unnecessary;
819 /* CQE csum doesn't cover padding octets in short ethernet
820 * frames. And the pad field is appended prior to calculating
821 * and appending the FCS field.
823 * Detecting these padded frames requires to verify and parse
824 * IP headers, so we simply force all those small frames to be
825 * CHECKSUM_UNNECESSARY even if they are not padded.
827 if (short_frame(skb->len))
828 goto csum_unnecessary;
830 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
831 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
832 goto csum_unnecessary;
834 skb->ip_summed = CHECKSUM_COMPLETE;
835 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
836 if (network_depth > ETH_HLEN)
837 /* CQE csum is calculated from the IP header and does
838 * not cover VLAN headers (if present). This will add
839 * the checksum manually.
841 skb->csum = csum_partial(skb->data + ETH_HLEN,
842 network_depth - ETH_HLEN,
845 mlx5e_skb_padding_csum(skb, network_depth, proto, stats);
846 stats->csum_complete++;
851 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
852 (cqe->hds_ip_ext & CQE_L4_OK))) {
853 skb->ip_summed = CHECKSUM_UNNECESSARY;
854 if (cqe_is_tunneled(cqe)) {
856 skb->encapsulation = 1;
857 stats->csum_unnecessary_inner++;
860 stats->csum_unnecessary++;
864 skb->ip_summed = CHECKSUM_NONE;
868 #define MLX5E_CE_BIT_MASK 0x80
870 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
875 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
876 struct mlx5e_rq_stats *stats = rq->stats;
877 struct net_device *netdev = rq->netdev;
879 skb->mac_len = ETH_HLEN;
881 #ifdef CONFIG_MLX5_EN_TLS
882 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
885 if (lro_num_seg > 1) {
886 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
887 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
888 /* Subtract one since we already counted this as one
889 * "regular" packet in mlx5e_complete_rx_cqe()
891 stats->packets += lro_num_seg - 1;
892 stats->lro_packets++;
893 stats->lro_bytes += cqe_bcnt;
896 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
897 skb_hwtstamps(skb)->hwtstamp =
898 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
900 skb_record_rx_queue(skb, rq->ix);
902 if (likely(netdev->features & NETIF_F_RXHASH))
903 mlx5e_skb_set_hash(cqe, skb);
905 if (cqe_has_vlan(cqe)) {
906 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
907 be16_to_cpu(cqe->vlan_info));
908 stats->removed_vlan_packets++;
911 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
913 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
914 /* checking CE bit in cqe - MSB in ml_path field */
915 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
916 mlx5e_enable_ecn(rq, skb);
918 skb->protocol = eth_type_trans(skb, netdev);
921 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
922 struct mlx5_cqe64 *cqe,
926 struct mlx5e_rq_stats *stats = rq->stats;
929 stats->bytes += cqe_bcnt;
930 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
934 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
935 u32 frag_size, u16 headroom,
938 struct sk_buff *skb = build_skb(va, frag_size);
940 if (unlikely(!skb)) {
941 rq->stats->buff_alloc_err++;
945 skb_reserve(skb, headroom);
946 skb_put(skb, cqe_bcnt);
952 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
953 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
955 struct mlx5e_dma_info *di = wi->di;
956 u16 rx_headroom = rq->buff.headroom;
962 va = page_address(di->page) + wi->offset;
963 data = va + rx_headroom;
964 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
966 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
967 frag_size, DMA_FROM_DEVICE);
968 prefetchw(va); /* xdp_frame data area */
971 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
972 rq->stats->wqe_err++;
977 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
980 return NULL; /* page/packet was consumed by XDP */
982 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
986 /* queue up for recycling/reuse */
987 page_ref_inc(di->page);
993 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
994 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
996 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
997 struct mlx5e_wqe_frag_info *head_wi = wi;
998 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
999 u16 frag_headlen = headlen;
1000 u16 byte_cnt = cqe_bcnt - headlen;
1001 struct sk_buff *skb;
1003 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1004 rq->stats->wqe_err++;
1008 /* XDP is not supported in this configuration, as incoming packets
1009 * might spread among multiple pages.
1011 skb = napi_alloc_skb(rq->cq.napi,
1012 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1013 if (unlikely(!skb)) {
1014 rq->stats->buff_alloc_err++;
1018 prefetchw(skb->data);
1021 u16 frag_consumed_bytes =
1022 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1024 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1025 frag_consumed_bytes, frag_info->frag_stride);
1026 byte_cnt -= frag_consumed_bytes;
1033 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
1035 /* skb linear part was allocated with headlen and aligned to long */
1036 skb->tail += headlen;
1037 skb->len += headlen;
1042 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1044 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1045 struct mlx5e_wqe_frag_info *wi;
1046 struct sk_buff *skb;
1050 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1051 wi = get_frag(rq, ci);
1052 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1054 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1056 /* probably for XDP */
1057 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1058 /* do not return page to cache,
1059 * it will be returned on XDP_TX completion.
1066 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1067 napi_gro_receive(rq->cq.napi, skb);
1070 mlx5e_free_rx_wqe(rq, wi, true);
1072 mlx5_wq_cyc_pop(wq);
1075 #ifdef CONFIG_MLX5_ESWITCH
1076 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1078 struct net_device *netdev = rq->netdev;
1079 struct mlx5e_priv *priv = netdev_priv(netdev);
1080 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1081 struct mlx5_eswitch_rep *rep = rpriv->rep;
1082 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1083 struct mlx5e_wqe_frag_info *wi;
1084 struct sk_buff *skb;
1088 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1089 wi = get_frag(rq, ci);
1090 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1092 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1094 /* probably for XDP */
1095 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1096 /* do not return page to cache,
1097 * it will be returned on XDP_TX completion.
1104 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1106 if (rep->vlan && skb_vlan_tag_present(skb))
1109 napi_gro_receive(rq->cq.napi, skb);
1112 mlx5e_free_rx_wqe(rq, wi, true);
1114 mlx5_wq_cyc_pop(wq);
1119 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1120 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1122 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1123 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1124 u32 frag_offset = head_offset + headlen;
1125 u32 byte_cnt = cqe_bcnt - headlen;
1126 struct mlx5e_dma_info *head_di = di;
1127 struct sk_buff *skb;
1129 skb = napi_alloc_skb(rq->cq.napi,
1130 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1131 if (unlikely(!skb)) {
1132 rq->stats->buff_alloc_err++;
1136 prefetchw(skb->data);
1138 if (unlikely(frag_offset >= PAGE_SIZE)) {
1140 frag_offset -= PAGE_SIZE;
1144 u32 pg_consumed_bytes =
1145 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1146 unsigned int truesize =
1147 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1149 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1150 pg_consumed_bytes, truesize);
1151 byte_cnt -= pg_consumed_bytes;
1156 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1157 head_offset, headlen);
1158 /* skb linear part was allocated with headlen and aligned to long */
1159 skb->tail += headlen;
1160 skb->len += headlen;
1166 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1167 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1169 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1170 u16 rx_headroom = rq->buff.headroom;
1171 u32 cqe_bcnt32 = cqe_bcnt;
1172 struct sk_buff *skb;
1177 /* Check packet size. Note LRO doesn't use linear SKB */
1178 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1179 rq->stats->oversize_pkts_sw_drop++;
1183 va = page_address(di->page) + head_offset;
1184 data = va + rx_headroom;
1185 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1187 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1188 frag_size, DMA_FROM_DEVICE);
1189 prefetchw(va); /* xdp_frame data area */
1193 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1196 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1197 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1198 return NULL; /* page/packet was consumed by XDP */
1201 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1205 /* queue up for recycling/reuse */
1206 page_ref_inc(di->page);
1211 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1213 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1214 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1215 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1216 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1217 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1218 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1219 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1220 struct mlx5e_rx_wqe_ll *wqe;
1221 struct mlx5_wq_ll *wq;
1222 struct sk_buff *skb;
1225 wi->consumed_strides += cstrides;
1227 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1228 rq->stats->wqe_err++;
1232 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1233 struct mlx5e_rq_stats *stats = rq->stats;
1235 stats->mpwqe_filler_cqes++;
1236 stats->mpwqe_filler_strides += cstrides;
1240 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1242 skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1247 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1248 napi_gro_receive(rq->cq.napi, skb);
1251 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1255 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1256 mlx5e_free_rx_mpwqe(rq, wi, true);
1257 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1260 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1262 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1263 struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
1264 struct mlx5_cqe64 *cqe;
1267 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1270 if (cq->decmprs_left) {
1271 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1272 if (cq->decmprs_left || work_done >= budget)
1276 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1278 if (unlikely(work_done))
1284 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1286 mlx5e_decompress_cqes_start(rq, cq,
1287 budget - work_done);
1291 mlx5_cqwq_pop(&cq->wq);
1293 rq->handle_rx_cqe(rq, cqe);
1294 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1297 if (xdpsq->doorbell) {
1298 mlx5e_xmit_xdp_doorbell(xdpsq);
1299 xdpsq->doorbell = false;
1302 if (xdpsq->redirect_flush) {
1304 xdpsq->redirect_flush = false;
1307 mlx5_cqwq_update_db_record(&cq->wq);
1309 /* ensure cq space is freed before enabling more cqes */
1315 #ifdef CONFIG_MLX5_CORE_IPOIB
1317 #define MLX5_IB_GRH_SGID_OFFSET 8
1318 #define MLX5_IB_GRH_DGID_OFFSET 24
1319 #define MLX5_GID_SIZE 16
1321 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1322 struct mlx5_cqe64 *cqe,
1324 struct sk_buff *skb)
1326 struct mlx5e_rq_stats *stats = rq->stats;
1327 struct hwtstamp_config *tstamp;
1328 struct net_device *netdev;
1329 struct mlx5e_priv *priv;
1330 char *pseudo_header;
1336 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1337 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1339 /* No mapping present, cannot process SKB. This might happen if a child
1340 * interface is going down while having unprocessed CQEs on parent RQ
1342 if (unlikely(!netdev)) {
1343 /* TODO: add drop counters support */
1345 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1349 priv = mlx5i_epriv(netdev);
1350 tstamp = &priv->tstamp;
1352 flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1353 g = (flags_rqpn >> 28) & 3;
1354 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1355 if ((!g) || dgid[0] != 0xff)
1356 skb->pkt_type = PACKET_HOST;
1357 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1358 skb->pkt_type = PACKET_BROADCAST;
1360 skb->pkt_type = PACKET_MULTICAST;
1362 /* Drop packets that this interface sent, ie multicast packets
1363 * that the HCA has replicated.
1365 if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1366 (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1367 MLX5_GID_SIZE) == 0)) {
1372 skb_pull(skb, MLX5_IB_GRH_BYTES);
1374 skb->protocol = *((__be16 *)(skb->data));
1376 if (netdev->features & NETIF_F_RXCSUM) {
1377 skb->ip_summed = CHECKSUM_COMPLETE;
1378 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1379 stats->csum_complete++;
1381 skb->ip_summed = CHECKSUM_NONE;
1385 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1386 skb_hwtstamps(skb)->hwtstamp =
1387 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1389 skb_record_rx_queue(skb, rq->ix);
1391 if (likely(netdev->features & NETIF_F_RXHASH))
1392 mlx5e_skb_set_hash(cqe, skb);
1394 /* 20 bytes of ipoib header and 4 for encap existing */
1395 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1396 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1397 skb_reset_mac_header(skb);
1398 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1403 stats->bytes += cqe_bcnt;
1406 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1408 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1409 struct mlx5e_wqe_frag_info *wi;
1410 struct sk_buff *skb;
1414 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1415 wi = get_frag(rq, ci);
1416 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1418 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1422 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1423 if (unlikely(!skb->dev)) {
1424 dev_kfree_skb_any(skb);
1427 napi_gro_receive(rq->cq.napi, skb);
1430 mlx5e_free_rx_wqe(rq, wi, true);
1431 mlx5_wq_cyc_pop(wq);
1434 #endif /* CONFIG_MLX5_CORE_IPOIB */
1436 #ifdef CONFIG_MLX5_EN_IPSEC
1438 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1440 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1441 struct mlx5e_wqe_frag_info *wi;
1442 struct sk_buff *skb;
1446 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1447 wi = get_frag(rq, ci);
1448 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1450 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1451 if (unlikely(!skb)) {
1452 /* a DROP, save the page-reuse checks */
1453 mlx5e_free_rx_wqe(rq, wi, true);
1456 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1457 if (unlikely(!skb)) {
1458 mlx5e_free_rx_wqe(rq, wi, true);
1462 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1463 napi_gro_receive(rq->cq.napi, skb);
1465 mlx5e_free_rx_wqe(rq, wi, true);
1467 mlx5_wq_cyc_pop(wq);
1470 #endif /* CONFIG_MLX5_EN_IPSEC */