2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/ipv6.h>
35 #include <linux/tcp.h>
36 #include <net/busy_poll.h>
41 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
43 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
46 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
49 u32 ci = cqcc & cq->wq.sz_m1;
51 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
54 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
55 struct mlx5e_cq *cq, u32 cqcc)
57 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
58 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
59 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
60 rq->stats.cqe_compress_blks++;
63 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
65 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
69 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
71 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
72 u32 wq_sz = 1 << cq->wq.log_sz;
73 u32 ci = cqcc & cq->wq.sz_m1;
74 u32 ci_top = min_t(u32, wq_sz, ci + n);
76 for (; ci < ci_top; ci++, n--) {
77 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
82 if (unlikely(ci == wq_sz)) {
84 for (ci = 0; ci < n; ci++) {
85 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
92 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
93 struct mlx5e_cq *cq, u32 cqcc)
95 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
96 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
97 cq->title.op_own &= 0xf0;
98 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
99 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
101 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
102 cq->decmprs_wqe_counter +=
103 mpwrq_get_cqe_consumed_strides(&cq->title);
105 cq->decmprs_wqe_counter =
106 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
109 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
110 struct mlx5e_cq *cq, u32 cqcc)
112 mlx5e_decompress_cqe(rq, cq, cqcc);
113 cq->title.rss_hash_type = 0;
114 cq->title.rss_hash_result = 0;
117 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
119 int update_owner_only,
122 u32 cqcc = cq->wq.cc + update_owner_only;
126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
128 for (i = update_owner_only; i < cqe_count;
129 i++, cq->mini_arr_idx++, cqcc++) {
130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
131 mlx5e_read_mini_arr_slot(cq, cqcc);
133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
134 rq->handle_rx_cqe(rq, &cq->title);
136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
138 cq->decmprs_left -= cqe_count;
139 rq->stats.cqe_compress_pkts += cqe_count;
144 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
148 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
151 rq->handle_rx_cqe(rq, &cq->title);
154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
157 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
164 mutex_lock(&priv->state_lock);
166 if (priv->params.rx_cqe_compress == val)
169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
171 mlx5e_close_locked(priv->netdev);
173 priv->params.rx_cqe_compress = val;
176 mlx5e_open_locked(priv->netdev);
179 mutex_unlock(&priv->state_lock);
182 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
184 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
185 struct mlx5e_dma_info *dma_info)
187 struct mlx5e_page_cache *cache = &rq->page_cache;
188 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
190 if (tail_next == cache->head) {
191 rq->stats.cache_full++;
195 if (unlikely(page_is_pfmemalloc(dma_info->page)))
198 cache->page_cache[cache->tail] = *dma_info;
199 cache->tail = tail_next;
203 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
204 struct mlx5e_dma_info *dma_info)
206 struct mlx5e_page_cache *cache = &rq->page_cache;
208 if (unlikely(cache->head == cache->tail)) {
209 rq->stats.cache_empty++;
213 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
214 rq->stats.cache_busy++;
218 *dma_info = cache->page_cache[cache->head];
219 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
220 rq->stats.cache_reuse++;
222 dma_sync_single_for_device(rq->pdev, dma_info->addr,
228 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
229 struct mlx5e_dma_info *dma_info)
233 if (mlx5e_rx_cache_get(rq, dma_info))
236 page = dev_alloc_pages(rq->buff.page_order);
240 dma_info->page = page;
241 dma_info->addr = dma_map_page(rq->pdev, page, 0,
242 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
243 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
251 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
254 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
257 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
259 put_page(dma_info->page);
262 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
264 struct mlx5e_dma_info *di = &rq->dma_info[ix];
266 if (unlikely(mlx5e_page_alloc_mapped(rq, di)))
269 wqe->data.addr = cpu_to_be64(di->addr + MLX5_RX_HEADROOM);
273 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
275 struct mlx5e_dma_info *di = &rq->dma_info[ix];
277 mlx5e_page_release(rq, di, true);
280 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
282 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
285 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
287 struct mlx5e_mpw_info *wi,
288 u32 page_idx, u32 frag_offset,
291 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
293 dma_sync_single_for_cpu(rq->pdev,
294 wi->umr.dma_info[page_idx].addr + frag_offset,
295 len, DMA_FROM_DEVICE);
296 wi->skbs_frags[page_idx]++;
297 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
298 wi->umr.dma_info[page_idx].page, frag_offset,
303 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
305 struct mlx5e_mpw_info *wi,
306 u32 page_idx, u32 offset,
309 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
310 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
313 /* Aligning len to sizeof(long) optimizes memcpy performance */
314 len = ALIGN(headlen_pg, sizeof(long));
315 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
317 skb_copy_to_linear_data_offset(skb, 0,
318 page_address(dma_info->page) + offset,
320 if (unlikely(offset + headlen > PAGE_SIZE)) {
323 len = ALIGN(headlen - headlen_pg, sizeof(long));
324 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
326 skb_copy_to_linear_data_offset(skb, headlen_pg,
327 page_address(dma_info->page),
332 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
334 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
335 struct mlx5e_sq *sq = &rq->channel->icosq;
336 struct mlx5_wq_cyc *wq = &sq->wq;
337 struct mlx5e_umr_wqe *wqe;
338 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
341 /* fill sq edge with nops to avoid wqe wrap around */
342 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
343 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
344 sq->db.ico_wqe[pi].num_wqebbs = 1;
345 mlx5e_send_nop(sq, false);
348 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
349 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
350 wqe->ctrl.opmod_idx_opcode =
351 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
354 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
355 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs;
356 sq->pc += num_wqebbs;
357 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
360 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
361 struct mlx5e_rx_wqe *wqe,
364 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
365 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
366 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
370 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
371 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
373 err = mlx5e_page_alloc_mapped(rq, dma_info);
376 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
377 page_ref_add(dma_info->page, pg_strides);
378 wi->skbs_frags[i] = 0;
381 wi->consumed_strides = 0;
382 wqe->data.addr = cpu_to_be64(dma_offset);
388 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
390 page_ref_sub(dma_info->page, pg_strides);
391 mlx5e_page_release(rq, dma_info, true);
397 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
399 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
402 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
403 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
405 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
406 mlx5e_page_release(rq, dma_info, true);
410 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
412 struct mlx5_wq_ll *wq = &rq->wq;
413 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
415 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
417 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) {
418 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
422 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
424 /* ensure wqes are visible to device before updating doorbell record */
427 mlx5_wq_ll_update_db_record(wq);
430 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
434 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix);
437 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
438 mlx5e_post_umr_wqe(rq, ix);
442 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
444 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
446 mlx5e_free_rx_mpwqe(rq, wi);
449 #define RQ_CANNOT_POST(rq) \
450 (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \
451 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
453 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
455 struct mlx5_wq_ll *wq = &rq->wq;
457 if (unlikely(RQ_CANNOT_POST(rq)))
460 while (!mlx5_wq_ll_is_full(wq)) {
461 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
464 err = rq->alloc_wqe(rq, wqe, wq->head);
468 rq->stats.buff_alloc_err++;
472 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
475 /* ensure wqes are visible to device before updating doorbell record */
478 mlx5_wq_ll_update_db_record(wq);
480 return !mlx5_wq_ll_is_full(wq);
483 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
486 struct ethhdr *eth = (struct ethhdr *)(skb->data);
488 struct ipv6hdr *ipv6;
490 int network_depth = 0;
494 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
495 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
496 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
498 skb->mac_len = ETH_HLEN;
499 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
501 ipv4 = (struct iphdr *)(skb->data + network_depth);
502 ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
503 tot_len = cqe_bcnt - network_depth;
505 if (proto == htons(ETH_P_IP)) {
506 tcp = (struct tcphdr *)(skb->data + network_depth +
507 sizeof(struct iphdr));
509 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
511 tcp = (struct tcphdr *)(skb->data + network_depth +
512 sizeof(struct ipv6hdr));
514 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
517 if (get_cqe_lro_tcppsh(cqe))
522 tcp->ack_seq = cqe->lro_ack_seq_num;
523 tcp->window = cqe->lro_tcp_win;
527 ipv4->ttl = cqe->lro_min_ttl;
528 ipv4->tot_len = cpu_to_be16(tot_len);
530 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
533 ipv6->hop_limit = cqe->lro_min_ttl;
534 ipv6->payload_len = cpu_to_be16(tot_len -
535 sizeof(struct ipv6hdr));
539 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
542 u8 cht = cqe->rss_hash_type;
543 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
544 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
546 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
549 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
551 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
553 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
556 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
558 static inline void mlx5e_handle_csum(struct net_device *netdev,
559 struct mlx5_cqe64 *cqe,
564 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
572 /* CQE csum doesn't cover padding octets in short ethernet
573 * frames. And the pad field is appended prior to calculating
574 * and appending the FCS field.
576 * Detecting these padded frames requires to verify and parse
577 * IP headers, so we simply force all those small frames to be
578 * CHECKSUM_UNNECESSARY even if they are not padded.
580 if (short_frame(skb->len))
581 goto csum_unnecessary;
583 if (is_first_ethertype_ip(skb)) {
584 skb->ip_summed = CHECKSUM_COMPLETE;
585 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
586 rq->stats.csum_complete++;
591 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
592 (cqe->hds_ip_ext & CQE_L4_OK))) {
593 skb->ip_summed = CHECKSUM_UNNECESSARY;
594 if (cqe_is_tunneled(cqe)) {
596 skb->encapsulation = 1;
597 rq->stats.csum_unnecessary_inner++;
602 skb->ip_summed = CHECKSUM_NONE;
603 rq->stats.csum_none++;
606 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
611 struct net_device *netdev = rq->netdev;
612 struct mlx5e_tstamp *tstamp = rq->tstamp;
615 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
616 if (lro_num_seg > 1) {
617 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
618 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
619 /* Subtract one since we already counted this as one
620 * "regular" packet in mlx5e_complete_rx_cqe()
622 rq->stats.packets += lro_num_seg - 1;
623 rq->stats.lro_packets++;
624 rq->stats.lro_bytes += cqe_bcnt;
627 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
628 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
630 skb_record_rx_queue(skb, rq->ix);
632 if (likely(netdev->features & NETIF_F_RXHASH))
633 mlx5e_skb_set_hash(cqe, skb);
635 if (cqe_has_vlan(cqe))
636 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
637 be16_to_cpu(cqe->vlan_info));
639 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
641 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
642 skb->protocol = eth_type_trans(skb, netdev);
645 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
646 struct mlx5_cqe64 *cqe,
651 rq->stats.bytes += cqe_bcnt;
652 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
655 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_sq *sq)
657 struct mlx5_wq_cyc *wq = &sq->wq;
658 struct mlx5e_tx_wqe *wqe;
659 u16 pi = (sq->pc - MLX5E_XDP_TX_WQEBBS) & wq->sz_m1; /* last pi */
661 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
663 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
664 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
667 static inline void mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
668 struct mlx5e_dma_info *di,
669 unsigned int data_offset,
672 struct mlx5e_sq *sq = &rq->channel->xdp_sq;
673 struct mlx5_wq_cyc *wq = &sq->wq;
674 u16 pi = sq->pc & wq->sz_m1;
675 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
676 struct mlx5e_sq_wqe_info *wi = &sq->db.xdp.wqe_info[pi];
678 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
679 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
680 struct mlx5_wqe_data_seg *dseg;
682 dma_addr_t dma_addr = di->addr + data_offset + MLX5E_XDP_MIN_INLINE;
683 unsigned int dma_len = len - MLX5E_XDP_MIN_INLINE;
684 void *data = page_address(di->page) + data_offset;
686 if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_XDP_TX_WQEBBS))) {
687 if (sq->db.xdp.doorbell) {
688 /* SQ is full, ring doorbell */
689 mlx5e_xmit_xdp_doorbell(sq);
690 sq->db.xdp.doorbell = false;
692 rq->stats.xdp_tx_full++;
693 mlx5e_page_release(rq, di, true);
697 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len,
700 memset(wqe, 0, sizeof(*wqe));
702 /* copy the inline part */
703 memcpy(eseg->inline_hdr_start, data, MLX5E_XDP_MIN_INLINE);
704 eseg->inline_hdr_sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
706 dseg = (struct mlx5_wqe_data_seg *)cseg + (MLX5E_XDP_TX_DS_COUNT - 1);
708 /* write the dma part */
709 dseg->addr = cpu_to_be64(dma_addr);
710 dseg->byte_count = cpu_to_be32(dma_len);
711 dseg->lkey = sq->mkey_be;
713 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
714 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | MLX5E_XDP_TX_DS_COUNT);
716 sq->db.xdp.di[pi] = *di;
717 wi->opcode = MLX5_OPCODE_SEND;
718 wi->num_wqebbs = MLX5E_XDP_TX_WQEBBS;
719 sq->pc += MLX5E_XDP_TX_WQEBBS;
721 sq->db.xdp.doorbell = true;
725 /* returns true if packet was consumed by xdp */
726 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
727 const struct bpf_prog *prog,
728 struct mlx5e_dma_info *di,
738 xdp.data_end = xdp.data + len;
739 act = bpf_prog_run_xdp(prog, &xdp);
744 mlx5e_xmit_xdp_frame(rq, di, MLX5_RX_HEADROOM, len);
747 bpf_warn_invalid_xdp_action(act);
750 rq->stats.xdp_drop++;
751 mlx5e_page_release(rq, di, true);
757 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
758 u16 wqe_counter, u32 cqe_bcnt)
760 struct bpf_prog *xdp_prog = READ_ONCE(rq->xdp_prog);
761 struct mlx5e_dma_info *di;
765 di = &rq->dma_info[wqe_counter];
766 va = page_address(di->page);
767 data = va + MLX5_RX_HEADROOM;
769 dma_sync_single_range_for_cpu(rq->pdev,
776 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
778 mlx5e_page_release(rq, di, true);
782 if (mlx5e_xdp_handle(rq, xdp_prog, di, data, cqe_bcnt))
783 return NULL; /* page/packet was consumed by XDP */
785 skb = build_skb(va, RQ_PAGE_SIZE(rq));
786 if (unlikely(!skb)) {
787 rq->stats.buff_alloc_err++;
788 mlx5e_page_release(rq, di, true);
792 /* queue up for recycling ..*/
793 page_ref_inc(di->page);
794 mlx5e_page_release(rq, di, true);
796 skb_reserve(skb, MLX5_RX_HEADROOM);
797 skb_put(skb, cqe_bcnt);
802 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
804 struct mlx5e_rx_wqe *wqe;
805 __be16 wqe_counter_be;
810 wqe_counter_be = cqe->wqe_counter;
811 wqe_counter = be16_to_cpu(wqe_counter_be);
812 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
813 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
815 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
819 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
820 napi_gro_receive(rq->cq.napi, skb);
823 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
824 &wqe->next.next_wqe_index);
827 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
829 struct net_device *netdev = rq->netdev;
830 struct mlx5e_priv *priv = netdev_priv(netdev);
831 struct mlx5_eswitch_rep *rep = priv->ppriv;
832 struct mlx5e_rx_wqe *wqe;
834 __be16 wqe_counter_be;
838 wqe_counter_be = cqe->wqe_counter;
839 wqe_counter = be16_to_cpu(wqe_counter_be);
840 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
841 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
843 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
847 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
849 if (rep->vlan && skb_vlan_tag_present(skb))
852 napi_gro_receive(rq->cq.napi, skb);
855 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
856 &wqe->next.next_wqe_index);
859 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
860 struct mlx5_cqe64 *cqe,
861 struct mlx5e_mpw_info *wi,
865 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
866 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
867 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
868 u32 page_idx = wqe_offset >> PAGE_SHIFT;
869 u32 head_page_idx = page_idx;
870 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
871 u32 frag_offset = head_offset + headlen;
872 u16 byte_cnt = cqe_bcnt - headlen;
874 if (unlikely(frag_offset >= PAGE_SIZE)) {
876 frag_offset -= PAGE_SIZE;
880 u32 pg_consumed_bytes =
881 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
883 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
885 byte_cnt -= pg_consumed_bytes;
890 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
891 head_offset, headlen);
892 /* skb linear part was allocated with headlen and aligned to long */
893 skb->tail += headlen;
897 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
899 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
900 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
901 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
902 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
906 wi->consumed_strides += cstrides;
908 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
913 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
914 rq->stats.mpwqe_filler++;
918 skb = napi_alloc_skb(rq->cq.napi,
919 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
921 if (unlikely(!skb)) {
922 rq->stats.buff_alloc_err++;
927 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
929 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
930 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
931 napi_gro_receive(rq->cq.napi, skb);
934 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
937 mlx5e_free_rx_mpwqe(rq, wi);
938 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
941 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
943 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
944 struct mlx5e_sq *xdp_sq = &rq->channel->xdp_sq;
947 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
950 if (cq->decmprs_left)
951 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
953 for (; work_done < budget; work_done++) {
954 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
959 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
961 mlx5e_decompress_cqes_start(rq, cq,
966 mlx5_cqwq_pop(&cq->wq);
968 rq->handle_rx_cqe(rq, cqe);
971 if (xdp_sq->db.xdp.doorbell) {
972 mlx5e_xmit_xdp_doorbell(xdp_sq);
973 xdp_sq->db.xdp.doorbell = false;
976 mlx5_cqwq_update_db_record(&cq->wq);
978 /* ensure cq space is freed before enabling more cqes */