drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "lib/vxlan.h"
  49 #include "lib/clock.h"
  50 #include "en/port.h"
  51 #include "en/xdp.h"
  52
  53 struct mlx5e_rq_param {
  54         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  55         struct mlx5_wq_param    wq;
  56         struct mlx5e_rq_frags_info frags_info;
  57 };
  58
  59 struct mlx5e_sq_param {
  60         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  61         struct mlx5_wq_param       wq;
  62 };
  63
  64 struct mlx5e_cq_param {
  65         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  66         struct mlx5_wq_param       wq;
  67         u16                        eq_ix;
  68         u8                         cq_period_mode;
  69 };
  70
  71 struct mlx5e_channel_param {
  72         struct mlx5e_rq_param      rq;
  73         struct mlx5e_sq_param      sq;
  74         struct mlx5e_sq_param      xdp_sq;
  75         struct mlx5e_sq_param      icosq;
  76         struct mlx5e_cq_param      rx_cq;
  77         struct mlx5e_cq_param      tx_cq;
  78         struct mlx5e_cq_param      icosq_cq;
  79 };
  80
  81 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  82 {
  83         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  84                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  85                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  86         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  87         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  88
  89         if (!striding_rq_umr)
  90                 return false;
  91         if (!inline_umr) {
  92                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  93                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  94                 return false;
  95         }
  96         return true;
  97 }
  98
  99 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
 100 {
 101         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 102         u16 linear_rq_headroom = params->xdp_prog ?
 103                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 104         u32 frag_sz;
 105
 106         linear_rq_headroom += NET_IP_ALIGN;
 107
 108         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 109
 110         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 111                 frag_sz = PAGE_SIZE;
 112
 113         return frag_sz;
 114 }
 115
 116 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 117 {
 118         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 119
 120         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 121 }
 122
 123 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 124                                    struct mlx5e_params *params)
 125 {
 126         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 127
 128         return !params->lro_en && frag_sz <= PAGE_SIZE;
 129 }
 130
 131 #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \
 132                                           MLX5_MPWQE_LOG_STRIDE_SZ_BASE)
 133 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 134                                          struct mlx5e_params *params)
 135 {
 136         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 137         s8 signed_log_num_strides_param;
 138         u8 log_num_strides;
 139
 140         if (!mlx5e_rx_is_linear_skb(mdev, params))
 141                 return false;
 142
 143         if (order_base_2(frag_sz) > MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ)
 144                 return false;
 145
 146         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 147                 return true;
 148
 149         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 150         signed_log_num_strides_param =
 151                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 152
 153         return signed_log_num_strides_param >= 0;
 154 }
 155
 156 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 157 {
 158         if (params->log_rq_mtu_frames <
 159             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 160                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 161
 162         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 163 }
 164
 165 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 166                                           struct mlx5e_params *params)
 167 {
 168         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 169                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 170
 171         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 172                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 173 }
 174
 175 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 176                                           struct mlx5e_params *params)
 177 {
 178         return MLX5_MPWRQ_LOG_WQE_SZ -
 179                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 180 }
 181
 182 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 183                                  struct mlx5e_params *params)
 184 {
 185         u16 linear_rq_headroom = params->xdp_prog ?
 186                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 187         bool is_linear_skb;
 188
 189         linear_rq_headroom += NET_IP_ALIGN;
 190
 191         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 192                 mlx5e_rx_is_linear_skb(mdev, params) :
 193                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 194
 195         return is_linear_skb ? linear_rq_headroom : 0;
 196 }
 197
 198 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 199                                struct mlx5e_params *params)
 200 {
 201         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 202         params->log_rq_mtu_frames = is_kdump_kernel() ?
 203                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 204                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 205
 206         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 207                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 208                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 209                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 210                        BIT(params->log_rq_mtu_frames),
 211                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 212                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 213 }
 214
 215 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 216                                 struct mlx5e_params *params)
 217 {
 218         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 219                 !MLX5_IPSEC_DEV(mdev) &&
 220                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 221 }
 222
 223 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 224 {
 225         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 226                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 227                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 228                 MLX5_WQ_TYPE_CYCLIC;
 229 }
 230
 231 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 232 {
 233         struct mlx5_core_dev *mdev = priv->mdev;
 234         u8 port_state;
 235
 236         port_state = mlx5_query_vport_state(mdev,
 237                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 238                                             0);
 239
 240         if (port_state == VPORT_STATE_UP) {
 241                 netdev_info(priv->netdev, "Link up\n");
 242                 netif_carrier_on(priv->netdev);
 243         } else {
 244                 netdev_info(priv->netdev, "Link down\n");
 245                 netif_carrier_off(priv->netdev);
 246         }
 247 }
 248
 249 static void mlx5e_update_carrier_work(struct work_struct *work)
 250 {
 251         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 252                                                update_carrier_work);
 253
 254         mutex_lock(&priv->state_lock);
 255         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 256                 if (priv->profile->update_carrier)
 257                         priv->profile->update_carrier(priv);
 258         mutex_unlock(&priv->state_lock);
 259 }
 260
 261 void mlx5e_update_stats(struct mlx5e_priv *priv)
 262 {
 263         int i;
 264
 265         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 266                 if (mlx5e_stats_grps[i].update_stats)
 267                         mlx5e_stats_grps[i].update_stats(priv);
 268 }
 269
 270 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 271 {
 272         int i;
 273
 274         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 275                 if (mlx5e_stats_grps[i].update_stats_mask &
 276                     MLX5E_NDO_UPDATE_STATS)
 277                         mlx5e_stats_grps[i].update_stats(priv);
 278 }
 279
 280 void mlx5e_update_stats_work(struct work_struct *work)
 281 {
 282         struct delayed_work *dwork = to_delayed_work(work);
 283         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 284                                                update_stats_work);
 285
 286         mutex_lock(&priv->state_lock);
 287         priv->profile->update_stats(priv);
 288         mutex_unlock(&priv->state_lock);
 289 }
 290
 291 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 292                               enum mlx5_dev_event event, unsigned long param)
 293 {
 294         struct mlx5e_priv *priv = vpriv;
 295
 296         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 297                 return;
 298
 299         switch (event) {
 300         case MLX5_DEV_EVENT_PORT_UP:
 301         case MLX5_DEV_EVENT_PORT_DOWN:
 302                 queue_work(priv->wq, &priv->update_carrier_work);
 303                 break;
 304         default:
 305                 break;
 306         }
 307 }
 308
 309 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 310 {
 311         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 312 }
 313
 314 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 315 {
 316         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 317         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 318 }
 319
 320 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 321                                        struct mlx5e_icosq *sq,
 322                                        struct mlx5e_umr_wqe *wqe)
 323 {
 324         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 325         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 326         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 327
 328         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 329                                       ds_cnt);
 330         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 331         cseg->imm       = rq->mkey_be;
 332
 333         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 334         ucseg->xlt_octowords =
 335                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 336         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 337 }
 338
 339 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 340 {
 341         switch (rq->wq_type) {
 342         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 343                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 344         default:
 345                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 346         }
 347 }
 348
 349 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 350 {
 351         switch (rq->wq_type) {
 352         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 353                 return rq->mpwqe.wq.cur_sz;
 354         default:
 355                 return rq->wqe.wq.cur_sz;
 356         }
 357 }
 358
 359 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 360                                      struct mlx5e_channel *c)
 361 {
 362         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 363
 364         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 365                                                   sizeof(*rq->mpwqe.info)),
 366                                        GFP_KERNEL, cpu_to_node(c->cpu));
 367         if (!rq->mpwqe.info)
 368                 return -ENOMEM;
 369
 370         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 371
 372         return 0;
 373 }
 374
 375 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 376                                  u64 npages, u8 page_shift,
 377                                  struct mlx5_core_mkey *umr_mkey)
 378 {
 379         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 380         void *mkc;
 381         u32 *in;
 382         int err;
 383
 384         in = kvzalloc(inlen, GFP_KERNEL);
 385         if (!in)
 386                 return -ENOMEM;
 387
 388         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 389
 390         MLX5_SET(mkc, mkc, free, 1);
 391         MLX5_SET(mkc, mkc, umr_en, 1);
 392         MLX5_SET(mkc, mkc, lw, 1);
 393         MLX5_SET(mkc, mkc, lr, 1);
 394         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 395
 396         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 397         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 398         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 399         MLX5_SET(mkc, mkc, translations_octword_size,
 400                  MLX5_MTT_OCTW(npages));
 401         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 402
 403         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 404
 405         kvfree(in);
 406         return err;
 407 }
 408
 409 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 410 {
 411         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 412
 413         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 414 }
 415
 416 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 417 {
 418         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 419 }
 420
 421 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 422 {
 423         struct mlx5e_wqe_frag_info next_frag = {};
 424         struct mlx5e_wqe_frag_info *prev = NULL;
 425         int i;
 426
 427         next_frag.di = &rq->wqe.di[0];
 428
 429         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 430                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 431                 struct mlx5e_wqe_frag_info *frag =
 432                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 433                 int f;
 434
 435                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 436                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 437                                 next_frag.di++;
 438                                 next_frag.offset = 0;
 439                                 if (prev)
 440                                         prev->last_in_page = true;
 441                         }
 442                         *frag = next_frag;
 443
 444                         /* prepare next */
 445                         next_frag.offset += frag_info[f].frag_stride;
 446                         prev = frag;
 447                 }
 448         }
 449
 450         if (prev)
 451                 prev->last_in_page = true;
 452 }
 453
 454 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 455                               struct mlx5e_params *params,
 456                               int wq_sz, int cpu)
 457 {
 458         int len = wq_sz << rq->wqe.info.log_num_frags;
 459
 460         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 461                                    GFP_KERNEL, cpu_to_node(cpu));
 462         if (!rq->wqe.di)
 463                 return -ENOMEM;
 464
 465         mlx5e_init_frags_partition(rq);
 466
 467         return 0;
 468 }
 469
 470 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 471 {
 472         kvfree(rq->wqe.di);
 473 }
 474
 475 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 476                           struct mlx5e_params *params,
 477                           struct mlx5e_rq_param *rqp,
 478                           struct mlx5e_rq *rq)
 479 {
 480         struct page_pool_params pp_params = { 0 };
 481         struct mlx5_core_dev *mdev = c->mdev;
 482         void *rqc = rqp->rqc;
 483         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 484         u32 pool_size;
 485         int wq_sz;
 486         int err;
 487         int i;
 488
 489         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 490
 491         rq->wq_type = params->rq_wq_type;
 492         rq->pdev    = c->pdev;
 493         rq->netdev  = c->netdev;
 494         rq->tstamp  = c->tstamp;
 495         rq->clock   = &mdev->clock;
 496         rq->channel = c;
 497         rq->ix      = c->ix;
 498         rq->mdev    = mdev;
 499         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 500         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 501
 502         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 503         if (IS_ERR(rq->xdp_prog)) {
 504                 err = PTR_ERR(rq->xdp_prog);
 505                 rq->xdp_prog = NULL;
 506                 goto err_rq_wq_destroy;
 507         }
 508
 509         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 510         if (err < 0)
 511                 goto err_rq_wq_destroy;
 512
 513         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 514         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 515         pool_size = 1 << params->log_rq_mtu_frames;
 516
 517         switch (rq->wq_type) {
 518         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 519                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 520                                         &rq->wq_ctrl);
 521                 if (err)
 522                         goto err_rq_wq_destroy;
 523
 524                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 525
 526                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 527
 528                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 529
 530                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 531                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 532
 533                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 534 #ifdef CONFIG_MLX5_EN_IPSEC
 535                 if (MLX5_IPSEC_DEV(mdev)) {
 536                         err = -EINVAL;
 537                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 538                         goto err_rq_wq_destroy;
 539                 }
 540 #endif
 541                 if (!rq->handle_rx_cqe) {
 542                         err = -EINVAL;
 543                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 544                         goto err_rq_wq_destroy;
 545                 }
 546
 547                 rq->mpwqe.skb_from_cqe_mpwrq =
 548                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 549                         mlx5e_skb_from_cqe_mpwrq_linear :
 550                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 551                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 552                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 553
 554                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 555                 if (err)
 556                         goto err_rq_wq_destroy;
 557                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 558
 559                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 560                 if (err)
 561                         goto err_free;
 562                 break;
 563         default: /* MLX5_WQ_TYPE_CYCLIC */
 564                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 565                                          &rq->wq_ctrl);
 566                 if (err)
 567                         goto err_rq_wq_destroy;
 568
 569                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 570
 571                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 572
 573                 rq->wqe.info = rqp->frags_info;
 574                 rq->wqe.frags =
 575                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 576                                         (wq_sz << rq->wqe.info.log_num_frags)),
 577                                       GFP_KERNEL, cpu_to_node(c->cpu));
 578                 if (!rq->wqe.frags) {
 579                         err = -ENOMEM;
 580                         goto err_free;
 581                 }
 582
 583                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 584                 if (err)
 585                         goto err_free;
 586                 rq->post_wqes = mlx5e_post_rx_wqes;
 587                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 588
 589 #ifdef CONFIG_MLX5_EN_IPSEC
 590                 if (c->priv->ipsec)
 591                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 592                 else
 593 #endif
 594                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 595                 if (!rq->handle_rx_cqe) {
 596                         err = -EINVAL;
 597                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 598                         goto err_free;
 599                 }
 600
 601                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 602                         mlx5e_skb_from_cqe_linear :
 603                         mlx5e_skb_from_cqe_nonlinear;
 604                 rq->mkey_be = c->mkey_be;
 605         }
 606
 607         /* Create a page_pool and register it with rxq */
 608         pp_params.order     = 0;
 609         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 610         pp_params.pool_size = pool_size;
 611         pp_params.nid       = cpu_to_node(c->cpu);
 612         pp_params.dev       = c->pdev;
 613         pp_params.dma_dir   = rq->buff.map_dir;
 614
 615         /* page_pool can be used even when there is no rq->xdp_prog,
 616          * given page_pool does not handle DMA mapping there is no
 617          * required state to clear. And page_pool gracefully handle
 618          * elevated refcnt.
 619          */
 620         rq->page_pool = page_pool_create(&pp_params);
 621         if (IS_ERR(rq->page_pool)) {
 622                 err = PTR_ERR(rq->page_pool);
 623                 rq->page_pool = NULL;
 624                 goto err_free;
 625         }
 626         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 627                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 628         if (err)
 629                 goto err_free;
 630
 631         for (i = 0; i < wq_sz; i++) {
 632                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 633                         struct mlx5e_rx_wqe_ll *wqe =
 634                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 635                         u32 byte_count =
 636                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 637                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 638
 639                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 640                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 641                         wqe->data[0].lkey = rq->mkey_be;
 642                 } else {
 643                         struct mlx5e_rx_wqe_cyc *wqe =
 644                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 645                         int f;
 646
 647                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 648                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 649                                         MLX5_HW_START_PADDING;
 650
 651                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 652                                 wqe->data[f].lkey = rq->mkey_be;
 653                         }
 654                         /* check if num_frags is not a pow of two */
 655                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 656                                 wqe->data[f].byte_count = 0;
 657                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 658                                 wqe->data[f].addr = 0;
 659                         }
 660                 }
 661         }
 662
 663         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 664
 665         switch (params->rx_cq_moderation.cq_period_mode) {
 666         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 667                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 668                 break;
 669         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 670         default:
 671                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 672         }
 673
 674         rq->page_cache.head = 0;
 675         rq->page_cache.tail = 0;
 676
 677         return 0;
 678
 679 err_free:
 680         switch (rq->wq_type) {
 681         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 682                 kvfree(rq->mpwqe.info);
 683                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 684                 break;
 685         default: /* MLX5_WQ_TYPE_CYCLIC */
 686                 kvfree(rq->wqe.frags);
 687                 mlx5e_free_di_list(rq);
 688         }
 689
 690 err_rq_wq_destroy:
 691         if (rq->xdp_prog)
 692                 bpf_prog_put(rq->xdp_prog);
 693         xdp_rxq_info_unreg(&rq->xdp_rxq);
 694         if (rq->page_pool)
 695                 page_pool_destroy(rq->page_pool);
 696         mlx5_wq_destroy(&rq->wq_ctrl);
 697
 698         return err;
 699 }
 700
 701 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 702 {
 703         int i;
 704
 705         if (rq->xdp_prog)
 706                 bpf_prog_put(rq->xdp_prog);
 707
 708         xdp_rxq_info_unreg(&rq->xdp_rxq);
 709         if (rq->page_pool)
 710                 page_pool_destroy(rq->page_pool);
 711
 712         switch (rq->wq_type) {
 713         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 714                 kvfree(rq->mpwqe.info);
 715                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 716                 break;
 717         default: /* MLX5_WQ_TYPE_CYCLIC */
 718                 kvfree(rq->wqe.frags);
 719                 mlx5e_free_di_list(rq);
 720         }
 721
 722         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 723              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 724                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 725
 726                 mlx5e_page_release(rq, dma_info, false);
 727         }
 728         mlx5_wq_destroy(&rq->wq_ctrl);
 729 }
 730
 731 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 732                            struct mlx5e_rq_param *param)
 733 {
 734         struct mlx5_core_dev *mdev = rq->mdev;
 735
 736         void *in;
 737         void *rqc;
 738         void *wq;
 739         int inlen;
 740         int err;
 741
 742         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 743                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 744         in = kvzalloc(inlen, GFP_KERNEL);
 745         if (!in)
 746                 return -ENOMEM;
 747
 748         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 749         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 750
 751         memcpy(rqc, param->rqc, sizeof(param->rqc));
 752
 753         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 754         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 755         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 756                                                 MLX5_ADAPTER_PAGE_SHIFT);
 757         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 758
 759         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 760                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 761
 762         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 763
 764         kvfree(in);
 765
 766         return err;
 767 }
 768
 769 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 770                                  int next_state)
 771 {
 772         struct mlx5_core_dev *mdev = rq->mdev;
 773
 774         void *in;
 775         void *rqc;
 776         int inlen;
 777         int err;
 778
 779         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 780         in = kvzalloc(inlen, GFP_KERNEL);
 781         if (!in)
 782                 return -ENOMEM;
 783
 784         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 785
 786         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 787         MLX5_SET(rqc, rqc, state, next_state);
 788
 789         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 790
 791         kvfree(in);
 792
 793         return err;
 794 }
 795
 796 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 797 {
 798         struct mlx5e_channel *c = rq->channel;
 799         struct mlx5e_priv *priv = c->priv;
 800         struct mlx5_core_dev *mdev = priv->mdev;
 801
 802         void *in;
 803         void *rqc;
 804         int inlen;
 805         int err;
 806
 807         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 808         in = kvzalloc(inlen, GFP_KERNEL);
 809         if (!in)
 810                 return -ENOMEM;
 811
 812         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 813
 814         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 815         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 816                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 817         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 818         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 819
 820         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 821
 822         kvfree(in);
 823
 824         return err;
 825 }
 826
 827 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 828 {
 829         struct mlx5e_channel *c = rq->channel;
 830         struct mlx5_core_dev *mdev = c->mdev;
 831         void *in;
 832         void *rqc;
 833         int inlen;
 834         int err;
 835
 836         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 837         in = kvzalloc(inlen, GFP_KERNEL);
 838         if (!in)
 839                 return -ENOMEM;
 840
 841         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 842
 843         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 844         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 845                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 846         MLX5_SET(rqc, rqc, vsd, vsd);
 847         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 848
 849         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 850
 851         kvfree(in);
 852
 853         return err;
 854 }
 855
 856 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 857 {
 858         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 859 }
 860
 861 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 862 {
 863         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 864         struct mlx5e_channel *c = rq->channel;
 865
 866         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 867
 868         do {
 869                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 870                         return 0;
 871
 872                 msleep(20);
 873         } while (time_before(jiffies, exp_time));
 874
 875         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 876                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 877
 878         return -ETIMEDOUT;
 879 }
 880
 881 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 882 {
 883         __be16 wqe_ix_be;
 884         u16 wqe_ix;
 885
 886         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 887                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 888
 889                 /* UMR WQE (if in progress) is always at wq->head */
 890                 if (rq->mpwqe.umr_in_progress)
 891                         rq->dealloc_wqe(rq, wq->head);
 892
 893                 while (!mlx5_wq_ll_is_empty(wq)) {
 894                         struct mlx5e_rx_wqe_ll *wqe;
 895
 896                         wqe_ix_be = *wq->tail_next;
 897                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 898                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 899                         rq->dealloc_wqe(rq, wqe_ix);
 900                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 901                                        &wqe->next.next_wqe_index);
 902                 }
 903         } else {
 904                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 905
 906                 while (!mlx5_wq_cyc_is_empty(wq)) {
 907                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 908                         rq->dealloc_wqe(rq, wqe_ix);
 909                         mlx5_wq_cyc_pop(wq);
 910                 }
 911         }
 912
 913 }
 914
 915 static int mlx5e_open_rq(struct mlx5e_channel *c,
 916                          struct mlx5e_params *params,
 917                          struct mlx5e_rq_param *param,
 918                          struct mlx5e_rq *rq)
 919 {
 920         int err;
 921
 922         err = mlx5e_alloc_rq(c, params, param, rq);
 923         if (err)
 924                 return err;
 925
 926         err = mlx5e_create_rq(rq, param);
 927         if (err)
 928                 goto err_free_rq;
 929
 930         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 931         if (err)
 932                 goto err_destroy_rq;
 933
 934         if (params->rx_dim_enabled)
 935                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 936
 937         /* We disable csum_complete when XDP is enabled since
 938          * XDP programs might manipulate packets which will render
 939          * skb->checksum incorrect.
 940          */
 941         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 942                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 943
 944         return 0;
 945
 946 err_destroy_rq:
 947         mlx5e_destroy_rq(rq);
 948 err_free_rq:
 949         mlx5e_free_rq(rq);
 950
 951         return err;
 952 }
 953
 954 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 955 {
 956         struct mlx5e_icosq *sq = &rq->channel->icosq;
 957         struct mlx5_wq_cyc *wq = &sq->wq;
 958         struct mlx5e_tx_wqe *nopwqe;
 959
 960         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 961
 962         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 963         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 964         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 965         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 966 }
 967
 968 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 969 {
 970         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 971         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 972 }
 973
 974 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 975 {
 976         cancel_work_sync(&rq->dim.work);
 977         mlx5e_destroy_rq(rq);
 978         mlx5e_free_rx_descs(rq);
 979         mlx5e_free_rq(rq);
 980 }
 981
 982 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 983 {
 984         kvfree(sq->db.xdpi);
 985 }
 986
 987 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 988 {
 989         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 990
 991         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
 992                                     GFP_KERNEL, numa);
 993         if (!sq->db.xdpi) {
 994                 mlx5e_free_xdpsq_db(sq);
 995                 return -ENOMEM;
 996         }
 997
 998         return 0;
 999 }
1000
1001 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1002                              struct mlx5e_params *params,
1003                              struct mlx5e_sq_param *param,
1004                              struct mlx5e_xdpsq *sq,
1005                              bool is_redirect)
1006 {
1007         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1008         struct mlx5_core_dev *mdev = c->mdev;
1009         struct mlx5_wq_cyc *wq = &sq->wq;
1010         int err;
1011
1012         sq->pdev      = c->pdev;
1013         sq->mkey_be   = c->mkey_be;
1014         sq->channel   = c;
1015         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1016         sq->min_inline_mode = params->tx_min_inline_mode;
1017         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1018         sq->stats     = is_redirect ?
1019                 &c->priv->channel_stats[c->ix].xdpsq :
1020                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1021
1022         param->wq.db_numa_node = cpu_to_node(c->cpu);
1023         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1024         if (err)
1025                 return err;
1026         wq->db = &wq->db[MLX5_SND_DBR];
1027
1028         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1029         if (err)
1030                 goto err_sq_wq_destroy;
1031
1032         return 0;
1033
1034 err_sq_wq_destroy:
1035         mlx5_wq_destroy(&sq->wq_ctrl);
1036
1037         return err;
1038 }
1039
1040 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1041 {
1042         mlx5e_free_xdpsq_db(sq);
1043         mlx5_wq_destroy(&sq->wq_ctrl);
1044 }
1045
1046 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1047 {
1048         kvfree(sq->db.ico_wqe);
1049 }
1050
1051 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1052 {
1053         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1054
1055         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1056                                                   sizeof(*sq->db.ico_wqe)),
1057                                        GFP_KERNEL, numa);
1058         if (!sq->db.ico_wqe)
1059                 return -ENOMEM;
1060
1061         return 0;
1062 }
1063
1064 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1065                              struct mlx5e_sq_param *param,
1066                              struct mlx5e_icosq *sq)
1067 {
1068         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1069         struct mlx5_core_dev *mdev = c->mdev;
1070         struct mlx5_wq_cyc *wq = &sq->wq;
1071         int err;
1072
1073         sq->channel   = c;
1074         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1075
1076         param->wq.db_numa_node = cpu_to_node(c->cpu);
1077         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1078         if (err)
1079                 return err;
1080         wq->db = &wq->db[MLX5_SND_DBR];
1081
1082         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1083         if (err)
1084                 goto err_sq_wq_destroy;
1085
1086         return 0;
1087
1088 err_sq_wq_destroy:
1089         mlx5_wq_destroy(&sq->wq_ctrl);
1090
1091         return err;
1092 }
1093
1094 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1095 {
1096         mlx5e_free_icosq_db(sq);
1097         mlx5_wq_destroy(&sq->wq_ctrl);
1098 }
1099
1100 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1101 {
1102         kvfree(sq->db.wqe_info);
1103         kvfree(sq->db.dma_fifo);
1104 }
1105
1106 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1107 {
1108         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1109         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1110
1111         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1112                                                    sizeof(*sq->db.dma_fifo)),
1113                                         GFP_KERNEL, numa);
1114         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1115                                                    sizeof(*sq->db.wqe_info)),
1116                                         GFP_KERNEL, numa);
1117         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1118                 mlx5e_free_txqsq_db(sq);
1119                 return -ENOMEM;
1120         }
1121
1122         sq->dma_fifo_mask = df_sz - 1;
1123
1124         return 0;
1125 }
1126
1127 static void mlx5e_sq_recover(struct work_struct *work);
1128 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1129                              int txq_ix,
1130                              struct mlx5e_params *params,
1131                              struct mlx5e_sq_param *param,
1132                              struct mlx5e_txqsq *sq,
1133                              int tc)
1134 {
1135         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1136         struct mlx5_core_dev *mdev = c->mdev;
1137         struct mlx5_wq_cyc *wq = &sq->wq;
1138         int err;
1139
1140         sq->pdev      = c->pdev;
1141         sq->tstamp    = c->tstamp;
1142         sq->clock     = &mdev->clock;
1143         sq->mkey_be   = c->mkey_be;
1144         sq->channel   = c;
1145         sq->txq_ix    = txq_ix;
1146         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1147         sq->min_inline_mode = params->tx_min_inline_mode;
1148         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1149         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1150         if (MLX5_IPSEC_DEV(c->priv->mdev))
1151                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1152         if (mlx5_accel_is_tls_device(c->priv->mdev))
1153                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1154
1155         param->wq.db_numa_node = cpu_to_node(c->cpu);
1156         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1157         if (err)
1158                 return err;
1159         wq->db    = &wq->db[MLX5_SND_DBR];
1160
1161         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1162         if (err)
1163                 goto err_sq_wq_destroy;
1164
1165         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1166         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1167
1168         return 0;
1169
1170 err_sq_wq_destroy:
1171         mlx5_wq_destroy(&sq->wq_ctrl);
1172
1173         return err;
1174 }
1175
1176 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1177 {
1178         mlx5e_free_txqsq_db(sq);
1179         mlx5_wq_destroy(&sq->wq_ctrl);
1180 }
1181
1182 struct mlx5e_create_sq_param {
1183         struct mlx5_wq_ctrl        *wq_ctrl;
1184         u32                         cqn;
1185         u32                         tisn;
1186         u8                          tis_lst_sz;
1187         u8                          min_inline_mode;
1188 };
1189
1190 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1191                            struct mlx5e_sq_param *param,
1192                            struct mlx5e_create_sq_param *csp,
1193                            u32 *sqn)
1194 {
1195         void *in;
1196         void *sqc;
1197         void *wq;
1198         int inlen;
1199         int err;
1200
1201         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1202                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1203         in = kvzalloc(inlen, GFP_KERNEL);
1204         if (!in)
1205                 return -ENOMEM;
1206
1207         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1208         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1209
1210         memcpy(sqc, param->sqc, sizeof(param->sqc));
1211         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1212         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1213         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1214
1215         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1216                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1217
1218         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1219         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1220
1221         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1222         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1223         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1224                                           MLX5_ADAPTER_PAGE_SHIFT);
1225         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1226
1227         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1228                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1229
1230         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1231
1232         kvfree(in);
1233
1234         return err;
1235 }
1236
1237 struct mlx5e_modify_sq_param {
1238         int curr_state;
1239         int next_state;
1240         bool rl_update;
1241         int rl_index;
1242 };
1243
1244 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1245                            struct mlx5e_modify_sq_param *p)
1246 {
1247         void *in;
1248         void *sqc;
1249         int inlen;
1250         int err;
1251
1252         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1253         in = kvzalloc(inlen, GFP_KERNEL);
1254         if (!in)
1255                 return -ENOMEM;
1256
1257         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1258
1259         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1260         MLX5_SET(sqc, sqc, state, p->next_state);
1261         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1262                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1263                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1264         }
1265
1266         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1267
1268         kvfree(in);
1269
1270         return err;
1271 }
1272
1273 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1274 {
1275         mlx5_core_destroy_sq(mdev, sqn);
1276 }
1277
1278 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1279                                struct mlx5e_sq_param *param,
1280                                struct mlx5e_create_sq_param *csp,
1281                                u32 *sqn)
1282 {
1283         struct mlx5e_modify_sq_param msp = {0};
1284         int err;
1285
1286         err = mlx5e_create_sq(mdev, param, csp, sqn);
1287         if (err)
1288                 return err;
1289
1290         msp.curr_state = MLX5_SQC_STATE_RST;
1291         msp.next_state = MLX5_SQC_STATE_RDY;
1292         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1293         if (err)
1294                 mlx5e_destroy_sq(mdev, *sqn);
1295
1296         return err;
1297 }
1298
1299 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1300                                 struct mlx5e_txqsq *sq, u32 rate);
1301
1302 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1303                             u32 tisn,
1304                             int txq_ix,
1305                             struct mlx5e_params *params,
1306                             struct mlx5e_sq_param *param,
1307                             struct mlx5e_txqsq *sq,
1308                             int tc)
1309 {
1310         struct mlx5e_create_sq_param csp = {};
1311         u32 tx_rate;
1312         int err;
1313
1314         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1315         if (err)
1316                 return err;
1317
1318         csp.tisn            = tisn;
1319         csp.tis_lst_sz      = 1;
1320         csp.cqn             = sq->cq.mcq.cqn;
1321         csp.wq_ctrl         = &sq->wq_ctrl;
1322         csp.min_inline_mode = sq->min_inline_mode;
1323         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1324         if (err)
1325                 goto err_free_txqsq;
1326
1327         tx_rate = c->priv->tx_rates[sq->txq_ix];
1328         if (tx_rate)
1329                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1330
1331         if (params->tx_dim_enabled)
1332                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1333
1334         return 0;
1335
1336 err_free_txqsq:
1337         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1338         mlx5e_free_txqsq(sq);
1339
1340         return err;
1341 }
1342
1343 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1344 {
1345         WARN_ONCE(sq->cc != sq->pc,
1346                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1347                   sq->sqn, sq->cc, sq->pc);
1348         sq->cc = 0;
1349         sq->dma_fifo_cc = 0;
1350         sq->pc = 0;
1351 }
1352
1353 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1354 {
1355         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1356         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1357         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1358         netdev_tx_reset_queue(sq->txq);
1359         netif_tx_start_queue(sq->txq);
1360 }
1361
1362 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1363 {
1364         __netif_tx_lock_bh(txq);
1365         netif_tx_stop_queue(txq);
1366         __netif_tx_unlock_bh(txq);
1367 }
1368
1369 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1370 {
1371         struct mlx5e_channel *c = sq->channel;
1372         struct mlx5_wq_cyc *wq = &sq->wq;
1373
1374         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1375         /* prevent netif_tx_wake_queue */
1376         napi_synchronize(&c->napi);
1377
1378         netif_tx_disable_queue(sq->txq);
1379
1380         /* last doorbell out, godspeed .. */
1381         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1382                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1383                 struct mlx5e_tx_wqe *nop;
1384
1385                 sq->db.wqe_info[pi].skb = NULL;
1386                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1387                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1388         }
1389 }
1390
1391 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1392 {
1393         struct mlx5e_channel *c = sq->channel;
1394         struct mlx5_core_dev *mdev = c->mdev;
1395         struct mlx5_rate_limit rl = {0};
1396
1397         cancel_work_sync(&sq->dim.work);
1398         mlx5e_destroy_sq(mdev, sq->sqn);
1399         if (sq->rate_limit) {
1400                 rl.rate = sq->rate_limit;
1401                 mlx5_rl_remove_rate(mdev, &rl);
1402         }
1403         mlx5e_free_txqsq_descs(sq);
1404         mlx5e_free_txqsq(sq);
1405 }
1406
1407 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1408 {
1409         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1410
1411         while (time_before(jiffies, exp_time)) {
1412                 if (sq->cc == sq->pc)
1413                         return 0;
1414
1415                 msleep(20);
1416         }
1417
1418         netdev_err(sq->channel->netdev,
1419                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1420                    sq->sqn, sq->cc, sq->pc);
1421
1422         return -ETIMEDOUT;
1423 }
1424
1425 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1426 {
1427         struct mlx5_core_dev *mdev = sq->channel->mdev;
1428         struct net_device *dev = sq->channel->netdev;
1429         struct mlx5e_modify_sq_param msp = {0};
1430         int err;
1431
1432         msp.curr_state = curr_state;
1433         msp.next_state = MLX5_SQC_STATE_RST;
1434
1435         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1436         if (err) {
1437                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1438                 return err;
1439         }
1440
1441         memset(&msp, 0, sizeof(msp));
1442         msp.curr_state = MLX5_SQC_STATE_RST;
1443         msp.next_state = MLX5_SQC_STATE_RDY;
1444
1445         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1446         if (err) {
1447                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1448                 return err;
1449         }
1450
1451         return 0;
1452 }
1453
1454 static void mlx5e_sq_recover(struct work_struct *work)
1455 {
1456         struct mlx5e_txqsq_recover *recover =
1457                 container_of(work, struct mlx5e_txqsq_recover,
1458                              recover_work);
1459         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1460                                               recover);
1461         struct mlx5_core_dev *mdev = sq->channel->mdev;
1462         struct net_device *dev = sq->channel->netdev;
1463         u8 state;
1464         int err;
1465
1466         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1467         if (err) {
1468                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1469                            sq->sqn, err);
1470                 return;
1471         }
1472
1473         if (state != MLX5_RQC_STATE_ERR) {
1474                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1475                 return;
1476         }
1477
1478         netif_tx_disable_queue(sq->txq);
1479
1480         if (mlx5e_wait_for_sq_flush(sq))
1481                 return;
1482
1483         /* If the interval between two consecutive recovers per SQ is too
1484          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1485          * If we reached this state, there is probably a bug that needs to be
1486          * fixed. let's keep the queue close and let tx timeout cleanup.
1487          */
1488         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1489             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1490                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1491                            sq->sqn);
1492                 return;
1493         }
1494
1495         /* At this point, no new packets will arrive from the stack as TXQ is
1496          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1497          * pending WQEs.  SQ can safely reset the SQ.
1498          */
1499         if (mlx5e_sq_to_ready(sq, state))
1500                 return;
1501
1502         mlx5e_reset_txqsq_cc_pc(sq);
1503         sq->stats->recover++;
1504         recover->last_recover = jiffies;
1505         mlx5e_activate_txqsq(sq);
1506 }
1507
1508 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1509                             struct mlx5e_params *params,
1510                             struct mlx5e_sq_param *param,
1511                             struct mlx5e_icosq *sq)
1512 {
1513         struct mlx5e_create_sq_param csp = {};
1514         int err;
1515
1516         err = mlx5e_alloc_icosq(c, param, sq);
1517         if (err)
1518                 return err;
1519
1520         csp.cqn             = sq->cq.mcq.cqn;
1521         csp.wq_ctrl         = &sq->wq_ctrl;
1522         csp.min_inline_mode = params->tx_min_inline_mode;
1523         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1524         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1525         if (err)
1526                 goto err_free_icosq;
1527
1528         return 0;
1529
1530 err_free_icosq:
1531         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532         mlx5e_free_icosq(sq);
1533
1534         return err;
1535 }
1536
1537 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1538 {
1539         struct mlx5e_channel *c = sq->channel;
1540
1541         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1542         napi_synchronize(&c->napi);
1543
1544         mlx5e_destroy_sq(c->mdev, sq->sqn);
1545         mlx5e_free_icosq(sq);
1546 }
1547
1548 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1549                             struct mlx5e_params *params,
1550                             struct mlx5e_sq_param *param,
1551                             struct mlx5e_xdpsq *sq,
1552                             bool is_redirect)
1553 {
1554         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1555         struct mlx5e_create_sq_param csp = {};
1556         unsigned int inline_hdr_sz = 0;
1557         int err;
1558         int i;
1559
1560         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1561         if (err)
1562                 return err;
1563
1564         csp.tis_lst_sz      = 1;
1565         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1566         csp.cqn             = sq->cq.mcq.cqn;
1567         csp.wq_ctrl         = &sq->wq_ctrl;
1568         csp.min_inline_mode = sq->min_inline_mode;
1569         if (is_redirect)
1570                 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1571         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1572         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1573         if (err)
1574                 goto err_free_xdpsq;
1575
1576         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1577                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1578                 ds_cnt++;
1579         }
1580
1581         /* Pre initialize fixed WQE fields */
1582         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1583                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1584                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1585                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1586                 struct mlx5_wqe_data_seg *dseg;
1587
1588                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1589                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1590
1591                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1592                 dseg->lkey = sq->mkey_be;
1593         }
1594
1595         return 0;
1596
1597 err_free_xdpsq:
1598         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1599         mlx5e_free_xdpsq(sq);
1600
1601         return err;
1602 }
1603
1604 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1605 {
1606         struct mlx5e_channel *c = sq->channel;
1607
1608         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1609         napi_synchronize(&c->napi);
1610
1611         mlx5e_destroy_sq(c->mdev, sq->sqn);
1612         mlx5e_free_xdpsq_descs(sq);
1613         mlx5e_free_xdpsq(sq);
1614 }
1615
1616 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1617                                  struct mlx5e_cq_param *param,
1618                                  struct mlx5e_cq *cq)
1619 {
1620         struct mlx5_core_cq *mcq = &cq->mcq;
1621         int eqn_not_used;
1622         unsigned int irqn;
1623         int err;
1624         u32 i;
1625
1626         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1627         if (err)
1628                 return err;
1629
1630         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1631                                &cq->wq_ctrl);
1632         if (err)
1633                 return err;
1634
1635         mcq->cqe_sz     = 64;
1636         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1637         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1638         *mcq->set_ci_db = 0;
1639         *mcq->arm_db    = 0;
1640         mcq->vector     = param->eq_ix;
1641         mcq->comp       = mlx5e_completion_event;
1642         mcq->event      = mlx5e_cq_error_event;
1643         mcq->irqn       = irqn;
1644
1645         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1646                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1647
1648                 cqe->op_own = 0xf1;
1649         }
1650
1651         cq->mdev = mdev;
1652
1653         return 0;
1654 }
1655
1656 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1657                           struct mlx5e_cq_param *param,
1658                           struct mlx5e_cq *cq)
1659 {
1660         struct mlx5_core_dev *mdev = c->priv->mdev;
1661         int err;
1662
1663         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1664         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1665         param->eq_ix   = c->ix;
1666
1667         err = mlx5e_alloc_cq_common(mdev, param, cq);
1668
1669         cq->napi    = &c->napi;
1670         cq->channel = c;
1671
1672         return err;
1673 }
1674
1675 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1676 {
1677         mlx5_wq_destroy(&cq->wq_ctrl);
1678 }
1679
1680 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1681 {
1682         struct mlx5_core_dev *mdev = cq->mdev;
1683         struct mlx5_core_cq *mcq = &cq->mcq;
1684
1685         void *in;
1686         void *cqc;
1687         int inlen;
1688         unsigned int irqn_not_used;
1689         int eqn;
1690         int err;
1691
1692         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1693         if (err)
1694                 return err;
1695
1696         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1697                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1698         in = kvzalloc(inlen, GFP_KERNEL);
1699         if (!in)
1700                 return -ENOMEM;
1701
1702         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1703
1704         memcpy(cqc, param->cqc, sizeof(param->cqc));
1705
1706         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1707                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1708
1709         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1710         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1711         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1712         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1713                                             MLX5_ADAPTER_PAGE_SHIFT);
1714         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1715
1716         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1717
1718         kvfree(in);
1719
1720         if (err)
1721                 return err;
1722
1723         mlx5e_cq_arm(cq);
1724
1725         return 0;
1726 }
1727
1728 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1729 {
1730         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1731 }
1732
1733 static int mlx5e_open_cq(struct mlx5e_channel *c,
1734                          struct net_dim_cq_moder moder,
1735                          struct mlx5e_cq_param *param,
1736                          struct mlx5e_cq *cq)
1737 {
1738         struct mlx5_core_dev *mdev = c->mdev;
1739         int err;
1740
1741         err = mlx5e_alloc_cq(c, param, cq);
1742         if (err)
1743                 return err;
1744
1745         err = mlx5e_create_cq(cq, param);
1746         if (err)
1747                 goto err_free_cq;
1748
1749         if (MLX5_CAP_GEN(mdev, cq_moderation))
1750                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1751         return 0;
1752
1753 err_free_cq:
1754         mlx5e_free_cq(cq);
1755
1756         return err;
1757 }
1758
1759 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1760 {
1761         mlx5e_destroy_cq(cq);
1762         mlx5e_free_cq(cq);
1763 }
1764
1765 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1766 {
1767         return cpumask_first(priv->mdev->priv.irq_info[ix + MLX5_EQ_VEC_COMP_BASE].mask);
1768 }
1769
1770 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1771                              struct mlx5e_params *params,
1772                              struct mlx5e_channel_param *cparam)
1773 {
1774         int err;
1775         int tc;
1776
1777         for (tc = 0; tc < c->num_tc; tc++) {
1778                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1779                                     &cparam->tx_cq, &c->sq[tc].cq);
1780                 if (err)
1781                         goto err_close_tx_cqs;
1782         }
1783
1784         return 0;
1785
1786 err_close_tx_cqs:
1787         for (tc--; tc >= 0; tc--)
1788                 mlx5e_close_cq(&c->sq[tc].cq);
1789
1790         return err;
1791 }
1792
1793 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1794 {
1795         int tc;
1796
1797         for (tc = 0; tc < c->num_tc; tc++)
1798                 mlx5e_close_cq(&c->sq[tc].cq);
1799 }
1800
1801 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1802                           struct mlx5e_params *params,
1803                           struct mlx5e_channel_param *cparam)
1804 {
1805         struct mlx5e_priv *priv = c->priv;
1806         int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1807
1808         for (tc = 0; tc < params->num_tc; tc++) {
1809                 int txq_ix = c->ix + tc * max_nch;
1810
1811                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1812                                        params, &cparam->sq, &c->sq[tc], tc);
1813                 if (err)
1814                         goto err_close_sqs;
1815         }
1816
1817         return 0;
1818
1819 err_close_sqs:
1820         for (tc--; tc >= 0; tc--)
1821                 mlx5e_close_txqsq(&c->sq[tc]);
1822
1823         return err;
1824 }
1825
1826 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1827 {
1828         int tc;
1829
1830         for (tc = 0; tc < c->num_tc; tc++)
1831                 mlx5e_close_txqsq(&c->sq[tc]);
1832 }
1833
1834 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1835                                 struct mlx5e_txqsq *sq, u32 rate)
1836 {
1837         struct mlx5e_priv *priv = netdev_priv(dev);
1838         struct mlx5_core_dev *mdev = priv->mdev;
1839         struct mlx5e_modify_sq_param msp = {0};
1840         struct mlx5_rate_limit rl = {0};
1841         u16 rl_index = 0;
1842         int err;
1843
1844         if (rate == sq->rate_limit)
1845                 /* nothing to do */
1846                 return 0;
1847
1848         if (sq->rate_limit) {
1849                 rl.rate = sq->rate_limit;
1850                 /* remove current rl index to free space to next ones */
1851                 mlx5_rl_remove_rate(mdev, &rl);
1852         }
1853
1854         sq->rate_limit = 0;
1855
1856         if (rate) {
1857                 rl.rate = rate;
1858                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1859                 if (err) {
1860                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1861                                    rate, err);
1862                         return err;
1863                 }
1864         }
1865
1866         msp.curr_state = MLX5_SQC_STATE_RDY;
1867         msp.next_state = MLX5_SQC_STATE_RDY;
1868         msp.rl_index   = rl_index;
1869         msp.rl_update  = true;
1870         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1871         if (err) {
1872                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1873                            rate, err);
1874                 /* remove the rate from the table */
1875                 if (rate)
1876                         mlx5_rl_remove_rate(mdev, &rl);
1877                 return err;
1878         }
1879
1880         sq->rate_limit = rate;
1881         return 0;
1882 }
1883
1884 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1885 {
1886         struct mlx5e_priv *priv = netdev_priv(dev);
1887         struct mlx5_core_dev *mdev = priv->mdev;
1888         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1889         int err = 0;
1890
1891         if (!mlx5_rl_is_supported(mdev)) {
1892                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1893                 return -EINVAL;
1894         }
1895
1896         /* rate is given in Mb/sec, HW config is in Kb/sec */
1897         rate = rate << 10;
1898
1899         /* Check whether rate in valid range, 0 is always valid */
1900         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1901                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1902                 return -ERANGE;
1903         }
1904
1905         mutex_lock(&priv->state_lock);
1906         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1907                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1908         if (!err)
1909                 priv->tx_rates[index] = rate;
1910         mutex_unlock(&priv->state_lock);
1911
1912         return err;
1913 }
1914
1915 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1916                               struct mlx5e_params *params,
1917                               struct mlx5e_channel_param *cparam,
1918                               struct mlx5e_channel **cp)
1919 {
1920         struct net_dim_cq_moder icocq_moder = {0, 0};
1921         struct net_device *netdev = priv->netdev;
1922         int cpu = mlx5e_get_cpu(priv, ix);
1923         struct mlx5e_channel *c;
1924         unsigned int irq;
1925         int err;
1926         int eqn;
1927
1928         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1929         if (err)
1930                 return err;
1931
1932         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1933         if (!c)
1934                 return -ENOMEM;
1935
1936         c->priv     = priv;
1937         c->mdev     = priv->mdev;
1938         c->tstamp   = &priv->tstamp;
1939         c->ix       = ix;
1940         c->cpu      = cpu;
1941         c->pdev     = &priv->mdev->pdev->dev;
1942         c->netdev   = priv->netdev;
1943         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1944         c->num_tc   = params->num_tc;
1945         c->xdp      = !!params->xdp_prog;
1946         c->stats    = &priv->channel_stats[ix].ch;
1947
1948         c->irq_desc = irq_to_desc(irq);
1949
1950         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1951
1952         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1953         if (err)
1954                 goto err_napi_del;
1955
1956         err = mlx5e_open_tx_cqs(c, params, cparam);
1957         if (err)
1958                 goto err_close_icosq_cq;
1959
1960         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1961         if (err)
1962                 goto err_close_tx_cqs;
1963
1964         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1965         if (err)
1966                 goto err_close_xdp_tx_cqs;
1967
1968         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1969         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1970                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1971         if (err)
1972                 goto err_close_rx_cq;
1973
1974         napi_enable(&c->napi);
1975
1976         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1977         if (err)
1978                 goto err_disable_napi;
1979
1980         err = mlx5e_open_sqs(c, params, cparam);
1981         if (err)
1982                 goto err_close_icosq;
1983
1984         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1985         if (err)
1986                 goto err_close_sqs;
1987
1988         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1989         if (err)
1990                 goto err_close_xdp_sq;
1991
1992         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1993         if (err)
1994                 goto err_close_rq;
1995
1996         *cp = c;
1997
1998         return 0;
1999
2000 err_close_rq:
2001         mlx5e_close_rq(&c->rq);
2002
2003 err_close_xdp_sq:
2004         if (c->xdp)
2005                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2006
2007 err_close_sqs:
2008         mlx5e_close_sqs(c);
2009
2010 err_close_icosq:
2011         mlx5e_close_icosq(&c->icosq);
2012
2013 err_disable_napi:
2014         napi_disable(&c->napi);
2015         if (c->xdp)
2016                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2017
2018 err_close_rx_cq:
2019         mlx5e_close_cq(&c->rq.cq);
2020
2021 err_close_xdp_tx_cqs:
2022         mlx5e_close_cq(&c->xdpsq.cq);
2023
2024 err_close_tx_cqs:
2025         mlx5e_close_tx_cqs(c);
2026
2027 err_close_icosq_cq:
2028         mlx5e_close_cq(&c->icosq.cq);
2029
2030 err_napi_del:
2031         netif_napi_del(&c->napi);
2032         kvfree(c);
2033
2034         return err;
2035 }
2036
2037 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2038 {
2039         int tc;
2040
2041         for (tc = 0; tc < c->num_tc; tc++)
2042                 mlx5e_activate_txqsq(&c->sq[tc]);
2043         mlx5e_activate_rq(&c->rq);
2044         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2045 }
2046
2047 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2048 {
2049         int tc;
2050
2051         mlx5e_deactivate_rq(&c->rq);
2052         for (tc = 0; tc < c->num_tc; tc++)
2053                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2054 }
2055
2056 static void mlx5e_close_channel(struct mlx5e_channel *c)
2057 {
2058         mlx5e_close_xdpsq(&c->xdpsq);
2059         mlx5e_close_rq(&c->rq);
2060         if (c->xdp)
2061                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2062         mlx5e_close_sqs(c);
2063         mlx5e_close_icosq(&c->icosq);
2064         napi_disable(&c->napi);
2065         if (c->xdp)
2066                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2067         mlx5e_close_cq(&c->rq.cq);
2068         mlx5e_close_cq(&c->xdpsq.cq);
2069         mlx5e_close_tx_cqs(c);
2070         mlx5e_close_cq(&c->icosq.cq);
2071         netif_napi_del(&c->napi);
2072
2073         kvfree(c);
2074 }
2075
2076 #define DEFAULT_FRAG_SIZE (2048)
2077
2078 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2079                                       struct mlx5e_params *params,
2080                                       struct mlx5e_rq_frags_info *info)
2081 {
2082         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2083         int frag_size_max = DEFAULT_FRAG_SIZE;
2084         u32 buf_size = 0;
2085         int i;
2086
2087 #ifdef CONFIG_MLX5_EN_IPSEC
2088         if (MLX5_IPSEC_DEV(mdev))
2089                 byte_count += MLX5E_METADATA_ETHER_LEN;
2090 #endif
2091
2092         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2093                 int frag_stride;
2094
2095                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2096                 frag_stride = roundup_pow_of_two(frag_stride);
2097
2098                 info->arr[0].frag_size = byte_count;
2099                 info->arr[0].frag_stride = frag_stride;
2100                 info->num_frags = 1;
2101                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2102                 goto out;
2103         }
2104
2105         if (byte_count > PAGE_SIZE +
2106             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2107                 frag_size_max = PAGE_SIZE;
2108
2109         i = 0;
2110         while (buf_size < byte_count) {
2111                 int frag_size = byte_count - buf_size;
2112
2113                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2114                         frag_size = min(frag_size, frag_size_max);
2115
2116                 info->arr[i].frag_size = frag_size;
2117                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2118
2119                 buf_size += frag_size;
2120                 i++;
2121         }
2122         info->num_frags = i;
2123         /* number of different wqes sharing a page */
2124         info->wqe_bulk = 1 + (info->num_frags % 2);
2125
2126 out:
2127         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2128         info->log_num_frags = order_base_2(info->num_frags);
2129 }
2130
2131 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2132 {
2133         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2134
2135         switch (wq_type) {
2136         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2137                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2138                 break;
2139         default: /* MLX5_WQ_TYPE_CYCLIC */
2140                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2141         }
2142
2143         return order_base_2(sz);
2144 }
2145
2146 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2147                                  struct mlx5e_params *params,
2148                                  struct mlx5e_rq_param *param)
2149 {
2150         struct mlx5_core_dev *mdev = priv->mdev;
2151         void *rqc = param->rqc;
2152         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2153         int ndsegs = 1;
2154
2155         switch (params->rq_wq_type) {
2156         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2157                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2158                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2159                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2160                 MLX5_SET(wq, wq, log_wqe_stride_size,
2161                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2162                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2163                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2164                 break;
2165         default: /* MLX5_WQ_TYPE_CYCLIC */
2166                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2167                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2168                 ndsegs = param->frags_info.num_frags;
2169         }
2170
2171         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2172         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2173         MLX5_SET(wq, wq, log_wq_stride,
2174                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2175         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2176         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2177         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2178         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2179
2180         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2181 }
2182
2183 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2184                                       struct mlx5e_rq_param *param)
2185 {
2186         struct mlx5_core_dev *mdev = priv->mdev;
2187         void *rqc = param->rqc;
2188         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2189
2190         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2191         MLX5_SET(wq, wq, log_wq_stride,
2192                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2193         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2194
2195         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2196 }
2197
2198 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2199                                         struct mlx5e_sq_param *param)
2200 {
2201         void *sqc = param->sqc;
2202         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2203
2204         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2205         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2206
2207         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2208 }
2209
2210 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2211                                  struct mlx5e_params *params,
2212                                  struct mlx5e_sq_param *param)
2213 {
2214         void *sqc = param->sqc;
2215         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2216
2217         mlx5e_build_sq_param_common(priv, param);
2218         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2219         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2220 }
2221
2222 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2223                                         struct mlx5e_cq_param *param)
2224 {
2225         void *cqc = param->cqc;
2226
2227         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2228 }
2229
2230 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2231                                     struct mlx5e_params *params,
2232                                     struct mlx5e_cq_param *param)
2233 {
2234         struct mlx5_core_dev *mdev = priv->mdev;
2235         void *cqc = param->cqc;
2236         u8 log_cq_size;
2237
2238         switch (params->rq_wq_type) {
2239         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2240                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2241                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2242                 break;
2243         default: /* MLX5_WQ_TYPE_CYCLIC */
2244                 log_cq_size = params->log_rq_mtu_frames;
2245         }
2246
2247         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2248         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2249                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2250                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2251         }
2252
2253         mlx5e_build_common_cq_param(priv, param);
2254         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2255 }
2256
2257 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2258                                     struct mlx5e_params *params,
2259                                     struct mlx5e_cq_param *param)
2260 {
2261         void *cqc = param->cqc;
2262
2263         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2264
2265         mlx5e_build_common_cq_param(priv, param);
2266         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2267 }
2268
2269 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2270                                      u8 log_wq_size,
2271                                      struct mlx5e_cq_param *param)
2272 {
2273         void *cqc = param->cqc;
2274
2275         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2276
2277         mlx5e_build_common_cq_param(priv, param);
2278
2279         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2280 }
2281
2282 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2283                                     u8 log_wq_size,
2284                                     struct mlx5e_sq_param *param)
2285 {
2286         void *sqc = param->sqc;
2287         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2288
2289         mlx5e_build_sq_param_common(priv, param);
2290
2291         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2292         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2293 }
2294
2295 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2296                                     struct mlx5e_params *params,
2297                                     struct mlx5e_sq_param *param)
2298 {
2299         void *sqc = param->sqc;
2300         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2301
2302         mlx5e_build_sq_param_common(priv, param);
2303         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2304 }
2305
2306 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2307                                       struct mlx5e_params *params,
2308                                       struct mlx5e_channel_param *cparam)
2309 {
2310         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2311
2312         mlx5e_build_rq_param(priv, params, &cparam->rq);
2313         mlx5e_build_sq_param(priv, params, &cparam->sq);
2314         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2315         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2316         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2317         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2318         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2319 }
2320
2321 int mlx5e_open_channels(struct mlx5e_priv *priv,
2322                         struct mlx5e_channels *chs)
2323 {
2324         struct mlx5e_channel_param *cparam;
2325         int err = -ENOMEM;
2326         int i;
2327
2328         chs->num = chs->params.num_channels;
2329
2330         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2331         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2332         if (!chs->c || !cparam)
2333                 goto err_free;
2334
2335         mlx5e_build_channel_param(priv, &chs->params, cparam);
2336         for (i = 0; i < chs->num; i++) {
2337                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2338                 if (err)
2339                         goto err_close_channels;
2340         }
2341
2342         kvfree(cparam);
2343         return 0;
2344
2345 err_close_channels:
2346         for (i--; i >= 0; i--)
2347                 mlx5e_close_channel(chs->c[i]);
2348
2349 err_free:
2350         kfree(chs->c);
2351         kvfree(cparam);
2352         chs->num = 0;
2353         return err;
2354 }
2355
2356 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2357 {
2358         int i;
2359
2360         for (i = 0; i < chs->num; i++)
2361                 mlx5e_activate_channel(chs->c[i]);
2362 }
2363
2364 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2365 {
2366         int err = 0;
2367         int i;
2368
2369         for (i = 0; i < chs->num; i++)
2370                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2371                                                   err ? 0 : 20000);
2372
2373         return err ? -ETIMEDOUT : 0;
2374 }
2375
2376 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2377 {
2378         int i;
2379
2380         for (i = 0; i < chs->num; i++)
2381                 mlx5e_deactivate_channel(chs->c[i]);
2382 }
2383
2384 void mlx5e_close_channels(struct mlx5e_channels *chs)
2385 {
2386         int i;
2387
2388         for (i = 0; i < chs->num; i++)
2389                 mlx5e_close_channel(chs->c[i]);
2390
2391         kfree(chs->c);
2392         chs->num = 0;
2393 }
2394
2395 static int
2396 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2397 {
2398         struct mlx5_core_dev *mdev = priv->mdev;
2399         void *rqtc;
2400         int inlen;
2401         int err;
2402         u32 *in;
2403         int i;
2404
2405         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2406         in = kvzalloc(inlen, GFP_KERNEL);
2407         if (!in)
2408                 return -ENOMEM;
2409
2410         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2411
2412         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2413         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2414
2415         for (i = 0; i < sz; i++)
2416                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2417
2418         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2419         if (!err)
2420                 rqt->enabled = true;
2421
2422         kvfree(in);
2423         return err;
2424 }
2425
2426 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2427 {
2428         rqt->enabled = false;
2429         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2430 }
2431
2432 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2433 {
2434         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2435         int err;
2436
2437         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2438         if (err)
2439                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2440         return err;
2441 }
2442
2443 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2444 {
2445         struct mlx5e_rqt *rqt;
2446         int err;
2447         int ix;
2448
2449         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2450                 rqt = &priv->direct_tir[ix].rqt;
2451                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2452                 if (err)
2453                         goto err_destroy_rqts;
2454         }
2455
2456         return 0;
2457
2458 err_destroy_rqts:
2459         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2460         for (ix--; ix >= 0; ix--)
2461                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2462
2463         return err;
2464 }
2465
2466 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2467 {
2468         int i;
2469
2470         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2471                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2472 }
2473
2474 static int mlx5e_rx_hash_fn(int hfunc)
2475 {
2476         return (hfunc == ETH_RSS_HASH_TOP) ?
2477                MLX5_RX_HASH_FN_TOEPLITZ :
2478                MLX5_RX_HASH_FN_INVERTED_XOR8;
2479 }
2480
2481 int mlx5e_bits_invert(unsigned long a, int size)
2482 {
2483         int inv = 0;
2484         int i;
2485
2486         for (i = 0; i < size; i++)
2487                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2488
2489         return inv;
2490 }
2491
2492 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2493                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2494 {
2495         int i;
2496
2497         for (i = 0; i < sz; i++) {
2498                 u32 rqn;
2499
2500                 if (rrp.is_rss) {
2501                         int ix = i;
2502
2503                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2504                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2505
2506                         ix = priv->channels.params.indirection_rqt[ix];
2507                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2508                 } else {
2509                         rqn = rrp.rqn;
2510                 }
2511                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2512         }
2513 }
2514
2515 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2516                        struct mlx5e_redirect_rqt_param rrp)
2517 {
2518         struct mlx5_core_dev *mdev = priv->mdev;
2519         void *rqtc;
2520         int inlen;
2521         u32 *in;
2522         int err;
2523
2524         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2525         in = kvzalloc(inlen, GFP_KERNEL);
2526         if (!in)
2527                 return -ENOMEM;
2528
2529         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2530
2531         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2532         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2533         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2534         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2535
2536         kvfree(in);
2537         return err;
2538 }
2539
2540 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2541                                 struct mlx5e_redirect_rqt_param rrp)
2542 {
2543         if (!rrp.is_rss)
2544                 return rrp.rqn;
2545
2546         if (ix >= rrp.rss.channels->num)
2547                 return priv->drop_rq.rqn;
2548
2549         return rrp.rss.channels->c[ix]->rq.rqn;
2550 }
2551
2552 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2553                                 struct mlx5e_redirect_rqt_param rrp)
2554 {
2555         u32 rqtn;
2556         int ix;
2557
2558         if (priv->indir_rqt.enabled) {
2559                 /* RSS RQ table */
2560                 rqtn = priv->indir_rqt.rqtn;
2561                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2562         }
2563
2564         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2565                 struct mlx5e_redirect_rqt_param direct_rrp = {
2566                         .is_rss = false,
2567                         {
2568                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2569                         },
2570                 };
2571
2572                 /* Direct RQ Tables */
2573                 if (!priv->direct_tir[ix].rqt.enabled)
2574                         continue;
2575
2576                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2577                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2578         }
2579 }
2580
2581 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2582                                             struct mlx5e_channels *chs)
2583 {
2584         struct mlx5e_redirect_rqt_param rrp = {
2585                 .is_rss        = true,
2586                 {
2587                         .rss = {
2588                                 .channels  = chs,
2589                                 .hfunc     = chs->params.rss_hfunc,
2590                         }
2591                 },
2592         };
2593
2594         mlx5e_redirect_rqts(priv, rrp);
2595 }
2596
2597 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2598 {
2599         struct mlx5e_redirect_rqt_param drop_rrp = {
2600                 .is_rss = false,
2601                 {
2602                         .rqn = priv->drop_rq.rqn,
2603                 },
2604         };
2605
2606         mlx5e_redirect_rqts(priv, drop_rrp);
2607 }
2608
2609 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2610 {
2611         if (!params->lro_en)
2612                 return;
2613
2614 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2615
2616         MLX5_SET(tirc, tirc, lro_enable_mask,
2617                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2618                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2619         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2620                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2621         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2622 }
2623
2624 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2625                                     enum mlx5e_traffic_types tt,
2626                                     void *tirc, bool inner)
2627 {
2628         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2629                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2630
2631 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2632                                  MLX5_HASH_FIELD_SEL_DST_IP)
2633
2634 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2635                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2636                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2637                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2638
2639 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2640                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2641                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2642
2643         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2644         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2645                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2646                                              rx_hash_toeplitz_key);
2647                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2648                                                rx_hash_toeplitz_key);
2649
2650                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2651                 memcpy(rss_key, params->toeplitz_hash_key, len);
2652         }
2653
2654         switch (tt) {
2655         case MLX5E_TT_IPV4_TCP:
2656                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2657                          MLX5_L3_PROT_TYPE_IPV4);
2658                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2659                          MLX5_L4_PROT_TYPE_TCP);
2660                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2661                          MLX5_HASH_IP_L4PORTS);
2662                 break;
2663
2664         case MLX5E_TT_IPV6_TCP:
2665                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2666                          MLX5_L3_PROT_TYPE_IPV6);
2667                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2668                          MLX5_L4_PROT_TYPE_TCP);
2669                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2670                          MLX5_HASH_IP_L4PORTS);
2671                 break;
2672
2673         case MLX5E_TT_IPV4_UDP:
2674                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2675                          MLX5_L3_PROT_TYPE_IPV4);
2676                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2677                          MLX5_L4_PROT_TYPE_UDP);
2678                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2679                          MLX5_HASH_IP_L4PORTS);
2680                 break;
2681
2682         case MLX5E_TT_IPV6_UDP:
2683                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2684                          MLX5_L3_PROT_TYPE_IPV6);
2685                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2686                          MLX5_L4_PROT_TYPE_UDP);
2687                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688                          MLX5_HASH_IP_L4PORTS);
2689                 break;
2690
2691         case MLX5E_TT_IPV4_IPSEC_AH:
2692                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2693                          MLX5_L3_PROT_TYPE_IPV4);
2694                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695                          MLX5_HASH_IP_IPSEC_SPI);
2696                 break;
2697
2698         case MLX5E_TT_IPV6_IPSEC_AH:
2699                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700                          MLX5_L3_PROT_TYPE_IPV6);
2701                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2702                          MLX5_HASH_IP_IPSEC_SPI);
2703                 break;
2704
2705         case MLX5E_TT_IPV4_IPSEC_ESP:
2706                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2707                          MLX5_L3_PROT_TYPE_IPV4);
2708                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2709                          MLX5_HASH_IP_IPSEC_SPI);
2710                 break;
2711
2712         case MLX5E_TT_IPV6_IPSEC_ESP:
2713                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2714                          MLX5_L3_PROT_TYPE_IPV6);
2715                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2716                          MLX5_HASH_IP_IPSEC_SPI);
2717                 break;
2718
2719         case MLX5E_TT_IPV4:
2720                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2721                          MLX5_L3_PROT_TYPE_IPV4);
2722                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2723                          MLX5_HASH_IP);
2724                 break;
2725
2726         case MLX5E_TT_IPV6:
2727                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2728                          MLX5_L3_PROT_TYPE_IPV6);
2729                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2730                          MLX5_HASH_IP);
2731                 break;
2732         default:
2733                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2734         }
2735 }
2736
2737 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2738 {
2739         struct mlx5_core_dev *mdev = priv->mdev;
2740
2741         void *in;
2742         void *tirc;
2743         int inlen;
2744         int err;
2745         int tt;
2746         int ix;
2747
2748         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2749         in = kvzalloc(inlen, GFP_KERNEL);
2750         if (!in)
2751                 return -ENOMEM;
2752
2753         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2754         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2755
2756         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2757
2758         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2759                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2760                                            inlen);
2761                 if (err)
2762                         goto free_in;
2763         }
2764
2765         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2766                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2767                                            in, inlen);
2768                 if (err)
2769                         goto free_in;
2770         }
2771
2772 free_in:
2773         kvfree(in);
2774
2775         return err;
2776 }
2777
2778 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2779                                             enum mlx5e_traffic_types tt,
2780                                             u32 *tirc)
2781 {
2782         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2783
2784         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2785
2786         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2787         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2788         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2789
2790         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2791 }
2792
2793 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2794                          struct mlx5e_params *params, u16 mtu)
2795 {
2796         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2797         int err;
2798
2799         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2800         if (err)
2801                 return err;
2802
2803         /* Update vport context MTU */
2804         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2805         return 0;
2806 }
2807
2808 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2809                             struct mlx5e_params *params, u16 *mtu)
2810 {
2811         u16 hw_mtu = 0;
2812         int err;
2813
2814         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2815         if (err || !hw_mtu) /* fallback to port oper mtu */
2816                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2817
2818         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2819 }
2820
2821 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2822 {
2823         struct mlx5e_params *params = &priv->channels.params;
2824         struct net_device *netdev = priv->netdev;
2825         struct mlx5_core_dev *mdev = priv->mdev;
2826         u16 mtu;
2827         int err;
2828
2829         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2830         if (err)
2831                 return err;
2832
2833         mlx5e_query_mtu(mdev, params, &mtu);
2834         if (mtu != params->sw_mtu)
2835                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2836                             __func__, mtu, params->sw_mtu);
2837
2838         params->sw_mtu = mtu;
2839         return 0;
2840 }
2841
2842 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2843 {
2844         struct mlx5e_priv *priv = netdev_priv(netdev);
2845         int nch = priv->channels.params.num_channels;
2846         int ntc = priv->channels.params.num_tc;
2847         int tc;
2848
2849         netdev_reset_tc(netdev);
2850
2851         if (ntc == 1)
2852                 return;
2853
2854         netdev_set_num_tc(netdev, ntc);
2855
2856         /* Map netdev TCs to offset 0
2857          * We have our own UP to TXQ mapping for QoS
2858          */
2859         for (tc = 0; tc < ntc; tc++)
2860                 netdev_set_tc_queue(netdev, tc, nch, 0);
2861 }
2862
2863 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2864 {
2865         int max_nch = priv->profile->max_nch(priv->mdev);
2866         int i, tc;
2867
2868         for (i = 0; i < max_nch; i++)
2869                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2870                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2871 }
2872
2873 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2874 {
2875         struct mlx5e_channel *c;
2876         struct mlx5e_txqsq *sq;
2877         int i, tc;
2878
2879         for (i = 0; i < priv->channels.num; i++) {
2880                 c = priv->channels.c[i];
2881                 for (tc = 0; tc < c->num_tc; tc++) {
2882                         sq = &c->sq[tc];
2883                         priv->txq2sq[sq->txq_ix] = sq;
2884                 }
2885         }
2886 }
2887
2888 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2889 {
2890         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2891         struct net_device *netdev = priv->netdev;
2892
2893         mlx5e_netdev_set_tcs(netdev);
2894         netif_set_real_num_tx_queues(netdev, num_txqs);
2895         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2896
2897         mlx5e_build_tx2sq_maps(priv);
2898         mlx5e_activate_channels(&priv->channels);
2899         mlx5e_xdp_tx_enable(priv);
2900         netif_tx_start_all_queues(priv->netdev);
2901
2902         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2903                 mlx5e_add_sqs_fwd_rules(priv);
2904
2905         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2906         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2907 }
2908
2909 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2910 {
2911         mlx5e_redirect_rqts_to_drop(priv);
2912
2913         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2914                 mlx5e_remove_sqs_fwd_rules(priv);
2915
2916         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2917          * polling for inactive tx queues.
2918          */
2919         netif_tx_stop_all_queues(priv->netdev);
2920         netif_tx_disable(priv->netdev);
2921         mlx5e_xdp_tx_disable(priv);
2922         mlx5e_deactivate_channels(&priv->channels);
2923 }
2924
2925 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2926                                 struct mlx5e_channels *new_chs,
2927                                 mlx5e_fp_hw_modify hw_modify)
2928 {
2929         struct net_device *netdev = priv->netdev;
2930         int new_num_txqs;
2931         int carrier_ok;
2932         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2933
2934         carrier_ok = netif_carrier_ok(netdev);
2935         netif_carrier_off(netdev);
2936
2937         if (new_num_txqs < netdev->real_num_tx_queues)
2938                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2939
2940         mlx5e_deactivate_priv_channels(priv);
2941         mlx5e_close_channels(&priv->channels);
2942
2943         priv->channels = *new_chs;
2944
2945         /* New channels are ready to roll, modify HW settings if needed */
2946         if (hw_modify)
2947                 hw_modify(priv);
2948
2949         mlx5e_refresh_tirs(priv, false);
2950         mlx5e_activate_priv_channels(priv);
2951
2952         /* return carrier back if needed */
2953         if (carrier_ok)
2954                 netif_carrier_on(netdev);
2955 }
2956
2957 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2958 {
2959         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2960         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2961 }
2962
2963 int mlx5e_open_locked(struct net_device *netdev)
2964 {
2965         struct mlx5e_priv *priv = netdev_priv(netdev);
2966         int err;
2967
2968         set_bit(MLX5E_STATE_OPENED, &priv->state);
2969
2970         err = mlx5e_open_channels(priv, &priv->channels);
2971         if (err)
2972                 goto err_clear_state_opened_flag;
2973
2974         mlx5e_refresh_tirs(priv, false);
2975         mlx5e_activate_priv_channels(priv);
2976         if (priv->profile->update_carrier)
2977                 priv->profile->update_carrier(priv);
2978
2979         if (priv->profile->update_stats)
2980                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2981
2982         return 0;
2983
2984 err_clear_state_opened_flag:
2985         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2986         return err;
2987 }
2988
2989 int mlx5e_open(struct net_device *netdev)
2990 {
2991         struct mlx5e_priv *priv = netdev_priv(netdev);
2992         int err;
2993
2994         mutex_lock(&priv->state_lock);
2995         err = mlx5e_open_locked(netdev);
2996         if (!err)
2997                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2998         mutex_unlock(&priv->state_lock);
2999
3000         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3001                 udp_tunnel_get_rx_info(netdev);
3002
3003         return err;
3004 }
3005
3006 int mlx5e_close_locked(struct net_device *netdev)
3007 {
3008         struct mlx5e_priv *priv = netdev_priv(netdev);
3009
3010         /* May already be CLOSED in case a previous configuration operation
3011          * (e.g RX/TX queue size change) that involves close&open failed.
3012          */
3013         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3014                 return 0;
3015
3016         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3017
3018         netif_carrier_off(priv->netdev);
3019         mlx5e_deactivate_priv_channels(priv);
3020         mlx5e_close_channels(&priv->channels);
3021
3022         return 0;
3023 }
3024
3025 int mlx5e_close(struct net_device *netdev)
3026 {
3027         struct mlx5e_priv *priv = netdev_priv(netdev);
3028         int err;
3029
3030         if (!netif_device_present(netdev))
3031                 return -ENODEV;
3032
3033         mutex_lock(&priv->state_lock);
3034         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3035         err = mlx5e_close_locked(netdev);
3036         mutex_unlock(&priv->state_lock);
3037
3038         return err;
3039 }
3040
3041 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3042                                struct mlx5e_rq *rq,
3043                                struct mlx5e_rq_param *param)
3044 {
3045         void *rqc = param->rqc;
3046         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3047         int err;
3048
3049         param->wq.db_numa_node = param->wq.buf_numa_node;
3050
3051         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3052                                  &rq->wq_ctrl);
3053         if (err)
3054                 return err;
3055
3056         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3057         xdp_rxq_info_unused(&rq->xdp_rxq);
3058
3059         rq->mdev = mdev;
3060
3061         return 0;
3062 }
3063
3064 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3065                                struct mlx5e_cq *cq,
3066                                struct mlx5e_cq_param *param)
3067 {
3068         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3069         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3070
3071         return mlx5e_alloc_cq_common(mdev, param, cq);
3072 }
3073
3074 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3075                               struct mlx5e_rq *drop_rq)
3076 {
3077         struct mlx5_core_dev *mdev = priv->mdev;
3078         struct mlx5e_cq_param cq_param = {};
3079         struct mlx5e_rq_param rq_param = {};
3080         struct mlx5e_cq *cq = &drop_rq->cq;
3081         int err;
3082
3083         mlx5e_build_drop_rq_param(priv, &rq_param);
3084
3085         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3086         if (err)
3087                 return err;
3088
3089         err = mlx5e_create_cq(cq, &cq_param);
3090         if (err)
3091                 goto err_free_cq;
3092
3093         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3094         if (err)
3095                 goto err_destroy_cq;
3096
3097         err = mlx5e_create_rq(drop_rq, &rq_param);
3098         if (err)
3099                 goto err_free_rq;
3100
3101         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3102         if (err)
3103                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3104
3105         return 0;
3106
3107 err_free_rq:
3108         mlx5e_free_rq(drop_rq);
3109
3110 err_destroy_cq:
3111         mlx5e_destroy_cq(cq);
3112
3113 err_free_cq:
3114         mlx5e_free_cq(cq);
3115
3116         return err;
3117 }
3118
3119 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3120 {
3121         mlx5e_destroy_rq(drop_rq);
3122         mlx5e_free_rq(drop_rq);
3123         mlx5e_destroy_cq(&drop_rq->cq);
3124         mlx5e_free_cq(&drop_rq->cq);
3125 }
3126
3127 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3128                      u32 underlay_qpn, u32 *tisn)
3129 {
3130         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3131         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3132
3133         MLX5_SET(tisc, tisc, prio, tc << 1);
3134         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3135         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3136
3137         if (mlx5_lag_is_lacp_owner(mdev))
3138                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3139
3140         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3141 }
3142
3143 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3144 {
3145         mlx5_core_destroy_tis(mdev, tisn);
3146 }
3147
3148 int mlx5e_create_tises(struct mlx5e_priv *priv)
3149 {
3150         int err;
3151         int tc;
3152
3153         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3154                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3155                 if (err)
3156                         goto err_close_tises;
3157         }
3158
3159         return 0;
3160
3161 err_close_tises:
3162         for (tc--; tc >= 0; tc--)
3163                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3164
3165         return err;
3166 }
3167
3168 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3169 {
3170         int tc;
3171
3172         for (tc = 0; tc < priv->profile->max_tc; tc++)
3173                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3174 }
3175
3176 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3177                                       enum mlx5e_traffic_types tt,
3178                                       u32 *tirc)
3179 {
3180         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3181
3182         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3183
3184         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3185         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3186         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3187 }
3188
3189 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3190 {
3191         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3192
3193         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3194
3195         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3196         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3197         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3198 }
3199
3200 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3201 {
3202         struct mlx5e_tir *tir;
3203         void *tirc;
3204         int inlen;
3205         int i = 0;
3206         int err;
3207         u32 *in;
3208         int tt;
3209
3210         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3211         in = kvzalloc(inlen, GFP_KERNEL);
3212         if (!in)
3213                 return -ENOMEM;
3214
3215         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3216                 memset(in, 0, inlen);
3217                 tir = &priv->indir_tir[tt];
3218                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3219                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3220                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3221                 if (err) {
3222                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3223                         goto err_destroy_inner_tirs;
3224                 }
3225         }
3226
3227         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3228                 goto out;
3229
3230         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3231                 memset(in, 0, inlen);
3232                 tir = &priv->inner_indir_tir[i];
3233                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3234                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3235                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3236                 if (err) {
3237                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3238                         goto err_destroy_inner_tirs;
3239                 }
3240         }
3241
3242 out:
3243         kvfree(in);
3244
3245         return 0;
3246
3247 err_destroy_inner_tirs:
3248         for (i--; i >= 0; i--)
3249                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3250
3251         for (tt--; tt >= 0; tt--)
3252                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3253
3254         kvfree(in);
3255
3256         return err;
3257 }
3258
3259 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3260 {
3261         int nch = priv->profile->max_nch(priv->mdev);
3262         struct mlx5e_tir *tir;
3263         void *tirc;
3264         int inlen;
3265         int err;
3266         u32 *in;
3267         int ix;
3268
3269         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3270         in = kvzalloc(inlen, GFP_KERNEL);
3271         if (!in)
3272                 return -ENOMEM;
3273
3274         for (ix = 0; ix < nch; ix++) {
3275                 memset(in, 0, inlen);
3276                 tir = &priv->direct_tir[ix];
3277                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3278                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3279                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3280                 if (err)
3281                         goto err_destroy_ch_tirs;
3282         }
3283
3284         kvfree(in);
3285
3286         return 0;
3287
3288 err_destroy_ch_tirs:
3289         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3290         for (ix--; ix >= 0; ix--)
3291                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3292
3293         kvfree(in);
3294
3295         return err;
3296 }
3297
3298 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3299 {
3300         int i;
3301
3302         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3303                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3304
3305         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3306                 return;
3307
3308         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3309                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3310 }
3311
3312 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3313 {
3314         int nch = priv->profile->max_nch(priv->mdev);
3315         int i;
3316
3317         for (i = 0; i < nch; i++)
3318                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3319 }
3320
3321 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3322 {
3323         int err = 0;
3324         int i;
3325
3326         for (i = 0; i < chs->num; i++) {
3327                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3328                 if (err)
3329                         return err;
3330         }
3331
3332         return 0;
3333 }
3334
3335 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3336 {
3337         int err = 0;
3338         int i;
3339
3340         for (i = 0; i < chs->num; i++) {
3341                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3342                 if (err)
3343                         return err;
3344         }
3345
3346         return 0;
3347 }
3348
3349 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3350                                  struct tc_mqprio_qopt *mqprio)
3351 {
3352         struct mlx5e_priv *priv = netdev_priv(netdev);
3353         struct mlx5e_channels new_channels = {};
3354         u8 tc = mqprio->num_tc;
3355         int err = 0;
3356
3357         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3358
3359         if (tc && tc != MLX5E_MAX_NUM_TC)
3360                 return -EINVAL;
3361
3362         mutex_lock(&priv->state_lock);
3363
3364         new_channels.params = priv->channels.params;
3365         new_channels.params.num_tc = tc ? tc : 1;
3366
3367         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3368                 priv->channels.params = new_channels.params;
3369                 goto out;
3370         }
3371
3372         err = mlx5e_open_channels(priv, &new_channels);
3373         if (err)
3374                 goto out;
3375
3376         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3377                                     new_channels.params.num_tc);
3378         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3379 out:
3380         mutex_unlock(&priv->state_lock);
3381         return err;
3382 }
3383
3384 #ifdef CONFIG_MLX5_ESWITCH
3385 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3386                                      struct tc_cls_flower_offload *cls_flower,
3387                                      int flags)
3388 {
3389         switch (cls_flower->command) {
3390         case TC_CLSFLOWER_REPLACE:
3391                 return mlx5e_configure_flower(priv, cls_flower, flags);
3392         case TC_CLSFLOWER_DESTROY:
3393                 return mlx5e_delete_flower(priv, cls_flower, flags);
3394         case TC_CLSFLOWER_STATS:
3395                 return mlx5e_stats_flower(priv, cls_flower, flags);
3396         default:
3397                 return -EOPNOTSUPP;
3398         }
3399 }
3400
3401 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3402                                    void *cb_priv)
3403 {
3404         struct mlx5e_priv *priv = cb_priv;
3405
3406         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3407                 return -EOPNOTSUPP;
3408
3409         switch (type) {
3410         case TC_SETUP_CLSFLOWER:
3411                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3412         default:
3413                 return -EOPNOTSUPP;
3414         }
3415 }
3416
3417 static int mlx5e_setup_tc_block(struct net_device *dev,
3418                                 struct tc_block_offload *f)
3419 {
3420         struct mlx5e_priv *priv = netdev_priv(dev);
3421
3422         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3423                 return -EOPNOTSUPP;
3424
3425         switch (f->command) {
3426         case TC_BLOCK_BIND:
3427                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3428                                              priv, priv, f->extack);
3429         case TC_BLOCK_UNBIND:
3430                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3431                                         priv);
3432                 return 0;
3433         default:
3434                 return -EOPNOTSUPP;
3435         }
3436 }
3437 #endif
3438
3439 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3440                           void *type_data)
3441 {
3442         switch (type) {
3443 #ifdef CONFIG_MLX5_ESWITCH
3444         case TC_SETUP_BLOCK:
3445                 return mlx5e_setup_tc_block(dev, type_data);
3446 #endif
3447         case TC_SETUP_QDISC_MQPRIO:
3448                 return mlx5e_setup_tc_mqprio(dev, type_data);
3449         default:
3450                 return -EOPNOTSUPP;
3451         }
3452 }
3453
3454 static void
3455 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3456 {
3457         struct mlx5e_priv *priv = netdev_priv(dev);
3458         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3459         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3460         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3461
3462         /* update HW stats in background for next time */
3463         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3464
3465         if (mlx5e_is_uplink_rep(priv)) {
3466                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3467                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3468                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3469                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3470         } else {
3471                 mlx5e_grp_sw_update_stats(priv);
3472                 stats->rx_packets = sstats->rx_packets;
3473                 stats->rx_bytes   = sstats->rx_bytes;
3474                 stats->tx_packets = sstats->tx_packets;
3475                 stats->tx_bytes   = sstats->tx_bytes;
3476                 stats->tx_dropped = sstats->tx_queue_dropped;
3477         }
3478
3479         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3480
3481         stats->rx_length_errors =
3482                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3483                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3484                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3485         stats->rx_crc_errors =
3486                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3487         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3488         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3489         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3490                            stats->rx_frame_errors;
3491         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3492
3493         /* vport multicast also counts packets that are dropped due to steering
3494          * or rx out of buffer
3495          */
3496         stats->multicast =
3497                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3498 }
3499
3500 static void mlx5e_set_rx_mode(struct net_device *dev)
3501 {
3502         struct mlx5e_priv *priv = netdev_priv(dev);
3503
3504         queue_work(priv->wq, &priv->set_rx_mode_work);
3505 }
3506
3507 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3508 {
3509         struct mlx5e_priv *priv = netdev_priv(netdev);
3510         struct sockaddr *saddr = addr;
3511
3512         if (!is_valid_ether_addr(saddr->sa_data))
3513                 return -EADDRNOTAVAIL;
3514
3515         netif_addr_lock_bh(netdev);
3516         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3517         netif_addr_unlock_bh(netdev);
3518
3519         queue_work(priv->wq, &priv->set_rx_mode_work);
3520
3521         return 0;
3522 }
3523
3524 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3525         do {                                            \
3526                 if (enable)                             \
3527                         *features |= feature;           \
3528                 else                                    \
3529                         *features &= ~feature;          \
3530         } while (0)
3531
3532 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3533
3534 static int set_feature_lro(struct net_device *netdev, bool enable)
3535 {
3536         struct mlx5e_priv *priv = netdev_priv(netdev);
3537         struct mlx5_core_dev *mdev = priv->mdev;
3538         struct mlx5e_channels new_channels = {};
3539         struct mlx5e_params *old_params;
3540         int err = 0;
3541         bool reset;
3542
3543         mutex_lock(&priv->state_lock);
3544
3545         old_params = &priv->channels.params;
3546         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3547                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3548                 err = -EINVAL;
3549                 goto out;
3550         }
3551
3552         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3553
3554         new_channels.params = *old_params;
3555         new_channels.params.lro_en = enable;
3556
3557         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3558                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3559                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3560                         reset = false;
3561         }
3562
3563         if (!reset) {
3564                 *old_params = new_channels.params;
3565                 err = mlx5e_modify_tirs_lro(priv);
3566                 goto out;
3567         }
3568
3569         err = mlx5e_open_channels(priv, &new_channels);
3570         if (err)
3571                 goto out;
3572
3573         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3574 out:
3575         mutex_unlock(&priv->state_lock);
3576         return err;
3577 }
3578
3579 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3580 {
3581         struct mlx5e_priv *priv = netdev_priv(netdev);
3582
3583         if (enable)
3584                 mlx5e_enable_cvlan_filter(priv);
3585         else
3586                 mlx5e_disable_cvlan_filter(priv);
3587
3588         return 0;
3589 }
3590
3591 #ifdef CONFIG_MLX5_ESWITCH
3592 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3593 {
3594         struct mlx5e_priv *priv = netdev_priv(netdev);
3595
3596         if (!enable && mlx5e_tc_num_filters(priv)) {
3597                 netdev_err(netdev,
3598                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3599                 return -EINVAL;
3600         }
3601
3602         return 0;
3603 }
3604 #endif
3605
3606 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3607 {
3608         struct mlx5e_priv *priv = netdev_priv(netdev);
3609         struct mlx5_core_dev *mdev = priv->mdev;
3610
3611         return mlx5_set_port_fcs(mdev, !enable);
3612 }
3613
3614 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3615 {
3616         struct mlx5e_priv *priv = netdev_priv(netdev);
3617         int err;
3618
3619         mutex_lock(&priv->state_lock);
3620
3621         priv->channels.params.scatter_fcs_en = enable;
3622         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3623         if (err)
3624                 priv->channels.params.scatter_fcs_en = !enable;
3625
3626         mutex_unlock(&priv->state_lock);
3627
3628         return err;
3629 }
3630
3631 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3632 {
3633         struct mlx5e_priv *priv = netdev_priv(netdev);
3634         int err = 0;
3635
3636         mutex_lock(&priv->state_lock);
3637
3638         priv->channels.params.vlan_strip_disable = !enable;
3639         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3640                 goto unlock;
3641
3642         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3643         if (err)
3644                 priv->channels.params.vlan_strip_disable = enable;
3645
3646 unlock:
3647         mutex_unlock(&priv->state_lock);
3648
3649         return err;
3650 }
3651
3652 #ifdef CONFIG_MLX5_EN_ARFS
3653 static int set_feature_arfs(struct net_device *netdev, bool enable)
3654 {
3655         struct mlx5e_priv *priv = netdev_priv(netdev);
3656         int err;
3657
3658         if (enable)
3659                 err = mlx5e_arfs_enable(priv);
3660         else
3661                 err = mlx5e_arfs_disable(priv);
3662
3663         return err;
3664 }
3665 #endif
3666
3667 static int mlx5e_handle_feature(struct net_device *netdev,
3668                                 netdev_features_t *features,
3669                                 netdev_features_t wanted_features,
3670                                 netdev_features_t feature,
3671                                 mlx5e_feature_handler feature_handler)
3672 {
3673         netdev_features_t changes = wanted_features ^ netdev->features;
3674         bool enable = !!(wanted_features & feature);
3675         int err;
3676
3677         if (!(changes & feature))
3678                 return 0;
3679
3680         err = feature_handler(netdev, enable);
3681         if (err) {
3682                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3683                            enable ? "Enable" : "Disable", &feature, err);
3684                 return err;
3685         }
3686
3687         MLX5E_SET_FEATURE(features, feature, enable);
3688         return 0;
3689 }
3690
3691 static int mlx5e_set_features(struct net_device *netdev,
3692                               netdev_features_t features)
3693 {
3694         netdev_features_t oper_features = netdev->features;
3695         int err = 0;
3696
3697 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3698         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3699
3700         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3701         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3702                                     set_feature_cvlan_filter);
3703 #ifdef CONFIG_MLX5_ESWITCH
3704         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3705 #endif
3706         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3707         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3708         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3709 #ifdef CONFIG_MLX5_EN_ARFS
3710         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3711 #endif
3712
3713         if (err) {
3714                 netdev->features = oper_features;
3715                 return -EINVAL;
3716         }
3717
3718         return 0;
3719 }
3720
3721 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3722                                             netdev_features_t features)
3723 {
3724         struct mlx5e_priv *priv = netdev_priv(netdev);
3725         struct mlx5e_params *params;
3726
3727         mutex_lock(&priv->state_lock);
3728         params = &priv->channels.params;
3729         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3730                 /* HW strips the outer C-tag header, this is a problem
3731                  * for S-tag traffic.
3732                  */
3733                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3734                 if (!params->vlan_strip_disable)
3735                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3736         }
3737         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3738                 features &= ~NETIF_F_LRO;
3739                 if (params->lro_en)
3740                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3741         }
3742
3743         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3744                 features &= ~NETIF_F_RXHASH;
3745                 if (netdev->features & NETIF_F_RXHASH)
3746                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3747         }
3748
3749         mutex_unlock(&priv->state_lock);
3750
3751         return features;
3752 }
3753
3754 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3755                      change_hw_mtu_cb set_mtu_cb)
3756 {
3757         struct mlx5e_priv *priv = netdev_priv(netdev);
3758         struct mlx5e_channels new_channels = {};
3759         struct mlx5e_params *params;
3760         int err = 0;
3761         bool reset;
3762
3763         mutex_lock(&priv->state_lock);
3764
3765         params = &priv->channels.params;
3766
3767         reset = !params->lro_en;
3768         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3769
3770         new_channels.params = *params;
3771         new_channels.params.sw_mtu = new_mtu;
3772
3773         if (params->xdp_prog &&
3774             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3775                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3776                            new_mtu, mlx5e_xdp_max_mtu(params));
3777                 err = -EINVAL;
3778                 goto out;
3779         }
3780
3781         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3782                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3783                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3784                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3785
3786                 reset = reset && (is_linear || (ppw_old != ppw_new));
3787         }
3788
3789         if (!reset) {
3790                 params->sw_mtu = new_mtu;
3791                 if (set_mtu_cb)
3792                         set_mtu_cb(priv);
3793                 netdev->mtu = params->sw_mtu;
3794                 goto out;
3795         }
3796
3797         err = mlx5e_open_channels(priv, &new_channels);
3798         if (err)
3799                 goto out;
3800
3801         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3802         netdev->mtu = new_channels.params.sw_mtu;
3803
3804 out:
3805         mutex_unlock(&priv->state_lock);
3806         return err;
3807 }
3808
3809 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3810 {
3811         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3812 }
3813
3814 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3815 {
3816         struct hwtstamp_config config;
3817         int err;
3818
3819         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3820             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3821                 return -EOPNOTSUPP;
3822
3823         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3824                 return -EFAULT;
3825
3826         /* TX HW timestamp */
3827         switch (config.tx_type) {
3828         case HWTSTAMP_TX_OFF:
3829         case HWTSTAMP_TX_ON:
3830                 break;
3831         default:
3832                 return -ERANGE;
3833         }
3834
3835         mutex_lock(&priv->state_lock);
3836         /* RX HW timestamp */
3837         switch (config.rx_filter) {
3838         case HWTSTAMP_FILTER_NONE:
3839                 /* Reset CQE compression to Admin default */
3840                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3841                 break;
3842         case HWTSTAMP_FILTER_ALL:
3843         case HWTSTAMP_FILTER_SOME:
3844         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3845         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3846         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3847         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3848         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3849         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3850         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3851         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3852         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3853         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3854         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3855         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3856         case HWTSTAMP_FILTER_NTP_ALL:
3857                 /* Disable CQE compression */
3858                 netdev_warn(priv->netdev, "Disabling cqe compression");
3859                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3860                 if (err) {
3861                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3862                         mutex_unlock(&priv->state_lock);
3863                         return err;
3864                 }
3865                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3866                 break;
3867         default:
3868                 mutex_unlock(&priv->state_lock);
3869                 return -ERANGE;
3870         }
3871
3872         memcpy(&priv->tstamp, &config, sizeof(config));
3873         mutex_unlock(&priv->state_lock);
3874
3875         /* might need to fix some features */
3876         netdev_update_features(priv->netdev);
3877
3878         return copy_to_user(ifr->ifr_data, &config,
3879                             sizeof(config)) ? -EFAULT : 0;
3880 }
3881
3882 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3883 {
3884         struct hwtstamp_config *cfg = &priv->tstamp;
3885
3886         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3887                 return -EOPNOTSUPP;
3888
3889         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3890 }
3891
3892 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3893 {
3894         struct mlx5e_priv *priv = netdev_priv(dev);
3895
3896         switch (cmd) {
3897         case SIOCSHWTSTAMP:
3898                 return mlx5e_hwstamp_set(priv, ifr);
3899         case SIOCGHWTSTAMP:
3900                 return mlx5e_hwstamp_get(priv, ifr);
3901         default:
3902                 return -EOPNOTSUPP;
3903         }
3904 }
3905
3906 #ifdef CONFIG_MLX5_ESWITCH
3907 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3908 {
3909         struct mlx5e_priv *priv = netdev_priv(dev);
3910         struct mlx5_core_dev *mdev = priv->mdev;
3911
3912         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3913 }
3914
3915 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3916                              __be16 vlan_proto)
3917 {
3918         struct mlx5e_priv *priv = netdev_priv(dev);
3919         struct mlx5_core_dev *mdev = priv->mdev;
3920
3921         if (vlan_proto != htons(ETH_P_8021Q))
3922                 return -EPROTONOSUPPORT;
3923
3924         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3925                                            vlan, qos);
3926 }
3927
3928 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3929 {
3930         struct mlx5e_priv *priv = netdev_priv(dev);
3931         struct mlx5_core_dev *mdev = priv->mdev;
3932
3933         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3934 }
3935
3936 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3937 {
3938         struct mlx5e_priv *priv = netdev_priv(dev);
3939         struct mlx5_core_dev *mdev = priv->mdev;
3940
3941         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3942 }
3943
3944 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3945                              int max_tx_rate)
3946 {
3947         struct mlx5e_priv *priv = netdev_priv(dev);
3948         struct mlx5_core_dev *mdev = priv->mdev;
3949
3950         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3951                                            max_tx_rate, min_tx_rate);
3952 }
3953
3954 static int mlx5_vport_link2ifla(u8 esw_link)
3955 {
3956         switch (esw_link) {
3957         case MLX5_VPORT_ADMIN_STATE_DOWN:
3958                 return IFLA_VF_LINK_STATE_DISABLE;
3959         case MLX5_VPORT_ADMIN_STATE_UP:
3960                 return IFLA_VF_LINK_STATE_ENABLE;
3961         }
3962         return IFLA_VF_LINK_STATE_AUTO;
3963 }
3964
3965 static int mlx5_ifla_link2vport(u8 ifla_link)
3966 {
3967         switch (ifla_link) {
3968         case IFLA_VF_LINK_STATE_DISABLE:
3969                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3970         case IFLA_VF_LINK_STATE_ENABLE:
3971                 return MLX5_VPORT_ADMIN_STATE_UP;
3972         }
3973         return MLX5_VPORT_ADMIN_STATE_AUTO;
3974 }
3975
3976 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3977                                    int link_state)
3978 {
3979         struct mlx5e_priv *priv = netdev_priv(dev);
3980         struct mlx5_core_dev *mdev = priv->mdev;
3981
3982         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3983                                             mlx5_ifla_link2vport(link_state));
3984 }
3985
3986 static int mlx5e_get_vf_config(struct net_device *dev,
3987                                int vf, struct ifla_vf_info *ivi)
3988 {
3989         struct mlx5e_priv *priv = netdev_priv(dev);
3990         struct mlx5_core_dev *mdev = priv->mdev;
3991         int err;
3992
3993         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3994         if (err)
3995                 return err;
3996         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3997         return 0;
3998 }
3999
4000 static int mlx5e_get_vf_stats(struct net_device *dev,
4001                               int vf, struct ifla_vf_stats *vf_stats)
4002 {
4003         struct mlx5e_priv *priv = netdev_priv(dev);
4004         struct mlx5_core_dev *mdev = priv->mdev;
4005
4006         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4007                                             vf_stats);
4008 }
4009 #endif
4010
4011 struct mlx5e_vxlan_work {
4012         struct work_struct      work;
4013         struct mlx5e_priv       *priv;
4014         u16                     port;
4015 };
4016
4017 static void mlx5e_vxlan_add_work(struct work_struct *work)
4018 {
4019         struct mlx5e_vxlan_work *vxlan_work =
4020                 container_of(work, struct mlx5e_vxlan_work, work);
4021         struct mlx5e_priv *priv = vxlan_work->priv;
4022         u16 port = vxlan_work->port;
4023
4024         mutex_lock(&priv->state_lock);
4025         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4026         mutex_unlock(&priv->state_lock);
4027
4028         kfree(vxlan_work);
4029 }
4030
4031 static void mlx5e_vxlan_del_work(struct work_struct *work)
4032 {
4033         struct mlx5e_vxlan_work *vxlan_work =
4034                 container_of(work, struct mlx5e_vxlan_work, work);
4035         struct mlx5e_priv *priv         = vxlan_work->priv;
4036         u16 port = vxlan_work->port;
4037
4038         mutex_lock(&priv->state_lock);
4039         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4040         mutex_unlock(&priv->state_lock);
4041         kfree(vxlan_work);
4042 }
4043
4044 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4045 {
4046         struct mlx5e_vxlan_work *vxlan_work;
4047
4048         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4049         if (!vxlan_work)
4050                 return;
4051
4052         if (add)
4053                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4054         else
4055                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4056
4057         vxlan_work->priv = priv;
4058         vxlan_work->port = port;
4059         queue_work(priv->wq, &vxlan_work->work);
4060 }
4061
4062 static void mlx5e_add_vxlan_port(struct net_device *netdev,
4063                                  struct udp_tunnel_info *ti)
4064 {
4065         struct mlx5e_priv *priv = netdev_priv(netdev);
4066
4067         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4068                 return;
4069
4070         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4071                 return;
4072
4073         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4074 }
4075
4076 static void mlx5e_del_vxlan_port(struct net_device *netdev,
4077                                  struct udp_tunnel_info *ti)
4078 {
4079         struct mlx5e_priv *priv = netdev_priv(netdev);
4080
4081         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4082                 return;
4083
4084         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4085                 return;
4086
4087         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4088 }
4089
4090 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4091                                                      struct sk_buff *skb,
4092                                                      netdev_features_t features)
4093 {
4094         unsigned int offset = 0;
4095         struct udphdr *udph;
4096         u8 proto;
4097         u16 port;
4098
4099         switch (vlan_get_protocol(skb)) {
4100         case htons(ETH_P_IP):
4101                 proto = ip_hdr(skb)->protocol;
4102                 break;
4103         case htons(ETH_P_IPV6):
4104                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4105                 break;
4106         default:
4107                 goto out;
4108         }
4109
4110         switch (proto) {
4111         case IPPROTO_GRE:
4112                 return features;
4113         case IPPROTO_UDP:
4114                 udph = udp_hdr(skb);
4115                 port = be16_to_cpu(udph->dest);
4116
4117                 /* Verify if UDP port is being offloaded by HW */
4118                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4119                         return features;
4120         }
4121
4122 out:
4123         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4124         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4125 }
4126
4127 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4128                                               struct net_device *netdev,
4129                                               netdev_features_t features)
4130 {
4131         struct mlx5e_priv *priv = netdev_priv(netdev);
4132
4133         features = vlan_features_check(skb, features);
4134         features = vxlan_features_check(skb, features);
4135
4136 #ifdef CONFIG_MLX5_EN_IPSEC
4137         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4138                 return features;
4139 #endif
4140
4141         /* Validate if the tunneled packet is being offloaded by HW */
4142         if (skb->encapsulation &&
4143             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4144                 return mlx5e_tunnel_features_check(priv, skb, features);
4145
4146         return features;
4147 }
4148
4149 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4150                                         struct mlx5e_txqsq *sq)
4151 {
4152         struct mlx5_eq *eq = sq->cq.mcq.eq;
4153         u32 eqe_count;
4154
4155         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4156                    eq->eqn, eq->cons_index, eq->irqn);
4157
4158         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4159         if (!eqe_count)
4160                 return false;
4161
4162         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4163         sq->channel->stats->eq_rearm++;
4164         return true;
4165 }
4166
4167 static void mlx5e_tx_timeout_work(struct work_struct *work)
4168 {
4169         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4170                                                tx_timeout_work);
4171         struct net_device *dev = priv->netdev;
4172         bool reopen_channels = false;
4173         int i, err;
4174
4175         rtnl_lock();
4176         mutex_lock(&priv->state_lock);
4177
4178         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4179                 goto unlock;
4180
4181         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4182                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4183                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4184
4185                 if (!netif_xmit_stopped(dev_queue))
4186                         continue;
4187
4188                 netdev_err(dev,
4189                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4190                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4191                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4192
4193                 /* If we recover a lost interrupt, most likely TX timeout will
4194                  * be resolved, skip reopening channels
4195                  */
4196                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4197                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4198                         reopen_channels = true;
4199                 }
4200         }
4201
4202         if (!reopen_channels)
4203                 goto unlock;
4204
4205         mlx5e_close_locked(dev);
4206         err = mlx5e_open_locked(dev);
4207         if (err)
4208                 netdev_err(priv->netdev,
4209                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4210                            err);
4211
4212 unlock:
4213         mutex_unlock(&priv->state_lock);
4214         rtnl_unlock();
4215 }
4216
4217 static void mlx5e_tx_timeout(struct net_device *dev)
4218 {
4219         struct mlx5e_priv *priv = netdev_priv(dev);
4220
4221         netdev_err(dev, "TX timeout detected\n");
4222         queue_work(priv->wq, &priv->tx_timeout_work);
4223 }
4224
4225 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4226 {
4227         struct net_device *netdev = priv->netdev;
4228         struct mlx5e_channels new_channels = {};
4229
4230         if (priv->channels.params.lro_en) {
4231                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4232                 return -EINVAL;
4233         }
4234
4235         if (MLX5_IPSEC_DEV(priv->mdev)) {
4236                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4237                 return -EINVAL;
4238         }
4239
4240         new_channels.params = priv->channels.params;
4241         new_channels.params.xdp_prog = prog;
4242
4243         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4244                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4245                             new_channels.params.sw_mtu,
4246                             mlx5e_xdp_max_mtu(&new_channels.params));
4247                 return -EINVAL;
4248         }
4249
4250         return 0;
4251 }
4252
4253 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4254 {
4255         struct mlx5e_priv *priv = netdev_priv(netdev);
4256         struct bpf_prog *old_prog;
4257         bool reset, was_opened;
4258         int err = 0;
4259         int i;
4260
4261         mutex_lock(&priv->state_lock);
4262
4263         if (prog) {
4264                 err = mlx5e_xdp_allowed(priv, prog);
4265                 if (err)
4266                         goto unlock;
4267         }
4268
4269         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4270         /* no need for full reset when exchanging programs */
4271         reset = (!priv->channels.params.xdp_prog || !prog);
4272
4273         if (was_opened && reset)
4274                 mlx5e_close_locked(netdev);
4275         if (was_opened && !reset) {
4276                 /* num_channels is invariant here, so we can take the
4277                  * batched reference right upfront.
4278                  */
4279                 prog = bpf_prog_add(prog, priv->channels.num);
4280                 if (IS_ERR(prog)) {
4281                         err = PTR_ERR(prog);
4282                         goto unlock;
4283                 }
4284         }
4285
4286         /* exchange programs, extra prog reference we got from caller
4287          * as long as we don't fail from this point onwards.
4288          */
4289         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4290         if (old_prog)
4291                 bpf_prog_put(old_prog);
4292
4293         if (reset) /* change RQ type according to priv->xdp_prog */
4294                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4295
4296         if (was_opened && reset)
4297                 mlx5e_open_locked(netdev);
4298
4299         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4300                 goto unlock;
4301
4302         /* exchanging programs w/o reset, we update ref counts on behalf
4303          * of the channels RQs here.
4304          */
4305         for (i = 0; i < priv->channels.num; i++) {
4306                 struct mlx5e_channel *c = priv->channels.c[i];
4307
4308                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4309                 napi_synchronize(&c->napi);
4310                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4311
4312                 old_prog = xchg(&c->rq.xdp_prog, prog);
4313
4314                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4315                 /* napi_schedule in case we have missed anything */
4316                 napi_schedule(&c->napi);
4317
4318                 if (old_prog)
4319                         bpf_prog_put(old_prog);
4320         }
4321
4322 unlock:
4323         mutex_unlock(&priv->state_lock);
4324         return err;
4325 }
4326
4327 static u32 mlx5e_xdp_query(struct net_device *dev)
4328 {
4329         struct mlx5e_priv *priv = netdev_priv(dev);
4330         const struct bpf_prog *xdp_prog;
4331         u32 prog_id = 0;
4332
4333         mutex_lock(&priv->state_lock);
4334         xdp_prog = priv->channels.params.xdp_prog;
4335         if (xdp_prog)
4336                 prog_id = xdp_prog->aux->id;
4337         mutex_unlock(&priv->state_lock);
4338
4339         return prog_id;
4340 }
4341
4342 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4343 {
4344         switch (xdp->command) {
4345         case XDP_SETUP_PROG:
4346                 return mlx5e_xdp_set(dev, xdp->prog);
4347         case XDP_QUERY_PROG:
4348                 xdp->prog_id = mlx5e_xdp_query(dev);
4349                 return 0;
4350         default:
4351                 return -EINVAL;
4352         }
4353 }
4354
4355 const struct net_device_ops mlx5e_netdev_ops = {
4356         .ndo_open                = mlx5e_open,
4357         .ndo_stop                = mlx5e_close,
4358         .ndo_start_xmit          = mlx5e_xmit,
4359         .ndo_setup_tc            = mlx5e_setup_tc,
4360         .ndo_select_queue        = mlx5e_select_queue,
4361         .ndo_get_stats64         = mlx5e_get_stats,
4362         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4363         .ndo_set_mac_address     = mlx5e_set_mac,
4364         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4365         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4366         .ndo_set_features        = mlx5e_set_features,
4367         .ndo_fix_features        = mlx5e_fix_features,
4368         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4369         .ndo_do_ioctl            = mlx5e_ioctl,
4370         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4371         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4372         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4373         .ndo_features_check      = mlx5e_features_check,
4374         .ndo_tx_timeout          = mlx5e_tx_timeout,
4375         .ndo_bpf                 = mlx5e_xdp,
4376         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4377 #ifdef CONFIG_MLX5_EN_ARFS
4378         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4379 #endif
4380 #ifdef CONFIG_MLX5_ESWITCH
4381         /* SRIOV E-Switch NDOs */
4382         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4383         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4384         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4385         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4386         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4387         .ndo_get_vf_config       = mlx5e_get_vf_config,
4388         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4389         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4390         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4391         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4392 #endif
4393 };
4394
4395 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4396 {
4397         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4398                 return -EOPNOTSUPP;
4399         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4400             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4401             !MLX5_CAP_ETH(mdev, csum_cap) ||
4402             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4403             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4404             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4405             MLX5_CAP_FLOWTABLE(mdev,
4406                                flow_table_properties_nic_receive.max_ft_level)
4407                                < 3) {
4408                 mlx5_core_warn(mdev,
4409                                "Not creating net device, some required device capabilities are missing\n");
4410                 return -EOPNOTSUPP;
4411         }
4412         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4413                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4414         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4415                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4416
4417         return 0;
4418 }
4419
4420 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4421                                    int num_channels)
4422 {
4423         int i;
4424
4425         for (i = 0; i < len; i++)
4426                 indirection_rqt[i] = i % num_channels;
4427 }
4428
4429 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4430 {
4431         u32 link_speed = 0;
4432         u32 pci_bw = 0;
4433
4434         mlx5e_port_max_linkspeed(mdev, &link_speed);
4435         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4436         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4437                            link_speed, pci_bw);
4438
4439 #define MLX5E_SLOW_PCI_RATIO (2)
4440
4441         return link_speed && pci_bw &&
4442                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4443 }
4444
4445 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4446 {
4447         struct net_dim_cq_moder moder;
4448
4449         moder.cq_period_mode = cq_period_mode;
4450         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4451         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4452         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4453                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4454
4455         return moder;
4456 }
4457
4458 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4459 {
4460         struct net_dim_cq_moder moder;
4461
4462         moder.cq_period_mode = cq_period_mode;
4463         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4464         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4465         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4466                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4467
4468         return moder;
4469 }
4470
4471 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4472 {
4473         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4474                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4475                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4476 }
4477
4478 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4479 {
4480         if (params->tx_dim_enabled) {
4481                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4482
4483                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4484         } else {
4485                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4486         }
4487
4488         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4489                         params->tx_cq_moderation.cq_period_mode ==
4490                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4491 }
4492
4493 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4494 {
4495         if (params->rx_dim_enabled) {
4496                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4497
4498                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4499         } else {
4500                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4501         }
4502
4503         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4504                         params->rx_cq_moderation.cq_period_mode ==
4505                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4506 }
4507
4508 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4509 {
4510         int i;
4511
4512         /* The supported periods are organized in ascending order */
4513         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4514                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4515                         break;
4516
4517         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4518 }
4519
4520 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4521                             struct mlx5e_params *params,
4522                             u16 max_channels, u16 mtu)
4523 {
4524         u8 rx_cq_period_mode;
4525
4526         params->sw_mtu = mtu;
4527         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4528         params->num_channels = max_channels;
4529         params->num_tc       = 1;
4530
4531         /* SQ */
4532         params->log_sq_size = is_kdump_kernel() ?
4533                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4534                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4535
4536         /* set CQE compression */
4537         params->rx_cqe_compress_def = false;
4538         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4539             MLX5_CAP_GEN(mdev, vport_group_manager))
4540                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4541
4542         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4543         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4544
4545         /* RQ */
4546         /* Prefer Striding RQ, unless any of the following holds:
4547          * - Striding RQ configuration is not possible/supported.
4548          * - Slow PCI heuristic.
4549          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4550          */
4551         if (!slow_pci_heuristic(mdev) &&
4552             mlx5e_striding_rq_possible(mdev, params) &&
4553             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4554              !mlx5e_rx_is_linear_skb(mdev, params)))
4555                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4556         mlx5e_set_rq_type(mdev, params);
4557         mlx5e_init_rq_type_params(mdev, params);
4558
4559         /* HW LRO */
4560
4561         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4562         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4563                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4564                         params->lro_en = !slow_pci_heuristic(mdev);
4565         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4566
4567         /* CQ moderation params */
4568         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4569                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4570                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4571         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4572         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4573         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4574         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4575
4576         /* TX inline */
4577         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4578
4579         /* RSS */
4580         params->rss_hfunc = ETH_RSS_HASH_XOR;
4581         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4582         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4583                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4584 }
4585
4586 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4587                                         struct net_device *netdev,
4588                                         const struct mlx5e_profile *profile,
4589                                         void *ppriv)
4590 {
4591         struct mlx5e_priv *priv = netdev_priv(netdev);
4592
4593         priv->mdev        = mdev;
4594         priv->netdev      = netdev;
4595         priv->profile     = profile;
4596         priv->ppriv       = ppriv;
4597         priv->msglevel    = MLX5E_MSG_LEVEL;
4598         priv->max_opened_tc = 1;
4599
4600         mlx5e_build_nic_params(mdev, &priv->channels.params,
4601                                profile->max_nch(mdev), netdev->mtu);
4602
4603         mutex_init(&priv->state_lock);
4604
4605         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4606         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4607         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4608         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4609
4610         mlx5e_timestamp_init(priv);
4611 }
4612
4613 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4614 {
4615         struct mlx5e_priv *priv = netdev_priv(netdev);
4616
4617         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4618         if (is_zero_ether_addr(netdev->dev_addr) &&
4619             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4620                 eth_hw_addr_random(netdev);
4621                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4622         }
4623 }
4624
4625 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4626 static const struct switchdev_ops mlx5e_switchdev_ops = {
4627         .switchdev_port_attr_get        = mlx5e_attr_get,
4628 };
4629 #endif
4630
4631 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4632 {
4633         struct mlx5e_priv *priv = netdev_priv(netdev);
4634         struct mlx5_core_dev *mdev = priv->mdev;
4635         bool fcs_supported;
4636         bool fcs_enabled;
4637
4638         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4639
4640         netdev->netdev_ops = &mlx5e_netdev_ops;
4641
4642 #ifdef CONFIG_MLX5_CORE_EN_DCB
4643         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4644                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4645 #endif
4646
4647         netdev->watchdog_timeo    = 15 * HZ;
4648
4649         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4650
4651         netdev->vlan_features    |= NETIF_F_SG;
4652         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4653         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4654         netdev->vlan_features    |= NETIF_F_GRO;
4655         netdev->vlan_features    |= NETIF_F_TSO;
4656         netdev->vlan_features    |= NETIF_F_TSO6;
4657         netdev->vlan_features    |= NETIF_F_RXCSUM;
4658         netdev->vlan_features    |= NETIF_F_RXHASH;
4659
4660         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4661         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4662
4663         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4664             mlx5e_check_fragmented_striding_rq_cap(mdev))
4665                 netdev->vlan_features    |= NETIF_F_LRO;
4666
4667         netdev->hw_features       = netdev->vlan_features;
4668         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4669         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4670         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4671         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4672
4673         if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4674                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4675                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4676                 netdev->hw_enc_features |= NETIF_F_TSO;
4677                 netdev->hw_enc_features |= NETIF_F_TSO6;
4678                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4679         }
4680
4681         if (mlx5_vxlan_allowed(mdev->vxlan)) {
4682                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4683                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4684         }
4685
4686         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4687                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4688                                            NETIF_F_GSO_GRE_CSUM;
4689                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4690                                            NETIF_F_GSO_GRE_CSUM;
4691                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4692                                                 NETIF_F_GSO_GRE_CSUM;
4693         }
4694
4695         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4696         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4697         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4698         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4699
4700         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4701
4702         if (fcs_supported)
4703                 netdev->hw_features |= NETIF_F_RXALL;
4704
4705         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4706                 netdev->hw_features |= NETIF_F_RXFCS;
4707
4708         netdev->features          = netdev->hw_features;
4709         if (!priv->channels.params.lro_en)
4710                 netdev->features  &= ~NETIF_F_LRO;
4711
4712         if (fcs_enabled)
4713                 netdev->features  &= ~NETIF_F_RXALL;
4714
4715         if (!priv->channels.params.scatter_fcs_en)
4716                 netdev->features  &= ~NETIF_F_RXFCS;
4717
4718         /* prefere CQE compression over rxhash */
4719         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4720                 netdev->features &= ~NETIF_F_RXHASH;
4721
4722 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4723         if (FT_CAP(flow_modify_en) &&
4724             FT_CAP(modify_root) &&
4725             FT_CAP(identified_miss_table_mode) &&
4726             FT_CAP(flow_table_modify)) {
4727 #ifdef CONFIG_MLX5_ESWITCH
4728                 netdev->hw_features      |= NETIF_F_HW_TC;
4729 #endif
4730 #ifdef CONFIG_MLX5_EN_ARFS
4731                 netdev->hw_features      |= NETIF_F_NTUPLE;
4732 #endif
4733         }
4734
4735         netdev->features         |= NETIF_F_HIGHDMA;
4736         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4737
4738         netdev->priv_flags       |= IFF_UNICAST_FLT;
4739
4740         mlx5e_set_netdev_dev_addr(netdev);
4741
4742 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4743         if (MLX5_ESWITCH_MANAGER(mdev))
4744                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4745 #endif
4746
4747         mlx5e_ipsec_build_netdev(priv);
4748         mlx5e_tls_build_netdev(priv);
4749 }
4750
4751 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4752 {
4753         struct mlx5_core_dev *mdev = priv->mdev;
4754         int err;
4755
4756         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4757         if (err) {
4758                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4759                 priv->q_counter = 0;
4760         }
4761
4762         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4763         if (err) {
4764                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4765                 priv->drop_rq_q_counter = 0;
4766         }
4767 }
4768
4769 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4770 {
4771         if (priv->q_counter)
4772                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4773
4774         if (priv->drop_rq_q_counter)
4775                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4776 }
4777
4778 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4779                            struct net_device *netdev,
4780                            const struct mlx5e_profile *profile,
4781                            void *ppriv)
4782 {
4783         struct mlx5e_priv *priv = netdev_priv(netdev);
4784         int err;
4785
4786         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4787         err = mlx5e_ipsec_init(priv);
4788         if (err)
4789                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4790         err = mlx5e_tls_init(priv);
4791         if (err)
4792                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4793         mlx5e_build_nic_netdev(netdev);
4794         mlx5e_build_tc2txq_maps(priv);
4795 }
4796
4797 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4798 {
4799         mlx5e_tls_cleanup(priv);
4800         mlx5e_ipsec_cleanup(priv);
4801 }
4802
4803 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4804 {
4805         struct mlx5_core_dev *mdev = priv->mdev;
4806         int err;
4807
4808         err = mlx5e_create_indirect_rqt(priv);
4809         if (err)
4810                 return err;
4811
4812         err = mlx5e_create_direct_rqts(priv);
4813         if (err)
4814                 goto err_destroy_indirect_rqts;
4815
4816         err = mlx5e_create_indirect_tirs(priv);
4817         if (err)
4818                 goto err_destroy_direct_rqts;
4819
4820         err = mlx5e_create_direct_tirs(priv);
4821         if (err)
4822                 goto err_destroy_indirect_tirs;
4823
4824         err = mlx5e_create_flow_steering(priv);
4825         if (err) {
4826                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4827                 goto err_destroy_direct_tirs;
4828         }
4829
4830         err = mlx5e_tc_nic_init(priv);
4831         if (err)
4832                 goto err_destroy_flow_steering;
4833
4834         return 0;
4835
4836 err_destroy_flow_steering:
4837         mlx5e_destroy_flow_steering(priv);
4838 err_destroy_direct_tirs:
4839         mlx5e_destroy_direct_tirs(priv);
4840 err_destroy_indirect_tirs:
4841         mlx5e_destroy_indirect_tirs(priv);
4842 err_destroy_direct_rqts:
4843         mlx5e_destroy_direct_rqts(priv);
4844 err_destroy_indirect_rqts:
4845         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4846         return err;
4847 }
4848
4849 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4850 {
4851         mlx5e_tc_nic_cleanup(priv);
4852         mlx5e_destroy_flow_steering(priv);
4853         mlx5e_destroy_direct_tirs(priv);
4854         mlx5e_destroy_indirect_tirs(priv);
4855         mlx5e_destroy_direct_rqts(priv);
4856         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4857 }
4858
4859 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4860 {
4861         int err;
4862
4863         err = mlx5e_create_tises(priv);
4864         if (err) {
4865                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4866                 return err;
4867         }
4868
4869 #ifdef CONFIG_MLX5_CORE_EN_DCB
4870         mlx5e_dcbnl_initialize(priv);
4871 #endif
4872         return 0;
4873 }
4874
4875 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4876 {
4877         struct net_device *netdev = priv->netdev;
4878         struct mlx5_core_dev *mdev = priv->mdev;
4879         u16 max_mtu;
4880
4881         mlx5e_init_l2_addr(priv);
4882
4883         /* Marking the link as currently not needed by the Driver */
4884         if (!netif_running(netdev))
4885                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4886
4887         /* MTU range: 68 - hw-specific max */
4888         netdev->min_mtu = ETH_MIN_MTU;
4889         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4890         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4891         mlx5e_set_dev_port_mtu(priv);
4892
4893         mlx5_lag_add(mdev, netdev);
4894
4895         mlx5e_enable_async_events(priv);
4896
4897         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4898                 mlx5e_register_vport_reps(priv);
4899
4900         if (netdev->reg_state != NETREG_REGISTERED)
4901                 return;
4902 #ifdef CONFIG_MLX5_CORE_EN_DCB
4903         mlx5e_dcbnl_init_app(priv);
4904 #endif
4905
4906         queue_work(priv->wq, &priv->set_rx_mode_work);
4907
4908         rtnl_lock();
4909         if (netif_running(netdev))
4910                 mlx5e_open(netdev);
4911         netif_device_attach(netdev);
4912         rtnl_unlock();
4913 }
4914
4915 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4916 {
4917         struct mlx5_core_dev *mdev = priv->mdev;
4918
4919 #ifdef CONFIG_MLX5_CORE_EN_DCB
4920         if (priv->netdev->reg_state == NETREG_REGISTERED)
4921                 mlx5e_dcbnl_delete_app(priv);
4922 #endif
4923
4924         rtnl_lock();
4925         if (netif_running(priv->netdev))
4926                 mlx5e_close(priv->netdev);
4927         netif_device_detach(priv->netdev);
4928         rtnl_unlock();
4929
4930         queue_work(priv->wq, &priv->set_rx_mode_work);
4931
4932         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4933                 mlx5e_unregister_vport_reps(priv);
4934
4935         mlx5e_disable_async_events(priv);
4936         mlx5_lag_remove(mdev);
4937 }
4938
4939 static const struct mlx5e_profile mlx5e_nic_profile = {
4940         .init              = mlx5e_nic_init,
4941         .cleanup           = mlx5e_nic_cleanup,
4942         .init_rx           = mlx5e_init_nic_rx,
4943         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4944         .init_tx           = mlx5e_init_nic_tx,
4945         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4946         .enable            = mlx5e_nic_enable,
4947         .disable           = mlx5e_nic_disable,
4948         .update_stats      = mlx5e_update_ndo_stats,
4949         .max_nch           = mlx5e_get_max_num_channels,
4950         .update_carrier    = mlx5e_update_carrier,
4951         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4952         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4953         .max_tc            = MLX5E_MAX_NUM_TC,
4954 };
4955
4956 /* mlx5e generic netdev management API (move to en_common.c) */
4957
4958 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4959                                        const struct mlx5e_profile *profile,
4960                                        void *ppriv)
4961 {
4962         int nch = profile->max_nch(mdev);
4963         struct net_device *netdev;
4964         struct mlx5e_priv *priv;
4965
4966         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4967                                     nch * profile->max_tc,
4968                                     nch);
4969         if (!netdev) {
4970                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4971                 return NULL;
4972         }
4973
4974 #ifdef CONFIG_MLX5_EN_ARFS
4975         netdev->rx_cpu_rmap = mdev->rmap;
4976 #endif
4977
4978         profile->init(mdev, netdev, profile, ppriv);
4979
4980         netif_carrier_off(netdev);
4981
4982         priv = netdev_priv(netdev);
4983
4984         priv->wq = create_singlethread_workqueue("mlx5e");
4985         if (!priv->wq)
4986                 goto err_cleanup_nic;
4987
4988         return netdev;
4989
4990 err_cleanup_nic:
4991         if (profile->cleanup)
4992                 profile->cleanup(priv);
4993         free_netdev(netdev);
4994
4995         return NULL;
4996 }
4997
4998 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4999 {
5000         struct mlx5_core_dev *mdev = priv->mdev;
5001         const struct mlx5e_profile *profile;
5002         int max_nch;
5003         int err;
5004
5005         profile = priv->profile;
5006         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5007
5008         /* max number of channels may have changed */
5009         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5010         if (priv->channels.params.num_channels > max_nch) {
5011                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5012                 priv->channels.params.num_channels = max_nch;
5013                 mlx5e_build_default_indir_rqt(priv->channels.params.indirection_rqt,
5014                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5015         }
5016
5017         err = profile->init_tx(priv);
5018         if (err)
5019                 goto out;
5020
5021         mlx5e_create_q_counters(priv);
5022
5023         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5024         if (err) {
5025                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5026                 goto err_destroy_q_counters;
5027         }
5028
5029         err = profile->init_rx(priv);
5030         if (err)
5031                 goto err_close_drop_rq;
5032
5033         if (profile->enable)
5034                 profile->enable(priv);
5035
5036         return 0;
5037
5038 err_close_drop_rq:
5039         mlx5e_close_drop_rq(&priv->drop_rq);
5040
5041 err_destroy_q_counters:
5042         mlx5e_destroy_q_counters(priv);
5043         profile->cleanup_tx(priv);
5044
5045 out:
5046         return err;
5047 }
5048
5049 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5050 {
5051         const struct mlx5e_profile *profile = priv->profile;
5052
5053         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5054
5055         if (profile->disable)
5056                 profile->disable(priv);
5057         flush_workqueue(priv->wq);
5058
5059         profile->cleanup_rx(priv);
5060         mlx5e_close_drop_rq(&priv->drop_rq);
5061         mlx5e_destroy_q_counters(priv);
5062         profile->cleanup_tx(priv);
5063         cancel_delayed_work_sync(&priv->update_stats_work);
5064 }
5065
5066 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5067 {
5068         const struct mlx5e_profile *profile = priv->profile;
5069         struct net_device *netdev = priv->netdev;
5070
5071         destroy_workqueue(priv->wq);
5072         if (profile->cleanup)
5073                 profile->cleanup(priv);
5074         free_netdev(netdev);
5075 }
5076
5077 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5078  * hardware contexts and to connect it to the current netdev.
5079  */
5080 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5081 {
5082         struct mlx5e_priv *priv = vpriv;
5083         struct net_device *netdev = priv->netdev;
5084         int err;
5085
5086         if (netif_device_present(netdev))
5087                 return 0;
5088
5089         err = mlx5e_create_mdev_resources(mdev);
5090         if (err)
5091                 return err;
5092
5093         err = mlx5e_attach_netdev(priv);
5094         if (err) {
5095                 mlx5e_destroy_mdev_resources(mdev);
5096                 return err;
5097         }
5098
5099         return 0;
5100 }
5101
5102 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5103 {
5104         struct mlx5e_priv *priv = vpriv;
5105         struct net_device *netdev = priv->netdev;
5106
5107         if (!netif_device_present(netdev))
5108                 return;
5109
5110         mlx5e_detach_netdev(priv);
5111         mlx5e_destroy_mdev_resources(mdev);
5112 }
5113
5114 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5115 {
5116         struct net_device *netdev;
5117         void *rpriv = NULL;
5118         void *priv;
5119         int err;
5120
5121         err = mlx5e_check_required_hca_cap(mdev);
5122         if (err)
5123                 return NULL;
5124
5125 #ifdef CONFIG_MLX5_ESWITCH
5126         if (MLX5_ESWITCH_MANAGER(mdev)) {
5127                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5128                 if (!rpriv) {
5129                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5130                         return NULL;
5131                 }
5132         }
5133 #endif
5134
5135         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
5136         if (!netdev) {
5137                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5138                 goto err_free_rpriv;
5139         }
5140
5141         priv = netdev_priv(netdev);
5142
5143         err = mlx5e_attach(mdev, priv);
5144         if (err) {
5145                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5146                 goto err_destroy_netdev;
5147         }
5148
5149         err = register_netdev(netdev);
5150         if (err) {
5151                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5152                 goto err_detach;
5153         }
5154
5155 #ifdef CONFIG_MLX5_CORE_EN_DCB
5156         mlx5e_dcbnl_init_app(priv);
5157 #endif
5158         return priv;
5159
5160 err_detach:
5161         mlx5e_detach(mdev, priv);
5162 err_destroy_netdev:
5163         mlx5e_destroy_netdev(priv);
5164 err_free_rpriv:
5165         kfree(rpriv);
5166         return NULL;
5167 }
5168
5169 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5170 {
5171         struct mlx5e_priv *priv = vpriv;
5172         void *ppriv = priv->ppriv;
5173
5174 #ifdef CONFIG_MLX5_CORE_EN_DCB
5175         mlx5e_dcbnl_delete_app(priv);
5176 #endif
5177         unregister_netdev(priv->netdev);
5178         mlx5e_detach(mdev, vpriv);
5179         mlx5e_destroy_netdev(priv);
5180         kfree(ppriv);
5181 }
5182
5183 static void *mlx5e_get_netdev(void *vpriv)
5184 {
5185         struct mlx5e_priv *priv = vpriv;
5186
5187         return priv->netdev;
5188 }
5189
5190 static struct mlx5_interface mlx5e_interface = {
5191         .add       = mlx5e_add,
5192         .remove    = mlx5e_remove,
5193         .attach    = mlx5e_attach,
5194         .detach    = mlx5e_detach,
5195         .event     = mlx5e_async_event,
5196         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5197         .get_dev   = mlx5e_get_netdev,
5198 };
5199
5200 void mlx5e_init(void)
5201 {
5202         mlx5e_ipsec_build_inverse_table();
5203         mlx5e_build_ptys2ethtool_map();
5204         mlx5_register_interface(&mlx5e_interface);
5205 }
5206
5207 void mlx5e_cleanup(void)
5208 {
5209         mlx5_unregister_interface(&mlx5e_interface);
5210 }