2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
38 #include <net/page_pool.h>
43 #include "en_accel/ipsec.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "en_accel/tls.h"
46 #include "accel/ipsec.h"
47 #include "accel/tls.h"
48 #include "lib/vxlan.h"
49 #include "lib/clock.h"
53 struct mlx5e_rq_param {
54 u32 rqc[MLX5_ST_SZ_DW(rqc)];
55 struct mlx5_wq_param wq;
56 struct mlx5e_rq_frags_info frags_info;
59 struct mlx5e_sq_param {
60 u32 sqc[MLX5_ST_SZ_DW(sqc)];
61 struct mlx5_wq_param wq;
64 struct mlx5e_cq_param {
65 u32 cqc[MLX5_ST_SZ_DW(cqc)];
66 struct mlx5_wq_param wq;
71 struct mlx5e_channel_param {
72 struct mlx5e_rq_param rq;
73 struct mlx5e_sq_param sq;
74 struct mlx5e_sq_param xdp_sq;
75 struct mlx5e_sq_param icosq;
76 struct mlx5e_cq_param rx_cq;
77 struct mlx5e_cq_param tx_cq;
78 struct mlx5e_cq_param icosq_cq;
81 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
83 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
84 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
85 MLX5_CAP_ETH(mdev, reg_umr_sq);
86 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
87 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
92 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
93 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
99 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
101 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
102 u16 linear_rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
106 linear_rq_headroom += NET_IP_ALIGN;
108 frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
110 if (params->xdp_prog && frag_sz < PAGE_SIZE)
116 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
118 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
120 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
123 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
124 struct mlx5e_params *params)
126 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
128 return !params->lro_en && frag_sz <= PAGE_SIZE;
131 #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \
132 MLX5_MPWQE_LOG_STRIDE_SZ_BASE)
133 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
134 struct mlx5e_params *params)
136 u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
137 s8 signed_log_num_strides_param;
140 if (!mlx5e_rx_is_linear_skb(mdev, params))
143 if (order_base_2(frag_sz) > MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ)
146 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
149 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
150 signed_log_num_strides_param =
151 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
153 return signed_log_num_strides_param >= 0;
156 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
158 if (params->log_rq_mtu_frames <
159 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
160 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
162 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
165 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
166 struct mlx5e_params *params)
168 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
169 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
171 return MLX5E_MPWQE_STRIDE_SZ(mdev,
172 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
175 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
176 struct mlx5e_params *params)
178 return MLX5_MPWRQ_LOG_WQE_SZ -
179 mlx5e_mpwqe_get_log_stride_size(mdev, params);
182 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
183 struct mlx5e_params *params)
185 u16 linear_rq_headroom = params->xdp_prog ?
186 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
189 linear_rq_headroom += NET_IP_ALIGN;
191 is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
192 mlx5e_rx_is_linear_skb(mdev, params) :
193 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
195 return is_linear_skb ? linear_rq_headroom : 0;
198 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
199 struct mlx5e_params *params)
201 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
202 params->log_rq_mtu_frames = is_kdump_kernel() ?
203 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
204 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
206 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
207 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
208 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
209 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
210 BIT(params->log_rq_mtu_frames),
211 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
212 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
215 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
216 struct mlx5e_params *params)
218 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
219 !MLX5_IPSEC_DEV(mdev) &&
220 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
223 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
225 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
226 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
227 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
231 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
233 struct mlx5_core_dev *mdev = priv->mdev;
236 port_state = mlx5_query_vport_state(mdev,
237 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
240 if (port_state == VPORT_STATE_UP) {
241 netdev_info(priv->netdev, "Link up\n");
242 netif_carrier_on(priv->netdev);
244 netdev_info(priv->netdev, "Link down\n");
245 netif_carrier_off(priv->netdev);
249 static void mlx5e_update_carrier_work(struct work_struct *work)
251 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
252 update_carrier_work);
254 mutex_lock(&priv->state_lock);
255 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
256 if (priv->profile->update_carrier)
257 priv->profile->update_carrier(priv);
258 mutex_unlock(&priv->state_lock);
261 void mlx5e_update_stats(struct mlx5e_priv *priv)
265 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
266 if (mlx5e_stats_grps[i].update_stats)
267 mlx5e_stats_grps[i].update_stats(priv);
270 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
274 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
275 if (mlx5e_stats_grps[i].update_stats_mask &
276 MLX5E_NDO_UPDATE_STATS)
277 mlx5e_stats_grps[i].update_stats(priv);
280 void mlx5e_update_stats_work(struct work_struct *work)
282 struct delayed_work *dwork = to_delayed_work(work);
283 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
286 mutex_lock(&priv->state_lock);
287 priv->profile->update_stats(priv);
288 mutex_unlock(&priv->state_lock);
291 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
292 enum mlx5_dev_event event, unsigned long param)
294 struct mlx5e_priv *priv = vpriv;
296 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
300 case MLX5_DEV_EVENT_PORT_UP:
301 case MLX5_DEV_EVENT_PORT_DOWN:
302 queue_work(priv->wq, &priv->update_carrier_work);
309 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
311 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
314 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
316 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
317 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
320 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
321 struct mlx5e_icosq *sq,
322 struct mlx5e_umr_wqe *wqe)
324 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
325 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
326 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
328 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
330 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
331 cseg->imm = rq->mkey_be;
333 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
334 ucseg->xlt_octowords =
335 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
336 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
339 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
341 switch (rq->wq_type) {
342 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
343 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
345 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
349 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
351 switch (rq->wq_type) {
352 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
353 return rq->mpwqe.wq.cur_sz;
355 return rq->wqe.wq.cur_sz;
359 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
360 struct mlx5e_channel *c)
362 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
364 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
365 sizeof(*rq->mpwqe.info)),
366 GFP_KERNEL, cpu_to_node(c->cpu));
370 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
375 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
376 u64 npages, u8 page_shift,
377 struct mlx5_core_mkey *umr_mkey)
379 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
384 in = kvzalloc(inlen, GFP_KERNEL);
388 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
390 MLX5_SET(mkc, mkc, free, 1);
391 MLX5_SET(mkc, mkc, umr_en, 1);
392 MLX5_SET(mkc, mkc, lw, 1);
393 MLX5_SET(mkc, mkc, lr, 1);
394 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
396 MLX5_SET(mkc, mkc, qpn, 0xffffff);
397 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
398 MLX5_SET64(mkc, mkc, len, npages << page_shift);
399 MLX5_SET(mkc, mkc, translations_octword_size,
400 MLX5_MTT_OCTW(npages));
401 MLX5_SET(mkc, mkc, log_page_size, page_shift);
403 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
409 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
411 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
413 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
416 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
418 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
421 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
423 struct mlx5e_wqe_frag_info next_frag = {};
424 struct mlx5e_wqe_frag_info *prev = NULL;
427 next_frag.di = &rq->wqe.di[0];
429 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
430 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
431 struct mlx5e_wqe_frag_info *frag =
432 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
435 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
436 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
438 next_frag.offset = 0;
440 prev->last_in_page = true;
445 next_frag.offset += frag_info[f].frag_stride;
451 prev->last_in_page = true;
454 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
455 struct mlx5e_params *params,
458 int len = wq_sz << rq->wqe.info.log_num_frags;
460 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
461 GFP_KERNEL, cpu_to_node(cpu));
465 mlx5e_init_frags_partition(rq);
470 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
475 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
476 struct mlx5e_params *params,
477 struct mlx5e_rq_param *rqp,
480 struct page_pool_params pp_params = { 0 };
481 struct mlx5_core_dev *mdev = c->mdev;
482 void *rqc = rqp->rqc;
483 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
489 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
491 rq->wq_type = params->rq_wq_type;
493 rq->netdev = c->netdev;
494 rq->tstamp = c->tstamp;
495 rq->clock = &mdev->clock;
499 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
500 rq->stats = &c->priv->channel_stats[c->ix].rq;
502 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
503 if (IS_ERR(rq->xdp_prog)) {
504 err = PTR_ERR(rq->xdp_prog);
506 goto err_rq_wq_destroy;
509 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
511 goto err_rq_wq_destroy;
513 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
514 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
515 pool_size = 1 << params->log_rq_mtu_frames;
517 switch (rq->wq_type) {
518 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
519 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
522 goto err_rq_wq_destroy;
524 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
526 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
528 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
530 rq->post_wqes = mlx5e_post_rx_mpwqes;
531 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
533 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
534 #ifdef CONFIG_MLX5_EN_IPSEC
535 if (MLX5_IPSEC_DEV(mdev)) {
537 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
538 goto err_rq_wq_destroy;
541 if (!rq->handle_rx_cqe) {
543 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
544 goto err_rq_wq_destroy;
547 rq->mpwqe.skb_from_cqe_mpwrq =
548 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
549 mlx5e_skb_from_cqe_mpwrq_linear :
550 mlx5e_skb_from_cqe_mpwrq_nonlinear;
551 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
552 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
554 err = mlx5e_create_rq_umr_mkey(mdev, rq);
556 goto err_rq_wq_destroy;
557 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
559 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
563 default: /* MLX5_WQ_TYPE_CYCLIC */
564 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
567 goto err_rq_wq_destroy;
569 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
571 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
573 rq->wqe.info = rqp->frags_info;
575 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
576 (wq_sz << rq->wqe.info.log_num_frags)),
577 GFP_KERNEL, cpu_to_node(c->cpu));
578 if (!rq->wqe.frags) {
583 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
586 rq->post_wqes = mlx5e_post_rx_wqes;
587 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
589 #ifdef CONFIG_MLX5_EN_IPSEC
591 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
594 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
595 if (!rq->handle_rx_cqe) {
597 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
601 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
602 mlx5e_skb_from_cqe_linear :
603 mlx5e_skb_from_cqe_nonlinear;
604 rq->mkey_be = c->mkey_be;
607 /* Create a page_pool and register it with rxq */
609 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
610 pp_params.pool_size = pool_size;
611 pp_params.nid = cpu_to_node(c->cpu);
612 pp_params.dev = c->pdev;
613 pp_params.dma_dir = rq->buff.map_dir;
615 /* page_pool can be used even when there is no rq->xdp_prog,
616 * given page_pool does not handle DMA mapping there is no
617 * required state to clear. And page_pool gracefully handle
620 rq->page_pool = page_pool_create(&pp_params);
621 if (IS_ERR(rq->page_pool)) {
622 err = PTR_ERR(rq->page_pool);
623 rq->page_pool = NULL;
626 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
627 MEM_TYPE_PAGE_POOL, rq->page_pool);
631 for (i = 0; i < wq_sz; i++) {
632 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
633 struct mlx5e_rx_wqe_ll *wqe =
634 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
636 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
637 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
639 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
640 wqe->data[0].byte_count = cpu_to_be32(byte_count);
641 wqe->data[0].lkey = rq->mkey_be;
643 struct mlx5e_rx_wqe_cyc *wqe =
644 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
647 for (f = 0; f < rq->wqe.info.num_frags; f++) {
648 u32 frag_size = rq->wqe.info.arr[f].frag_size |
649 MLX5_HW_START_PADDING;
651 wqe->data[f].byte_count = cpu_to_be32(frag_size);
652 wqe->data[f].lkey = rq->mkey_be;
654 /* check if num_frags is not a pow of two */
655 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
656 wqe->data[f].byte_count = 0;
657 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
658 wqe->data[f].addr = 0;
663 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
665 switch (params->rx_cq_moderation.cq_period_mode) {
666 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
667 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
669 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
671 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
674 rq->page_cache.head = 0;
675 rq->page_cache.tail = 0;
680 switch (rq->wq_type) {
681 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
682 kvfree(rq->mpwqe.info);
683 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
685 default: /* MLX5_WQ_TYPE_CYCLIC */
686 kvfree(rq->wqe.frags);
687 mlx5e_free_di_list(rq);
692 bpf_prog_put(rq->xdp_prog);
693 xdp_rxq_info_unreg(&rq->xdp_rxq);
695 page_pool_destroy(rq->page_pool);
696 mlx5_wq_destroy(&rq->wq_ctrl);
701 static void mlx5e_free_rq(struct mlx5e_rq *rq)
706 bpf_prog_put(rq->xdp_prog);
708 xdp_rxq_info_unreg(&rq->xdp_rxq);
710 page_pool_destroy(rq->page_pool);
712 switch (rq->wq_type) {
713 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
714 kvfree(rq->mpwqe.info);
715 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
717 default: /* MLX5_WQ_TYPE_CYCLIC */
718 kvfree(rq->wqe.frags);
719 mlx5e_free_di_list(rq);
722 for (i = rq->page_cache.head; i != rq->page_cache.tail;
723 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
724 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
726 mlx5e_page_release(rq, dma_info, false);
728 mlx5_wq_destroy(&rq->wq_ctrl);
731 static int mlx5e_create_rq(struct mlx5e_rq *rq,
732 struct mlx5e_rq_param *param)
734 struct mlx5_core_dev *mdev = rq->mdev;
742 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
743 sizeof(u64) * rq->wq_ctrl.buf.npages;
744 in = kvzalloc(inlen, GFP_KERNEL);
748 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
749 wq = MLX5_ADDR_OF(rqc, rqc, wq);
751 memcpy(rqc, param->rqc, sizeof(param->rqc));
753 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
754 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
755 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
756 MLX5_ADAPTER_PAGE_SHIFT);
757 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
759 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
760 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
762 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
769 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
772 struct mlx5_core_dev *mdev = rq->mdev;
779 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
780 in = kvzalloc(inlen, GFP_KERNEL);
784 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
786 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
787 MLX5_SET(rqc, rqc, state, next_state);
789 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
796 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
798 struct mlx5e_channel *c = rq->channel;
799 struct mlx5e_priv *priv = c->priv;
800 struct mlx5_core_dev *mdev = priv->mdev;
807 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
808 in = kvzalloc(inlen, GFP_KERNEL);
812 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
814 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
815 MLX5_SET64(modify_rq_in, in, modify_bitmask,
816 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
817 MLX5_SET(rqc, rqc, scatter_fcs, enable);
818 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
820 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
827 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
829 struct mlx5e_channel *c = rq->channel;
830 struct mlx5_core_dev *mdev = c->mdev;
836 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
837 in = kvzalloc(inlen, GFP_KERNEL);
841 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
843 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
844 MLX5_SET64(modify_rq_in, in, modify_bitmask,
845 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
846 MLX5_SET(rqc, rqc, vsd, vsd);
847 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
849 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
856 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
858 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
861 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
863 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
864 struct mlx5e_channel *c = rq->channel;
866 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
869 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
873 } while (time_before(jiffies, exp_time));
875 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
876 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
881 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
886 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
887 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
889 /* UMR WQE (if in progress) is always at wq->head */
890 if (rq->mpwqe.umr_in_progress)
891 rq->dealloc_wqe(rq, wq->head);
893 while (!mlx5_wq_ll_is_empty(wq)) {
894 struct mlx5e_rx_wqe_ll *wqe;
896 wqe_ix_be = *wq->tail_next;
897 wqe_ix = be16_to_cpu(wqe_ix_be);
898 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
899 rq->dealloc_wqe(rq, wqe_ix);
900 mlx5_wq_ll_pop(wq, wqe_ix_be,
901 &wqe->next.next_wqe_index);
904 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
906 while (!mlx5_wq_cyc_is_empty(wq)) {
907 wqe_ix = mlx5_wq_cyc_get_tail(wq);
908 rq->dealloc_wqe(rq, wqe_ix);
915 static int mlx5e_open_rq(struct mlx5e_channel *c,
916 struct mlx5e_params *params,
917 struct mlx5e_rq_param *param,
922 err = mlx5e_alloc_rq(c, params, param, rq);
926 err = mlx5e_create_rq(rq, param);
930 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
934 if (params->rx_dim_enabled)
935 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
937 /* We disable csum_complete when XDP is enabled since
938 * XDP programs might manipulate packets which will render
939 * skb->checksum incorrect.
941 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
942 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
947 mlx5e_destroy_rq(rq);
954 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
956 struct mlx5e_icosq *sq = &rq->channel->icosq;
957 struct mlx5_wq_cyc *wq = &sq->wq;
958 struct mlx5e_tx_wqe *nopwqe;
960 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
962 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
963 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
964 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
965 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
968 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
970 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
971 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
974 static void mlx5e_close_rq(struct mlx5e_rq *rq)
976 cancel_work_sync(&rq->dim.work);
977 mlx5e_destroy_rq(rq);
978 mlx5e_free_rx_descs(rq);
982 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
987 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
989 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
991 sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
994 mlx5e_free_xdpsq_db(sq);
1001 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1002 struct mlx5e_params *params,
1003 struct mlx5e_sq_param *param,
1004 struct mlx5e_xdpsq *sq,
1007 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1008 struct mlx5_core_dev *mdev = c->mdev;
1009 struct mlx5_wq_cyc *wq = &sq->wq;
1013 sq->mkey_be = c->mkey_be;
1015 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1016 sq->min_inline_mode = params->tx_min_inline_mode;
1017 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1018 sq->stats = is_redirect ?
1019 &c->priv->channel_stats[c->ix].xdpsq :
1020 &c->priv->channel_stats[c->ix].rq_xdpsq;
1022 param->wq.db_numa_node = cpu_to_node(c->cpu);
1023 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1026 wq->db = &wq->db[MLX5_SND_DBR];
1028 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1030 goto err_sq_wq_destroy;
1035 mlx5_wq_destroy(&sq->wq_ctrl);
1040 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1042 mlx5e_free_xdpsq_db(sq);
1043 mlx5_wq_destroy(&sq->wq_ctrl);
1046 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1048 kvfree(sq->db.ico_wqe);
1051 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1053 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1055 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1056 sizeof(*sq->db.ico_wqe)),
1058 if (!sq->db.ico_wqe)
1064 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1065 struct mlx5e_sq_param *param,
1066 struct mlx5e_icosq *sq)
1068 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1069 struct mlx5_core_dev *mdev = c->mdev;
1070 struct mlx5_wq_cyc *wq = &sq->wq;
1074 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1076 param->wq.db_numa_node = cpu_to_node(c->cpu);
1077 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1080 wq->db = &wq->db[MLX5_SND_DBR];
1082 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1084 goto err_sq_wq_destroy;
1089 mlx5_wq_destroy(&sq->wq_ctrl);
1094 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1096 mlx5e_free_icosq_db(sq);
1097 mlx5_wq_destroy(&sq->wq_ctrl);
1100 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1102 kvfree(sq->db.wqe_info);
1103 kvfree(sq->db.dma_fifo);
1106 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1108 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1109 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1111 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1112 sizeof(*sq->db.dma_fifo)),
1114 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1115 sizeof(*sq->db.wqe_info)),
1117 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1118 mlx5e_free_txqsq_db(sq);
1122 sq->dma_fifo_mask = df_sz - 1;
1127 static void mlx5e_sq_recover(struct work_struct *work);
1128 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1130 struct mlx5e_params *params,
1131 struct mlx5e_sq_param *param,
1132 struct mlx5e_txqsq *sq,
1135 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1136 struct mlx5_core_dev *mdev = c->mdev;
1137 struct mlx5_wq_cyc *wq = &sq->wq;
1141 sq->tstamp = c->tstamp;
1142 sq->clock = &mdev->clock;
1143 sq->mkey_be = c->mkey_be;
1145 sq->txq_ix = txq_ix;
1146 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1147 sq->min_inline_mode = params->tx_min_inline_mode;
1148 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1149 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1150 if (MLX5_IPSEC_DEV(c->priv->mdev))
1151 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1152 if (mlx5_accel_is_tls_device(c->priv->mdev))
1153 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1155 param->wq.db_numa_node = cpu_to_node(c->cpu);
1156 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1159 wq->db = &wq->db[MLX5_SND_DBR];
1161 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1163 goto err_sq_wq_destroy;
1165 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1166 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1171 mlx5_wq_destroy(&sq->wq_ctrl);
1176 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1178 mlx5e_free_txqsq_db(sq);
1179 mlx5_wq_destroy(&sq->wq_ctrl);
1182 struct mlx5e_create_sq_param {
1183 struct mlx5_wq_ctrl *wq_ctrl;
1190 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1191 struct mlx5e_sq_param *param,
1192 struct mlx5e_create_sq_param *csp,
1201 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1202 sizeof(u64) * csp->wq_ctrl->buf.npages;
1203 in = kvzalloc(inlen, GFP_KERNEL);
1207 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1208 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1210 memcpy(sqc, param->sqc, sizeof(param->sqc));
1211 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1212 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1213 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1215 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1216 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1218 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1219 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1221 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1222 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1223 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1224 MLX5_ADAPTER_PAGE_SHIFT);
1225 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1227 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1228 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1230 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1237 struct mlx5e_modify_sq_param {
1244 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1245 struct mlx5e_modify_sq_param *p)
1252 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1253 in = kvzalloc(inlen, GFP_KERNEL);
1257 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1259 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1260 MLX5_SET(sqc, sqc, state, p->next_state);
1261 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1262 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1263 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1266 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1273 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1275 mlx5_core_destroy_sq(mdev, sqn);
1278 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1279 struct mlx5e_sq_param *param,
1280 struct mlx5e_create_sq_param *csp,
1283 struct mlx5e_modify_sq_param msp = {0};
1286 err = mlx5e_create_sq(mdev, param, csp, sqn);
1290 msp.curr_state = MLX5_SQC_STATE_RST;
1291 msp.next_state = MLX5_SQC_STATE_RDY;
1292 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1294 mlx5e_destroy_sq(mdev, *sqn);
1299 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1300 struct mlx5e_txqsq *sq, u32 rate);
1302 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1305 struct mlx5e_params *params,
1306 struct mlx5e_sq_param *param,
1307 struct mlx5e_txqsq *sq,
1310 struct mlx5e_create_sq_param csp = {};
1314 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1320 csp.cqn = sq->cq.mcq.cqn;
1321 csp.wq_ctrl = &sq->wq_ctrl;
1322 csp.min_inline_mode = sq->min_inline_mode;
1323 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1325 goto err_free_txqsq;
1327 tx_rate = c->priv->tx_rates[sq->txq_ix];
1329 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1331 if (params->tx_dim_enabled)
1332 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1337 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1338 mlx5e_free_txqsq(sq);
1343 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1345 WARN_ONCE(sq->cc != sq->pc,
1346 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1347 sq->sqn, sq->cc, sq->pc);
1349 sq->dma_fifo_cc = 0;
1353 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1355 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1356 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1357 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1358 netdev_tx_reset_queue(sq->txq);
1359 netif_tx_start_queue(sq->txq);
1362 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1364 __netif_tx_lock_bh(txq);
1365 netif_tx_stop_queue(txq);
1366 __netif_tx_unlock_bh(txq);
1369 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1371 struct mlx5e_channel *c = sq->channel;
1372 struct mlx5_wq_cyc *wq = &sq->wq;
1374 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1375 /* prevent netif_tx_wake_queue */
1376 napi_synchronize(&c->napi);
1378 netif_tx_disable_queue(sq->txq);
1380 /* last doorbell out, godspeed .. */
1381 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1382 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1383 struct mlx5e_tx_wqe *nop;
1385 sq->db.wqe_info[pi].skb = NULL;
1386 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1387 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1391 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1393 struct mlx5e_channel *c = sq->channel;
1394 struct mlx5_core_dev *mdev = c->mdev;
1395 struct mlx5_rate_limit rl = {0};
1397 cancel_work_sync(&sq->dim.work);
1398 mlx5e_destroy_sq(mdev, sq->sqn);
1399 if (sq->rate_limit) {
1400 rl.rate = sq->rate_limit;
1401 mlx5_rl_remove_rate(mdev, &rl);
1403 mlx5e_free_txqsq_descs(sq);
1404 mlx5e_free_txqsq(sq);
1407 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1409 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1411 while (time_before(jiffies, exp_time)) {
1412 if (sq->cc == sq->pc)
1418 netdev_err(sq->channel->netdev,
1419 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1420 sq->sqn, sq->cc, sq->pc);
1425 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1427 struct mlx5_core_dev *mdev = sq->channel->mdev;
1428 struct net_device *dev = sq->channel->netdev;
1429 struct mlx5e_modify_sq_param msp = {0};
1432 msp.curr_state = curr_state;
1433 msp.next_state = MLX5_SQC_STATE_RST;
1435 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1437 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1441 memset(&msp, 0, sizeof(msp));
1442 msp.curr_state = MLX5_SQC_STATE_RST;
1443 msp.next_state = MLX5_SQC_STATE_RDY;
1445 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1447 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1454 static void mlx5e_sq_recover(struct work_struct *work)
1456 struct mlx5e_txqsq_recover *recover =
1457 container_of(work, struct mlx5e_txqsq_recover,
1459 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1461 struct mlx5_core_dev *mdev = sq->channel->mdev;
1462 struct net_device *dev = sq->channel->netdev;
1466 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1468 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1473 if (state != MLX5_RQC_STATE_ERR) {
1474 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1478 netif_tx_disable_queue(sq->txq);
1480 if (mlx5e_wait_for_sq_flush(sq))
1483 /* If the interval between two consecutive recovers per SQ is too
1484 * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1485 * If we reached this state, there is probably a bug that needs to be
1486 * fixed. let's keep the queue close and let tx timeout cleanup.
1488 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1489 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1490 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1495 /* At this point, no new packets will arrive from the stack as TXQ is
1496 * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1497 * pending WQEs. SQ can safely reset the SQ.
1499 if (mlx5e_sq_to_ready(sq, state))
1502 mlx5e_reset_txqsq_cc_pc(sq);
1503 sq->stats->recover++;
1504 recover->last_recover = jiffies;
1505 mlx5e_activate_txqsq(sq);
1508 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1509 struct mlx5e_params *params,
1510 struct mlx5e_sq_param *param,
1511 struct mlx5e_icosq *sq)
1513 struct mlx5e_create_sq_param csp = {};
1516 err = mlx5e_alloc_icosq(c, param, sq);
1520 csp.cqn = sq->cq.mcq.cqn;
1521 csp.wq_ctrl = &sq->wq_ctrl;
1522 csp.min_inline_mode = params->tx_min_inline_mode;
1523 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1524 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1526 goto err_free_icosq;
1531 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532 mlx5e_free_icosq(sq);
1537 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1539 struct mlx5e_channel *c = sq->channel;
1541 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1542 napi_synchronize(&c->napi);
1544 mlx5e_destroy_sq(c->mdev, sq->sqn);
1545 mlx5e_free_icosq(sq);
1548 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1549 struct mlx5e_params *params,
1550 struct mlx5e_sq_param *param,
1551 struct mlx5e_xdpsq *sq,
1554 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1555 struct mlx5e_create_sq_param csp = {};
1556 unsigned int inline_hdr_sz = 0;
1560 err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1565 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1566 csp.cqn = sq->cq.mcq.cqn;
1567 csp.wq_ctrl = &sq->wq_ctrl;
1568 csp.min_inline_mode = sq->min_inline_mode;
1570 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1571 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1572 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1574 goto err_free_xdpsq;
1576 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1577 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1581 /* Pre initialize fixed WQE fields */
1582 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1583 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1584 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1585 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1586 struct mlx5_wqe_data_seg *dseg;
1588 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1589 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1591 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1592 dseg->lkey = sq->mkey_be;
1598 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1599 mlx5e_free_xdpsq(sq);
1604 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1606 struct mlx5e_channel *c = sq->channel;
1608 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1609 napi_synchronize(&c->napi);
1611 mlx5e_destroy_sq(c->mdev, sq->sqn);
1612 mlx5e_free_xdpsq_descs(sq);
1613 mlx5e_free_xdpsq(sq);
1616 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1617 struct mlx5e_cq_param *param,
1618 struct mlx5e_cq *cq)
1620 struct mlx5_core_cq *mcq = &cq->mcq;
1626 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1630 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1636 mcq->set_ci_db = cq->wq_ctrl.db.db;
1637 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1638 *mcq->set_ci_db = 0;
1640 mcq->vector = param->eq_ix;
1641 mcq->comp = mlx5e_completion_event;
1642 mcq->event = mlx5e_cq_error_event;
1645 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1646 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1656 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1657 struct mlx5e_cq_param *param,
1658 struct mlx5e_cq *cq)
1660 struct mlx5_core_dev *mdev = c->priv->mdev;
1663 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1664 param->wq.db_numa_node = cpu_to_node(c->cpu);
1665 param->eq_ix = c->ix;
1667 err = mlx5e_alloc_cq_common(mdev, param, cq);
1669 cq->napi = &c->napi;
1675 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1677 mlx5_wq_destroy(&cq->wq_ctrl);
1680 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1682 struct mlx5_core_dev *mdev = cq->mdev;
1683 struct mlx5_core_cq *mcq = &cq->mcq;
1688 unsigned int irqn_not_used;
1692 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1696 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1697 sizeof(u64) * cq->wq_ctrl.buf.npages;
1698 in = kvzalloc(inlen, GFP_KERNEL);
1702 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1704 memcpy(cqc, param->cqc, sizeof(param->cqc));
1706 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1707 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1709 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1710 MLX5_SET(cqc, cqc, c_eqn, eqn);
1711 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1712 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1713 MLX5_ADAPTER_PAGE_SHIFT);
1714 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1716 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1728 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1730 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1733 static int mlx5e_open_cq(struct mlx5e_channel *c,
1734 struct net_dim_cq_moder moder,
1735 struct mlx5e_cq_param *param,
1736 struct mlx5e_cq *cq)
1738 struct mlx5_core_dev *mdev = c->mdev;
1741 err = mlx5e_alloc_cq(c, param, cq);
1745 err = mlx5e_create_cq(cq, param);
1749 if (MLX5_CAP_GEN(mdev, cq_moderation))
1750 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1759 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1761 mlx5e_destroy_cq(cq);
1765 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1767 return cpumask_first(priv->mdev->priv.irq_info[ix + MLX5_EQ_VEC_COMP_BASE].mask);
1770 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1771 struct mlx5e_params *params,
1772 struct mlx5e_channel_param *cparam)
1777 for (tc = 0; tc < c->num_tc; tc++) {
1778 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1779 &cparam->tx_cq, &c->sq[tc].cq);
1781 goto err_close_tx_cqs;
1787 for (tc--; tc >= 0; tc--)
1788 mlx5e_close_cq(&c->sq[tc].cq);
1793 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1797 for (tc = 0; tc < c->num_tc; tc++)
1798 mlx5e_close_cq(&c->sq[tc].cq);
1801 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1802 struct mlx5e_params *params,
1803 struct mlx5e_channel_param *cparam)
1805 struct mlx5e_priv *priv = c->priv;
1806 int err, tc, max_nch = priv->profile->max_nch(priv->mdev);
1808 for (tc = 0; tc < params->num_tc; tc++) {
1809 int txq_ix = c->ix + tc * max_nch;
1811 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1812 params, &cparam->sq, &c->sq[tc], tc);
1820 for (tc--; tc >= 0; tc--)
1821 mlx5e_close_txqsq(&c->sq[tc]);
1826 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1830 for (tc = 0; tc < c->num_tc; tc++)
1831 mlx5e_close_txqsq(&c->sq[tc]);
1834 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1835 struct mlx5e_txqsq *sq, u32 rate)
1837 struct mlx5e_priv *priv = netdev_priv(dev);
1838 struct mlx5_core_dev *mdev = priv->mdev;
1839 struct mlx5e_modify_sq_param msp = {0};
1840 struct mlx5_rate_limit rl = {0};
1844 if (rate == sq->rate_limit)
1848 if (sq->rate_limit) {
1849 rl.rate = sq->rate_limit;
1850 /* remove current rl index to free space to next ones */
1851 mlx5_rl_remove_rate(mdev, &rl);
1858 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1860 netdev_err(dev, "Failed configuring rate %u: %d\n",
1866 msp.curr_state = MLX5_SQC_STATE_RDY;
1867 msp.next_state = MLX5_SQC_STATE_RDY;
1868 msp.rl_index = rl_index;
1869 msp.rl_update = true;
1870 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1872 netdev_err(dev, "Failed configuring rate %u: %d\n",
1874 /* remove the rate from the table */
1876 mlx5_rl_remove_rate(mdev, &rl);
1880 sq->rate_limit = rate;
1884 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1886 struct mlx5e_priv *priv = netdev_priv(dev);
1887 struct mlx5_core_dev *mdev = priv->mdev;
1888 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1891 if (!mlx5_rl_is_supported(mdev)) {
1892 netdev_err(dev, "Rate limiting is not supported on this device\n");
1896 /* rate is given in Mb/sec, HW config is in Kb/sec */
1899 /* Check whether rate in valid range, 0 is always valid */
1900 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1901 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1905 mutex_lock(&priv->state_lock);
1906 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1907 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1909 priv->tx_rates[index] = rate;
1910 mutex_unlock(&priv->state_lock);
1915 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1916 struct mlx5e_params *params,
1917 struct mlx5e_channel_param *cparam,
1918 struct mlx5e_channel **cp)
1920 struct net_dim_cq_moder icocq_moder = {0, 0};
1921 struct net_device *netdev = priv->netdev;
1922 int cpu = mlx5e_get_cpu(priv, ix);
1923 struct mlx5e_channel *c;
1928 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1932 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1937 c->mdev = priv->mdev;
1938 c->tstamp = &priv->tstamp;
1941 c->pdev = &priv->mdev->pdev->dev;
1942 c->netdev = priv->netdev;
1943 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1944 c->num_tc = params->num_tc;
1945 c->xdp = !!params->xdp_prog;
1946 c->stats = &priv->channel_stats[ix].ch;
1948 c->irq_desc = irq_to_desc(irq);
1950 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1952 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1956 err = mlx5e_open_tx_cqs(c, params, cparam);
1958 goto err_close_icosq_cq;
1960 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1962 goto err_close_tx_cqs;
1964 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1966 goto err_close_xdp_tx_cqs;
1968 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1969 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1970 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1972 goto err_close_rx_cq;
1974 napi_enable(&c->napi);
1976 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1978 goto err_disable_napi;
1980 err = mlx5e_open_sqs(c, params, cparam);
1982 goto err_close_icosq;
1984 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1988 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1990 goto err_close_xdp_sq;
1992 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
2001 mlx5e_close_rq(&c->rq);
2005 mlx5e_close_xdpsq(&c->rq.xdpsq);
2011 mlx5e_close_icosq(&c->icosq);
2014 napi_disable(&c->napi);
2016 mlx5e_close_cq(&c->rq.xdpsq.cq);
2019 mlx5e_close_cq(&c->rq.cq);
2021 err_close_xdp_tx_cqs:
2022 mlx5e_close_cq(&c->xdpsq.cq);
2025 mlx5e_close_tx_cqs(c);
2028 mlx5e_close_cq(&c->icosq.cq);
2031 netif_napi_del(&c->napi);
2037 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2041 for (tc = 0; tc < c->num_tc; tc++)
2042 mlx5e_activate_txqsq(&c->sq[tc]);
2043 mlx5e_activate_rq(&c->rq);
2044 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2047 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2051 mlx5e_deactivate_rq(&c->rq);
2052 for (tc = 0; tc < c->num_tc; tc++)
2053 mlx5e_deactivate_txqsq(&c->sq[tc]);
2056 static void mlx5e_close_channel(struct mlx5e_channel *c)
2058 mlx5e_close_xdpsq(&c->xdpsq);
2059 mlx5e_close_rq(&c->rq);
2061 mlx5e_close_xdpsq(&c->rq.xdpsq);
2063 mlx5e_close_icosq(&c->icosq);
2064 napi_disable(&c->napi);
2066 mlx5e_close_cq(&c->rq.xdpsq.cq);
2067 mlx5e_close_cq(&c->rq.cq);
2068 mlx5e_close_cq(&c->xdpsq.cq);
2069 mlx5e_close_tx_cqs(c);
2070 mlx5e_close_cq(&c->icosq.cq);
2071 netif_napi_del(&c->napi);
2076 #define DEFAULT_FRAG_SIZE (2048)
2078 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2079 struct mlx5e_params *params,
2080 struct mlx5e_rq_frags_info *info)
2082 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2083 int frag_size_max = DEFAULT_FRAG_SIZE;
2087 #ifdef CONFIG_MLX5_EN_IPSEC
2088 if (MLX5_IPSEC_DEV(mdev))
2089 byte_count += MLX5E_METADATA_ETHER_LEN;
2092 if (mlx5e_rx_is_linear_skb(mdev, params)) {
2095 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2096 frag_stride = roundup_pow_of_two(frag_stride);
2098 info->arr[0].frag_size = byte_count;
2099 info->arr[0].frag_stride = frag_stride;
2100 info->num_frags = 1;
2101 info->wqe_bulk = PAGE_SIZE / frag_stride;
2105 if (byte_count > PAGE_SIZE +
2106 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2107 frag_size_max = PAGE_SIZE;
2110 while (buf_size < byte_count) {
2111 int frag_size = byte_count - buf_size;
2113 if (i < MLX5E_MAX_RX_FRAGS - 1)
2114 frag_size = min(frag_size, frag_size_max);
2116 info->arr[i].frag_size = frag_size;
2117 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2119 buf_size += frag_size;
2122 info->num_frags = i;
2123 /* number of different wqes sharing a page */
2124 info->wqe_bulk = 1 + (info->num_frags % 2);
2127 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2128 info->log_num_frags = order_base_2(info->num_frags);
2131 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2133 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2136 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2137 sz += sizeof(struct mlx5e_rx_wqe_ll);
2139 default: /* MLX5_WQ_TYPE_CYCLIC */
2140 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2143 return order_base_2(sz);
2146 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2147 struct mlx5e_params *params,
2148 struct mlx5e_rq_param *param)
2150 struct mlx5_core_dev *mdev = priv->mdev;
2151 void *rqc = param->rqc;
2152 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2155 switch (params->rq_wq_type) {
2156 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2157 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2158 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2159 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2160 MLX5_SET(wq, wq, log_wqe_stride_size,
2161 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2162 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2163 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2165 default: /* MLX5_WQ_TYPE_CYCLIC */
2166 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2167 mlx5e_build_rq_frags_info(mdev, params, ¶m->frags_info);
2168 ndsegs = param->frags_info.num_frags;
2171 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2172 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2173 MLX5_SET(wq, wq, log_wq_stride,
2174 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2175 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2176 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2177 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2178 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2180 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2183 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2184 struct mlx5e_rq_param *param)
2186 struct mlx5_core_dev *mdev = priv->mdev;
2187 void *rqc = param->rqc;
2188 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2190 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2191 MLX5_SET(wq, wq, log_wq_stride,
2192 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2193 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2195 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2198 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2199 struct mlx5e_sq_param *param)
2201 void *sqc = param->sqc;
2202 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2204 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2205 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2207 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2210 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2211 struct mlx5e_params *params,
2212 struct mlx5e_sq_param *param)
2214 void *sqc = param->sqc;
2215 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2217 mlx5e_build_sq_param_common(priv, param);
2218 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2219 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2222 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2223 struct mlx5e_cq_param *param)
2225 void *cqc = param->cqc;
2227 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2230 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2231 struct mlx5e_params *params,
2232 struct mlx5e_cq_param *param)
2234 struct mlx5_core_dev *mdev = priv->mdev;
2235 void *cqc = param->cqc;
2238 switch (params->rq_wq_type) {
2239 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2240 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2241 mlx5e_mpwqe_get_log_num_strides(mdev, params);
2243 default: /* MLX5_WQ_TYPE_CYCLIC */
2244 log_cq_size = params->log_rq_mtu_frames;
2247 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2248 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2249 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2250 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2253 mlx5e_build_common_cq_param(priv, param);
2254 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2257 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2258 struct mlx5e_params *params,
2259 struct mlx5e_cq_param *param)
2261 void *cqc = param->cqc;
2263 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2265 mlx5e_build_common_cq_param(priv, param);
2266 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2269 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2271 struct mlx5e_cq_param *param)
2273 void *cqc = param->cqc;
2275 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2277 mlx5e_build_common_cq_param(priv, param);
2279 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2282 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2284 struct mlx5e_sq_param *param)
2286 void *sqc = param->sqc;
2287 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2289 mlx5e_build_sq_param_common(priv, param);
2291 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2292 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2295 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2296 struct mlx5e_params *params,
2297 struct mlx5e_sq_param *param)
2299 void *sqc = param->sqc;
2300 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2302 mlx5e_build_sq_param_common(priv, param);
2303 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2306 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2307 struct mlx5e_params *params,
2308 struct mlx5e_channel_param *cparam)
2310 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2312 mlx5e_build_rq_param(priv, params, &cparam->rq);
2313 mlx5e_build_sq_param(priv, params, &cparam->sq);
2314 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2315 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2316 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2317 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2318 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2321 int mlx5e_open_channels(struct mlx5e_priv *priv,
2322 struct mlx5e_channels *chs)
2324 struct mlx5e_channel_param *cparam;
2328 chs->num = chs->params.num_channels;
2330 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2331 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2332 if (!chs->c || !cparam)
2335 mlx5e_build_channel_param(priv, &chs->params, cparam);
2336 for (i = 0; i < chs->num; i++) {
2337 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2339 goto err_close_channels;
2346 for (i--; i >= 0; i--)
2347 mlx5e_close_channel(chs->c[i]);
2356 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2360 for (i = 0; i < chs->num; i++)
2361 mlx5e_activate_channel(chs->c[i]);
2364 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2369 for (i = 0; i < chs->num; i++)
2370 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2373 return err ? -ETIMEDOUT : 0;
2376 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2380 for (i = 0; i < chs->num; i++)
2381 mlx5e_deactivate_channel(chs->c[i]);
2384 void mlx5e_close_channels(struct mlx5e_channels *chs)
2388 for (i = 0; i < chs->num; i++)
2389 mlx5e_close_channel(chs->c[i]);
2396 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2398 struct mlx5_core_dev *mdev = priv->mdev;
2405 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2406 in = kvzalloc(inlen, GFP_KERNEL);
2410 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2412 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2413 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2415 for (i = 0; i < sz; i++)
2416 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2418 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2420 rqt->enabled = true;
2426 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2428 rqt->enabled = false;
2429 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2432 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2434 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2437 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2439 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2443 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2445 struct mlx5e_rqt *rqt;
2449 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2450 rqt = &priv->direct_tir[ix].rqt;
2451 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2453 goto err_destroy_rqts;
2459 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2460 for (ix--; ix >= 0; ix--)
2461 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2466 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2470 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2471 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2474 static int mlx5e_rx_hash_fn(int hfunc)
2476 return (hfunc == ETH_RSS_HASH_TOP) ?
2477 MLX5_RX_HASH_FN_TOEPLITZ :
2478 MLX5_RX_HASH_FN_INVERTED_XOR8;
2481 int mlx5e_bits_invert(unsigned long a, int size)
2486 for (i = 0; i < size; i++)
2487 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2492 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2493 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2497 for (i = 0; i < sz; i++) {
2503 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2504 ix = mlx5e_bits_invert(i, ilog2(sz));
2506 ix = priv->channels.params.indirection_rqt[ix];
2507 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2511 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2515 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2516 struct mlx5e_redirect_rqt_param rrp)
2518 struct mlx5_core_dev *mdev = priv->mdev;
2524 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2525 in = kvzalloc(inlen, GFP_KERNEL);
2529 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2531 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2532 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2533 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2534 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2540 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2541 struct mlx5e_redirect_rqt_param rrp)
2546 if (ix >= rrp.rss.channels->num)
2547 return priv->drop_rq.rqn;
2549 return rrp.rss.channels->c[ix]->rq.rqn;
2552 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2553 struct mlx5e_redirect_rqt_param rrp)
2558 if (priv->indir_rqt.enabled) {
2560 rqtn = priv->indir_rqt.rqtn;
2561 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2564 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2565 struct mlx5e_redirect_rqt_param direct_rrp = {
2568 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2572 /* Direct RQ Tables */
2573 if (!priv->direct_tir[ix].rqt.enabled)
2576 rqtn = priv->direct_tir[ix].rqt.rqtn;
2577 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2581 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2582 struct mlx5e_channels *chs)
2584 struct mlx5e_redirect_rqt_param rrp = {
2589 .hfunc = chs->params.rss_hfunc,
2594 mlx5e_redirect_rqts(priv, rrp);
2597 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2599 struct mlx5e_redirect_rqt_param drop_rrp = {
2602 .rqn = priv->drop_rq.rqn,
2606 mlx5e_redirect_rqts(priv, drop_rrp);
2609 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2611 if (!params->lro_en)
2614 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2616 MLX5_SET(tirc, tirc, lro_enable_mask,
2617 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2618 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2619 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2620 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2621 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2624 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2625 enum mlx5e_traffic_types tt,
2626 void *tirc, bool inner)
2628 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2629 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2631 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2632 MLX5_HASH_FIELD_SEL_DST_IP)
2634 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2635 MLX5_HASH_FIELD_SEL_DST_IP |\
2636 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2637 MLX5_HASH_FIELD_SEL_L4_DPORT)
2639 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2640 MLX5_HASH_FIELD_SEL_DST_IP |\
2641 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2643 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2644 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2645 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2646 rx_hash_toeplitz_key);
2647 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2648 rx_hash_toeplitz_key);
2650 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2651 memcpy(rss_key, params->toeplitz_hash_key, len);
2655 case MLX5E_TT_IPV4_TCP:
2656 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2657 MLX5_L3_PROT_TYPE_IPV4);
2658 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2659 MLX5_L4_PROT_TYPE_TCP);
2660 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2661 MLX5_HASH_IP_L4PORTS);
2664 case MLX5E_TT_IPV6_TCP:
2665 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2666 MLX5_L3_PROT_TYPE_IPV6);
2667 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2668 MLX5_L4_PROT_TYPE_TCP);
2669 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2670 MLX5_HASH_IP_L4PORTS);
2673 case MLX5E_TT_IPV4_UDP:
2674 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2675 MLX5_L3_PROT_TYPE_IPV4);
2676 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2677 MLX5_L4_PROT_TYPE_UDP);
2678 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2679 MLX5_HASH_IP_L4PORTS);
2682 case MLX5E_TT_IPV6_UDP:
2683 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2684 MLX5_L3_PROT_TYPE_IPV6);
2685 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2686 MLX5_L4_PROT_TYPE_UDP);
2687 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2688 MLX5_HASH_IP_L4PORTS);
2691 case MLX5E_TT_IPV4_IPSEC_AH:
2692 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2693 MLX5_L3_PROT_TYPE_IPV4);
2694 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695 MLX5_HASH_IP_IPSEC_SPI);
2698 case MLX5E_TT_IPV6_IPSEC_AH:
2699 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2700 MLX5_L3_PROT_TYPE_IPV6);
2701 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2702 MLX5_HASH_IP_IPSEC_SPI);
2705 case MLX5E_TT_IPV4_IPSEC_ESP:
2706 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2707 MLX5_L3_PROT_TYPE_IPV4);
2708 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2709 MLX5_HASH_IP_IPSEC_SPI);
2712 case MLX5E_TT_IPV6_IPSEC_ESP:
2713 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2714 MLX5_L3_PROT_TYPE_IPV6);
2715 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2716 MLX5_HASH_IP_IPSEC_SPI);
2720 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2721 MLX5_L3_PROT_TYPE_IPV4);
2722 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2727 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2728 MLX5_L3_PROT_TYPE_IPV6);
2729 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2733 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2737 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2739 struct mlx5_core_dev *mdev = priv->mdev;
2748 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2749 in = kvzalloc(inlen, GFP_KERNEL);
2753 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2754 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2756 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2758 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2759 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2765 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2766 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2778 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2779 enum mlx5e_traffic_types tt,
2782 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2784 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2786 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2787 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2788 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2790 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2793 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2794 struct mlx5e_params *params, u16 mtu)
2796 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2799 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2803 /* Update vport context MTU */
2804 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2808 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2809 struct mlx5e_params *params, u16 *mtu)
2814 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2815 if (err || !hw_mtu) /* fallback to port oper mtu */
2816 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2818 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2821 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2823 struct mlx5e_params *params = &priv->channels.params;
2824 struct net_device *netdev = priv->netdev;
2825 struct mlx5_core_dev *mdev = priv->mdev;
2829 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2833 mlx5e_query_mtu(mdev, params, &mtu);
2834 if (mtu != params->sw_mtu)
2835 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2836 __func__, mtu, params->sw_mtu);
2838 params->sw_mtu = mtu;
2842 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2844 struct mlx5e_priv *priv = netdev_priv(netdev);
2845 int nch = priv->channels.params.num_channels;
2846 int ntc = priv->channels.params.num_tc;
2849 netdev_reset_tc(netdev);
2854 netdev_set_num_tc(netdev, ntc);
2856 /* Map netdev TCs to offset 0
2857 * We have our own UP to TXQ mapping for QoS
2859 for (tc = 0; tc < ntc; tc++)
2860 netdev_set_tc_queue(netdev, tc, nch, 0);
2863 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2865 int max_nch = priv->profile->max_nch(priv->mdev);
2868 for (i = 0; i < max_nch; i++)
2869 for (tc = 0; tc < priv->profile->max_tc; tc++)
2870 priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2873 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2875 struct mlx5e_channel *c;
2876 struct mlx5e_txqsq *sq;
2879 for (i = 0; i < priv->channels.num; i++) {
2880 c = priv->channels.c[i];
2881 for (tc = 0; tc < c->num_tc; tc++) {
2883 priv->txq2sq[sq->txq_ix] = sq;
2888 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2890 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2891 struct net_device *netdev = priv->netdev;
2893 mlx5e_netdev_set_tcs(netdev);
2894 netif_set_real_num_tx_queues(netdev, num_txqs);
2895 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2897 mlx5e_build_tx2sq_maps(priv);
2898 mlx5e_activate_channels(&priv->channels);
2899 mlx5e_xdp_tx_enable(priv);
2900 netif_tx_start_all_queues(priv->netdev);
2902 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2903 mlx5e_add_sqs_fwd_rules(priv);
2905 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2906 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2909 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2911 mlx5e_redirect_rqts_to_drop(priv);
2913 if (MLX5_ESWITCH_MANAGER(priv->mdev))
2914 mlx5e_remove_sqs_fwd_rules(priv);
2916 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2917 * polling for inactive tx queues.
2919 netif_tx_stop_all_queues(priv->netdev);
2920 netif_tx_disable(priv->netdev);
2921 mlx5e_xdp_tx_disable(priv);
2922 mlx5e_deactivate_channels(&priv->channels);
2925 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2926 struct mlx5e_channels *new_chs,
2927 mlx5e_fp_hw_modify hw_modify)
2929 struct net_device *netdev = priv->netdev;
2932 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2934 carrier_ok = netif_carrier_ok(netdev);
2935 netif_carrier_off(netdev);
2937 if (new_num_txqs < netdev->real_num_tx_queues)
2938 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2940 mlx5e_deactivate_priv_channels(priv);
2941 mlx5e_close_channels(&priv->channels);
2943 priv->channels = *new_chs;
2945 /* New channels are ready to roll, modify HW settings if needed */
2949 mlx5e_refresh_tirs(priv, false);
2950 mlx5e_activate_priv_channels(priv);
2952 /* return carrier back if needed */
2954 netif_carrier_on(netdev);
2957 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2959 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2960 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2963 int mlx5e_open_locked(struct net_device *netdev)
2965 struct mlx5e_priv *priv = netdev_priv(netdev);
2968 set_bit(MLX5E_STATE_OPENED, &priv->state);
2970 err = mlx5e_open_channels(priv, &priv->channels);
2972 goto err_clear_state_opened_flag;
2974 mlx5e_refresh_tirs(priv, false);
2975 mlx5e_activate_priv_channels(priv);
2976 if (priv->profile->update_carrier)
2977 priv->profile->update_carrier(priv);
2979 if (priv->profile->update_stats)
2980 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2984 err_clear_state_opened_flag:
2985 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2989 int mlx5e_open(struct net_device *netdev)
2991 struct mlx5e_priv *priv = netdev_priv(netdev);
2994 mutex_lock(&priv->state_lock);
2995 err = mlx5e_open_locked(netdev);
2997 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2998 mutex_unlock(&priv->state_lock);
3000 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3001 udp_tunnel_get_rx_info(netdev);
3006 int mlx5e_close_locked(struct net_device *netdev)
3008 struct mlx5e_priv *priv = netdev_priv(netdev);
3010 /* May already be CLOSED in case a previous configuration operation
3011 * (e.g RX/TX queue size change) that involves close&open failed.
3013 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3016 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3018 netif_carrier_off(priv->netdev);
3019 mlx5e_deactivate_priv_channels(priv);
3020 mlx5e_close_channels(&priv->channels);
3025 int mlx5e_close(struct net_device *netdev)
3027 struct mlx5e_priv *priv = netdev_priv(netdev);
3030 if (!netif_device_present(netdev))
3033 mutex_lock(&priv->state_lock);
3034 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3035 err = mlx5e_close_locked(netdev);
3036 mutex_unlock(&priv->state_lock);
3041 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3042 struct mlx5e_rq *rq,
3043 struct mlx5e_rq_param *param)
3045 void *rqc = param->rqc;
3046 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3049 param->wq.db_numa_node = param->wq.buf_numa_node;
3051 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3056 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3057 xdp_rxq_info_unused(&rq->xdp_rxq);
3064 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3065 struct mlx5e_cq *cq,
3066 struct mlx5e_cq_param *param)
3068 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3069 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
3071 return mlx5e_alloc_cq_common(mdev, param, cq);
3074 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3075 struct mlx5e_rq *drop_rq)
3077 struct mlx5_core_dev *mdev = priv->mdev;
3078 struct mlx5e_cq_param cq_param = {};
3079 struct mlx5e_rq_param rq_param = {};
3080 struct mlx5e_cq *cq = &drop_rq->cq;
3083 mlx5e_build_drop_rq_param(priv, &rq_param);
3085 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3089 err = mlx5e_create_cq(cq, &cq_param);
3093 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3095 goto err_destroy_cq;
3097 err = mlx5e_create_rq(drop_rq, &rq_param);
3101 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3103 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3108 mlx5e_free_rq(drop_rq);
3111 mlx5e_destroy_cq(cq);
3119 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3121 mlx5e_destroy_rq(drop_rq);
3122 mlx5e_free_rq(drop_rq);
3123 mlx5e_destroy_cq(&drop_rq->cq);
3124 mlx5e_free_cq(&drop_rq->cq);
3127 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3128 u32 underlay_qpn, u32 *tisn)
3130 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3131 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3133 MLX5_SET(tisc, tisc, prio, tc << 1);
3134 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3135 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3137 if (mlx5_lag_is_lacp_owner(mdev))
3138 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3140 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3143 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3145 mlx5_core_destroy_tis(mdev, tisn);
3148 int mlx5e_create_tises(struct mlx5e_priv *priv)
3153 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3154 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3156 goto err_close_tises;
3162 for (tc--; tc >= 0; tc--)
3163 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3168 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3172 for (tc = 0; tc < priv->profile->max_tc; tc++)
3173 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3176 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3177 enum mlx5e_traffic_types tt,
3180 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3182 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3184 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3185 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3186 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3189 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3191 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3193 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3195 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3196 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3197 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3200 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
3202 struct mlx5e_tir *tir;
3210 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3211 in = kvzalloc(inlen, GFP_KERNEL);
3215 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3216 memset(in, 0, inlen);
3217 tir = &priv->indir_tir[tt];
3218 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3219 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3220 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3222 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3223 goto err_destroy_inner_tirs;
3227 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3230 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3231 memset(in, 0, inlen);
3232 tir = &priv->inner_indir_tir[i];
3233 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3234 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3235 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3237 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3238 goto err_destroy_inner_tirs;
3247 err_destroy_inner_tirs:
3248 for (i--; i >= 0; i--)
3249 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3251 for (tt--; tt >= 0; tt--)
3252 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3259 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3261 int nch = priv->profile->max_nch(priv->mdev);
3262 struct mlx5e_tir *tir;
3269 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3270 in = kvzalloc(inlen, GFP_KERNEL);
3274 for (ix = 0; ix < nch; ix++) {
3275 memset(in, 0, inlen);
3276 tir = &priv->direct_tir[ix];
3277 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3278 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3279 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3281 goto err_destroy_ch_tirs;
3288 err_destroy_ch_tirs:
3289 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3290 for (ix--; ix >= 0; ix--)
3291 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3298 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3302 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3303 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3305 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3308 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3309 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3312 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3314 int nch = priv->profile->max_nch(priv->mdev);
3317 for (i = 0; i < nch; i++)
3318 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3321 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3326 for (i = 0; i < chs->num; i++) {
3327 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3335 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3340 for (i = 0; i < chs->num; i++) {
3341 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3349 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3350 struct tc_mqprio_qopt *mqprio)
3352 struct mlx5e_priv *priv = netdev_priv(netdev);
3353 struct mlx5e_channels new_channels = {};
3354 u8 tc = mqprio->num_tc;
3357 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3359 if (tc && tc != MLX5E_MAX_NUM_TC)
3362 mutex_lock(&priv->state_lock);
3364 new_channels.params = priv->channels.params;
3365 new_channels.params.num_tc = tc ? tc : 1;
3367 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3368 priv->channels.params = new_channels.params;
3372 err = mlx5e_open_channels(priv, &new_channels);
3376 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3377 new_channels.params.num_tc);
3378 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3380 mutex_unlock(&priv->state_lock);
3384 #ifdef CONFIG_MLX5_ESWITCH
3385 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3386 struct tc_cls_flower_offload *cls_flower,
3389 switch (cls_flower->command) {
3390 case TC_CLSFLOWER_REPLACE:
3391 return mlx5e_configure_flower(priv, cls_flower, flags);
3392 case TC_CLSFLOWER_DESTROY:
3393 return mlx5e_delete_flower(priv, cls_flower, flags);
3394 case TC_CLSFLOWER_STATS:
3395 return mlx5e_stats_flower(priv, cls_flower, flags);
3401 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3404 struct mlx5e_priv *priv = cb_priv;
3406 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3410 case TC_SETUP_CLSFLOWER:
3411 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3417 static int mlx5e_setup_tc_block(struct net_device *dev,
3418 struct tc_block_offload *f)
3420 struct mlx5e_priv *priv = netdev_priv(dev);
3422 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3425 switch (f->command) {
3427 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3428 priv, priv, f->extack);
3429 case TC_BLOCK_UNBIND:
3430 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3439 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3443 #ifdef CONFIG_MLX5_ESWITCH
3444 case TC_SETUP_BLOCK:
3445 return mlx5e_setup_tc_block(dev, type_data);
3447 case TC_SETUP_QDISC_MQPRIO:
3448 return mlx5e_setup_tc_mqprio(dev, type_data);
3455 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3457 struct mlx5e_priv *priv = netdev_priv(dev);
3458 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3459 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3460 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3462 /* update HW stats in background for next time */
3463 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
3465 if (mlx5e_is_uplink_rep(priv)) {
3466 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3467 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3468 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3469 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3471 mlx5e_grp_sw_update_stats(priv);
3472 stats->rx_packets = sstats->rx_packets;
3473 stats->rx_bytes = sstats->rx_bytes;
3474 stats->tx_packets = sstats->tx_packets;
3475 stats->tx_bytes = sstats->tx_bytes;
3476 stats->tx_dropped = sstats->tx_queue_dropped;
3479 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3481 stats->rx_length_errors =
3482 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3483 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3484 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3485 stats->rx_crc_errors =
3486 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3487 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3488 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3489 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3490 stats->rx_frame_errors;
3491 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3493 /* vport multicast also counts packets that are dropped due to steering
3494 * or rx out of buffer
3497 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3500 static void mlx5e_set_rx_mode(struct net_device *dev)
3502 struct mlx5e_priv *priv = netdev_priv(dev);
3504 queue_work(priv->wq, &priv->set_rx_mode_work);
3507 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3509 struct mlx5e_priv *priv = netdev_priv(netdev);
3510 struct sockaddr *saddr = addr;
3512 if (!is_valid_ether_addr(saddr->sa_data))
3513 return -EADDRNOTAVAIL;
3515 netif_addr_lock_bh(netdev);
3516 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3517 netif_addr_unlock_bh(netdev);
3519 queue_work(priv->wq, &priv->set_rx_mode_work);
3524 #define MLX5E_SET_FEATURE(features, feature, enable) \
3527 *features |= feature; \
3529 *features &= ~feature; \
3532 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3534 static int set_feature_lro(struct net_device *netdev, bool enable)
3536 struct mlx5e_priv *priv = netdev_priv(netdev);
3537 struct mlx5_core_dev *mdev = priv->mdev;
3538 struct mlx5e_channels new_channels = {};
3539 struct mlx5e_params *old_params;
3543 mutex_lock(&priv->state_lock);
3545 old_params = &priv->channels.params;
3546 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3547 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3552 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3554 new_channels.params = *old_params;
3555 new_channels.params.lro_en = enable;
3557 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3558 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3559 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3564 *old_params = new_channels.params;
3565 err = mlx5e_modify_tirs_lro(priv);
3569 err = mlx5e_open_channels(priv, &new_channels);
3573 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3575 mutex_unlock(&priv->state_lock);
3579 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3581 struct mlx5e_priv *priv = netdev_priv(netdev);
3584 mlx5e_enable_cvlan_filter(priv);
3586 mlx5e_disable_cvlan_filter(priv);
3591 #ifdef CONFIG_MLX5_ESWITCH
3592 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3594 struct mlx5e_priv *priv = netdev_priv(netdev);
3596 if (!enable && mlx5e_tc_num_filters(priv)) {
3598 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3606 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3608 struct mlx5e_priv *priv = netdev_priv(netdev);
3609 struct mlx5_core_dev *mdev = priv->mdev;
3611 return mlx5_set_port_fcs(mdev, !enable);
3614 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3616 struct mlx5e_priv *priv = netdev_priv(netdev);
3619 mutex_lock(&priv->state_lock);
3621 priv->channels.params.scatter_fcs_en = enable;
3622 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3624 priv->channels.params.scatter_fcs_en = !enable;
3626 mutex_unlock(&priv->state_lock);
3631 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3633 struct mlx5e_priv *priv = netdev_priv(netdev);
3636 mutex_lock(&priv->state_lock);
3638 priv->channels.params.vlan_strip_disable = !enable;
3639 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3642 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3644 priv->channels.params.vlan_strip_disable = enable;
3647 mutex_unlock(&priv->state_lock);
3652 #ifdef CONFIG_MLX5_EN_ARFS
3653 static int set_feature_arfs(struct net_device *netdev, bool enable)
3655 struct mlx5e_priv *priv = netdev_priv(netdev);
3659 err = mlx5e_arfs_enable(priv);
3661 err = mlx5e_arfs_disable(priv);
3667 static int mlx5e_handle_feature(struct net_device *netdev,
3668 netdev_features_t *features,
3669 netdev_features_t feature,
3670 mlx5e_feature_handler feature_handler)
3672 netdev_features_t changes = *features ^ netdev->features;
3673 bool enable = !!(*features & feature);
3676 if (!(changes & feature))
3679 err = feature_handler(netdev, enable);
3681 MLX5E_SET_FEATURE(features, feature, !enable);
3682 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3683 enable ? "Enable" : "Disable", &feature, err);
3690 static int mlx5e_set_features(struct net_device *netdev,
3691 netdev_features_t features)
3693 netdev_features_t oper_features = features;
3696 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3697 mlx5e_handle_feature(netdev, &oper_features, feature, handler)
3699 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3700 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3701 set_feature_cvlan_filter);
3702 #ifdef CONFIG_MLX5_ESWITCH
3703 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3705 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3706 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3707 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3708 #ifdef CONFIG_MLX5_EN_ARFS
3709 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3713 netdev->features = oper_features;
3720 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3721 netdev_features_t features)
3723 struct mlx5e_priv *priv = netdev_priv(netdev);
3724 struct mlx5e_params *params;
3726 mutex_lock(&priv->state_lock);
3727 params = &priv->channels.params;
3728 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3729 /* HW strips the outer C-tag header, this is a problem
3730 * for S-tag traffic.
3732 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3733 if (!params->vlan_strip_disable)
3734 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3736 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3737 features &= ~NETIF_F_LRO;
3739 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3742 if (params->xdp_prog) {
3743 if (features & NETIF_F_LRO) {
3744 netdev_warn(netdev, "LRO is incompatible with XDP\n");
3745 features &= ~NETIF_F_LRO;
3749 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3750 features &= ~NETIF_F_RXHASH;
3751 if (netdev->features & NETIF_F_RXHASH)
3752 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3755 mutex_unlock(&priv->state_lock);
3760 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3761 change_hw_mtu_cb set_mtu_cb)
3763 struct mlx5e_priv *priv = netdev_priv(netdev);
3764 struct mlx5e_channels new_channels = {};
3765 struct mlx5e_params *params;
3769 mutex_lock(&priv->state_lock);
3771 params = &priv->channels.params;
3773 reset = !params->lro_en;
3774 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3776 new_channels.params = *params;
3777 new_channels.params.sw_mtu = new_mtu;
3779 if (params->xdp_prog &&
3780 !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3781 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3782 new_mtu, mlx5e_xdp_max_mtu(params));
3787 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3788 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3789 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3790 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3792 reset = reset && (is_linear || (ppw_old != ppw_new));
3796 params->sw_mtu = new_mtu;
3799 netdev->mtu = params->sw_mtu;
3803 err = mlx5e_open_channels(priv, &new_channels);
3807 mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3808 netdev->mtu = new_channels.params.sw_mtu;
3811 mutex_unlock(&priv->state_lock);
3815 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3817 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3820 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3822 struct hwtstamp_config config;
3825 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3826 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3829 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3832 /* TX HW timestamp */
3833 switch (config.tx_type) {
3834 case HWTSTAMP_TX_OFF:
3835 case HWTSTAMP_TX_ON:
3841 mutex_lock(&priv->state_lock);
3842 /* RX HW timestamp */
3843 switch (config.rx_filter) {
3844 case HWTSTAMP_FILTER_NONE:
3845 /* Reset CQE compression to Admin default */
3846 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3848 case HWTSTAMP_FILTER_ALL:
3849 case HWTSTAMP_FILTER_SOME:
3850 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3851 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3852 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3853 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3854 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3855 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3856 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3857 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3858 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3859 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3860 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3861 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3862 case HWTSTAMP_FILTER_NTP_ALL:
3863 /* Disable CQE compression */
3864 netdev_warn(priv->netdev, "Disabling cqe compression");
3865 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3867 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3868 mutex_unlock(&priv->state_lock);
3871 config.rx_filter = HWTSTAMP_FILTER_ALL;
3874 mutex_unlock(&priv->state_lock);
3878 memcpy(&priv->tstamp, &config, sizeof(config));
3879 mutex_unlock(&priv->state_lock);
3881 /* might need to fix some features */
3882 netdev_update_features(priv->netdev);
3884 return copy_to_user(ifr->ifr_data, &config,
3885 sizeof(config)) ? -EFAULT : 0;
3888 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3890 struct hwtstamp_config *cfg = &priv->tstamp;
3892 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3895 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3898 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3900 struct mlx5e_priv *priv = netdev_priv(dev);
3904 return mlx5e_hwstamp_set(priv, ifr);
3906 return mlx5e_hwstamp_get(priv, ifr);
3912 #ifdef CONFIG_MLX5_ESWITCH
3913 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3915 struct mlx5e_priv *priv = netdev_priv(dev);
3916 struct mlx5_core_dev *mdev = priv->mdev;
3918 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3921 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3924 struct mlx5e_priv *priv = netdev_priv(dev);
3925 struct mlx5_core_dev *mdev = priv->mdev;
3927 if (vlan_proto != htons(ETH_P_8021Q))
3928 return -EPROTONOSUPPORT;
3930 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3934 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3936 struct mlx5e_priv *priv = netdev_priv(dev);
3937 struct mlx5_core_dev *mdev = priv->mdev;
3939 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3942 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3944 struct mlx5e_priv *priv = netdev_priv(dev);
3945 struct mlx5_core_dev *mdev = priv->mdev;
3947 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3950 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3953 struct mlx5e_priv *priv = netdev_priv(dev);
3954 struct mlx5_core_dev *mdev = priv->mdev;
3956 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3957 max_tx_rate, min_tx_rate);
3960 static int mlx5_vport_link2ifla(u8 esw_link)
3963 case MLX5_VPORT_ADMIN_STATE_DOWN:
3964 return IFLA_VF_LINK_STATE_DISABLE;
3965 case MLX5_VPORT_ADMIN_STATE_UP:
3966 return IFLA_VF_LINK_STATE_ENABLE;
3968 return IFLA_VF_LINK_STATE_AUTO;
3971 static int mlx5_ifla_link2vport(u8 ifla_link)
3973 switch (ifla_link) {
3974 case IFLA_VF_LINK_STATE_DISABLE:
3975 return MLX5_VPORT_ADMIN_STATE_DOWN;
3976 case IFLA_VF_LINK_STATE_ENABLE:
3977 return MLX5_VPORT_ADMIN_STATE_UP;
3979 return MLX5_VPORT_ADMIN_STATE_AUTO;
3982 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3985 struct mlx5e_priv *priv = netdev_priv(dev);
3986 struct mlx5_core_dev *mdev = priv->mdev;
3988 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3989 mlx5_ifla_link2vport(link_state));
3992 static int mlx5e_get_vf_config(struct net_device *dev,
3993 int vf, struct ifla_vf_info *ivi)
3995 struct mlx5e_priv *priv = netdev_priv(dev);
3996 struct mlx5_core_dev *mdev = priv->mdev;
3999 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4002 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4006 static int mlx5e_get_vf_stats(struct net_device *dev,
4007 int vf, struct ifla_vf_stats *vf_stats)
4009 struct mlx5e_priv *priv = netdev_priv(dev);
4010 struct mlx5_core_dev *mdev = priv->mdev;
4012 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4017 struct mlx5e_vxlan_work {
4018 struct work_struct work;
4019 struct mlx5e_priv *priv;
4023 static void mlx5e_vxlan_add_work(struct work_struct *work)
4025 struct mlx5e_vxlan_work *vxlan_work =
4026 container_of(work, struct mlx5e_vxlan_work, work);
4027 struct mlx5e_priv *priv = vxlan_work->priv;
4028 u16 port = vxlan_work->port;
4030 mutex_lock(&priv->state_lock);
4031 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4032 mutex_unlock(&priv->state_lock);
4037 static void mlx5e_vxlan_del_work(struct work_struct *work)
4039 struct mlx5e_vxlan_work *vxlan_work =
4040 container_of(work, struct mlx5e_vxlan_work, work);
4041 struct mlx5e_priv *priv = vxlan_work->priv;
4042 u16 port = vxlan_work->port;
4044 mutex_lock(&priv->state_lock);
4045 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4046 mutex_unlock(&priv->state_lock);
4050 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4052 struct mlx5e_vxlan_work *vxlan_work;
4054 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4059 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4061 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4063 vxlan_work->priv = priv;
4064 vxlan_work->port = port;
4065 queue_work(priv->wq, &vxlan_work->work);
4068 static void mlx5e_add_vxlan_port(struct net_device *netdev,
4069 struct udp_tunnel_info *ti)
4071 struct mlx5e_priv *priv = netdev_priv(netdev);
4073 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4076 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4079 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4082 static void mlx5e_del_vxlan_port(struct net_device *netdev,
4083 struct udp_tunnel_info *ti)
4085 struct mlx5e_priv *priv = netdev_priv(netdev);
4087 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4090 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4093 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4096 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4097 struct sk_buff *skb,
4098 netdev_features_t features)
4100 unsigned int offset = 0;
4101 struct udphdr *udph;
4105 switch (vlan_get_protocol(skb)) {
4106 case htons(ETH_P_IP):
4107 proto = ip_hdr(skb)->protocol;
4109 case htons(ETH_P_IPV6):
4110 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4120 udph = udp_hdr(skb);
4121 port = be16_to_cpu(udph->dest);
4123 /* Verify if UDP port is being offloaded by HW */
4124 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4129 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4130 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4133 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4134 struct net_device *netdev,
4135 netdev_features_t features)
4137 struct mlx5e_priv *priv = netdev_priv(netdev);
4139 features = vlan_features_check(skb, features);
4140 features = vxlan_features_check(skb, features);
4142 #ifdef CONFIG_MLX5_EN_IPSEC
4143 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4147 /* Validate if the tunneled packet is being offloaded by HW */
4148 if (skb->encapsulation &&
4149 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4150 return mlx5e_tunnel_features_check(priv, skb, features);
4155 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4156 struct mlx5e_txqsq *sq)
4158 struct mlx5_eq *eq = sq->cq.mcq.eq;
4161 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4162 eq->eqn, eq->cons_index, eq->irqn);
4164 eqe_count = mlx5_eq_poll_irq_disabled(eq);
4168 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4169 sq->channel->stats->eq_rearm++;
4173 static void mlx5e_tx_timeout_work(struct work_struct *work)
4175 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4177 struct net_device *dev = priv->netdev;
4178 bool reopen_channels = false;
4182 mutex_lock(&priv->state_lock);
4184 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4187 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4188 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4189 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4191 if (!netif_xmit_stopped(dev_queue))
4195 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4196 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4197 jiffies_to_usecs(jiffies - dev_queue->trans_start));
4199 /* If we recover a lost interrupt, most likely TX timeout will
4200 * be resolved, skip reopening channels
4202 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4203 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4204 reopen_channels = true;
4208 if (!reopen_channels)
4211 mlx5e_close_locked(dev);
4212 err = mlx5e_open_locked(dev);
4214 netdev_err(priv->netdev,
4215 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4219 mutex_unlock(&priv->state_lock);
4223 static void mlx5e_tx_timeout(struct net_device *dev)
4225 struct mlx5e_priv *priv = netdev_priv(dev);
4227 netdev_err(dev, "TX timeout detected\n");
4228 queue_work(priv->wq, &priv->tx_timeout_work);
4231 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4233 struct net_device *netdev = priv->netdev;
4234 struct mlx5e_channels new_channels = {};
4236 if (priv->channels.params.lro_en) {
4237 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4241 if (MLX5_IPSEC_DEV(priv->mdev)) {
4242 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4246 new_channels.params = priv->channels.params;
4247 new_channels.params.xdp_prog = prog;
4249 if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4250 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4251 new_channels.params.sw_mtu,
4252 mlx5e_xdp_max_mtu(&new_channels.params));
4259 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4261 struct mlx5e_priv *priv = netdev_priv(netdev);
4262 struct bpf_prog *old_prog;
4263 bool reset, was_opened;
4267 mutex_lock(&priv->state_lock);
4270 err = mlx5e_xdp_allowed(priv, prog);
4275 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4276 /* no need for full reset when exchanging programs */
4277 reset = (!priv->channels.params.xdp_prog || !prog);
4279 if (was_opened && reset)
4280 mlx5e_close_locked(netdev);
4281 if (was_opened && !reset) {
4282 /* num_channels is invariant here, so we can take the
4283 * batched reference right upfront.
4285 prog = bpf_prog_add(prog, priv->channels.num);
4287 err = PTR_ERR(prog);
4292 /* exchange programs, extra prog reference we got from caller
4293 * as long as we don't fail from this point onwards.
4295 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4297 bpf_prog_put(old_prog);
4299 if (reset) /* change RQ type according to priv->xdp_prog */
4300 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4302 if (was_opened && reset)
4303 mlx5e_open_locked(netdev);
4305 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4308 /* exchanging programs w/o reset, we update ref counts on behalf
4309 * of the channels RQs here.
4311 for (i = 0; i < priv->channels.num; i++) {
4312 struct mlx5e_channel *c = priv->channels.c[i];
4314 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4315 napi_synchronize(&c->napi);
4316 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4318 old_prog = xchg(&c->rq.xdp_prog, prog);
4320 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4321 /* napi_schedule in case we have missed anything */
4322 napi_schedule(&c->napi);
4325 bpf_prog_put(old_prog);
4329 mutex_unlock(&priv->state_lock);
4333 static u32 mlx5e_xdp_query(struct net_device *dev)
4335 struct mlx5e_priv *priv = netdev_priv(dev);
4336 const struct bpf_prog *xdp_prog;
4339 mutex_lock(&priv->state_lock);
4340 xdp_prog = priv->channels.params.xdp_prog;
4342 prog_id = xdp_prog->aux->id;
4343 mutex_unlock(&priv->state_lock);
4348 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4350 switch (xdp->command) {
4351 case XDP_SETUP_PROG:
4352 return mlx5e_xdp_set(dev, xdp->prog);
4353 case XDP_QUERY_PROG:
4354 xdp->prog_id = mlx5e_xdp_query(dev);
4361 const struct net_device_ops mlx5e_netdev_ops = {
4362 .ndo_open = mlx5e_open,
4363 .ndo_stop = mlx5e_close,
4364 .ndo_start_xmit = mlx5e_xmit,
4365 .ndo_setup_tc = mlx5e_setup_tc,
4366 .ndo_select_queue = mlx5e_select_queue,
4367 .ndo_get_stats64 = mlx5e_get_stats,
4368 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4369 .ndo_set_mac_address = mlx5e_set_mac,
4370 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4371 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4372 .ndo_set_features = mlx5e_set_features,
4373 .ndo_fix_features = mlx5e_fix_features,
4374 .ndo_change_mtu = mlx5e_change_nic_mtu,
4375 .ndo_do_ioctl = mlx5e_ioctl,
4376 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4377 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4378 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4379 .ndo_features_check = mlx5e_features_check,
4380 .ndo_tx_timeout = mlx5e_tx_timeout,
4381 .ndo_bpf = mlx5e_xdp,
4382 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4383 #ifdef CONFIG_MLX5_EN_ARFS
4384 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4386 #ifdef CONFIG_MLX5_ESWITCH
4387 /* SRIOV E-Switch NDOs */
4388 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4389 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4390 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4391 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4392 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4393 .ndo_get_vf_config = mlx5e_get_vf_config,
4394 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4395 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4396 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4397 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4401 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4403 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4405 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4406 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4407 !MLX5_CAP_ETH(mdev, csum_cap) ||
4408 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4409 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4410 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4411 MLX5_CAP_FLOWTABLE(mdev,
4412 flow_table_properties_nic_receive.max_ft_level)
4414 mlx5_core_warn(mdev,
4415 "Not creating net device, some required device capabilities are missing\n");
4418 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4419 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4420 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4421 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4426 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4431 for (i = 0; i < len; i++)
4432 indirection_rqt[i] = i % num_channels;
4435 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4440 mlx5e_port_max_linkspeed(mdev, &link_speed);
4441 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4442 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4443 link_speed, pci_bw);
4445 #define MLX5E_SLOW_PCI_RATIO (2)
4447 return link_speed && pci_bw &&
4448 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4451 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4453 struct net_dim_cq_moder moder;
4455 moder.cq_period_mode = cq_period_mode;
4456 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4457 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4458 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4459 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4464 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4466 struct net_dim_cq_moder moder;
4468 moder.cq_period_mode = cq_period_mode;
4469 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4470 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4471 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4472 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4477 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4479 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4480 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4481 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4484 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4486 if (params->tx_dim_enabled) {
4487 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4489 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4491 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4494 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4495 params->tx_cq_moderation.cq_period_mode ==
4496 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4499 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4501 if (params->rx_dim_enabled) {
4502 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4504 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4506 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4509 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4510 params->rx_cq_moderation.cq_period_mode ==
4511 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4514 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4518 /* The supported periods are organized in ascending order */
4519 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4520 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4523 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4526 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4527 struct mlx5e_params *params,
4528 u16 max_channels, u16 mtu)
4530 u8 rx_cq_period_mode;
4532 params->sw_mtu = mtu;
4533 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4534 params->num_channels = max_channels;
4538 params->log_sq_size = is_kdump_kernel() ?
4539 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4540 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4542 /* set CQE compression */
4543 params->rx_cqe_compress_def = false;
4544 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4545 MLX5_CAP_GEN(mdev, vport_group_manager))
4546 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4548 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4549 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4552 /* Prefer Striding RQ, unless any of the following holds:
4553 * - Striding RQ configuration is not possible/supported.
4554 * - Slow PCI heuristic.
4555 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4557 if (!slow_pci_heuristic(mdev) &&
4558 mlx5e_striding_rq_possible(mdev, params) &&
4559 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4560 !mlx5e_rx_is_linear_skb(mdev, params)))
4561 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4562 mlx5e_set_rq_type(mdev, params);
4563 mlx5e_init_rq_type_params(mdev, params);
4567 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4568 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4569 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4570 params->lro_en = !slow_pci_heuristic(mdev);
4571 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4573 /* CQ moderation params */
4574 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4575 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4576 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4577 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4578 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4579 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4580 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4583 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4586 params->rss_hfunc = ETH_RSS_HASH_XOR;
4587 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4588 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4589 MLX5E_INDIR_RQT_SIZE, max_channels);
4592 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4593 struct net_device *netdev,
4594 const struct mlx5e_profile *profile,
4597 struct mlx5e_priv *priv = netdev_priv(netdev);
4600 priv->netdev = netdev;
4601 priv->profile = profile;
4602 priv->ppriv = ppriv;
4603 priv->msglevel = MLX5E_MSG_LEVEL;
4604 priv->max_opened_tc = 1;
4606 mlx5e_build_nic_params(mdev, &priv->channels.params,
4607 profile->max_nch(mdev), netdev->mtu);
4609 mutex_init(&priv->state_lock);
4611 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4612 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4613 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4614 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4616 mlx5e_timestamp_init(priv);
4619 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4621 struct mlx5e_priv *priv = netdev_priv(netdev);
4623 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4624 if (is_zero_ether_addr(netdev->dev_addr) &&
4625 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4626 eth_hw_addr_random(netdev);
4627 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4631 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4632 static const struct switchdev_ops mlx5e_switchdev_ops = {
4633 .switchdev_port_attr_get = mlx5e_attr_get,
4637 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4639 struct mlx5e_priv *priv = netdev_priv(netdev);
4640 struct mlx5_core_dev *mdev = priv->mdev;
4644 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4646 netdev->netdev_ops = &mlx5e_netdev_ops;
4648 #ifdef CONFIG_MLX5_CORE_EN_DCB
4649 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4650 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4653 netdev->watchdog_timeo = 15 * HZ;
4655 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4657 netdev->vlan_features |= NETIF_F_SG;
4658 netdev->vlan_features |= NETIF_F_IP_CSUM;
4659 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4660 netdev->vlan_features |= NETIF_F_GRO;
4661 netdev->vlan_features |= NETIF_F_TSO;
4662 netdev->vlan_features |= NETIF_F_TSO6;
4663 netdev->vlan_features |= NETIF_F_RXCSUM;
4664 netdev->vlan_features |= NETIF_F_RXHASH;
4666 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4667 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4669 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4670 mlx5e_check_fragmented_striding_rq_cap(mdev))
4671 netdev->vlan_features |= NETIF_F_LRO;
4673 netdev->hw_features = netdev->vlan_features;
4674 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4675 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4676 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4677 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4679 if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4680 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4681 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4682 netdev->hw_enc_features |= NETIF_F_TSO;
4683 netdev->hw_enc_features |= NETIF_F_TSO6;
4684 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4687 if (mlx5_vxlan_allowed(mdev->vxlan)) {
4688 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
4689 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4692 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4693 netdev->hw_features |= NETIF_F_GSO_GRE |
4694 NETIF_F_GSO_GRE_CSUM;
4695 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4696 NETIF_F_GSO_GRE_CSUM;
4697 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4698 NETIF_F_GSO_GRE_CSUM;
4701 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4702 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4703 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4704 netdev->features |= NETIF_F_GSO_UDP_L4;
4706 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4709 netdev->hw_features |= NETIF_F_RXALL;
4711 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4712 netdev->hw_features |= NETIF_F_RXFCS;
4714 netdev->features = netdev->hw_features;
4715 if (!priv->channels.params.lro_en)
4716 netdev->features &= ~NETIF_F_LRO;
4719 netdev->features &= ~NETIF_F_RXALL;
4721 if (!priv->channels.params.scatter_fcs_en)
4722 netdev->features &= ~NETIF_F_RXFCS;
4724 /* prefere CQE compression over rxhash */
4725 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4726 netdev->features &= ~NETIF_F_RXHASH;
4728 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4729 if (FT_CAP(flow_modify_en) &&
4730 FT_CAP(modify_root) &&
4731 FT_CAP(identified_miss_table_mode) &&
4732 FT_CAP(flow_table_modify)) {
4733 #ifdef CONFIG_MLX5_ESWITCH
4734 netdev->hw_features |= NETIF_F_HW_TC;
4736 #ifdef CONFIG_MLX5_EN_ARFS
4737 netdev->hw_features |= NETIF_F_NTUPLE;
4741 netdev->features |= NETIF_F_HIGHDMA;
4742 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4744 netdev->priv_flags |= IFF_UNICAST_FLT;
4746 mlx5e_set_netdev_dev_addr(netdev);
4748 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4749 if (MLX5_ESWITCH_MANAGER(mdev))
4750 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4753 mlx5e_ipsec_build_netdev(priv);
4754 mlx5e_tls_build_netdev(priv);
4757 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4759 struct mlx5_core_dev *mdev = priv->mdev;
4762 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4764 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4765 priv->q_counter = 0;
4768 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4770 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4771 priv->drop_rq_q_counter = 0;
4775 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4777 if (priv->q_counter)
4778 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4780 if (priv->drop_rq_q_counter)
4781 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4784 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4785 struct net_device *netdev,
4786 const struct mlx5e_profile *profile,
4789 struct mlx5e_priv *priv = netdev_priv(netdev);
4792 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4793 err = mlx5e_ipsec_init(priv);
4795 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4796 err = mlx5e_tls_init(priv);
4798 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4799 mlx5e_build_nic_netdev(netdev);
4800 mlx5e_build_tc2txq_maps(priv);
4803 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4805 mlx5e_tls_cleanup(priv);
4806 mlx5e_ipsec_cleanup(priv);
4809 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4811 struct mlx5_core_dev *mdev = priv->mdev;
4814 err = mlx5e_create_indirect_rqt(priv);
4818 err = mlx5e_create_direct_rqts(priv);
4820 goto err_destroy_indirect_rqts;
4822 err = mlx5e_create_indirect_tirs(priv);
4824 goto err_destroy_direct_rqts;
4826 err = mlx5e_create_direct_tirs(priv);
4828 goto err_destroy_indirect_tirs;
4830 err = mlx5e_create_flow_steering(priv);
4832 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4833 goto err_destroy_direct_tirs;
4836 err = mlx5e_tc_nic_init(priv);
4838 goto err_destroy_flow_steering;
4842 err_destroy_flow_steering:
4843 mlx5e_destroy_flow_steering(priv);
4844 err_destroy_direct_tirs:
4845 mlx5e_destroy_direct_tirs(priv);
4846 err_destroy_indirect_tirs:
4847 mlx5e_destroy_indirect_tirs(priv);
4848 err_destroy_direct_rqts:
4849 mlx5e_destroy_direct_rqts(priv);
4850 err_destroy_indirect_rqts:
4851 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4855 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4857 mlx5e_tc_nic_cleanup(priv);
4858 mlx5e_destroy_flow_steering(priv);
4859 mlx5e_destroy_direct_tirs(priv);
4860 mlx5e_destroy_indirect_tirs(priv);
4861 mlx5e_destroy_direct_rqts(priv);
4862 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4865 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4869 err = mlx5e_create_tises(priv);
4871 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4875 #ifdef CONFIG_MLX5_CORE_EN_DCB
4876 mlx5e_dcbnl_initialize(priv);
4881 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4883 struct net_device *netdev = priv->netdev;
4884 struct mlx5_core_dev *mdev = priv->mdev;
4887 mlx5e_init_l2_addr(priv);
4889 /* Marking the link as currently not needed by the Driver */
4890 if (!netif_running(netdev))
4891 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4893 /* MTU range: 68 - hw-specific max */
4894 netdev->min_mtu = ETH_MIN_MTU;
4895 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4896 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4897 mlx5e_set_dev_port_mtu(priv);
4899 mlx5_lag_add(mdev, netdev);
4901 mlx5e_enable_async_events(priv);
4903 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4904 mlx5e_register_vport_reps(priv);
4906 if (netdev->reg_state != NETREG_REGISTERED)
4908 #ifdef CONFIG_MLX5_CORE_EN_DCB
4909 mlx5e_dcbnl_init_app(priv);
4912 queue_work(priv->wq, &priv->set_rx_mode_work);
4915 if (netif_running(netdev))
4917 netif_device_attach(netdev);
4921 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4923 struct mlx5_core_dev *mdev = priv->mdev;
4925 #ifdef CONFIG_MLX5_CORE_EN_DCB
4926 if (priv->netdev->reg_state == NETREG_REGISTERED)
4927 mlx5e_dcbnl_delete_app(priv);
4931 if (netif_running(priv->netdev))
4932 mlx5e_close(priv->netdev);
4933 netif_device_detach(priv->netdev);
4936 queue_work(priv->wq, &priv->set_rx_mode_work);
4938 if (MLX5_ESWITCH_MANAGER(priv->mdev))
4939 mlx5e_unregister_vport_reps(priv);
4941 mlx5e_disable_async_events(priv);
4942 mlx5_lag_remove(mdev);
4945 static const struct mlx5e_profile mlx5e_nic_profile = {
4946 .init = mlx5e_nic_init,
4947 .cleanup = mlx5e_nic_cleanup,
4948 .init_rx = mlx5e_init_nic_rx,
4949 .cleanup_rx = mlx5e_cleanup_nic_rx,
4950 .init_tx = mlx5e_init_nic_tx,
4951 .cleanup_tx = mlx5e_cleanup_nic_tx,
4952 .enable = mlx5e_nic_enable,
4953 .disable = mlx5e_nic_disable,
4954 .update_stats = mlx5e_update_ndo_stats,
4955 .max_nch = mlx5e_get_max_num_channels,
4956 .update_carrier = mlx5e_update_carrier,
4957 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4958 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4959 .max_tc = MLX5E_MAX_NUM_TC,
4962 /* mlx5e generic netdev management API (move to en_common.c) */
4964 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4965 const struct mlx5e_profile *profile,
4968 int nch = profile->max_nch(mdev);
4969 struct net_device *netdev;
4970 struct mlx5e_priv *priv;
4972 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4973 nch * profile->max_tc,
4976 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4980 #ifdef CONFIG_MLX5_EN_ARFS
4981 netdev->rx_cpu_rmap = mdev->rmap;
4984 profile->init(mdev, netdev, profile, ppriv);
4986 netif_carrier_off(netdev);
4988 priv = netdev_priv(netdev);
4990 priv->wq = create_singlethread_workqueue("mlx5e");
4992 goto err_cleanup_nic;
4997 if (profile->cleanup)
4998 profile->cleanup(priv);
4999 free_netdev(netdev);
5004 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5006 struct mlx5_core_dev *mdev = priv->mdev;
5007 const struct mlx5e_profile *profile;
5011 profile = priv->profile;
5012 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5014 /* max number of channels may have changed */
5015 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5016 if (priv->channels.params.num_channels > max_nch) {
5017 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5018 priv->channels.params.num_channels = max_nch;
5019 mlx5e_build_default_indir_rqt(priv->channels.params.indirection_rqt,
5020 MLX5E_INDIR_RQT_SIZE, max_nch);
5023 err = profile->init_tx(priv);
5027 mlx5e_create_q_counters(priv);
5029 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5031 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5032 goto err_destroy_q_counters;
5035 err = profile->init_rx(priv);
5037 goto err_close_drop_rq;
5039 if (profile->enable)
5040 profile->enable(priv);
5045 mlx5e_close_drop_rq(&priv->drop_rq);
5047 err_destroy_q_counters:
5048 mlx5e_destroy_q_counters(priv);
5049 profile->cleanup_tx(priv);
5055 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5057 const struct mlx5e_profile *profile = priv->profile;
5059 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5061 if (profile->disable)
5062 profile->disable(priv);
5063 flush_workqueue(priv->wq);
5065 profile->cleanup_rx(priv);
5066 mlx5e_close_drop_rq(&priv->drop_rq);
5067 mlx5e_destroy_q_counters(priv);
5068 profile->cleanup_tx(priv);
5069 cancel_delayed_work_sync(&priv->update_stats_work);
5072 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5074 const struct mlx5e_profile *profile = priv->profile;
5075 struct net_device *netdev = priv->netdev;
5077 destroy_workqueue(priv->wq);
5078 if (profile->cleanup)
5079 profile->cleanup(priv);
5080 free_netdev(netdev);
5083 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5084 * hardware contexts and to connect it to the current netdev.
5086 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5088 struct mlx5e_priv *priv = vpriv;
5089 struct net_device *netdev = priv->netdev;
5092 if (netif_device_present(netdev))
5095 err = mlx5e_create_mdev_resources(mdev);
5099 err = mlx5e_attach_netdev(priv);
5101 mlx5e_destroy_mdev_resources(mdev);
5108 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5110 struct mlx5e_priv *priv = vpriv;
5111 struct net_device *netdev = priv->netdev;
5113 if (!netif_device_present(netdev))
5116 mlx5e_detach_netdev(priv);
5117 mlx5e_destroy_mdev_resources(mdev);
5120 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5122 struct net_device *netdev;
5127 err = mlx5e_check_required_hca_cap(mdev);
5131 #ifdef CONFIG_MLX5_ESWITCH
5132 if (MLX5_ESWITCH_MANAGER(mdev)) {
5133 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5135 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5141 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
5143 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5144 goto err_free_rpriv;
5147 priv = netdev_priv(netdev);
5149 err = mlx5e_attach(mdev, priv);
5151 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5152 goto err_destroy_netdev;
5155 err = register_netdev(netdev);
5157 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5161 #ifdef CONFIG_MLX5_CORE_EN_DCB
5162 mlx5e_dcbnl_init_app(priv);
5167 mlx5e_detach(mdev, priv);
5169 mlx5e_destroy_netdev(priv);
5175 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5177 struct mlx5e_priv *priv = vpriv;
5178 void *ppriv = priv->ppriv;
5180 #ifdef CONFIG_MLX5_CORE_EN_DCB
5181 mlx5e_dcbnl_delete_app(priv);
5183 unregister_netdev(priv->netdev);
5184 mlx5e_detach(mdev, vpriv);
5185 mlx5e_destroy_netdev(priv);
5189 static void *mlx5e_get_netdev(void *vpriv)
5191 struct mlx5e_priv *priv = vpriv;
5193 return priv->netdev;
5196 static struct mlx5_interface mlx5e_interface = {
5198 .remove = mlx5e_remove,
5199 .attach = mlx5e_attach,
5200 .detach = mlx5e_detach,
5201 .event = mlx5e_async_event,
5202 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5203 .get_dev = mlx5e_get_netdev,
5206 void mlx5e_init(void)
5208 mlx5e_ipsec_build_inverse_table();
5209 mlx5e_build_ptys2ethtool_map();
5210 mlx5_register_interface(&mlx5e_interface);
5213 void mlx5e_cleanup(void)
5215 mlx5_unregister_interface(&mlx5e_interface);