2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
43 struct mlx5e_rq_param {
44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
49 struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
54 enum mlx5e_sq_type type;
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
81 static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
83 priv->params.rq_wq_type = rq_type;
84 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
85 switch (priv->params.rq_wq_type) {
86 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
87 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
88 priv->params.mpwqe_log_stride_sz = priv->params.rx_cqe_compress ?
89 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90 MLX5_MPWRQ_LOG_STRIDE_SIZE;
91 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 priv->params.mpwqe_log_stride_sz;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
95 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
97 /* Extra room needed for build_skb */
98 priv->params.lro_wqe_sz -= MLX5_RX_HEADROOM +
99 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
101 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
102 BIT(priv->params.log_rq_size));
104 mlx5_core_info(priv->mdev,
105 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(priv->params.log_rq_size),
108 BIT(priv->params.mpwqe_log_stride_sz),
109 priv->params.rx_cqe_compress_admin);
112 static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
118 mlx5e_set_rq_type_params(priv, rq_type);
121 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
123 struct mlx5_core_dev *mdev = priv->mdev;
126 port_state = mlx5_query_vport_state(mdev,
127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
131 netif_carrier_on(priv->netdev);
133 netdev_info(priv->netdev, "Link down\n");
134 netif_carrier_off(priv->netdev);
138 static void mlx5e_update_carrier_work(struct work_struct *work)
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
149 static void mlx5e_tx_timeout_work(struct work_struct *work)
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
165 mutex_unlock(&priv->state_lock);
169 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
171 struct mlx5e_sw_stats *s = &priv->stats.sw;
172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
174 u64 tx_offload_none = 0;
177 memset(s, 0, sizeof(*s));
178 for (i = 0; i < priv->params.num_channels; i++) {
179 rq_stats = &priv->channel[i]->rq.stats;
181 s->rx_packets += rq_stats->packets;
182 s->rx_bytes += rq_stats->bytes;
183 s->rx_lro_packets += rq_stats->lro_packets;
184 s->rx_lro_bytes += rq_stats->lro_bytes;
185 s->rx_csum_none += rq_stats->csum_none;
186 s->rx_csum_complete += rq_stats->csum_complete;
187 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
188 s->rx_xdp_drop += rq_stats->xdp_drop;
189 s->rx_xdp_tx += rq_stats->xdp_tx;
190 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
191 s->rx_wqe_err += rq_stats->wqe_err;
192 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
193 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
194 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
195 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
196 s->rx_cache_reuse += rq_stats->cache_reuse;
197 s->rx_cache_full += rq_stats->cache_full;
198 s->rx_cache_empty += rq_stats->cache_empty;
199 s->rx_cache_busy += rq_stats->cache_busy;
201 for (j = 0; j < priv->params.num_tc; j++) {
202 sq_stats = &priv->channel[i]->sq[j].stats;
204 s->tx_packets += sq_stats->packets;
205 s->tx_bytes += sq_stats->bytes;
206 s->tx_tso_packets += sq_stats->tso_packets;
207 s->tx_tso_bytes += sq_stats->tso_bytes;
208 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
209 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
210 s->tx_queue_stopped += sq_stats->stopped;
211 s->tx_queue_wake += sq_stats->wake;
212 s->tx_queue_dropped += sq_stats->dropped;
213 s->tx_xmit_more += sq_stats->xmit_more;
214 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
215 tx_offload_none += sq_stats->csum_none;
219 /* Update calculated offload counters */
220 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
221 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
223 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
224 priv->stats.pport.phy_counters,
225 counter_set.phys_layer_cntrs.link_down_events);
228 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
230 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
231 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
232 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
233 struct mlx5_core_dev *mdev = priv->mdev;
235 MLX5_SET(query_vport_counter_in, in, opcode,
236 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
237 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
238 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
240 memset(out, 0, outlen);
241 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
244 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
246 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
247 struct mlx5_core_dev *mdev = priv->mdev;
248 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
253 in = mlx5_vzalloc(sz);
257 MLX5_SET(ppcnt_reg, in, local_port, 1);
259 out = pstats->IEEE_802_3_counters;
260 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
261 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
263 out = pstats->RFC_2863_counters;
264 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
265 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
267 out = pstats->RFC_2819_counters;
268 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
269 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
271 out = pstats->phy_counters;
272 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
273 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
275 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
276 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
277 out = pstats->per_prio_counters[prio];
278 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
279 mlx5_core_access_reg(mdev, in, sz, out, sz,
280 MLX5_REG_PPCNT, 0, 0);
287 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
289 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
291 if (!priv->q_counter)
294 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
295 &qcnt->rx_out_of_buffer);
298 void mlx5e_update_stats(struct mlx5e_priv *priv)
300 mlx5e_update_q_counter(priv);
301 mlx5e_update_vport_counters(priv);
302 mlx5e_update_pport_counters(priv);
303 mlx5e_update_sw_counters(priv);
306 void mlx5e_update_stats_work(struct work_struct *work)
308 struct delayed_work *dwork = to_delayed_work(work);
309 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
311 mutex_lock(&priv->state_lock);
312 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
313 priv->profile->update_stats(priv);
314 queue_delayed_work(priv->wq, dwork,
315 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
317 mutex_unlock(&priv->state_lock);
320 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
321 enum mlx5_dev_event event, unsigned long param)
323 struct mlx5e_priv *priv = vpriv;
325 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
329 case MLX5_DEV_EVENT_PORT_UP:
330 case MLX5_DEV_EVENT_PORT_DOWN:
331 queue_work(priv->wq, &priv->update_carrier_work);
339 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
341 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
344 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
346 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
347 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
350 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
351 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
353 static inline int mlx5e_get_wqe_mtt_sz(void)
355 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
356 * To avoid copying garbage after the mtt array, we allocate
359 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
360 MLX5_UMR_MTT_ALIGNMENT);
363 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
364 struct mlx5e_umr_wqe *wqe, u16 ix)
366 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
367 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
368 struct mlx5_wqe_data_seg *dseg = &wqe->data;
369 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
370 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
371 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
373 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
375 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
376 cseg->imm = rq->mkey_be;
378 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
379 ucseg->klm_octowords =
380 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
381 ucseg->bsf_octowords =
382 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
383 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
385 dseg->lkey = sq->mkey_be;
386 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
389 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
390 struct mlx5e_channel *c)
392 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
393 int mtt_sz = mlx5e_get_wqe_mtt_sz();
394 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
397 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
398 GFP_KERNEL, cpu_to_node(c->cpu));
402 /* We allocate more than mtt_sz as we will align the pointer */
403 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
404 cpu_to_node(c->cpu));
405 if (unlikely(!rq->mpwqe.mtt_no_align))
406 goto err_free_wqe_info;
408 for (i = 0; i < wq_sz; i++) {
409 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
411 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
413 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
415 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
418 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
425 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
427 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
430 kfree(rq->mpwqe.mtt_no_align);
432 kfree(rq->mpwqe.info);
438 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
440 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
441 int mtt_sz = mlx5e_get_wqe_mtt_sz();
444 for (i = 0; i < wq_sz; i++) {
445 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
447 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
450 kfree(rq->mpwqe.mtt_no_align);
451 kfree(rq->mpwqe.info);
454 static bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv)
456 struct mlx5_eswitch_rep *rep = (struct mlx5_eswitch_rep *)priv->ppriv;
458 if (rep && rep->vport != FDB_UPLINK_VPORT)
464 static int mlx5e_create_rq(struct mlx5e_channel *c,
465 struct mlx5e_rq_param *param,
468 struct mlx5e_priv *priv = c->priv;
469 struct mlx5_core_dev *mdev = priv->mdev;
470 void *rqc = param->rqc;
471 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
479 param->wq.db_numa_node = cpu_to_node(c->cpu);
481 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
486 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
488 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
490 rq->wq_type = priv->params.rq_wq_type;
492 rq->netdev = c->netdev;
493 rq->tstamp = &priv->tstamp;
497 rq->xdp_prog = priv->xdp_prog;
499 rq->buff.map_dir = DMA_FROM_DEVICE;
501 rq->buff.map_dir = DMA_BIDIRECTIONAL;
503 switch (priv->params.rq_wq_type) {
504 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
505 if (mlx5e_is_vf_vport_rep(priv)) {
507 goto err_rq_wq_destroy;
510 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
511 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
512 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
514 rq->mpwqe.mtt_offset = c->ix *
515 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
517 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
518 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
520 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
521 byte_count = rq->buff.wqe_sz;
522 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
523 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
525 goto err_rq_wq_destroy;
527 default: /* MLX5_WQ_TYPE_LINKED_LIST */
528 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
529 GFP_KERNEL, cpu_to_node(c->cpu));
532 goto err_rq_wq_destroy;
535 if (mlx5e_is_vf_vport_rep(priv))
536 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
538 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
540 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
541 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
543 rq->buff.wqe_sz = (priv->params.lro_en) ?
544 priv->params.lro_wqe_sz :
545 MLX5E_SW2HW_MTU(priv->netdev->mtu);
546 byte_count = rq->buff.wqe_sz;
548 /* calc the required page order */
549 frag_sz = MLX5_RX_HEADROOM +
550 byte_count /* packet data */ +
551 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
552 frag_sz = SKB_DATA_ALIGN(frag_sz);
554 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
555 rq->buff.page_order = order_base_2(npages);
557 byte_count |= MLX5_HW_START_PADDING;
558 rq->mkey_be = c->mkey_be;
561 for (i = 0; i < wq_sz; i++) {
562 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
564 wqe->data.byte_count = cpu_to_be32(byte_count);
565 wqe->data.lkey = rq->mkey_be;
568 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
569 rq->am.mode = priv->params.rx_cq_period_mode;
571 rq->page_cache.head = 0;
572 rq->page_cache.tail = 0;
575 bpf_prog_add(rq->xdp_prog, 1);
580 mlx5_wq_destroy(&rq->wq_ctrl);
585 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
590 bpf_prog_put(rq->xdp_prog);
592 switch (rq->wq_type) {
593 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
594 mlx5e_rq_free_mpwqe_info(rq);
596 default: /* MLX5_WQ_TYPE_LINKED_LIST */
600 for (i = rq->page_cache.head; i != rq->page_cache.tail;
601 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
602 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
604 mlx5e_page_release(rq, dma_info, false);
606 mlx5_wq_destroy(&rq->wq_ctrl);
609 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
611 struct mlx5e_priv *priv = rq->priv;
612 struct mlx5_core_dev *mdev = priv->mdev;
620 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
621 sizeof(u64) * rq->wq_ctrl.buf.npages;
622 in = mlx5_vzalloc(inlen);
626 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
627 wq = MLX5_ADDR_OF(rqc, rqc, wq);
629 memcpy(rqc, param->rqc, sizeof(param->rqc));
631 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
632 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
633 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
634 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
635 MLX5_ADAPTER_PAGE_SHIFT);
636 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
638 mlx5_fill_page_array(&rq->wq_ctrl.buf,
639 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
641 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
648 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
651 struct mlx5e_channel *c = rq->channel;
652 struct mlx5e_priv *priv = c->priv;
653 struct mlx5_core_dev *mdev = priv->mdev;
660 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
661 in = mlx5_vzalloc(inlen);
665 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
667 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
668 MLX5_SET(rqc, rqc, state, next_state);
670 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
677 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
679 struct mlx5e_channel *c = rq->channel;
680 struct mlx5e_priv *priv = c->priv;
681 struct mlx5_core_dev *mdev = priv->mdev;
688 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
689 in = mlx5_vzalloc(inlen);
693 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
695 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
696 MLX5_SET64(modify_rq_in, in, modify_bitmask,
697 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
698 MLX5_SET(rqc, rqc, vsd, vsd);
699 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
701 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
708 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
710 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
713 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
715 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
716 struct mlx5e_channel *c = rq->channel;
717 struct mlx5e_priv *priv = c->priv;
718 struct mlx5_wq_ll *wq = &rq->wq;
720 while (time_before(jiffies, exp_time)) {
721 if (wq->cur_sz >= priv->params.min_rx_wqes)
730 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
732 struct mlx5_wq_ll *wq = &rq->wq;
733 struct mlx5e_rx_wqe *wqe;
737 /* UMR WQE (if in progress) is always at wq->head */
738 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
739 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
741 while (!mlx5_wq_ll_is_empty(wq)) {
742 wqe_ix_be = *wq->tail_next;
743 wqe_ix = be16_to_cpu(wqe_ix_be);
744 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
745 rq->dealloc_wqe(rq, wqe_ix);
746 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
747 &wqe->next.next_wqe_index);
751 static int mlx5e_open_rq(struct mlx5e_channel *c,
752 struct mlx5e_rq_param *param,
755 struct mlx5e_sq *sq = &c->icosq;
756 u16 pi = sq->pc & sq->wq.sz_m1;
759 err = mlx5e_create_rq(c, param, rq);
763 err = mlx5e_enable_rq(rq, param);
767 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
768 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
772 if (param->am_enabled)
773 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
775 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
776 sq->db.ico_wqe[pi].num_wqebbs = 1;
777 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
782 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
783 mlx5e_disable_rq(rq);
785 mlx5e_destroy_rq(rq);
790 static void mlx5e_close_rq(struct mlx5e_rq *rq)
792 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
793 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
794 cancel_work_sync(&rq->am.work);
796 mlx5e_disable_rq(rq);
797 mlx5e_free_rx_descs(rq);
798 mlx5e_destroy_rq(rq);
801 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
803 kfree(sq->db.xdp.di);
804 kfree(sq->db.xdp.wqe_info);
807 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
809 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
811 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
813 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
815 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
816 mlx5e_free_sq_xdp_db(sq);
823 static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
825 kfree(sq->db.ico_wqe);
828 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
830 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
832 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
840 static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
842 kfree(sq->db.txq.wqe_info);
843 kfree(sq->db.txq.dma_fifo);
844 kfree(sq->db.txq.skb);
847 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
849 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
850 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
852 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
854 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
856 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
858 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
859 mlx5e_free_sq_txq_db(sq);
863 sq->dma_fifo_mask = df_sz - 1;
868 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
872 mlx5e_free_sq_txq_db(sq);
875 mlx5e_free_sq_ico_db(sq);
878 mlx5e_free_sq_xdp_db(sq);
883 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
887 return mlx5e_alloc_sq_txq_db(sq, numa);
889 return mlx5e_alloc_sq_ico_db(sq, numa);
891 return mlx5e_alloc_sq_xdp_db(sq, numa);
897 static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
901 return MLX5E_ICOSQ_MAX_WQEBBS;
903 return MLX5E_XDP_TX_WQEBBS;
905 return MLX5_SEND_WQE_MAX_WQEBBS;
908 static int mlx5e_create_sq(struct mlx5e_channel *c,
910 struct mlx5e_sq_param *param,
913 struct mlx5e_priv *priv = c->priv;
914 struct mlx5_core_dev *mdev = priv->mdev;
916 void *sqc = param->sqc;
917 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
920 sq->type = param->type;
922 sq->tstamp = &priv->tstamp;
923 sq->mkey_be = c->mkey_be;
927 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
931 param->wq.db_numa_node = cpu_to_node(c->cpu);
933 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
936 goto err_unmap_free_uar;
938 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
939 if (sq->uar.bf_map) {
940 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
941 sq->uar_map = sq->uar.bf_map;
943 sq->uar_map = sq->uar.map;
945 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
946 sq->max_inline = param->max_inline;
947 sq->min_inline_mode =
948 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
949 param->min_inline_mode : 0;
951 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
953 goto err_sq_wq_destroy;
955 if (sq->type == MLX5E_SQ_TXQ) {
958 txq_ix = c->ix + tc * priv->params.num_channels;
959 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
960 priv->txq_to_sq_map[txq_ix] = sq;
963 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
964 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
969 mlx5_wq_destroy(&sq->wq_ctrl);
972 mlx5_unmap_free_uar(mdev, &sq->uar);
977 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
979 struct mlx5e_channel *c = sq->channel;
980 struct mlx5e_priv *priv = c->priv;
982 mlx5e_free_sq_db(sq);
983 mlx5_wq_destroy(&sq->wq_ctrl);
984 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
987 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
989 struct mlx5e_channel *c = sq->channel;
990 struct mlx5e_priv *priv = c->priv;
991 struct mlx5_core_dev *mdev = priv->mdev;
999 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1000 sizeof(u64) * sq->wq_ctrl.buf.npages;
1001 in = mlx5_vzalloc(inlen);
1005 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1006 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1008 memcpy(sqc, param->sqc, sizeof(param->sqc));
1010 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1011 0 : priv->tisn[sq->tc]);
1012 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1013 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
1014 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1015 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
1017 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1018 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1019 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1020 MLX5_ADAPTER_PAGE_SHIFT);
1021 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1023 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1024 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1026 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1033 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1034 int next_state, bool update_rl, int rl_index)
1036 struct mlx5e_channel *c = sq->channel;
1037 struct mlx5e_priv *priv = c->priv;
1038 struct mlx5_core_dev *mdev = priv->mdev;
1045 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1046 in = mlx5_vzalloc(inlen);
1050 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1052 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1053 MLX5_SET(sqc, sqc, state, next_state);
1054 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1055 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1056 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1059 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
1066 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1068 struct mlx5e_channel *c = sq->channel;
1069 struct mlx5e_priv *priv = c->priv;
1070 struct mlx5_core_dev *mdev = priv->mdev;
1072 mlx5_core_destroy_sq(mdev, sq->sqn);
1074 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1077 static int mlx5e_open_sq(struct mlx5e_channel *c,
1079 struct mlx5e_sq_param *param,
1080 struct mlx5e_sq *sq)
1084 err = mlx5e_create_sq(c, tc, param, sq);
1088 err = mlx5e_enable_sq(sq, param);
1090 goto err_destroy_sq;
1092 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1093 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1096 goto err_disable_sq;
1099 netdev_tx_reset_queue(sq->txq);
1100 netif_tx_start_queue(sq->txq);
1106 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1107 mlx5e_disable_sq(sq);
1109 mlx5e_destroy_sq(sq);
1114 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1116 __netif_tx_lock_bh(txq);
1117 netif_tx_stop_queue(txq);
1118 __netif_tx_unlock_bh(txq);
1121 static void mlx5e_close_sq(struct mlx5e_sq *sq)
1123 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1124 /* prevent netif_tx_wake_queue */
1125 napi_synchronize(&sq->channel->napi);
1128 netif_tx_disable_queue(sq->txq);
1130 /* last doorbell out, godspeed .. */
1131 if (mlx5e_sq_has_room_for(sq, 1)) {
1132 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
1133 mlx5e_send_nop(sq, true);
1137 mlx5e_disable_sq(sq);
1138 mlx5e_free_sq_descs(sq);
1139 mlx5e_destroy_sq(sq);
1142 static int mlx5e_create_cq(struct mlx5e_channel *c,
1143 struct mlx5e_cq_param *param,
1144 struct mlx5e_cq *cq)
1146 struct mlx5e_priv *priv = c->priv;
1147 struct mlx5_core_dev *mdev = priv->mdev;
1148 struct mlx5_core_cq *mcq = &cq->mcq;
1154 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1155 param->wq.db_numa_node = cpu_to_node(c->cpu);
1156 param->eq_ix = c->ix;
1158 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1163 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1165 cq->napi = &c->napi;
1168 mcq->set_ci_db = cq->wq_ctrl.db.db;
1169 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1170 *mcq->set_ci_db = 0;
1172 mcq->vector = param->eq_ix;
1173 mcq->comp = mlx5e_completion_event;
1174 mcq->event = mlx5e_cq_error_event;
1176 mcq->uar = &mdev->mlx5e_res.cq_uar;
1178 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1179 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1190 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1192 mlx5_wq_destroy(&cq->wq_ctrl);
1195 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1197 struct mlx5e_priv *priv = cq->priv;
1198 struct mlx5_core_dev *mdev = priv->mdev;
1199 struct mlx5_core_cq *mcq = &cq->mcq;
1204 unsigned int irqn_not_used;
1208 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1209 sizeof(u64) * cq->wq_ctrl.buf.npages;
1210 in = mlx5_vzalloc(inlen);
1214 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1216 memcpy(cqc, param->cqc, sizeof(param->cqc));
1218 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1219 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1221 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1223 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1224 MLX5_SET(cqc, cqc, c_eqn, eqn);
1225 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1226 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1227 MLX5_ADAPTER_PAGE_SHIFT);
1228 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1230 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1242 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1244 struct mlx5e_priv *priv = cq->priv;
1245 struct mlx5_core_dev *mdev = priv->mdev;
1247 mlx5_core_destroy_cq(mdev, &cq->mcq);
1250 static int mlx5e_open_cq(struct mlx5e_channel *c,
1251 struct mlx5e_cq_param *param,
1252 struct mlx5e_cq *cq,
1253 struct mlx5e_cq_moder moderation)
1256 struct mlx5e_priv *priv = c->priv;
1257 struct mlx5_core_dev *mdev = priv->mdev;
1259 err = mlx5e_create_cq(c, param, cq);
1263 err = mlx5e_enable_cq(cq, param);
1265 goto err_destroy_cq;
1267 if (MLX5_CAP_GEN(mdev, cq_moderation))
1268 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1274 mlx5e_destroy_cq(cq);
1279 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1281 mlx5e_disable_cq(cq);
1282 mlx5e_destroy_cq(cq);
1285 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1287 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1290 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1291 struct mlx5e_channel_param *cparam)
1293 struct mlx5e_priv *priv = c->priv;
1297 for (tc = 0; tc < c->num_tc; tc++) {
1298 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1299 priv->params.tx_cq_moderation);
1301 goto err_close_tx_cqs;
1307 for (tc--; tc >= 0; tc--)
1308 mlx5e_close_cq(&c->sq[tc].cq);
1313 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1317 for (tc = 0; tc < c->num_tc; tc++)
1318 mlx5e_close_cq(&c->sq[tc].cq);
1321 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1322 struct mlx5e_channel_param *cparam)
1327 for (tc = 0; tc < c->num_tc; tc++) {
1328 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1336 for (tc--; tc >= 0; tc--)
1337 mlx5e_close_sq(&c->sq[tc]);
1342 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1346 for (tc = 0; tc < c->num_tc; tc++)
1347 mlx5e_close_sq(&c->sq[tc]);
1350 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1354 for (i = 0; i < priv->profile->max_tc; i++)
1355 priv->channeltc_to_txq_map[ix][i] =
1356 ix + i * priv->params.num_channels;
1359 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1360 struct mlx5e_sq *sq, u32 rate)
1362 struct mlx5e_priv *priv = netdev_priv(dev);
1363 struct mlx5_core_dev *mdev = priv->mdev;
1367 if (rate == sq->rate_limit)
1372 /* remove current rl index to free space to next ones */
1373 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1378 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1380 netdev_err(dev, "Failed configuring rate %u: %d\n",
1386 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1387 MLX5_SQC_STATE_RDY, true, rl_index);
1389 netdev_err(dev, "Failed configuring rate %u: %d\n",
1391 /* remove the rate from the table */
1393 mlx5_rl_remove_rate(mdev, rate);
1397 sq->rate_limit = rate;
1401 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1403 struct mlx5e_priv *priv = netdev_priv(dev);
1404 struct mlx5_core_dev *mdev = priv->mdev;
1405 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1408 if (!mlx5_rl_is_supported(mdev)) {
1409 netdev_err(dev, "Rate limiting is not supported on this device\n");
1413 /* rate is given in Mb/sec, HW config is in Kb/sec */
1416 /* Check whether rate in valid range, 0 is always valid */
1417 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1418 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1422 mutex_lock(&priv->state_lock);
1423 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1424 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1426 priv->tx_rates[index] = rate;
1427 mutex_unlock(&priv->state_lock);
1432 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1433 struct mlx5e_channel_param *cparam,
1434 struct mlx5e_channel **cp)
1436 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1437 struct net_device *netdev = priv->netdev;
1438 struct mlx5e_cq_moder rx_cq_profile;
1439 int cpu = mlx5e_get_cpu(priv, ix);
1440 struct mlx5e_channel *c;
1441 struct mlx5e_sq *sq;
1445 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1452 c->pdev = &priv->mdev->pdev->dev;
1453 c->netdev = priv->netdev;
1454 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1455 c->num_tc = priv->params.num_tc;
1456 c->xdp = !!priv->xdp_prog;
1458 if (priv->params.rx_am_enabled)
1459 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1461 rx_cq_profile = priv->params.rx_cq_moderation;
1463 mlx5e_build_channeltc_to_txq_map(priv, ix);
1465 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1467 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1471 err = mlx5e_open_tx_cqs(c, cparam);
1473 goto err_close_icosq_cq;
1475 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1478 goto err_close_tx_cqs;
1480 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1481 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1482 priv->params.tx_cq_moderation) : 0;
1484 goto err_close_rx_cq;
1486 napi_enable(&c->napi);
1488 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1490 goto err_disable_napi;
1492 err = mlx5e_open_sqs(c, cparam);
1494 goto err_close_icosq;
1496 for (i = 0; i < priv->params.num_tc; i++) {
1497 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1499 if (priv->tx_rates[txq_ix]) {
1500 sq = priv->txq_to_sq_map[txq_ix];
1501 mlx5e_set_sq_maxrate(priv->netdev, sq,
1502 priv->tx_rates[txq_ix]);
1506 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1510 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1512 goto err_close_xdp_sq;
1514 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1520 mlx5e_close_sq(&c->xdp_sq);
1526 mlx5e_close_sq(&c->icosq);
1529 napi_disable(&c->napi);
1531 mlx5e_close_cq(&c->xdp_sq.cq);
1534 mlx5e_close_cq(&c->rq.cq);
1537 mlx5e_close_tx_cqs(c);
1540 mlx5e_close_cq(&c->icosq.cq);
1543 netif_napi_del(&c->napi);
1544 napi_hash_del(&c->napi);
1550 static void mlx5e_close_channel(struct mlx5e_channel *c)
1552 mlx5e_close_rq(&c->rq);
1554 mlx5e_close_sq(&c->xdp_sq);
1556 mlx5e_close_sq(&c->icosq);
1557 napi_disable(&c->napi);
1559 mlx5e_close_cq(&c->xdp_sq.cq);
1560 mlx5e_close_cq(&c->rq.cq);
1561 mlx5e_close_tx_cqs(c);
1562 mlx5e_close_cq(&c->icosq.cq);
1563 netif_napi_del(&c->napi);
1565 napi_hash_del(&c->napi);
1571 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1572 struct mlx5e_rq_param *param)
1574 void *rqc = param->rqc;
1575 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1577 switch (priv->params.rq_wq_type) {
1578 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1579 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1580 priv->params.mpwqe_log_num_strides - 9);
1581 MLX5_SET(wq, wq, log_wqe_stride_size,
1582 priv->params.mpwqe_log_stride_sz - 6);
1583 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1585 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1586 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1589 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1590 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1591 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1592 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1593 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1595 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1596 param->wq.linear = 1;
1598 param->am_enabled = priv->params.rx_am_enabled;
1601 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1603 void *rqc = param->rqc;
1604 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1606 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1607 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1610 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1611 struct mlx5e_sq_param *param)
1613 void *sqc = param->sqc;
1614 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1616 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1617 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1619 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1622 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1623 struct mlx5e_sq_param *param)
1625 void *sqc = param->sqc;
1626 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1628 mlx5e_build_sq_param_common(priv, param);
1629 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1631 param->max_inline = priv->params.tx_max_inline;
1632 param->min_inline_mode = priv->params.tx_min_inline_mode;
1633 param->type = MLX5E_SQ_TXQ;
1636 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1637 struct mlx5e_cq_param *param)
1639 void *cqc = param->cqc;
1641 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1644 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1645 struct mlx5e_cq_param *param)
1647 void *cqc = param->cqc;
1650 switch (priv->params.rq_wq_type) {
1651 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1652 log_cq_size = priv->params.log_rq_size +
1653 priv->params.mpwqe_log_num_strides;
1655 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1656 log_cq_size = priv->params.log_rq_size;
1659 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1660 if (priv->params.rx_cqe_compress) {
1661 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1662 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1665 mlx5e_build_common_cq_param(priv, param);
1667 param->cq_period_mode = priv->params.rx_cq_period_mode;
1670 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1671 struct mlx5e_cq_param *param)
1673 void *cqc = param->cqc;
1675 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1677 mlx5e_build_common_cq_param(priv, param);
1679 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1682 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1683 struct mlx5e_cq_param *param,
1686 void *cqc = param->cqc;
1688 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1690 mlx5e_build_common_cq_param(priv, param);
1692 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1695 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1696 struct mlx5e_sq_param *param,
1699 void *sqc = param->sqc;
1700 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1702 mlx5e_build_sq_param_common(priv, param);
1704 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1705 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1707 param->type = MLX5E_SQ_ICO;
1710 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1711 struct mlx5e_sq_param *param)
1713 void *sqc = param->sqc;
1714 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1716 mlx5e_build_sq_param_common(priv, param);
1717 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1719 param->max_inline = priv->params.tx_max_inline;
1720 /* FOR XDP SQs will support only L2 inline mode */
1721 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1722 param->type = MLX5E_SQ_XDP;
1725 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1727 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1729 mlx5e_build_rq_param(priv, &cparam->rq);
1730 mlx5e_build_sq_param(priv, &cparam->sq);
1731 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
1732 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1733 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1734 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1735 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1738 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1740 struct mlx5e_channel_param *cparam;
1741 int nch = priv->params.num_channels;
1746 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1749 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1750 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1752 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1754 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1755 goto err_free_txq_to_sq_map;
1757 mlx5e_build_channel_param(priv, cparam);
1759 for (i = 0; i < nch; i++) {
1760 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1762 goto err_close_channels;
1765 for (j = 0; j < nch; j++) {
1766 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1768 goto err_close_channels;
1771 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1772 * polling for inactive tx queues.
1774 netif_tx_start_all_queues(priv->netdev);
1780 for (i--; i >= 0; i--)
1781 mlx5e_close_channel(priv->channel[i]);
1783 err_free_txq_to_sq_map:
1784 kfree(priv->txq_to_sq_map);
1785 kfree(priv->channel);
1791 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1795 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1796 * polling for inactive tx queues.
1798 netif_tx_stop_all_queues(priv->netdev);
1799 netif_tx_disable(priv->netdev);
1801 for (i = 0; i < priv->params.num_channels; i++)
1802 mlx5e_close_channel(priv->channel[i]);
1804 kfree(priv->txq_to_sq_map);
1805 kfree(priv->channel);
1808 static int mlx5e_rx_hash_fn(int hfunc)
1810 return (hfunc == ETH_RSS_HASH_TOP) ?
1811 MLX5_RX_HASH_FN_TOEPLITZ :
1812 MLX5_RX_HASH_FN_INVERTED_XOR8;
1815 static int mlx5e_bits_invert(unsigned long a, int size)
1820 for (i = 0; i < size; i++)
1821 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1826 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1830 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1834 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1835 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1837 ix = priv->params.indirection_rqt[ix];
1838 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1839 priv->channel[ix]->rq.rqn :
1841 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1845 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1848 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1849 priv->channel[ix]->rq.rqn :
1852 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1855 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1856 int ix, struct mlx5e_rqt *rqt)
1858 struct mlx5_core_dev *mdev = priv->mdev;
1864 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1865 in = mlx5_vzalloc(inlen);
1869 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1871 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1872 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1874 if (sz > 1) /* RSS */
1875 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1877 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1879 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1881 rqt->enabled = true;
1887 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1889 rqt->enabled = false;
1890 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1893 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1895 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1897 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1900 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1902 struct mlx5e_rqt *rqt;
1906 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1907 rqt = &priv->direct_tir[ix].rqt;
1908 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1910 goto err_destroy_rqts;
1916 for (ix--; ix >= 0; ix--)
1917 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1922 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1924 struct mlx5_core_dev *mdev = priv->mdev;
1930 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1931 in = mlx5_vzalloc(inlen);
1935 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1937 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1938 if (sz > 1) /* RSS */
1939 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1941 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1943 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1945 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1952 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1957 if (priv->indir_rqt.enabled) {
1958 rqtn = priv->indir_rqt.rqtn;
1959 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1962 for (ix = 0; ix < priv->params.num_channels; ix++) {
1963 if (!priv->direct_tir[ix].rqt.enabled)
1965 rqtn = priv->direct_tir[ix].rqt.rqtn;
1966 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1970 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1972 if (!priv->params.lro_en)
1975 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1977 MLX5_SET(tirc, tirc, lro_enable_mask,
1978 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1979 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1980 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1981 (priv->params.lro_wqe_sz -
1982 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1983 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
1986 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
1987 enum mlx5e_traffic_types tt)
1989 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1991 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1992 MLX5_HASH_FIELD_SEL_DST_IP)
1994 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1995 MLX5_HASH_FIELD_SEL_DST_IP |\
1996 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1997 MLX5_HASH_FIELD_SEL_L4_DPORT)
1999 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2000 MLX5_HASH_FIELD_SEL_DST_IP |\
2001 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2003 MLX5_SET(tirc, tirc, rx_hash_fn,
2004 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
2005 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
2006 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2007 rx_hash_toeplitz_key);
2008 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2009 rx_hash_toeplitz_key);
2011 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2012 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2016 case MLX5E_TT_IPV4_TCP:
2017 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2018 MLX5_L3_PROT_TYPE_IPV4);
2019 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2020 MLX5_L4_PROT_TYPE_TCP);
2021 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2022 MLX5_HASH_IP_L4PORTS);
2025 case MLX5E_TT_IPV6_TCP:
2026 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2027 MLX5_L3_PROT_TYPE_IPV6);
2028 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2029 MLX5_L4_PROT_TYPE_TCP);
2030 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2031 MLX5_HASH_IP_L4PORTS);
2034 case MLX5E_TT_IPV4_UDP:
2035 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2036 MLX5_L3_PROT_TYPE_IPV4);
2037 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2038 MLX5_L4_PROT_TYPE_UDP);
2039 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2040 MLX5_HASH_IP_L4PORTS);
2043 case MLX5E_TT_IPV6_UDP:
2044 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2045 MLX5_L3_PROT_TYPE_IPV6);
2046 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2047 MLX5_L4_PROT_TYPE_UDP);
2048 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2049 MLX5_HASH_IP_L4PORTS);
2052 case MLX5E_TT_IPV4_IPSEC_AH:
2053 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2054 MLX5_L3_PROT_TYPE_IPV4);
2055 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2056 MLX5_HASH_IP_IPSEC_SPI);
2059 case MLX5E_TT_IPV6_IPSEC_AH:
2060 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2061 MLX5_L3_PROT_TYPE_IPV6);
2062 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2063 MLX5_HASH_IP_IPSEC_SPI);
2066 case MLX5E_TT_IPV4_IPSEC_ESP:
2067 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2068 MLX5_L3_PROT_TYPE_IPV4);
2069 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2070 MLX5_HASH_IP_IPSEC_SPI);
2073 case MLX5E_TT_IPV6_IPSEC_ESP:
2074 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2075 MLX5_L3_PROT_TYPE_IPV6);
2076 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2077 MLX5_HASH_IP_IPSEC_SPI);
2081 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2082 MLX5_L3_PROT_TYPE_IPV4);
2083 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2088 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2089 MLX5_L3_PROT_TYPE_IPV6);
2090 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2094 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2098 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2100 struct mlx5_core_dev *mdev = priv->mdev;
2109 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2110 in = mlx5_vzalloc(inlen);
2114 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2115 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2117 mlx5e_build_tir_ctx_lro(tirc, priv);
2119 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2120 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2126 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2127 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2139 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2141 struct mlx5_core_dev *mdev = priv->mdev;
2142 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2145 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2149 /* Update vport context MTU */
2150 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2154 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2156 struct mlx5_core_dev *mdev = priv->mdev;
2160 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2161 if (err || !hw_mtu) /* fallback to port oper mtu */
2162 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2164 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2167 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2169 struct mlx5e_priv *priv = netdev_priv(netdev);
2173 err = mlx5e_set_mtu(priv, netdev->mtu);
2177 mlx5e_query_mtu(priv, &mtu);
2178 if (mtu != netdev->mtu)
2179 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2180 __func__, mtu, netdev->mtu);
2186 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2188 struct mlx5e_priv *priv = netdev_priv(netdev);
2189 int nch = priv->params.num_channels;
2190 int ntc = priv->params.num_tc;
2193 netdev_reset_tc(netdev);
2198 netdev_set_num_tc(netdev, ntc);
2200 /* Map netdev TCs to offset 0
2201 * We have our own UP to TXQ mapping for QoS
2203 for (tc = 0; tc < ntc; tc++)
2204 netdev_set_tc_queue(netdev, tc, nch, 0);
2207 int mlx5e_open_locked(struct net_device *netdev)
2209 struct mlx5e_priv *priv = netdev_priv(netdev);
2210 struct mlx5_core_dev *mdev = priv->mdev;
2214 set_bit(MLX5E_STATE_OPENED, &priv->state);
2216 mlx5e_netdev_set_tcs(netdev);
2218 num_txqs = priv->params.num_channels * priv->params.num_tc;
2219 netif_set_real_num_tx_queues(netdev, num_txqs);
2220 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2222 err = mlx5e_open_channels(priv);
2224 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2226 goto err_clear_state_opened_flag;
2229 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
2231 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2233 goto err_close_channels;
2236 mlx5e_redirect_rqts(priv);
2237 mlx5e_update_carrier(priv);
2238 mlx5e_timestamp_init(priv);
2239 #ifdef CONFIG_RFS_ACCEL
2240 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2242 if (priv->profile->update_stats)
2243 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2245 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2246 err = mlx5e_add_sqs_fwd_rules(priv);
2248 goto err_close_channels;
2253 mlx5e_close_channels(priv);
2254 err_clear_state_opened_flag:
2255 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2259 int mlx5e_open(struct net_device *netdev)
2261 struct mlx5e_priv *priv = netdev_priv(netdev);
2264 mutex_lock(&priv->state_lock);
2265 err = mlx5e_open_locked(netdev);
2266 mutex_unlock(&priv->state_lock);
2271 int mlx5e_close_locked(struct net_device *netdev)
2273 struct mlx5e_priv *priv = netdev_priv(netdev);
2274 struct mlx5_core_dev *mdev = priv->mdev;
2276 /* May already be CLOSED in case a previous configuration operation
2277 * (e.g RX/TX queue size change) that involves close&open failed.
2279 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2282 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2284 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2285 mlx5e_remove_sqs_fwd_rules(priv);
2287 mlx5e_timestamp_cleanup(priv);
2288 netif_carrier_off(priv->netdev);
2289 mlx5e_redirect_rqts(priv);
2290 mlx5e_close_channels(priv);
2295 int mlx5e_close(struct net_device *netdev)
2297 struct mlx5e_priv *priv = netdev_priv(netdev);
2300 if (!netif_device_present(netdev))
2303 mutex_lock(&priv->state_lock);
2304 err = mlx5e_close_locked(netdev);
2305 mutex_unlock(&priv->state_lock);
2310 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2311 struct mlx5e_rq *rq,
2312 struct mlx5e_rq_param *param)
2314 struct mlx5_core_dev *mdev = priv->mdev;
2315 void *rqc = param->rqc;
2316 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2319 param->wq.db_numa_node = param->wq.buf_numa_node;
2321 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2331 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2332 struct mlx5e_cq *cq,
2333 struct mlx5e_cq_param *param)
2335 struct mlx5_core_dev *mdev = priv->mdev;
2336 struct mlx5_core_cq *mcq = &cq->mcq;
2341 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2346 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2349 mcq->set_ci_db = cq->wq_ctrl.db.db;
2350 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2351 *mcq->set_ci_db = 0;
2353 mcq->vector = param->eq_ix;
2354 mcq->comp = mlx5e_completion_event;
2355 mcq->event = mlx5e_cq_error_event;
2357 mcq->uar = &mdev->mlx5e_res.cq_uar;
2364 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2366 struct mlx5e_cq_param cq_param;
2367 struct mlx5e_rq_param rq_param;
2368 struct mlx5e_rq *rq = &priv->drop_rq;
2369 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2372 memset(&cq_param, 0, sizeof(cq_param));
2373 memset(&rq_param, 0, sizeof(rq_param));
2374 mlx5e_build_drop_rq_param(&rq_param);
2376 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2380 err = mlx5e_enable_cq(cq, &cq_param);
2382 goto err_destroy_cq;
2384 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2386 goto err_disable_cq;
2388 err = mlx5e_enable_rq(rq, &rq_param);
2390 goto err_destroy_rq;
2395 mlx5e_destroy_rq(&priv->drop_rq);
2398 mlx5e_disable_cq(&priv->drop_rq.cq);
2401 mlx5e_destroy_cq(&priv->drop_rq.cq);
2406 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2408 mlx5e_disable_rq(&priv->drop_rq);
2409 mlx5e_destroy_rq(&priv->drop_rq);
2410 mlx5e_disable_cq(&priv->drop_rq.cq);
2411 mlx5e_destroy_cq(&priv->drop_rq.cq);
2414 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2416 struct mlx5_core_dev *mdev = priv->mdev;
2417 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2418 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2420 MLX5_SET(tisc, tisc, prio, tc << 1);
2421 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2423 if (mlx5_lag_is_lacp_owner(mdev))
2424 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2426 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2429 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2431 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2434 int mlx5e_create_tises(struct mlx5e_priv *priv)
2439 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2440 err = mlx5e_create_tis(priv, tc);
2442 goto err_close_tises;
2448 for (tc--; tc >= 0; tc--)
2449 mlx5e_destroy_tis(priv, tc);
2454 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2458 for (tc = 0; tc < priv->profile->max_tc; tc++)
2459 mlx5e_destroy_tis(priv, tc);
2462 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2463 enum mlx5e_traffic_types tt)
2465 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2467 mlx5e_build_tir_ctx_lro(tirc, priv);
2469 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2470 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2471 mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
2474 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2477 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2479 mlx5e_build_tir_ctx_lro(tirc, priv);
2481 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2482 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2483 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2486 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2488 struct mlx5e_tir *tir;
2495 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2496 in = mlx5_vzalloc(inlen);
2500 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2501 memset(in, 0, inlen);
2502 tir = &priv->indir_tir[tt];
2503 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2504 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2505 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2507 goto err_destroy_tirs;
2515 for (tt--; tt >= 0; tt--)
2516 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2523 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2525 int nch = priv->profile->max_nch(priv->mdev);
2526 struct mlx5e_tir *tir;
2533 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2534 in = mlx5_vzalloc(inlen);
2538 for (ix = 0; ix < nch; ix++) {
2539 memset(in, 0, inlen);
2540 tir = &priv->direct_tir[ix];
2541 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2542 mlx5e_build_direct_tir_ctx(priv, tirc,
2543 priv->direct_tir[ix].rqt.rqtn);
2544 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2546 goto err_destroy_ch_tirs;
2553 err_destroy_ch_tirs:
2554 for (ix--; ix >= 0; ix--)
2555 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2562 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2566 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2567 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2570 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2572 int nch = priv->profile->max_nch(priv->mdev);
2575 for (i = 0; i < nch; i++)
2576 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2579 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2584 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2587 for (i = 0; i < priv->params.num_channels; i++) {
2588 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2596 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2598 struct mlx5e_priv *priv = netdev_priv(netdev);
2602 if (tc && tc != MLX5E_MAX_NUM_TC)
2605 mutex_lock(&priv->state_lock);
2607 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2609 mlx5e_close_locked(priv->netdev);
2611 priv->params.num_tc = tc ? tc : 1;
2614 err = mlx5e_open_locked(priv->netdev);
2616 mutex_unlock(&priv->state_lock);
2621 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2622 __be16 proto, struct tc_to_netdev *tc)
2624 struct mlx5e_priv *priv = netdev_priv(dev);
2626 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2630 case TC_SETUP_CLSFLOWER:
2631 switch (tc->cls_flower->command) {
2632 case TC_CLSFLOWER_REPLACE:
2633 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2634 case TC_CLSFLOWER_DESTROY:
2635 return mlx5e_delete_flower(priv, tc->cls_flower);
2636 case TC_CLSFLOWER_STATS:
2637 return mlx5e_stats_flower(priv, tc->cls_flower);
2644 if (tc->type != TC_SETUP_MQPRIO)
2647 return mlx5e_setup_tc(dev, tc->tc);
2650 struct rtnl_link_stats64 *
2651 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2653 struct mlx5e_priv *priv = netdev_priv(dev);
2654 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2655 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2656 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2658 stats->rx_packets = sstats->rx_packets;
2659 stats->rx_bytes = sstats->rx_bytes;
2660 stats->tx_packets = sstats->tx_packets;
2661 stats->tx_bytes = sstats->tx_bytes;
2663 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2664 stats->tx_dropped = sstats->tx_queue_dropped;
2666 stats->rx_length_errors =
2667 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2668 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2669 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2670 stats->rx_crc_errors =
2671 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2672 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2673 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2674 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2675 stats->rx_frame_errors;
2676 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2678 /* vport multicast also counts packets that are dropped due to steering
2679 * or rx out of buffer
2682 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2687 static void mlx5e_set_rx_mode(struct net_device *dev)
2689 struct mlx5e_priv *priv = netdev_priv(dev);
2691 queue_work(priv->wq, &priv->set_rx_mode_work);
2694 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2696 struct mlx5e_priv *priv = netdev_priv(netdev);
2697 struct sockaddr *saddr = addr;
2699 if (!is_valid_ether_addr(saddr->sa_data))
2700 return -EADDRNOTAVAIL;
2702 netif_addr_lock_bh(netdev);
2703 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2704 netif_addr_unlock_bh(netdev);
2706 queue_work(priv->wq, &priv->set_rx_mode_work);
2711 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2714 netdev->features |= feature; \
2716 netdev->features &= ~feature; \
2719 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2721 static int set_feature_lro(struct net_device *netdev, bool enable)
2723 struct mlx5e_priv *priv = netdev_priv(netdev);
2724 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2727 mutex_lock(&priv->state_lock);
2729 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2730 mlx5e_close_locked(priv->netdev);
2732 priv->params.lro_en = enable;
2733 err = mlx5e_modify_tirs_lro(priv);
2735 netdev_err(netdev, "lro modify failed, %d\n", err);
2736 priv->params.lro_en = !enable;
2739 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2740 mlx5e_open_locked(priv->netdev);
2742 mutex_unlock(&priv->state_lock);
2744 if (mlx5e_vxlan_allowed(priv->mdev))
2745 udp_tunnel_get_rx_info(netdev);
2750 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2752 struct mlx5e_priv *priv = netdev_priv(netdev);
2755 mlx5e_enable_vlan_filter(priv);
2757 mlx5e_disable_vlan_filter(priv);
2762 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2764 struct mlx5e_priv *priv = netdev_priv(netdev);
2766 if (!enable && mlx5e_tc_num_filters(priv)) {
2768 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2775 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2777 struct mlx5e_priv *priv = netdev_priv(netdev);
2778 struct mlx5_core_dev *mdev = priv->mdev;
2780 return mlx5_set_port_fcs(mdev, !enable);
2783 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2785 struct mlx5e_priv *priv = netdev_priv(netdev);
2788 mutex_lock(&priv->state_lock);
2790 priv->params.vlan_strip_disable = !enable;
2791 err = mlx5e_modify_rqs_vsd(priv, !enable);
2793 priv->params.vlan_strip_disable = enable;
2795 mutex_unlock(&priv->state_lock);
2800 #ifdef CONFIG_RFS_ACCEL
2801 static int set_feature_arfs(struct net_device *netdev, bool enable)
2803 struct mlx5e_priv *priv = netdev_priv(netdev);
2807 err = mlx5e_arfs_enable(priv);
2809 err = mlx5e_arfs_disable(priv);
2815 static int mlx5e_handle_feature(struct net_device *netdev,
2816 netdev_features_t wanted_features,
2817 netdev_features_t feature,
2818 mlx5e_feature_handler feature_handler)
2820 netdev_features_t changes = wanted_features ^ netdev->features;
2821 bool enable = !!(wanted_features & feature);
2824 if (!(changes & feature))
2827 err = feature_handler(netdev, enable);
2829 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2830 enable ? "Enable" : "Disable", feature, err);
2834 MLX5E_SET_FEATURE(netdev, feature, enable);
2838 static int mlx5e_set_features(struct net_device *netdev,
2839 netdev_features_t features)
2843 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2845 err |= mlx5e_handle_feature(netdev, features,
2846 NETIF_F_HW_VLAN_CTAG_FILTER,
2847 set_feature_vlan_filter);
2848 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2849 set_feature_tc_num_filters);
2850 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2851 set_feature_rx_all);
2852 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2853 set_feature_rx_vlan);
2854 #ifdef CONFIG_RFS_ACCEL
2855 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2859 return err ? -EINVAL : 0;
2862 #define MXL5_HW_MIN_MTU 64
2863 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2865 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2867 struct mlx5e_priv *priv = netdev_priv(netdev);
2868 struct mlx5_core_dev *mdev = priv->mdev;
2875 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2877 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2878 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2880 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2882 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2883 __func__, new_mtu, min_mtu, max_mtu);
2887 mutex_lock(&priv->state_lock);
2889 reset = !priv->params.lro_en &&
2890 (priv->params.rq_wq_type !=
2891 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2893 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2894 if (was_opened && reset)
2895 mlx5e_close_locked(netdev);
2897 netdev->mtu = new_mtu;
2898 mlx5e_set_dev_port_mtu(netdev);
2900 if (was_opened && reset)
2901 err = mlx5e_open_locked(netdev);
2903 mutex_unlock(&priv->state_lock);
2908 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2912 return mlx5e_hwstamp_set(dev, ifr);
2914 return mlx5e_hwstamp_get(dev, ifr);
2920 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2922 struct mlx5e_priv *priv = netdev_priv(dev);
2923 struct mlx5_core_dev *mdev = priv->mdev;
2925 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2928 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2931 struct mlx5e_priv *priv = netdev_priv(dev);
2932 struct mlx5_core_dev *mdev = priv->mdev;
2934 if (vlan_proto != htons(ETH_P_8021Q))
2935 return -EPROTONOSUPPORT;
2937 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2941 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2943 struct mlx5e_priv *priv = netdev_priv(dev);
2944 struct mlx5_core_dev *mdev = priv->mdev;
2946 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2949 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2951 struct mlx5e_priv *priv = netdev_priv(dev);
2952 struct mlx5_core_dev *mdev = priv->mdev;
2954 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2956 static int mlx5_vport_link2ifla(u8 esw_link)
2959 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2960 return IFLA_VF_LINK_STATE_DISABLE;
2961 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2962 return IFLA_VF_LINK_STATE_ENABLE;
2964 return IFLA_VF_LINK_STATE_AUTO;
2967 static int mlx5_ifla_link2vport(u8 ifla_link)
2969 switch (ifla_link) {
2970 case IFLA_VF_LINK_STATE_DISABLE:
2971 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2972 case IFLA_VF_LINK_STATE_ENABLE:
2973 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2975 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2978 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2981 struct mlx5e_priv *priv = netdev_priv(dev);
2982 struct mlx5_core_dev *mdev = priv->mdev;
2984 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2985 mlx5_ifla_link2vport(link_state));
2988 static int mlx5e_get_vf_config(struct net_device *dev,
2989 int vf, struct ifla_vf_info *ivi)
2991 struct mlx5e_priv *priv = netdev_priv(dev);
2992 struct mlx5_core_dev *mdev = priv->mdev;
2995 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2998 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3002 static int mlx5e_get_vf_stats(struct net_device *dev,
3003 int vf, struct ifla_vf_stats *vf_stats)
3005 struct mlx5e_priv *priv = netdev_priv(dev);
3006 struct mlx5_core_dev *mdev = priv->mdev;
3008 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3012 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3013 struct udp_tunnel_info *ti)
3015 struct mlx5e_priv *priv = netdev_priv(netdev);
3017 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3020 if (!mlx5e_vxlan_allowed(priv->mdev))
3023 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3026 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3027 struct udp_tunnel_info *ti)
3029 struct mlx5e_priv *priv = netdev_priv(netdev);
3031 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3034 if (!mlx5e_vxlan_allowed(priv->mdev))
3037 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3040 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3041 struct sk_buff *skb,
3042 netdev_features_t features)
3044 unsigned int offset = 0;
3045 struct udphdr *udph;
3049 switch (vlan_get_protocol(skb)) {
3050 case htons(ETH_P_IP):
3051 proto = ip_hdr(skb)->protocol;
3053 case htons(ETH_P_IPV6):
3054 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3060 if (proto == IPPROTO_UDP) {
3061 udph = udp_hdr(skb);
3062 port = be16_to_cpu(udph->dest);
3065 /* Verify if UDP port is being offloaded by HW */
3066 if (port && mlx5e_vxlan_lookup_port(priv, port))
3070 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3071 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3074 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3075 struct net_device *netdev,
3076 netdev_features_t features)
3078 struct mlx5e_priv *priv = netdev_priv(netdev);
3080 features = vlan_features_check(skb, features);
3081 features = vxlan_features_check(skb, features);
3083 /* Validate if the tunneled packet is being offloaded by HW */
3084 if (skb->encapsulation &&
3085 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3086 return mlx5e_vxlan_features_check(priv, skb, features);
3091 static void mlx5e_tx_timeout(struct net_device *dev)
3093 struct mlx5e_priv *priv = netdev_priv(dev);
3094 bool sched_work = false;
3097 netdev_err(dev, "TX timeout detected\n");
3099 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3100 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3102 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3105 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3106 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3107 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3110 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3111 schedule_work(&priv->tx_timeout_work);
3114 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3116 struct mlx5e_priv *priv = netdev_priv(netdev);
3117 struct bpf_prog *old_prog;
3119 bool reset, was_opened;
3122 mutex_lock(&priv->state_lock);
3124 if ((netdev->features & NETIF_F_LRO) && prog) {
3125 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3130 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3131 /* no need for full reset when exchanging programs */
3132 reset = (!priv->xdp_prog || !prog);
3134 if (was_opened && reset)
3135 mlx5e_close_locked(netdev);
3137 /* exchange programs */
3138 old_prog = xchg(&priv->xdp_prog, prog);
3140 bpf_prog_add(prog, 1);
3142 bpf_prog_put(old_prog);
3144 if (reset) /* change RQ type according to priv->xdp_prog */
3145 mlx5e_set_rq_priv_params(priv);
3147 if (was_opened && reset)
3148 mlx5e_open_locked(netdev);
3150 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3153 /* exchanging programs w/o reset, we update ref counts on behalf
3154 * of the channels RQs here.
3156 bpf_prog_add(prog, priv->params.num_channels);
3157 for (i = 0; i < priv->params.num_channels; i++) {
3158 struct mlx5e_channel *c = priv->channel[i];
3160 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3161 napi_synchronize(&c->napi);
3162 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3164 old_prog = xchg(&c->rq.xdp_prog, prog);
3166 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3167 /* napi_schedule in case we have missed anything */
3168 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3169 napi_schedule(&c->napi);
3172 bpf_prog_put(old_prog);
3176 mutex_unlock(&priv->state_lock);
3180 static bool mlx5e_xdp_attached(struct net_device *dev)
3182 struct mlx5e_priv *priv = netdev_priv(dev);
3184 return !!priv->xdp_prog;
3187 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3189 switch (xdp->command) {
3190 case XDP_SETUP_PROG:
3191 return mlx5e_xdp_set(dev, xdp->prog);
3192 case XDP_QUERY_PROG:
3193 xdp->prog_attached = mlx5e_xdp_attached(dev);
3200 #ifdef CONFIG_NET_POLL_CONTROLLER
3201 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3202 * reenabling interrupts.
3204 static void mlx5e_netpoll(struct net_device *dev)
3206 struct mlx5e_priv *priv = netdev_priv(dev);
3209 for (i = 0; i < priv->params.num_channels; i++)
3210 napi_schedule(&priv->channel[i]->napi);
3214 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3215 .ndo_open = mlx5e_open,
3216 .ndo_stop = mlx5e_close,
3217 .ndo_start_xmit = mlx5e_xmit,
3218 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3219 .ndo_select_queue = mlx5e_select_queue,
3220 .ndo_get_stats64 = mlx5e_get_stats,
3221 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3222 .ndo_set_mac_address = mlx5e_set_mac,
3223 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3224 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3225 .ndo_set_features = mlx5e_set_features,
3226 .ndo_change_mtu = mlx5e_change_mtu,
3227 .ndo_do_ioctl = mlx5e_ioctl,
3228 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3229 #ifdef CONFIG_RFS_ACCEL
3230 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3232 .ndo_tx_timeout = mlx5e_tx_timeout,
3233 .ndo_xdp = mlx5e_xdp,
3234 #ifdef CONFIG_NET_POLL_CONTROLLER
3235 .ndo_poll_controller = mlx5e_netpoll,
3239 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3240 .ndo_open = mlx5e_open,
3241 .ndo_stop = mlx5e_close,
3242 .ndo_start_xmit = mlx5e_xmit,
3243 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3244 .ndo_select_queue = mlx5e_select_queue,
3245 .ndo_get_stats64 = mlx5e_get_stats,
3246 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3247 .ndo_set_mac_address = mlx5e_set_mac,
3248 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3249 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3250 .ndo_set_features = mlx5e_set_features,
3251 .ndo_change_mtu = mlx5e_change_mtu,
3252 .ndo_do_ioctl = mlx5e_ioctl,
3253 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3254 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3255 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3256 .ndo_features_check = mlx5e_features_check,
3257 #ifdef CONFIG_RFS_ACCEL
3258 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3260 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3261 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3262 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3263 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3264 .ndo_get_vf_config = mlx5e_get_vf_config,
3265 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3266 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3267 .ndo_tx_timeout = mlx5e_tx_timeout,
3268 .ndo_xdp = mlx5e_xdp,
3269 #ifdef CONFIG_NET_POLL_CONTROLLER
3270 .ndo_poll_controller = mlx5e_netpoll,
3274 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3276 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3278 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3279 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3280 !MLX5_CAP_ETH(mdev, csum_cap) ||
3281 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3282 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3283 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3284 MLX5_CAP_FLOWTABLE(mdev,
3285 flow_table_properties_nic_receive.max_ft_level)
3287 mlx5_core_warn(mdev,
3288 "Not creating net device, some required device capabilities are missing\n");
3291 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3292 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3293 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3294 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3299 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3301 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3303 return bf_buf_size -
3304 sizeof(struct mlx5e_tx_wqe) +
3305 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3308 #ifdef CONFIG_MLX5_CORE_EN_DCB
3309 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3313 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3314 for (i = 0; i < priv->params.ets.ets_cap; i++) {
3315 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3316 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3317 priv->params.ets.prio_tc[i] = i;
3320 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3321 priv->params.ets.prio_tc[0] = 1;
3322 priv->params.ets.prio_tc[1] = 0;
3326 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3327 u32 *indirection_rqt, int len,
3330 int node = mdev->priv.numa_node;
3331 int node_num_of_cores;
3335 node = first_online_node;
3337 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3339 if (node_num_of_cores)
3340 num_channels = min_t(int, num_channels, node_num_of_cores);
3342 for (i = 0; i < len; i++)
3343 indirection_rqt[i] = i % num_channels;
3346 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3348 enum pcie_link_width width;
3349 enum pci_bus_speed speed;
3352 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3356 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3360 case PCIE_SPEED_2_5GT:
3361 *pci_bw = 2500 * width;
3363 case PCIE_SPEED_5_0GT:
3364 *pci_bw = 5000 * width;
3366 case PCIE_SPEED_8_0GT:
3367 *pci_bw = 8000 * width;
3376 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3378 return (link_speed && pci_bw &&
3379 (pci_bw < 40000) && (pci_bw < link_speed));
3382 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3384 params->rx_cq_period_mode = cq_period_mode;
3386 params->rx_cq_moderation.pkts =
3387 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3388 params->rx_cq_moderation.usec =
3389 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3391 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3392 params->rx_cq_moderation.usec =
3393 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3396 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3397 u8 *min_inline_mode)
3399 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3400 case MLX5E_INLINE_MODE_L2:
3401 *min_inline_mode = MLX5_INLINE_MODE_L2;
3403 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3404 mlx5_query_nic_vport_min_inline(mdev,
3407 case MLX5_INLINE_MODE_NOT_REQUIRED:
3408 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3413 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3417 /* The supported periods are organized in ascending order */
3418 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3419 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3422 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3425 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3426 struct net_device *netdev,
3427 const struct mlx5e_profile *profile,
3430 struct mlx5e_priv *priv = netdev_priv(netdev);
3433 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3434 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3435 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3438 priv->netdev = netdev;
3439 priv->params.num_channels = profile->max_nch(mdev);
3440 priv->profile = profile;
3441 priv->ppriv = ppriv;
3443 priv->params.lro_timeout =
3444 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3446 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3448 /* set CQE compression */
3449 priv->params.rx_cqe_compress_admin = false;
3450 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3451 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3452 mlx5e_get_max_linkspeed(mdev, &link_speed);
3453 mlx5e_get_pci_bw(mdev, &pci_bw);
3454 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3455 link_speed, pci_bw);
3456 priv->params.rx_cqe_compress_admin =
3457 cqe_compress_heuristic(link_speed, pci_bw);
3459 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3461 mlx5e_set_rq_priv_params(priv);
3462 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3463 priv->params.lro_en = true;
3465 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3466 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3468 priv->params.tx_cq_moderation.usec =
3469 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3470 priv->params.tx_cq_moderation.pkts =
3471 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3472 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3473 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3474 priv->params.num_tc = 1;
3475 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
3477 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3478 sizeof(priv->params.toeplitz_hash_key));
3480 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3481 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3483 /* Initialize pflags */
3484 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3485 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3487 #ifdef CONFIG_MLX5_CORE_EN_DCB
3488 mlx5e_ets_init(priv);
3491 mutex_init(&priv->state_lock);
3493 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3494 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3495 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3496 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3499 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3501 struct mlx5e_priv *priv = netdev_priv(netdev);
3503 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3504 if (is_zero_ether_addr(netdev->dev_addr) &&
3505 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3506 eth_hw_addr_random(netdev);
3507 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3511 static const struct switchdev_ops mlx5e_switchdev_ops = {
3512 .switchdev_port_attr_get = mlx5e_attr_get,
3515 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3517 struct mlx5e_priv *priv = netdev_priv(netdev);
3518 struct mlx5_core_dev *mdev = priv->mdev;
3522 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3524 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3525 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3526 #ifdef CONFIG_MLX5_CORE_EN_DCB
3527 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3530 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3533 netdev->watchdog_timeo = 15 * HZ;
3535 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3537 netdev->vlan_features |= NETIF_F_SG;
3538 netdev->vlan_features |= NETIF_F_IP_CSUM;
3539 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3540 netdev->vlan_features |= NETIF_F_GRO;
3541 netdev->vlan_features |= NETIF_F_TSO;
3542 netdev->vlan_features |= NETIF_F_TSO6;
3543 netdev->vlan_features |= NETIF_F_RXCSUM;
3544 netdev->vlan_features |= NETIF_F_RXHASH;
3546 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3547 netdev->vlan_features |= NETIF_F_LRO;
3549 netdev->hw_features = netdev->vlan_features;
3550 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3551 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3552 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3554 if (mlx5e_vxlan_allowed(mdev)) {
3555 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3556 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3557 NETIF_F_GSO_PARTIAL;
3558 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3559 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3560 netdev->hw_enc_features |= NETIF_F_TSO;
3561 netdev->hw_enc_features |= NETIF_F_TSO6;
3562 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3563 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3564 NETIF_F_GSO_PARTIAL;
3565 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3568 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3571 netdev->hw_features |= NETIF_F_RXALL;
3573 netdev->features = netdev->hw_features;
3574 if (!priv->params.lro_en)
3575 netdev->features &= ~NETIF_F_LRO;
3578 netdev->features &= ~NETIF_F_RXALL;
3580 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3581 if (FT_CAP(flow_modify_en) &&
3582 FT_CAP(modify_root) &&
3583 FT_CAP(identified_miss_table_mode) &&
3584 FT_CAP(flow_table_modify)) {
3585 netdev->hw_features |= NETIF_F_HW_TC;
3586 #ifdef CONFIG_RFS_ACCEL
3587 netdev->hw_features |= NETIF_F_NTUPLE;
3591 netdev->features |= NETIF_F_HIGHDMA;
3593 netdev->priv_flags |= IFF_UNICAST_FLT;
3595 mlx5e_set_netdev_dev_addr(netdev);
3597 #ifdef CONFIG_NET_SWITCHDEV
3598 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3599 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3603 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3605 struct mlx5_core_dev *mdev = priv->mdev;
3608 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3610 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3611 priv->q_counter = 0;
3615 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3617 if (!priv->q_counter)
3620 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3623 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3625 struct mlx5_core_dev *mdev = priv->mdev;
3626 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3627 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3628 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3633 in = mlx5_vzalloc(inlen);
3637 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3639 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3641 MLX5_SET(mkc, mkc, free, 1);
3642 MLX5_SET(mkc, mkc, umr_en, 1);
3643 MLX5_SET(mkc, mkc, lw, 1);
3644 MLX5_SET(mkc, mkc, lr, 1);
3645 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3647 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3648 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3649 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3650 MLX5_SET(mkc, mkc, translations_octword_size,
3651 MLX5_MTT_OCTW(npages));
3652 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3654 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3660 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3661 struct net_device *netdev,
3662 const struct mlx5e_profile *profile,
3665 struct mlx5e_priv *priv = netdev_priv(netdev);
3667 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3668 mlx5e_build_nic_netdev(netdev);
3669 mlx5e_vxlan_init(priv);
3672 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3674 struct mlx5_core_dev *mdev = priv->mdev;
3675 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3677 mlx5e_vxlan_cleanup(priv);
3679 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3680 mlx5_eswitch_unregister_vport_rep(esw, 0);
3683 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3685 struct mlx5_core_dev *mdev = priv->mdev;
3689 err = mlx5e_create_indirect_rqts(priv);
3691 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3695 err = mlx5e_create_direct_rqts(priv);
3697 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3698 goto err_destroy_indirect_rqts;
3701 err = mlx5e_create_indirect_tirs(priv);
3703 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3704 goto err_destroy_direct_rqts;
3707 err = mlx5e_create_direct_tirs(priv);
3709 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3710 goto err_destroy_indirect_tirs;
3713 err = mlx5e_create_flow_steering(priv);
3715 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3716 goto err_destroy_direct_tirs;
3719 err = mlx5e_tc_init(priv);
3721 goto err_destroy_flow_steering;
3725 err_destroy_flow_steering:
3726 mlx5e_destroy_flow_steering(priv);
3727 err_destroy_direct_tirs:
3728 mlx5e_destroy_direct_tirs(priv);
3729 err_destroy_indirect_tirs:
3730 mlx5e_destroy_indirect_tirs(priv);
3731 err_destroy_direct_rqts:
3732 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3733 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3734 err_destroy_indirect_rqts:
3735 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3739 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3743 mlx5e_tc_cleanup(priv);
3744 mlx5e_destroy_flow_steering(priv);
3745 mlx5e_destroy_direct_tirs(priv);
3746 mlx5e_destroy_indirect_tirs(priv);
3747 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3748 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3749 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3752 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3756 err = mlx5e_create_tises(priv);
3758 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3762 #ifdef CONFIG_MLX5_CORE_EN_DCB
3763 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3768 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3770 struct net_device *netdev = priv->netdev;
3771 struct mlx5_core_dev *mdev = priv->mdev;
3772 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3773 struct mlx5_eswitch_rep rep;
3775 mlx5_lag_add(mdev, netdev);
3777 mlx5e_enable_async_events(priv);
3779 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3780 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3781 rep.load = mlx5e_nic_rep_load;
3782 rep.unload = mlx5e_nic_rep_unload;
3783 rep.vport = FDB_UPLINK_VPORT;
3784 rep.priv_data = priv;
3785 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
3788 if (netdev->reg_state != NETREG_REGISTERED)
3791 queue_work(priv->wq, &priv->set_rx_mode_work);
3794 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3796 queue_work(priv->wq, &priv->set_rx_mode_work);
3797 mlx5e_disable_async_events(priv);
3798 mlx5_lag_remove(priv->mdev);
3801 static const struct mlx5e_profile mlx5e_nic_profile = {
3802 .init = mlx5e_nic_init,
3803 .cleanup = mlx5e_nic_cleanup,
3804 .init_rx = mlx5e_init_nic_rx,
3805 .cleanup_rx = mlx5e_cleanup_nic_rx,
3806 .init_tx = mlx5e_init_nic_tx,
3807 .cleanup_tx = mlx5e_cleanup_nic_tx,
3808 .enable = mlx5e_nic_enable,
3809 .disable = mlx5e_nic_disable,
3810 .update_stats = mlx5e_update_stats,
3811 .max_nch = mlx5e_get_max_num_channels,
3812 .max_tc = MLX5E_MAX_NUM_TC,
3815 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3816 const struct mlx5e_profile *profile,
3819 int nch = profile->max_nch(mdev);
3820 struct net_device *netdev;
3821 struct mlx5e_priv *priv;
3823 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3824 nch * profile->max_tc,
3827 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3831 profile->init(mdev, netdev, profile, ppriv);
3833 netif_carrier_off(netdev);
3835 priv = netdev_priv(netdev);
3837 priv->wq = create_singlethread_workqueue("mlx5e");
3839 goto err_cleanup_nic;
3844 if (profile->cleanup)
3845 profile->cleanup(priv);
3846 free_netdev(netdev);
3851 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3853 const struct mlx5e_profile *profile;
3854 struct mlx5e_priv *priv;
3857 priv = netdev_priv(netdev);
3858 profile = priv->profile;
3859 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3861 err = mlx5e_create_umr_mkey(priv);
3863 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3867 err = profile->init_tx(priv);
3869 goto err_destroy_umr_mkey;
3871 err = mlx5e_open_drop_rq(priv);
3873 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3874 goto err_cleanup_tx;
3877 err = profile->init_rx(priv);
3879 goto err_close_drop_rq;
3881 mlx5e_create_q_counter(priv);
3883 mlx5e_init_l2_addr(priv);
3885 mlx5e_set_dev_port_mtu(netdev);
3887 if (profile->enable)
3888 profile->enable(priv);
3891 if (netif_running(netdev))
3893 netif_device_attach(netdev);
3899 mlx5e_close_drop_rq(priv);
3902 profile->cleanup_tx(priv);
3904 err_destroy_umr_mkey:
3905 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3911 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3913 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3914 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3918 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3921 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3923 for (vport = 1; vport < total_vfs; vport++) {
3924 struct mlx5_eswitch_rep rep;
3926 rep.load = mlx5e_vport_rep_load;
3927 rep.unload = mlx5e_vport_rep_unload;
3929 ether_addr_copy(rep.hw_id, mac);
3930 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
3934 static void mlx5e_unregister_vport_rep(struct mlx5_core_dev *mdev)
3936 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3937 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3940 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3943 for (vport = 1; vport < total_vfs; vport++)
3944 mlx5_eswitch_unregister_vport_rep(esw, vport);
3947 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3949 struct mlx5e_priv *priv = netdev_priv(netdev);
3950 const struct mlx5e_profile *profile = priv->profile;
3952 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3955 if (netif_running(netdev))
3956 mlx5e_close(netdev);
3957 netif_device_detach(netdev);
3960 if (profile->disable)
3961 profile->disable(priv);
3962 flush_workqueue(priv->wq);
3964 mlx5e_destroy_q_counter(priv);
3965 profile->cleanup_rx(priv);
3966 mlx5e_close_drop_rq(priv);
3967 profile->cleanup_tx(priv);
3968 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3969 cancel_delayed_work_sync(&priv->update_stats_work);
3972 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3973 * hardware contexts and to connect it to the current netdev.
3975 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3977 struct mlx5e_priv *priv = vpriv;
3978 struct net_device *netdev = priv->netdev;
3981 if (netif_device_present(netdev))
3984 err = mlx5e_create_mdev_resources(mdev);
3988 err = mlx5e_attach_netdev(mdev, netdev);
3990 mlx5e_destroy_mdev_resources(mdev);
3994 mlx5e_register_vport_rep(mdev);
3998 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4000 struct mlx5e_priv *priv = vpriv;
4001 struct net_device *netdev = priv->netdev;
4003 if (!netif_device_present(netdev))
4006 mlx5e_unregister_vport_rep(mdev);
4007 mlx5e_detach_netdev(mdev, netdev);
4008 mlx5e_destroy_mdev_resources(mdev);
4011 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4013 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4014 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4019 struct net_device *netdev;
4021 err = mlx5e_check_required_hca_cap(mdev);
4025 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4026 ppriv = &esw->offloads.vport_reps[0];
4028 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4030 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4031 goto err_unregister_reps;
4034 priv = netdev_priv(netdev);
4036 err = mlx5e_attach(mdev, priv);
4038 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4039 goto err_destroy_netdev;
4042 err = register_netdev(netdev);
4044 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4051 mlx5e_detach(mdev, priv);
4054 mlx5e_destroy_netdev(mdev, priv);
4056 err_unregister_reps:
4057 for (vport = 1; vport < total_vfs; vport++)
4058 mlx5_eswitch_unregister_vport_rep(esw, vport);
4063 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
4065 const struct mlx5e_profile *profile = priv->profile;
4066 struct net_device *netdev = priv->netdev;
4068 destroy_workqueue(priv->wq);
4069 if (profile->cleanup)
4070 profile->cleanup(priv);
4071 free_netdev(netdev);
4074 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4076 struct mlx5e_priv *priv = vpriv;
4078 unregister_netdev(priv->netdev);
4079 mlx5e_detach(mdev, vpriv);
4080 mlx5e_destroy_netdev(mdev, priv);
4083 static void *mlx5e_get_netdev(void *vpriv)
4085 struct mlx5e_priv *priv = vpriv;
4087 return priv->netdev;
4090 static struct mlx5_interface mlx5e_interface = {
4092 .remove = mlx5e_remove,
4093 .attach = mlx5e_attach,
4094 .detach = mlx5e_detach,
4095 .event = mlx5e_async_event,
4096 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4097 .get_dev = mlx5e_get_netdev,
4100 void mlx5e_init(void)
4102 mlx5e_build_ptys2ethtool_map();
4103 mlx5_register_interface(&mlx5e_interface);
4106 void mlx5e_cleanup(void)
4108 mlx5_unregister_interface(&mlx5e_interface);