2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/device.h>
33 #include <linux/netdevice.h>
36 #define MLX5E_MAX_PRIORITY 8
38 #define MLX5E_100MB (100000)
39 #define MLX5E_1GB (1000000)
41 #define MLX5E_CEE_STATE_UP 1
42 #define MLX5E_CEE_STATE_DOWN 0
45 MLX5E_VENDOR_TC_GROUP_NUM = 7,
46 MLX5E_LOWEST_PRIO_GROUP = 0,
49 /* If dcbx mode is non-host set the dcbx mode to host.
51 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
52 enum mlx5_dcbx_oper_mode mode)
54 struct mlx5_core_dev *mdev = priv->mdev;
55 u32 param[MLX5_ST_SZ_DW(dcbx_param)];
58 err = mlx5_query_port_dcbx_param(mdev, param);
62 MLX5_SET(dcbx_param, param, version_admin, mode);
63 if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
64 MLX5_SET(dcbx_param, param, willing_admin, 1);
66 return mlx5_set_port_dcbx_param(mdev, param);
69 static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
71 struct mlx5e_dcbx *dcbx = &priv->dcbx;
74 if (!MLX5_CAP_GEN(priv->mdev, dcbx))
77 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
80 err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
84 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
88 static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
91 struct mlx5e_priv *priv = netdev_priv(netdev);
92 struct mlx5_core_dev *mdev = priv->mdev;
93 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
94 bool is_tc_group_6_exist = false;
95 bool is_zero_bw_ets_tc = false;
99 if (!MLX5_CAP_GEN(priv->mdev, ets))
102 ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
103 for (i = 0; i < ets->ets_cap; i++) {
104 err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
108 err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]);
112 err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
116 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
117 tc_group[i] == (MLX5E_LOWEST_PRIO_GROUP + 1))
118 is_zero_bw_ets_tc = true;
120 if (tc_group[i] == (MLX5E_VENDOR_TC_GROUP_NUM - 1))
121 is_tc_group_6_exist = true;
124 /* Report 0% ets tc if exits*/
125 if (is_zero_bw_ets_tc) {
126 for (i = 0; i < ets->ets_cap; i++)
127 if (tc_group[i] == MLX5E_LOWEST_PRIO_GROUP)
128 ets->tc_tx_bw[i] = 0;
131 /* Update tc_tsa based on fw setting*/
132 for (i = 0; i < ets->ets_cap; i++) {
133 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
134 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
135 else if (tc_group[i] == MLX5E_VENDOR_TC_GROUP_NUM &&
136 !is_tc_group_6_exist)
137 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
139 memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
144 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
146 bool any_tc_mapped_to_ets = false;
147 bool ets_zero_bw = false;
151 for (i = 0; i <= max_tc; i++) {
152 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
153 any_tc_mapped_to_ets = true;
154 if (!ets->tc_tx_bw[i])
159 /* strict group has higher priority than ets group */
160 strict_group = MLX5E_LOWEST_PRIO_GROUP;
161 if (any_tc_mapped_to_ets)
166 for (i = 0; i <= max_tc; i++) {
167 switch (ets->tc_tsa[i]) {
168 case IEEE_8021QAZ_TSA_VENDOR:
169 tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
171 case IEEE_8021QAZ_TSA_STRICT:
172 tc_group[i] = strict_group++;
174 case IEEE_8021QAZ_TSA_ETS:
175 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP;
176 if (ets->tc_tx_bw[i] && ets_zero_bw)
177 tc_group[i] = MLX5E_LOWEST_PRIO_GROUP + 1;
183 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
184 u8 *tc_group, int max_tc)
186 int bw_for_ets_zero_bw_tc = 0;
187 int last_ets_zero_bw_tc = -1;
188 int num_ets_zero_bw = 0;
191 for (i = 0; i <= max_tc; i++) {
192 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
195 last_ets_zero_bw_tc = i;
200 bw_for_ets_zero_bw_tc = MLX5E_MAX_BW_ALLOC / num_ets_zero_bw;
202 for (i = 0; i <= max_tc; i++) {
203 switch (ets->tc_tsa[i]) {
204 case IEEE_8021QAZ_TSA_VENDOR:
205 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
207 case IEEE_8021QAZ_TSA_STRICT:
208 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
210 case IEEE_8021QAZ_TSA_ETS:
211 tc_tx_bw[i] = ets->tc_tx_bw[i] ?
213 bw_for_ets_zero_bw_tc;
218 /* Make sure the total bw for ets zero bw group is 100% */
219 if (last_ets_zero_bw_tc != -1)
220 tc_tx_bw[last_ets_zero_bw_tc] +=
221 MLX5E_MAX_BW_ALLOC % num_ets_zero_bw;
224 /* If there are ETS BW 0,
225 * Set ETS group # to 1 for all ETS non zero BW tcs. Their sum must be 100%.
226 * Set group #0 to all the ETS BW 0 tcs and
227 * equally splits the 100% BW between them
228 * Report both group #0 and #1 as ETS type.
229 * All the tcs in group #0 will be reported with 0% BW.
231 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
233 struct mlx5_core_dev *mdev = priv->mdev;
234 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
235 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
236 int max_tc = mlx5_max_tc(mdev);
239 mlx5e_build_tc_group(ets, tc_group, max_tc);
240 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
242 err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
246 err = mlx5_set_port_tc_group(mdev, tc_group);
250 err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
255 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
259 static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
260 struct ieee_ets *ets,
261 bool zero_sum_allowed)
263 bool have_ets_tc = false;
267 /* Validate Priority */
268 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
269 if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
271 "Failed to validate ETS: priority value greater than max(%d)\n",
277 /* Validate Bandwidth Sum */
278 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
279 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
281 bw_sum += ets->tc_tx_bw[i];
285 if (have_ets_tc && bw_sum != 100) {
286 if (bw_sum || (!bw_sum && !zero_sum_allowed))
288 "Failed to validate ETS: BW sum is illegal\n");
294 static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
295 struct ieee_ets *ets)
297 struct mlx5e_priv *priv = netdev_priv(netdev);
300 if (!MLX5_CAP_GEN(priv->mdev, ets))
303 err = mlx5e_dbcnl_validate_ets(netdev, ets, false);
307 err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
314 static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
315 struct ieee_pfc *pfc)
317 struct mlx5e_priv *priv = netdev_priv(dev);
318 struct mlx5_core_dev *mdev = priv->mdev;
319 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
322 pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
323 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
324 pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
325 pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
328 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
331 static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
332 struct ieee_pfc *pfc)
334 struct mlx5e_priv *priv = netdev_priv(dev);
335 struct mlx5_core_dev *mdev = priv->mdev;
339 mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
341 if (pfc->pfc_en == curr_pfc_en)
344 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
345 mlx5_toggle_port_link(mdev);
350 static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
352 struct mlx5e_priv *priv = netdev_priv(dev);
354 return priv->dcbx.cap;
357 static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
359 struct mlx5e_priv *priv = netdev_priv(dev);
360 struct mlx5e_dcbx *dcbx = &priv->dcbx;
362 if (mode & DCB_CAP_DCBX_LLD_MANAGED)
365 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
366 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
369 /* set dcbx to fw controlled */
370 if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
371 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
372 dcbx->cap &= ~DCB_CAP_DCBX_HOST;
379 if (!(mode & DCB_CAP_DCBX_HOST))
382 if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
390 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
391 struct ieee_maxrate *maxrate)
393 struct mlx5e_priv *priv = netdev_priv(netdev);
394 struct mlx5_core_dev *mdev = priv->mdev;
395 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
396 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
400 err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
404 memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
406 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
407 switch (max_bw_unit[i]) {
408 case MLX5_100_MBPS_UNIT:
409 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
412 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
414 case MLX5_BW_NO_LIMIT:
417 WARN(true, "non-supported BW unit");
425 static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
426 struct ieee_maxrate *maxrate)
428 struct mlx5e_priv *priv = netdev_priv(netdev);
429 struct mlx5_core_dev *mdev = priv->mdev;
430 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
431 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
432 __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
435 memset(max_bw_value, 0, sizeof(max_bw_value));
436 memset(max_bw_unit, 0, sizeof(max_bw_unit));
438 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
439 if (!maxrate->tc_maxrate[i]) {
440 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
443 if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
444 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
446 max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
447 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
449 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
451 max_bw_unit[i] = MLX5_GBPS_UNIT;
455 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
458 static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
460 struct mlx5e_priv *priv = netdev_priv(netdev);
461 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
462 struct mlx5_core_dev *mdev = priv->mdev;
465 int err = -EOPNOTSUPP;
468 if (!MLX5_CAP_GEN(mdev, ets))
471 memset(&ets, 0, sizeof(ets));
472 memset(&pfc, 0, sizeof(pfc));
474 ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
475 for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
476 ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
477 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
478 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
479 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
482 err = mlx5e_dbcnl_validate_ets(netdev, &ets, true);
486 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
489 "%s, Failed to set ETS: %d\n", __func__, err);
494 pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
495 if (!cee_cfg->pfc_enable)
498 for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
499 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
501 err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
504 "%s, Failed to set PFC: %d\n", __func__, err);
508 return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
511 static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
513 return MLX5E_CEE_STATE_UP;
516 static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
519 struct mlx5e_priv *priv = netdev_priv(netdev);
524 memset(perm_addr, 0xff, MAX_ADDR_LEN);
526 mlx5_query_nic_vport_mac_address(priv->mdev, 0, perm_addr);
529 static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
530 int priority, u8 prio_type,
531 u8 pgid, u8 bw_pct, u8 up_map)
533 struct mlx5e_priv *priv = netdev_priv(netdev);
534 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
536 if (priority >= CEE_DCBX_MAX_PRIO) {
538 "%s, priority is out of range\n", __func__);
542 if (pgid >= CEE_DCBX_MAX_PGS) {
544 "%s, priority group is out of range\n", __func__);
548 cee_cfg->prio_to_pg_map[priority] = pgid;
551 static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
554 struct mlx5e_priv *priv = netdev_priv(netdev);
555 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
557 if (pgid >= CEE_DCBX_MAX_PGS) {
559 "%s, priority group is out of range\n", __func__);
563 cee_cfg->pg_bw_pct[pgid] = bw_pct;
566 static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
567 int priority, u8 *prio_type,
568 u8 *pgid, u8 *bw_pct, u8 *up_map)
570 struct mlx5e_priv *priv = netdev_priv(netdev);
571 struct mlx5_core_dev *mdev = priv->mdev;
573 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
574 netdev_err(netdev, "%s, ets is not supported\n", __func__);
578 if (priority >= CEE_DCBX_MAX_PRIO) {
580 "%s, priority is out of range\n", __func__);
588 if (mlx5_query_port_prio_tc(mdev, priority, pgid))
592 static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
593 int pgid, u8 *bw_pct)
597 if (pgid >= CEE_DCBX_MAX_PGS) {
599 "%s, priority group is out of range\n", __func__);
603 mlx5e_dcbnl_ieee_getets(netdev, &ets);
604 *bw_pct = ets.tc_tx_bw[pgid];
607 static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
608 int priority, u8 setting)
610 struct mlx5e_priv *priv = netdev_priv(netdev);
611 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
613 if (priority >= CEE_DCBX_MAX_PRIO) {
615 "%s, priority is out of range\n", __func__);
622 cee_cfg->pfc_setting[priority] = setting;
626 mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
627 int priority, u8 *setting)
632 err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
637 *setting = (pfc.pfc_en >> priority) & 0x01;
642 static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
643 int priority, u8 *setting)
645 if (priority >= CEE_DCBX_MAX_PRIO) {
647 "%s, priority is out of range\n", __func__);
654 mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
657 static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
660 struct mlx5e_priv *priv = netdev_priv(netdev);
661 struct mlx5_core_dev *mdev = priv->mdev;
665 case DCB_CAP_ATTR_PG:
668 case DCB_CAP_ATTR_PFC:
671 case DCB_CAP_ATTR_UP2TC:
674 case DCB_CAP_ATTR_PG_TCS:
675 *cap = 1 << mlx5_max_tc(mdev);
677 case DCB_CAP_ATTR_PFC_TCS:
678 *cap = 1 << mlx5_max_tc(mdev);
680 case DCB_CAP_ATTR_GSP:
683 case DCB_CAP_ATTR_BCN:
686 case DCB_CAP_ATTR_DCBX:
687 *cap = priv->dcbx.cap |
688 DCB_CAP_DCBX_VER_CEE |
689 DCB_CAP_DCBX_VER_IEEE;
700 static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
703 struct mlx5e_priv *priv = netdev_priv(netdev);
704 struct mlx5_core_dev *mdev = priv->mdev;
707 case DCB_NUMTCS_ATTR_PG:
708 case DCB_NUMTCS_ATTR_PFC:
709 *num = mlx5_max_tc(mdev) + 1;
718 static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
722 if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
723 return MLX5E_CEE_STATE_DOWN;
725 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
728 static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
730 struct mlx5e_priv *priv = netdev_priv(netdev);
731 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
733 if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
736 cee_cfg->pfc_enable = state;
739 const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
740 .ieee_getets = mlx5e_dcbnl_ieee_getets,
741 .ieee_setets = mlx5e_dcbnl_ieee_setets,
742 .ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
743 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
744 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
745 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
746 .getdcbx = mlx5e_dcbnl_getdcbx,
747 .setdcbx = mlx5e_dcbnl_setdcbx,
750 .setall = mlx5e_dcbnl_setall,
751 .getstate = mlx5e_dcbnl_getstate,
752 .getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
754 .setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
755 .setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
756 .getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
757 .getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
759 .setpfccfg = mlx5e_dcbnl_setpfccfg,
760 .getpfccfg = mlx5e_dcbnl_getpfccfg,
761 .getcap = mlx5e_dcbnl_getcap,
762 .getnumtcs = mlx5e_dcbnl_getnumtcs,
763 .getpfcstate = mlx5e_dcbnl_getpfcstate,
764 .setpfcstate = mlx5e_dcbnl_setpfcstate,
767 static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
768 enum mlx5_dcbx_oper_mode *mode)
770 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
772 *mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
774 if (!mlx5_query_port_dcbx_param(priv->mdev, out))
775 *mode = MLX5_GET(dcbx_param, out, version_oper);
777 /* From driver's point of view, we only care if the mode
778 * is host (HOST) or non-host (AUTO)
780 if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
781 *mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
784 static void mlx5e_ets_init(struct mlx5e_priv *priv)
789 if (!MLX5_CAP_GEN(priv->mdev, ets))
792 memset(&ets, 0, sizeof(ets));
793 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
794 for (i = 0; i < ets.ets_cap; i++) {
795 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
796 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
800 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
804 mlx5e_dcbnl_ieee_setets_core(priv, &ets);
807 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
809 struct mlx5e_dcbx *dcbx = &priv->dcbx;
811 if (!MLX5_CAP_GEN(priv->mdev, qos))
814 if (MLX5_CAP_GEN(priv->mdev, dcbx))
815 mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
817 priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
818 DCB_CAP_DCBX_VER_IEEE;
819 if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
820 priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
822 mlx5e_ets_init(priv);