drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static u8 xor8_buf(void *buf, size_t offset, int len)
 139 {
 140         u8 *ptr = buf;
 141         u8 sum = 0;
 142         int i;
 143         int end = len + offset;
 144
 145         for (i = offset; i < end; i++)
 146                 sum ^= ptr[i];
 147
 148         return sum;
 149 }
 150
 151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 152 {
 153         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 154         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 155
 156         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 157                 return -EINVAL;
 158
 159         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 160                 return -EINVAL;
 161
 162         return 0;
 163 }
 164
 165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 166 {
 167         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 168         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 169
 170         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 171         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 172 }
 173
 174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 175 {
 176         struct mlx5_cmd_mailbox *next = msg->next;
 177         int size = msg->len;
 178         int blen = size - min_t(int, sizeof(msg->first.data), size);
 179         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 180                 / MLX5_CMD_DATA_BLOCK_SIZE;
 181         int i = 0;
 182
 183         for (i = 0; i < n && next; i++)  {
 184                 calc_block_sig(next->buf);
 185                 next = next->next;
 186         }
 187 }
 188
 189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 190 {
 191         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 192         if (csum) {
 193                 calc_chain_sig(ent->in);
 194                 calc_chain_sig(ent->out);
 195         }
 196 }
 197
 198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 199 {
 200         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 201         u8 own;
 202
 203         do {
 204                 own = ent->lay->status_own;
 205                 if (!(own & CMD_OWNER_HW)) {
 206                         ent->ret = 0;
 207                         return;
 208                 }
 209                 usleep_range(5000, 10000);
 210         } while (time_before(jiffies, poll_end));
 211
 212         ent->ret = -ETIMEDOUT;
 213 }
 214
 215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 216 {
 217         kfree(ent);
 218 }
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225         int size = ent->out->len;
 226         int blen = size - min_t(int, sizeof(ent->out->first.data), size);
 227         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 228                 / MLX5_CMD_DATA_BLOCK_SIZE;
 229         int i = 0;
 230
 231         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 232         if (sig != 0xff)
 233                 return -EINVAL;
 234
 235         for (i = 0; i < n && next; i++) {
 236                 err = verify_block_sig(next->buf);
 237                 if (err)
 238                         return err;
 239
 240                 next = next->next;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void dump_buf(void *buf, int size, int data_only, int offset)
 247 {
 248         __be32 *p = buf;
 249         int i;
 250
 251         for (i = 0; i < size; i += 16) {
 252                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 253                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 254                          be32_to_cpu(p[3]));
 255                 p += 4;
 256                 offset += 16;
 257         }
 258         if (!data_only)
 259                 pr_debug("\n");
 260 }
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 282         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 283         case MLX5_CMD_OP_DEALLOC_PD:
 284         case MLX5_CMD_OP_DEALLOC_UAR:
 285         case MLX5_CMD_OP_DETACH_FROM_MCG:
 286         case MLX5_CMD_OP_DEALLOC_XRCD:
 287         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 288         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 289         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 290         case MLX5_CMD_OP_DESTROY_LAG:
 291         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 292         case MLX5_CMD_OP_DESTROY_TIR:
 293         case MLX5_CMD_OP_DESTROY_SQ:
 294         case MLX5_CMD_OP_DESTROY_RQ:
 295         case MLX5_CMD_OP_DESTROY_RMP:
 296         case MLX5_CMD_OP_DESTROY_TIS:
 297         case MLX5_CMD_OP_DESTROY_RQT:
 298         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 299         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 300         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 301         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 302         case MLX5_CMD_OP_2ERR_QP:
 303         case MLX5_CMD_OP_2RST_QP:
 304         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 305         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 306         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 307         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 308         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 309         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 310         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 311                 return MLX5_CMD_STAT_OK;
 312
 313         case MLX5_CMD_OP_QUERY_HCA_CAP:
 314         case MLX5_CMD_OP_QUERY_ADAPTER:
 315         case MLX5_CMD_OP_INIT_HCA:
 316         case MLX5_CMD_OP_ENABLE_HCA:
 317         case MLX5_CMD_OP_QUERY_PAGES:
 318         case MLX5_CMD_OP_SET_HCA_CAP:
 319         case MLX5_CMD_OP_QUERY_ISSI:
 320         case MLX5_CMD_OP_SET_ISSI:
 321         case MLX5_CMD_OP_CREATE_MKEY:
 322         case MLX5_CMD_OP_QUERY_MKEY:
 323         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325         case MLX5_CMD_OP_CREATE_EQ:
 326         case MLX5_CMD_OP_QUERY_EQ:
 327         case MLX5_CMD_OP_GEN_EQE:
 328         case MLX5_CMD_OP_CREATE_CQ:
 329         case MLX5_CMD_OP_QUERY_CQ:
 330         case MLX5_CMD_OP_MODIFY_CQ:
 331         case MLX5_CMD_OP_CREATE_QP:
 332         case MLX5_CMD_OP_RST2INIT_QP:
 333         case MLX5_CMD_OP_INIT2RTR_QP:
 334         case MLX5_CMD_OP_RTR2RTS_QP:
 335         case MLX5_CMD_OP_RTS2RTS_QP:
 336         case MLX5_CMD_OP_SQERR2RTS_QP:
 337         case MLX5_CMD_OP_QUERY_QP:
 338         case MLX5_CMD_OP_SQD_RTS_QP:
 339         case MLX5_CMD_OP_INIT2INIT_QP:
 340         case MLX5_CMD_OP_CREATE_PSV:
 341         case MLX5_CMD_OP_CREATE_SRQ:
 342         case MLX5_CMD_OP_QUERY_SRQ:
 343         case MLX5_CMD_OP_ARM_RQ:
 344         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 345         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 346         case MLX5_CMD_OP_ARM_XRC_SRQ:
 347         case MLX5_CMD_OP_CREATE_DCT:
 348         case MLX5_CMD_OP_DRAIN_DCT:
 349         case MLX5_CMD_OP_QUERY_DCT:
 350         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 351         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 352         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 353         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 354         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 355         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 357         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 358         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 359         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 360         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 361         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 362         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 363         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 364         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 365         case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
 366         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 367         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 368         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 369         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 370         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 371         case MLX5_CMD_OP_ALLOC_PD:
 372         case MLX5_CMD_OP_ALLOC_UAR:
 373         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 374         case MLX5_CMD_OP_ACCESS_REG:
 375         case MLX5_CMD_OP_ATTACH_TO_MCG:
 376         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 377         case MLX5_CMD_OP_MAD_IFC:
 378         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 379         case MLX5_CMD_OP_SET_MAD_DEMUX:
 380         case MLX5_CMD_OP_NOP:
 381         case MLX5_CMD_OP_ALLOC_XRCD:
 382         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 383         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 384         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 385         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 386         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 387         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 388         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 389         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 390         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 391         case MLX5_CMD_OP_CREATE_LAG:
 392         case MLX5_CMD_OP_MODIFY_LAG:
 393         case MLX5_CMD_OP_QUERY_LAG:
 394         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 395         case MLX5_CMD_OP_CREATE_TIR:
 396         case MLX5_CMD_OP_MODIFY_TIR:
 397         case MLX5_CMD_OP_QUERY_TIR:
 398         case MLX5_CMD_OP_CREATE_SQ:
 399         case MLX5_CMD_OP_MODIFY_SQ:
 400         case MLX5_CMD_OP_QUERY_SQ:
 401         case MLX5_CMD_OP_CREATE_RQ:
 402         case MLX5_CMD_OP_MODIFY_RQ:
 403         case MLX5_CMD_OP_QUERY_RQ:
 404         case MLX5_CMD_OP_CREATE_RMP:
 405         case MLX5_CMD_OP_MODIFY_RMP:
 406         case MLX5_CMD_OP_QUERY_RMP:
 407         case MLX5_CMD_OP_CREATE_TIS:
 408         case MLX5_CMD_OP_MODIFY_TIS:
 409         case MLX5_CMD_OP_QUERY_TIS:
 410         case MLX5_CMD_OP_CREATE_RQT:
 411         case MLX5_CMD_OP_MODIFY_RQT:
 412         case MLX5_CMD_OP_QUERY_RQT:
 413
 414         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 415         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 416         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 417         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 418         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 419         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 420         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 421         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 422         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 423         case MLX5_CMD_OP_FPGA_CREATE_QP:
 424         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 425         case MLX5_CMD_OP_FPGA_QUERY_QP:
 426         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 427                 *status = MLX5_DRIVER_STATUS_ABORTED;
 428                 *synd = MLX5_DRIVER_SYND;
 429                 return -EIO;
 430         default:
 431                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 432                 return -EINVAL;
 433         }
 434 }
 435
 436 const char *mlx5_command_str(int command)
 437 {
 438 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 439
 440         switch (command) {
 441         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 442         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 443         MLX5_COMMAND_STR_CASE(INIT_HCA);
 444         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 445         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 446         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 447         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 448         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 449         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 450         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 451         MLX5_COMMAND_STR_CASE(SET_ISSI);
 452         MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
 453         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 454         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 455         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 456         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 457         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 458         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 459         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 460         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 461         MLX5_COMMAND_STR_CASE(GEN_EQE);
 462         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 463         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 464         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 465         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 466         MLX5_COMMAND_STR_CASE(CREATE_QP);
 467         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 468         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 469         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 470         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 471         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 472         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 473         MLX5_COMMAND_STR_CASE(2ERR_QP);
 474         MLX5_COMMAND_STR_CASE(2RST_QP);
 475         MLX5_COMMAND_STR_CASE(QUERY_QP);
 476         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 477         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 478         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 479         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 480         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 481         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 482         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 483         MLX5_COMMAND_STR_CASE(ARM_RQ);
 484         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 485         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 486         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 487         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 488         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 489         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 490         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 491         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 492         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 493         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 494         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 495         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 496         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 497         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 498         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 499         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 500         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 501         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 502         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 503         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 504         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 505         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 506         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 507         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 508         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 509         MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
 510         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 511         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 512         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 513         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 514         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 515         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 516         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 517         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 518         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 519         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 520         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 521         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 522         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 523         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 524         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 525         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 526         MLX5_COMMAND_STR_CASE(MAD_IFC);
 527         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 528         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 529         MLX5_COMMAND_STR_CASE(NOP);
 530         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 531         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 532         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 533         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 534         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 535         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 536         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 537         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 538         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 539         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 540         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 541         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 542         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 543         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 544         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 545         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 546         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 547         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 548         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 549         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 550         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 551         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 552         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 553         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 554         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 555         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 556         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 557         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 558         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 559         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 560         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 561         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 562         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 563         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 564         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 565         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 566         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 567         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 568         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 569         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 570         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 571         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 572         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 573         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 574         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 575         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 576         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 577         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 578         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 579         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 580         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 581         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 582         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 583         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 584         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 585         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 586         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 587         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 588         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 589         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 590         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 591         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 592         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 593         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 594         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 595         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 596         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 597         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 598         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 599         default: return "unknown command opcode";
 600         }
 601 }
 602
 603 static const char *cmd_status_str(u8 status)
 604 {
 605         switch (status) {
 606         case MLX5_CMD_STAT_OK:
 607                 return "OK";
 608         case MLX5_CMD_STAT_INT_ERR:
 609                 return "internal error";
 610         case MLX5_CMD_STAT_BAD_OP_ERR:
 611                 return "bad operation";
 612         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 613                 return "bad parameter";
 614         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 615                 return "bad system state";
 616         case MLX5_CMD_STAT_BAD_RES_ERR:
 617                 return "bad resource";
 618         case MLX5_CMD_STAT_RES_BUSY:
 619                 return "resource busy";
 620         case MLX5_CMD_STAT_LIM_ERR:
 621                 return "limits exceeded";
 622         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 623                 return "bad resource state";
 624         case MLX5_CMD_STAT_IX_ERR:
 625                 return "bad index";
 626         case MLX5_CMD_STAT_NO_RES_ERR:
 627                 return "no resources";
 628         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 629                 return "bad input length";
 630         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 631                 return "bad output length";
 632         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 633                 return "bad QP state";
 634         case MLX5_CMD_STAT_BAD_PKT_ERR:
 635                 return "bad packet (discarded)";
 636         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 637                 return "bad size too many outstanding CQEs";
 638         default:
 639                 return "unknown status";
 640         }
 641 }
 642
 643 static int cmd_status_to_err(u8 status)
 644 {
 645         switch (status) {
 646         case MLX5_CMD_STAT_OK:                          return 0;
 647         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 648         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 649         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 650         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 651         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 652         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 653         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 654         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 655         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 656         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 657         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 658         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 659         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 660         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 661         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 662         default:                                        return -EIO;
 663         }
 664 }
 665
 666 struct mlx5_ifc_mbox_out_bits {
 667         u8         status[0x8];
 668         u8         reserved_at_8[0x18];
 669
 670         u8         syndrome[0x20];
 671
 672         u8         reserved_at_40[0x40];
 673 };
 674
 675 struct mlx5_ifc_mbox_in_bits {
 676         u8         opcode[0x10];
 677         u8         reserved_at_10[0x10];
 678
 679         u8         reserved_at_20[0x10];
 680         u8         op_mod[0x10];
 681
 682         u8         reserved_at_40[0x40];
 683 };
 684
 685 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 686 {
 687         *status = MLX5_GET(mbox_out, out, status);
 688         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 689 }
 690
 691 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 692 {
 693         u32 syndrome;
 694         u8  status;
 695         u16 opcode;
 696         u16 op_mod;
 697
 698         mlx5_cmd_mbox_status(out, &status, &syndrome);
 699         if (!status)
 700                 return 0;
 701
 702         opcode = MLX5_GET(mbox_in, in, opcode);
 703         op_mod = MLX5_GET(mbox_in, in, op_mod);
 704
 705         mlx5_core_err(dev,
 706                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 707                       mlx5_command_str(opcode),
 708                       opcode, op_mod,
 709                       cmd_status_str(status),
 710                       status,
 711                       syndrome);
 712
 713         return cmd_status_to_err(status);
 714 }
 715
 716 static void dump_command(struct mlx5_core_dev *dev,
 717                          struct mlx5_cmd_work_ent *ent, int input)
 718 {
 719         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 720         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 721         struct mlx5_cmd_mailbox *next = msg->next;
 722         int data_only;
 723         u32 offset = 0;
 724         int dump_len;
 725
 726         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 727
 728         if (data_only)
 729                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 730                                    "dump command data %s(0x%x) %s\n",
 731                                    mlx5_command_str(op), op,
 732                                    input ? "INPUT" : "OUTPUT");
 733         else
 734                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 735                               mlx5_command_str(op), op,
 736                               input ? "INPUT" : "OUTPUT");
 737
 738         if (data_only) {
 739                 if (input) {
 740                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 741                         offset += sizeof(ent->lay->in);
 742                 } else {
 743                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 744                         offset += sizeof(ent->lay->out);
 745                 }
 746         } else {
 747                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 748                 offset += sizeof(*ent->lay);
 749         }
 750
 751         while (next && offset < msg->len) {
 752                 if (data_only) {
 753                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 754                         dump_buf(next->buf, dump_len, 1, offset);
 755                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 756                 } else {
 757                         mlx5_core_dbg(dev, "command block:\n");
 758                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 759                         offset += sizeof(struct mlx5_cmd_prot_block);
 760                 }
 761                 next = next->next;
 762         }
 763
 764         if (data_only)
 765                 pr_debug("\n");
 766 }
 767
 768 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 769 {
 770         return MLX5_GET(mbox_in, in->first.data, opcode);
 771 }
 772
 773 static void cb_timeout_handler(struct work_struct *work)
 774 {
 775         struct delayed_work *dwork = container_of(work, struct delayed_work,
 776                                                   work);
 777         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 778                                                      struct mlx5_cmd_work_ent,
 779                                                      cb_timeout_work);
 780         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 781                                                  cmd);
 782
 783         ent->ret = -ETIMEDOUT;
 784         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 785                        mlx5_command_str(msg_to_opcode(ent->in)),
 786                        msg_to_opcode(ent->in));
 787         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 788 }
 789
 790 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 791 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 792                               struct mlx5_cmd_msg *msg);
 793
 794 static void cmd_work_handler(struct work_struct *work)
 795 {
 796         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 797         struct mlx5_cmd *cmd = ent->cmd;
 798         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 799         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 800         struct mlx5_cmd_layout *lay;
 801         struct semaphore *sem;
 802         unsigned long flags;
 803         bool poll_cmd = ent->polling;
 804         int alloc_ret;
 805         int cmd_mode;
 806
 807         complete(&ent->handling);
 808         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 809         down(sem);
 810         if (!ent->page_queue) {
 811                 alloc_ret = alloc_ent(cmd);
 812                 if (alloc_ret < 0) {
 813                         mlx5_core_err(dev, "failed to allocate command entry\n");
 814                         if (ent->callback) {
 815                                 ent->callback(-EAGAIN, ent->context);
 816                                 mlx5_free_cmd_msg(dev, ent->out);
 817                                 free_msg(dev, ent->in);
 818                                 free_cmd(ent);
 819                         } else {
 820                                 ent->ret = -EAGAIN;
 821                                 complete(&ent->done);
 822                         }
 823                         up(sem);
 824                         return;
 825                 }
 826                 ent->idx = alloc_ret;
 827         } else {
 828                 ent->idx = cmd->max_reg_cmds;
 829                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 830                 clear_bit(ent->idx, &cmd->bitmask);
 831                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 832         }
 833
 834         cmd->ent_arr[ent->idx] = ent;
 835         lay = get_inst(cmd, ent->idx);
 836         ent->lay = lay;
 837         memset(lay, 0, sizeof(*lay));
 838         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 839         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 840         if (ent->in->next)
 841                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 842         lay->inlen = cpu_to_be32(ent->in->len);
 843         if (ent->out->next)
 844                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 845         lay->outlen = cpu_to_be32(ent->out->len);
 846         lay->type = MLX5_PCI_CMD_XPORT;
 847         lay->token = ent->token;
 848         lay->status_own = CMD_OWNER_HW;
 849         set_signature(ent, !cmd->checksum_disabled);
 850         dump_command(dev, ent, 1);
 851         ent->ts1 = ktime_get_ns();
 852         cmd_mode = cmd->mode;
 853
 854         if (ent->callback)
 855                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 856         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 857
 858         /* Skip sending command to fw if internal error */
 859         if (pci_channel_offline(dev->pdev) ||
 860             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 861                 u8 status = 0;
 862                 u32 drv_synd;
 863
 864                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 865                 MLX5_SET(mbox_out, ent->out, status, status);
 866                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 867
 868                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 869                 /* no doorbell, no need to keep the entry */
 870                 free_ent(cmd, ent->idx);
 871                 if (ent->callback)
 872                         free_cmd(ent);
 873                 return;
 874         }
 875
 876         /* ring doorbell after the descriptor is valid */
 877         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 878         wmb();
 879         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 880         mmiowb();
 881         /* if not in polling don't use ent after this point */
 882         if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
 883                 poll_timeout(ent);
 884                 /* make sure we read the descriptor after ownership is SW */
 885                 rmb();
 886                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 887         }
 888 }
 889
 890 static const char *deliv_status_to_str(u8 status)
 891 {
 892         switch (status) {
 893         case MLX5_CMD_DELIVERY_STAT_OK:
 894                 return "no errors";
 895         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 896                 return "signature error";
 897         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 898                 return "token error";
 899         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 900                 return "bad block number";
 901         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 902                 return "output pointer not aligned to block size";
 903         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 904                 return "input pointer not aligned to block size";
 905         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 906                 return "firmware internal error";
 907         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 908                 return "command input length error";
 909         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 910                 return "command output length error";
 911         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 912                 return "reserved fields not cleared";
 913         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 914                 return "bad command descriptor type";
 915         default:
 916                 return "unknown status code";
 917         }
 918 }
 919
 920 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 921 {
 922         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 923         struct mlx5_cmd *cmd = &dev->cmd;
 924         int err;
 925
 926         if (!wait_for_completion_timeout(&ent->handling, timeout) &&
 927             cancel_work_sync(&ent->work)) {
 928                 ent->ret = -ECANCELED;
 929                 goto out_err;
 930         }
 931         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 932                 wait_for_completion(&ent->done);
 933         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 934                 ent->ret = -ETIMEDOUT;
 935                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 936         }
 937
 938 out_err:
 939         err = ent->ret;
 940
 941         if (err == -ETIMEDOUT) {
 942                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 943                                mlx5_command_str(msg_to_opcode(ent->in)),
 944                                msg_to_opcode(ent->in));
 945         } else if (err == -ECANCELED) {
 946                 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
 947                                mlx5_command_str(msg_to_opcode(ent->in)),
 948                                msg_to_opcode(ent->in));
 949         }
 950         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 951                       err, deliv_status_to_str(ent->status), ent->status);
 952
 953         return err;
 954 }
 955
 956 /*  Notes:
 957  *    1. Callback functions may not sleep
 958  *    2. page queue commands do not support asynchrous completion
 959  */
 960 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 961                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 962                            mlx5_cmd_cbk_t callback,
 963                            void *context, int page_queue, u8 *status,
 964                            u8 token, bool force_polling)
 965 {
 966         struct mlx5_cmd *cmd = &dev->cmd;
 967         struct mlx5_cmd_work_ent *ent;
 968         struct mlx5_cmd_stats *stats;
 969         int err = 0;
 970         s64 ds;
 971         u16 op;
 972
 973         if (callback && page_queue)
 974                 return -EINVAL;
 975
 976         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 977                         page_queue);
 978         if (IS_ERR(ent))
 979                 return PTR_ERR(ent);
 980
 981         ent->token = token;
 982         ent->polling = force_polling;
 983
 984         init_completion(&ent->handling);
 985         if (!callback)
 986                 init_completion(&ent->done);
 987
 988         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
 989         INIT_WORK(&ent->work, cmd_work_handler);
 990         if (page_queue) {
 991                 cmd_work_handler(&ent->work);
 992         } else if (!queue_work(cmd->wq, &ent->work)) {
 993                 mlx5_core_warn(dev, "failed to queue work\n");
 994                 err = -ENOMEM;
 995                 goto out_free;
 996         }
 997
 998         if (callback)
 999                 goto out;
1000
1001         err = wait_func(dev, ent);
1002         if (err == -ETIMEDOUT)
1003                 goto out;
1004         if (err == -ECANCELED)
1005                 goto out_free;
1006
1007         ds = ent->ts2 - ent->ts1;
1008         op = MLX5_GET(mbox_in, in->first.data, opcode);
1009         if (op < ARRAY_SIZE(cmd->stats)) {
1010                 stats = &cmd->stats[op];
1011                 spin_lock_irq(&stats->lock);
1012                 stats->sum += ds;
1013                 ++stats->n;
1014                 spin_unlock_irq(&stats->lock);
1015         }
1016         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1017                            "fw exec time for %s is %lld nsec\n",
1018                            mlx5_command_str(op), ds);
1019         *status = ent->status;
1020
1021 out_free:
1022         free_cmd(ent);
1023 out:
1024         return err;
1025 }
1026
1027 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1028                          size_t count, loff_t *pos)
1029 {
1030         struct mlx5_core_dev *dev = filp->private_data;
1031         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1032         char lbuf[3];
1033         int err;
1034
1035         if (!dbg->in_msg || !dbg->out_msg)
1036                 return -ENOMEM;
1037
1038         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1039                 return -EFAULT;
1040
1041         lbuf[sizeof(lbuf) - 1] = 0;
1042
1043         if (strcmp(lbuf, "go"))
1044                 return -EINVAL;
1045
1046         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1047
1048         return err ? err : count;
1049 }
1050
1051 static const struct file_operations fops = {
1052         .owner  = THIS_MODULE,
1053         .open   = simple_open,
1054         .write  = dbg_write,
1055 };
1056
1057 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1058                             u8 token)
1059 {
1060         struct mlx5_cmd_prot_block *block;
1061         struct mlx5_cmd_mailbox *next;
1062         int copy;
1063
1064         if (!to || !from)
1065                 return -ENOMEM;
1066
1067         copy = min_t(int, size, sizeof(to->first.data));
1068         memcpy(to->first.data, from, copy);
1069         size -= copy;
1070         from += copy;
1071
1072         next = to->next;
1073         while (size) {
1074                 if (!next) {
1075                         /* this is a BUG */
1076                         return -ENOMEM;
1077                 }
1078
1079                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1080                 block = next->buf;
1081                 memcpy(block->data, from, copy);
1082                 from += copy;
1083                 size -= copy;
1084                 block->token = token;
1085                 next = next->next;
1086         }
1087
1088         return 0;
1089 }
1090
1091 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1092 {
1093         struct mlx5_cmd_prot_block *block;
1094         struct mlx5_cmd_mailbox *next;
1095         int copy;
1096
1097         if (!to || !from)
1098                 return -ENOMEM;
1099
1100         copy = min_t(int, size, sizeof(from->first.data));
1101         memcpy(to, from->first.data, copy);
1102         size -= copy;
1103         to += copy;
1104
1105         next = from->next;
1106         while (size) {
1107                 if (!next) {
1108                         /* this is a BUG */
1109                         return -ENOMEM;
1110                 }
1111
1112                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1113                 block = next->buf;
1114
1115                 memcpy(to, block->data, copy);
1116                 to += copy;
1117                 size -= copy;
1118                 next = next->next;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1125                                               gfp_t flags)
1126 {
1127         struct mlx5_cmd_mailbox *mailbox;
1128
1129         mailbox = kmalloc(sizeof(*mailbox), flags);
1130         if (!mailbox)
1131                 return ERR_PTR(-ENOMEM);
1132
1133         mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1134                                        &mailbox->dma);
1135         if (!mailbox->buf) {
1136                 mlx5_core_dbg(dev, "failed allocation\n");
1137                 kfree(mailbox);
1138                 return ERR_PTR(-ENOMEM);
1139         }
1140         mailbox->next = NULL;
1141
1142         return mailbox;
1143 }
1144
1145 static void free_cmd_box(struct mlx5_core_dev *dev,
1146                          struct mlx5_cmd_mailbox *mailbox)
1147 {
1148         dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1149         kfree(mailbox);
1150 }
1151
1152 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1153                                                gfp_t flags, int size,
1154                                                u8 token)
1155 {
1156         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1157         struct mlx5_cmd_prot_block *block;
1158         struct mlx5_cmd_msg *msg;
1159         int blen;
1160         int err;
1161         int n;
1162         int i;
1163
1164         msg = kzalloc(sizeof(*msg), flags);
1165         if (!msg)
1166                 return ERR_PTR(-ENOMEM);
1167
1168         blen = size - min_t(int, sizeof(msg->first.data), size);
1169         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1170
1171         for (i = 0; i < n; i++) {
1172                 tmp = alloc_cmd_box(dev, flags);
1173                 if (IS_ERR(tmp)) {
1174                         mlx5_core_warn(dev, "failed allocating block\n");
1175                         err = PTR_ERR(tmp);
1176                         goto err_alloc;
1177                 }
1178
1179                 block = tmp->buf;
1180                 tmp->next = head;
1181                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1182                 block->block_num = cpu_to_be32(n - i - 1);
1183                 block->token = token;
1184                 head = tmp;
1185         }
1186         msg->next = head;
1187         msg->len = size;
1188         return msg;
1189
1190 err_alloc:
1191         while (head) {
1192                 tmp = head->next;
1193                 free_cmd_box(dev, head);
1194                 head = tmp;
1195         }
1196         kfree(msg);
1197
1198         return ERR_PTR(err);
1199 }
1200
1201 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1202                               struct mlx5_cmd_msg *msg)
1203 {
1204         struct mlx5_cmd_mailbox *head = msg->next;
1205         struct mlx5_cmd_mailbox *next;
1206
1207         while (head) {
1208                 next = head->next;
1209                 free_cmd_box(dev, head);
1210                 head = next;
1211         }
1212         kfree(msg);
1213 }
1214
1215 static ssize_t data_write(struct file *filp, const char __user *buf,
1216                           size_t count, loff_t *pos)
1217 {
1218         struct mlx5_core_dev *dev = filp->private_data;
1219         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1220         void *ptr;
1221
1222         if (*pos != 0)
1223                 return -EINVAL;
1224
1225         kfree(dbg->in_msg);
1226         dbg->in_msg = NULL;
1227         dbg->inlen = 0;
1228         ptr = memdup_user(buf, count);
1229         if (IS_ERR(ptr))
1230                 return PTR_ERR(ptr);
1231         dbg->in_msg = ptr;
1232         dbg->inlen = count;
1233
1234         *pos = count;
1235
1236         return count;
1237 }
1238
1239 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1240                          loff_t *pos)
1241 {
1242         struct mlx5_core_dev *dev = filp->private_data;
1243         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1244         int copy;
1245
1246         if (*pos)
1247                 return 0;
1248
1249         if (!dbg->out_msg)
1250                 return -ENOMEM;
1251
1252         copy = min_t(int, count, dbg->outlen);
1253         if (copy_to_user(buf, dbg->out_msg, copy))
1254                 return -EFAULT;
1255
1256         *pos += copy;
1257
1258         return copy;
1259 }
1260
1261 static const struct file_operations dfops = {
1262         .owner  = THIS_MODULE,
1263         .open   = simple_open,
1264         .write  = data_write,
1265         .read   = data_read,
1266 };
1267
1268 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1269                            loff_t *pos)
1270 {
1271         struct mlx5_core_dev *dev = filp->private_data;
1272         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1273         char outlen[8];
1274         int err;
1275
1276         if (*pos)
1277                 return 0;
1278
1279         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1280         if (err < 0)
1281                 return err;
1282
1283         if (copy_to_user(buf, &outlen, err))
1284                 return -EFAULT;
1285
1286         *pos += err;
1287
1288         return err;
1289 }
1290
1291 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1292                             size_t count, loff_t *pos)
1293 {
1294         struct mlx5_core_dev *dev = filp->private_data;
1295         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1296         char outlen_str[8] = {0};
1297         int outlen;
1298         void *ptr;
1299         int err;
1300
1301         if (*pos != 0 || count > 6)
1302                 return -EINVAL;
1303
1304         kfree(dbg->out_msg);
1305         dbg->out_msg = NULL;
1306         dbg->outlen = 0;
1307
1308         if (copy_from_user(outlen_str, buf, count))
1309                 return -EFAULT;
1310
1311         err = sscanf(outlen_str, "%d", &outlen);
1312         if (err < 0)
1313                 return err;
1314
1315         ptr = kzalloc(outlen, GFP_KERNEL);
1316         if (!ptr)
1317                 return -ENOMEM;
1318
1319         dbg->out_msg = ptr;
1320         dbg->outlen = outlen;
1321
1322         *pos = count;
1323
1324         return count;
1325 }
1326
1327 static const struct file_operations olfops = {
1328         .owner  = THIS_MODULE,
1329         .open   = simple_open,
1330         .write  = outlen_write,
1331         .read   = outlen_read,
1332 };
1333
1334 static void set_wqname(struct mlx5_core_dev *dev)
1335 {
1336         struct mlx5_cmd *cmd = &dev->cmd;
1337
1338         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1339                  dev_name(&dev->pdev->dev));
1340 }
1341
1342 static void clean_debug_files(struct mlx5_core_dev *dev)
1343 {
1344         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1345
1346         if (!mlx5_debugfs_root)
1347                 return;
1348
1349         mlx5_cmdif_debugfs_cleanup(dev);
1350         debugfs_remove_recursive(dbg->dbg_root);
1351 }
1352
1353 static int create_debugfs_files(struct mlx5_core_dev *dev)
1354 {
1355         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1356         int err = -ENOMEM;
1357
1358         if (!mlx5_debugfs_root)
1359                 return 0;
1360
1361         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1362         if (!dbg->dbg_root)
1363                 return err;
1364
1365         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1366                                           dev, &dfops);
1367         if (!dbg->dbg_in)
1368                 goto err_dbg;
1369
1370         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1371                                            dev, &dfops);
1372         if (!dbg->dbg_out)
1373                 goto err_dbg;
1374
1375         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1376                                               dev, &olfops);
1377         if (!dbg->dbg_outlen)
1378                 goto err_dbg;
1379
1380         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1381                                             &dbg->status);
1382         if (!dbg->dbg_status)
1383                 goto err_dbg;
1384
1385         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1386         if (!dbg->dbg_run)
1387                 goto err_dbg;
1388
1389         mlx5_cmdif_debugfs_init(dev);
1390
1391         return 0;
1392
1393 err_dbg:
1394         clean_debug_files(dev);
1395         return err;
1396 }
1397
1398 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1399 {
1400         struct mlx5_cmd *cmd = &dev->cmd;
1401         int i;
1402
1403         for (i = 0; i < cmd->max_reg_cmds; i++)
1404                 down(&cmd->sem);
1405         down(&cmd->pages_sem);
1406
1407         cmd->mode = mode;
1408
1409         up(&cmd->pages_sem);
1410         for (i = 0; i < cmd->max_reg_cmds; i++)
1411                 up(&cmd->sem);
1412 }
1413
1414 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1415 {
1416         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1417 }
1418
1419 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1420 {
1421         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1422 }
1423
1424 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1425 {
1426         unsigned long flags;
1427
1428         if (msg->parent) {
1429                 spin_lock_irqsave(&msg->parent->lock, flags);
1430                 list_add_tail(&msg->list, &msg->parent->head);
1431                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1432         } else {
1433                 mlx5_free_cmd_msg(dev, msg);
1434         }
1435 }
1436
1437 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1438 {
1439         struct mlx5_cmd *cmd = &dev->cmd;
1440         struct mlx5_cmd_work_ent *ent;
1441         mlx5_cmd_cbk_t callback;
1442         void *context;
1443         int err;
1444         int i;
1445         s64 ds;
1446         struct mlx5_cmd_stats *stats;
1447         unsigned long flags;
1448         unsigned long vector;
1449
1450         /* there can be at most 32 command queues */
1451         vector = vec & 0xffffffff;
1452         for (i = 0; i < (1 << cmd->log_sz); i++) {
1453                 if (test_bit(i, &vector)) {
1454                         struct semaphore *sem;
1455
1456                         ent = cmd->ent_arr[i];
1457
1458                         /* if we already completed the command, ignore it */
1459                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1460                                                 &ent->state)) {
1461                                 /* only real completion can free the cmd slot */
1462                                 if (!forced) {
1463                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1464                                                       ent->idx);
1465                                         free_ent(cmd, ent->idx);
1466                                         free_cmd(ent);
1467                                 }
1468                                 continue;
1469                         }
1470
1471                         if (ent->callback)
1472                                 cancel_delayed_work(&ent->cb_timeout_work);
1473                         if (ent->page_queue)
1474                                 sem = &cmd->pages_sem;
1475                         else
1476                                 sem = &cmd->sem;
1477                         ent->ts2 = ktime_get_ns();
1478                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1479                         dump_command(dev, ent, 0);
1480                         if (!ent->ret) {
1481                                 if (!cmd->checksum_disabled)
1482                                         ent->ret = verify_signature(ent);
1483                                 else
1484                                         ent->ret = 0;
1485                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1486                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1487                                 else
1488                                         ent->status = ent->lay->status_own >> 1;
1489
1490                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1491                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1492                         }
1493
1494                         /* only real completion will free the entry slot */
1495                         if (!forced)
1496                                 free_ent(cmd, ent->idx);
1497
1498                         if (ent->callback) {
1499                                 ds = ent->ts2 - ent->ts1;
1500                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1501                                         stats = &cmd->stats[ent->op];
1502                                         spin_lock_irqsave(&stats->lock, flags);
1503                                         stats->sum += ds;
1504                                         ++stats->n;
1505                                         spin_unlock_irqrestore(&stats->lock, flags);
1506                                 }
1507
1508                                 callback = ent->callback;
1509                                 context = ent->context;
1510                                 err = ent->ret;
1511                                 if (!err) {
1512                                         err = mlx5_copy_from_msg(ent->uout,
1513                                                                  ent->out,
1514                                                                  ent->uout_size);
1515
1516                                         err = err ? err : mlx5_cmd_check(dev,
1517                                                                         ent->in->first.data,
1518                                                                         ent->uout);
1519                                 }
1520
1521                                 mlx5_free_cmd_msg(dev, ent->out);
1522                                 free_msg(dev, ent->in);
1523
1524                                 err = err ? err : ent->status;
1525                                 if (!forced)
1526                                         free_cmd(ent);
1527                                 callback(err, context);
1528                         } else {
1529                                 complete(&ent->done);
1530                         }
1531                         up(sem);
1532                 }
1533         }
1534 }
1535 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1536
1537 static int status_to_err(u8 status)
1538 {
1539         return status ? -1 : 0; /* TBD more meaningful codes */
1540 }
1541
1542 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1543                                       gfp_t gfp)
1544 {
1545         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1546         struct cmd_msg_cache *ch = NULL;
1547         struct mlx5_cmd *cmd = &dev->cmd;
1548         int i;
1549
1550         if (in_size <= 16)
1551                 goto cache_miss;
1552
1553         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1554                 ch = &cmd->cache[i];
1555                 if (in_size > ch->max_inbox_size)
1556                         continue;
1557                 spin_lock_irq(&ch->lock);
1558                 if (list_empty(&ch->head)) {
1559                         spin_unlock_irq(&ch->lock);
1560                         continue;
1561                 }
1562                 msg = list_entry(ch->head.next, typeof(*msg), list);
1563                 /* For cached lists, we must explicitly state what is
1564                  * the real size
1565                  */
1566                 msg->len = in_size;
1567                 list_del(&msg->list);
1568                 spin_unlock_irq(&ch->lock);
1569                 break;
1570         }
1571
1572         if (!IS_ERR(msg))
1573                 return msg;
1574
1575 cache_miss:
1576         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1577         return msg;
1578 }
1579
1580 static int is_manage_pages(void *in)
1581 {
1582         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1583 }
1584
1585 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1586                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1587                     bool force_polling)
1588 {
1589         struct mlx5_cmd_msg *inb;
1590         struct mlx5_cmd_msg *outb;
1591         int pages_queue;
1592         gfp_t gfp;
1593         int err;
1594         u8 status = 0;
1595         u32 drv_synd;
1596         u8 token;
1597
1598         if (pci_channel_offline(dev->pdev) ||
1599             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1600                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1601
1602                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1603                 MLX5_SET(mbox_out, out, status, status);
1604                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1605                 return err;
1606         }
1607
1608         pages_queue = is_manage_pages(in);
1609         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1610
1611         inb = alloc_msg(dev, in_size, gfp);
1612         if (IS_ERR(inb)) {
1613                 err = PTR_ERR(inb);
1614                 return err;
1615         }
1616
1617         token = alloc_token(&dev->cmd);
1618
1619         err = mlx5_copy_to_msg(inb, in, in_size, token);
1620         if (err) {
1621                 mlx5_core_warn(dev, "err %d\n", err);
1622                 goto out_in;
1623         }
1624
1625         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1626         if (IS_ERR(outb)) {
1627                 err = PTR_ERR(outb);
1628                 goto out_in;
1629         }
1630
1631         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1632                               pages_queue, &status, token, force_polling);
1633         if (err)
1634                 goto out_out;
1635
1636         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1637         if (status) {
1638                 err = status_to_err(status);
1639                 goto out_out;
1640         }
1641
1642         if (!callback)
1643                 err = mlx5_copy_from_msg(out, outb, out_size);
1644
1645 out_out:
1646         if (!callback)
1647                 mlx5_free_cmd_msg(dev, outb);
1648
1649 out_in:
1650         if (!callback)
1651                 free_msg(dev, inb);
1652         return err;
1653 }
1654
1655 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1656                   int out_size)
1657 {
1658         int err;
1659
1660         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1661         return err ? : mlx5_cmd_check(dev, in, out);
1662 }
1663 EXPORT_SYMBOL(mlx5_cmd_exec);
1664
1665 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1666                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1667                      void *context)
1668 {
1669         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1670                         false);
1671 }
1672 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1673
1674 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1675                           void *out, int out_size)
1676 {
1677         int err;
1678
1679         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1680
1681         return err ? : mlx5_cmd_check(dev, in, out);
1682 }
1683 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1684
1685 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1686 {
1687         struct cmd_msg_cache *ch;
1688         struct mlx5_cmd_msg *msg;
1689         struct mlx5_cmd_msg *n;
1690         int i;
1691
1692         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1693                 ch = &dev->cmd.cache[i];
1694                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1695                         list_del(&msg->list);
1696                         mlx5_free_cmd_msg(dev, msg);
1697                 }
1698         }
1699 }
1700
1701 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1702         512, 32, 16, 8, 2
1703 };
1704
1705 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1706         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1707         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1708         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1709         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1710         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1711 };
1712
1713 static void create_msg_cache(struct mlx5_core_dev *dev)
1714 {
1715         struct mlx5_cmd *cmd = &dev->cmd;
1716         struct cmd_msg_cache *ch;
1717         struct mlx5_cmd_msg *msg;
1718         int i;
1719         int k;
1720
1721         /* Initialize and fill the caches with initial entries */
1722         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1723                 ch = &cmd->cache[k];
1724                 spin_lock_init(&ch->lock);
1725                 INIT_LIST_HEAD(&ch->head);
1726                 ch->num_ent = cmd_cache_num_ent[k];
1727                 ch->max_inbox_size = cmd_cache_ent_size[k];
1728                 for (i = 0; i < ch->num_ent; i++) {
1729                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1730                                                  ch->max_inbox_size, 0);
1731                         if (IS_ERR(msg))
1732                                 break;
1733                         msg->parent = ch;
1734                         list_add_tail(&msg->list, &ch->head);
1735                 }
1736         }
1737 }
1738
1739 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1740 {
1741         struct device *ddev = &dev->pdev->dev;
1742
1743         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1744                                                  &cmd->alloc_dma, GFP_KERNEL);
1745         if (!cmd->cmd_alloc_buf)
1746                 return -ENOMEM;
1747
1748         /* make sure it is aligned to 4K */
1749         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1750                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1751                 cmd->dma = cmd->alloc_dma;
1752                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1753                 return 0;
1754         }
1755
1756         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1757                           cmd->alloc_dma);
1758         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1759                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1760                                                  &cmd->alloc_dma, GFP_KERNEL);
1761         if (!cmd->cmd_alloc_buf)
1762                 return -ENOMEM;
1763
1764         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1765         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1766         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1767         return 0;
1768 }
1769
1770 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1771 {
1772         struct device *ddev = &dev->pdev->dev;
1773
1774         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1775                           cmd->alloc_dma);
1776 }
1777
1778 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1779 {
1780         int size = sizeof(struct mlx5_cmd_prot_block);
1781         int align = roundup_pow_of_two(size);
1782         struct mlx5_cmd *cmd = &dev->cmd;
1783         u32 cmd_h, cmd_l;
1784         u16 cmd_if_rev;
1785         int err;
1786         int i;
1787
1788         memset(cmd, 0, sizeof(*cmd));
1789         cmd_if_rev = cmdif_rev(dev);
1790         if (cmd_if_rev != CMD_IF_REV) {
1791                 dev_err(&dev->pdev->dev,
1792                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1793                         CMD_IF_REV, cmd_if_rev);
1794                 return -EINVAL;
1795         }
1796
1797         cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1798                                     0);
1799         if (!cmd->pool)
1800                 return -ENOMEM;
1801
1802         err = alloc_cmd_page(dev, cmd);
1803         if (err)
1804                 goto err_free_pool;
1805
1806         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1807         cmd->log_sz = cmd_l >> 4 & 0xf;
1808         cmd->log_stride = cmd_l & 0xf;
1809         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1810                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1811                         1 << cmd->log_sz);
1812                 err = -EINVAL;
1813                 goto err_free_page;
1814         }
1815
1816         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1817                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1818                 err = -EINVAL;
1819                 goto err_free_page;
1820         }
1821
1822         cmd->checksum_disabled = 1;
1823         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1824         cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1825
1826         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1827         if (cmd->cmdif_rev > CMD_IF_REV) {
1828                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1829                         CMD_IF_REV, cmd->cmdif_rev);
1830                 err = -EOPNOTSUPP;
1831                 goto err_free_page;
1832         }
1833
1834         spin_lock_init(&cmd->alloc_lock);
1835         spin_lock_init(&cmd->token_lock);
1836         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1837                 spin_lock_init(&cmd->stats[i].lock);
1838
1839         sema_init(&cmd->sem, cmd->max_reg_cmds);
1840         sema_init(&cmd->pages_sem, 1);
1841
1842         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1843         cmd_l = (u32)(cmd->dma);
1844         if (cmd_l & 0xfff) {
1845                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1846                 err = -ENOMEM;
1847                 goto err_free_page;
1848         }
1849
1850         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1851         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1852
1853         /* Make sure firmware sees the complete address before we proceed */
1854         wmb();
1855
1856         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1857
1858         cmd->mode = CMD_MODE_POLLING;
1859
1860         create_msg_cache(dev);
1861
1862         set_wqname(dev);
1863         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1864         if (!cmd->wq) {
1865                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1866                 err = -ENOMEM;
1867                 goto err_cache;
1868         }
1869
1870         err = create_debugfs_files(dev);
1871         if (err) {
1872                 err = -ENOMEM;
1873                 goto err_wq;
1874         }
1875
1876         return 0;
1877
1878 err_wq:
1879         destroy_workqueue(cmd->wq);
1880
1881 err_cache:
1882         destroy_msg_cache(dev);
1883
1884 err_free_page:
1885         free_cmd_page(dev, cmd);
1886
1887 err_free_pool:
1888         dma_pool_destroy(cmd->pool);
1889
1890         return err;
1891 }
1892 EXPORT_SYMBOL(mlx5_cmd_init);
1893
1894 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1895 {
1896         struct mlx5_cmd *cmd = &dev->cmd;
1897
1898         clean_debug_files(dev);
1899         destroy_workqueue(cmd->wq);
1900         destroy_msg_cache(dev);
1901         free_cmd_page(dev, cmd);
1902         dma_pool_destroy(cmd->pool);
1903 }
1904 EXPORT_SYMBOL(mlx5_cmd_cleanup);