2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/sched.h>
37 #include <linux/pci.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/mlx4/cmd.h>
43 #include <linux/mlx4/qp.h>
44 #include <linux/if_ether.h>
45 #include <linux/etherdevice.h>
49 #include "mlx4_stats.h"
51 #define MLX4_MAC_VALID (1ull << 63)
52 #define MLX4_PF_COUNTERS_PER_PORT 2
53 #define MLX4_VF_COUNTERS_PER_PORT 1
56 struct list_head list;
64 struct list_head list;
72 struct list_head list;
80 const char *func_name;
88 struct list_head list;
90 enum mlx4_protocol prot;
91 enum mlx4_steer_type steer;
96 RES_QP_BUSY = RES_ANY_BUSY,
98 /* QP number was allocated */
101 /* ICM memory for QP context was mapped */
104 /* QP is in hw ownership */
109 struct res_common com;
114 struct list_head mcg_list;
119 /* saved qp params before VST enforcement in order to restore on VGT */
129 enum res_mtt_states {
130 RES_MTT_BUSY = RES_ANY_BUSY,
134 static inline const char *mtt_states_str(enum res_mtt_states state)
137 case RES_MTT_BUSY: return "RES_MTT_BUSY";
138 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
139 default: return "Unknown";
144 struct res_common com;
149 enum res_mpt_states {
150 RES_MPT_BUSY = RES_ANY_BUSY,
157 struct res_common com;
163 RES_EQ_BUSY = RES_ANY_BUSY,
169 struct res_common com;
174 RES_CQ_BUSY = RES_ANY_BUSY,
180 struct res_common com;
185 enum res_srq_states {
186 RES_SRQ_BUSY = RES_ANY_BUSY,
192 struct res_common com;
198 enum res_counter_states {
199 RES_COUNTER_BUSY = RES_ANY_BUSY,
200 RES_COUNTER_ALLOCATED,
204 struct res_common com;
208 enum res_xrcdn_states {
209 RES_XRCD_BUSY = RES_ANY_BUSY,
214 struct res_common com;
218 enum res_fs_rule_states {
219 RES_FS_RULE_BUSY = RES_ANY_BUSY,
220 RES_FS_RULE_ALLOCATED,
224 struct res_common com;
226 /* VF DMFS mbox with port flipped */
228 /* > 0 --> apply mirror when getting into HA mode */
229 /* = 0 --> un-apply mirror when getting out of HA mode */
231 struct list_head mirr_list;
235 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
237 struct rb_node *node = root->rb_node;
240 struct res_common *res = rb_entry(node, struct res_common,
243 if (res_id < res->res_id)
244 node = node->rb_left;
245 else if (res_id > res->res_id)
246 node = node->rb_right;
253 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
255 struct rb_node **new = &(root->rb_node), *parent = NULL;
257 /* Figure out where to put new node */
259 struct res_common *this = rb_entry(*new, struct res_common,
263 if (res->res_id < this->res_id)
264 new = &((*new)->rb_left);
265 else if (res->res_id > this->res_id)
266 new = &((*new)->rb_right);
271 /* Add new node and rebalance tree. */
272 rb_link_node(&res->node, parent, new);
273 rb_insert_color(&res->node, root);
288 static const char *resource_str(enum mlx4_resource rt)
291 case RES_QP: return "RES_QP";
292 case RES_CQ: return "RES_CQ";
293 case RES_SRQ: return "RES_SRQ";
294 case RES_MPT: return "RES_MPT";
295 case RES_MTT: return "RES_MTT";
296 case RES_MAC: return "RES_MAC";
297 case RES_VLAN: return "RES_VLAN";
298 case RES_EQ: return "RES_EQ";
299 case RES_COUNTER: return "RES_COUNTER";
300 case RES_FS_RULE: return "RES_FS_RULE";
301 case RES_XRCD: return "RES_XRCD";
302 default: return "Unknown resource type !!!";
306 static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
307 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
308 enum mlx4_resource res_type, int count,
311 struct mlx4_priv *priv = mlx4_priv(dev);
312 struct resource_allocator *res_alloc =
313 &priv->mfunc.master.res_tracker.res_alloc[res_type];
315 int allocated, free, reserved, guaranteed, from_free;
318 if (slave > dev->persist->num_vfs)
321 spin_lock(&res_alloc->alloc_lock);
322 allocated = (port > 0) ?
323 res_alloc->allocated[(port - 1) *
324 (dev->persist->num_vfs + 1) + slave] :
325 res_alloc->allocated[slave];
326 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
328 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
329 res_alloc->res_reserved;
330 guaranteed = res_alloc->guaranteed[slave];
332 if (allocated + count > res_alloc->quota[slave]) {
333 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
334 slave, port, resource_str(res_type), count,
335 allocated, res_alloc->quota[slave]);
339 if (allocated + count <= guaranteed) {
343 /* portion may need to be obtained from free area */
344 if (guaranteed - allocated > 0)
345 from_free = count - (guaranteed - allocated);
349 from_rsvd = count - from_free;
351 if (free - from_free >= reserved)
354 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
355 slave, port, resource_str(res_type), free,
356 from_free, reserved);
360 /* grant the request */
362 res_alloc->allocated[(port - 1) *
363 (dev->persist->num_vfs + 1) + slave] += count;
364 res_alloc->res_port_free[port - 1] -= count;
365 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
367 res_alloc->allocated[slave] += count;
368 res_alloc->res_free -= count;
369 res_alloc->res_reserved -= from_rsvd;
374 spin_unlock(&res_alloc->alloc_lock);
378 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
379 enum mlx4_resource res_type, int count,
382 struct mlx4_priv *priv = mlx4_priv(dev);
383 struct resource_allocator *res_alloc =
384 &priv->mfunc.master.res_tracker.res_alloc[res_type];
385 int allocated, guaranteed, from_rsvd;
387 if (slave > dev->persist->num_vfs)
390 spin_lock(&res_alloc->alloc_lock);
392 allocated = (port > 0) ?
393 res_alloc->allocated[(port - 1) *
394 (dev->persist->num_vfs + 1) + slave] :
395 res_alloc->allocated[slave];
396 guaranteed = res_alloc->guaranteed[slave];
398 if (allocated - count >= guaranteed) {
401 /* portion may need to be returned to reserved area */
402 if (allocated - guaranteed > 0)
403 from_rsvd = count - (allocated - guaranteed);
409 res_alloc->allocated[(port - 1) *
410 (dev->persist->num_vfs + 1) + slave] -= count;
411 res_alloc->res_port_free[port - 1] += count;
412 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
414 res_alloc->allocated[slave] -= count;
415 res_alloc->res_free += count;
416 res_alloc->res_reserved += from_rsvd;
419 spin_unlock(&res_alloc->alloc_lock);
423 static inline void initialize_res_quotas(struct mlx4_dev *dev,
424 struct resource_allocator *res_alloc,
425 enum mlx4_resource res_type,
426 int vf, int num_instances)
428 res_alloc->guaranteed[vf] = num_instances /
429 (2 * (dev->persist->num_vfs + 1));
430 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
431 if (vf == mlx4_master_func_num(dev)) {
432 res_alloc->res_free = num_instances;
433 if (res_type == RES_MTT) {
434 /* reserved mtts will be taken out of the PF allocation */
435 res_alloc->res_free += dev->caps.reserved_mtts;
436 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
437 res_alloc->quota[vf] += dev->caps.reserved_mtts;
442 void mlx4_init_quotas(struct mlx4_dev *dev)
444 struct mlx4_priv *priv = mlx4_priv(dev);
447 /* quotas for VFs are initialized in mlx4_slave_cap */
448 if (mlx4_is_slave(dev))
451 if (!mlx4_is_mfunc(dev)) {
452 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
453 mlx4_num_reserved_sqps(dev);
454 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
455 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
456 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
457 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
461 pf = mlx4_master_func_num(dev);
463 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
465 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
467 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
469 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
471 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
475 mlx4_calc_res_counter_guaranteed(struct mlx4_dev *dev,
476 struct resource_allocator *res_alloc,
479 struct mlx4_active_ports actv_ports;
480 int ports, counters_guaranteed;
482 /* For master, only allocate according to the number of phys ports */
483 if (vf == mlx4_master_func_num(dev))
484 return MLX4_PF_COUNTERS_PER_PORT * dev->caps.num_ports;
486 /* calculate real number of ports for the VF */
487 actv_ports = mlx4_get_active_ports(dev, vf);
488 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
489 counters_guaranteed = ports * MLX4_VF_COUNTERS_PER_PORT;
491 /* If we do not have enough counters for this VF, do not
492 * allocate any for it. '-1' to reduce the sink counter.
494 if ((res_alloc->res_reserved + counters_guaranteed) >
495 (dev->caps.max_counters - 1))
498 return counters_guaranteed;
501 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
503 struct mlx4_priv *priv = mlx4_priv(dev);
507 priv->mfunc.master.res_tracker.slave_list =
508 kcalloc(dev->num_slaves, sizeof(struct slave_list),
510 if (!priv->mfunc.master.res_tracker.slave_list)
513 for (i = 0 ; i < dev->num_slaves; i++) {
514 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
515 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
516 slave_list[i].res_list[t]);
517 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
520 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
522 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
523 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
525 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
526 struct resource_allocator *res_alloc =
527 &priv->mfunc.master.res_tracker.res_alloc[i];
528 res_alloc->quota = kmalloc_array(dev->persist->num_vfs + 1,
531 res_alloc->guaranteed = kmalloc_array(dev->persist->num_vfs + 1,
534 if (i == RES_MAC || i == RES_VLAN)
535 res_alloc->allocated =
536 kcalloc(MLX4_MAX_PORTS *
537 (dev->persist->num_vfs + 1),
538 sizeof(int), GFP_KERNEL);
540 res_alloc->allocated =
541 kcalloc(dev->persist->num_vfs + 1,
542 sizeof(int), GFP_KERNEL);
543 /* Reduce the sink counter */
544 if (i == RES_COUNTER)
545 res_alloc->res_free = dev->caps.max_counters - 1;
547 if (!res_alloc->quota || !res_alloc->guaranteed ||
548 !res_alloc->allocated)
551 spin_lock_init(&res_alloc->alloc_lock);
552 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
553 struct mlx4_active_ports actv_ports =
554 mlx4_get_active_ports(dev, t);
557 initialize_res_quotas(dev, res_alloc, RES_QP,
558 t, dev->caps.num_qps -
559 dev->caps.reserved_qps -
560 mlx4_num_reserved_sqps(dev));
563 initialize_res_quotas(dev, res_alloc, RES_CQ,
564 t, dev->caps.num_cqs -
565 dev->caps.reserved_cqs);
568 initialize_res_quotas(dev, res_alloc, RES_SRQ,
569 t, dev->caps.num_srqs -
570 dev->caps.reserved_srqs);
573 initialize_res_quotas(dev, res_alloc, RES_MPT,
574 t, dev->caps.num_mpts -
575 dev->caps.reserved_mrws);
578 initialize_res_quotas(dev, res_alloc, RES_MTT,
579 t, dev->caps.num_mtts -
580 dev->caps.reserved_mtts);
583 if (t == mlx4_master_func_num(dev)) {
584 int max_vfs_pport = 0;
585 /* Calculate the max vfs per port for */
587 for (j = 0; j < dev->caps.num_ports;
589 struct mlx4_slaves_pport slaves_pport =
590 mlx4_phys_to_slaves_pport(dev, j + 1);
591 unsigned current_slaves =
592 bitmap_weight(slaves_pport.slaves,
593 dev->caps.num_ports) - 1;
594 if (max_vfs_pport < current_slaves)
598 res_alloc->quota[t] =
601 res_alloc->guaranteed[t] = 2;
602 for (j = 0; j < MLX4_MAX_PORTS; j++)
603 res_alloc->res_port_free[j] =
606 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
607 res_alloc->guaranteed[t] = 2;
611 if (t == mlx4_master_func_num(dev)) {
612 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
613 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
614 for (j = 0; j < MLX4_MAX_PORTS; j++)
615 res_alloc->res_port_free[j] =
618 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
619 res_alloc->guaranteed[t] = 0;
623 res_alloc->quota[t] = dev->caps.max_counters;
624 res_alloc->guaranteed[t] =
625 mlx4_calc_res_counter_guaranteed(dev, res_alloc, t);
630 if (i == RES_MAC || i == RES_VLAN) {
631 for (j = 0; j < dev->caps.num_ports; j++)
632 if (test_bit(j, actv_ports.ports))
633 res_alloc->res_port_rsvd[j] +=
634 res_alloc->guaranteed[t];
636 res_alloc->res_reserved += res_alloc->guaranteed[t];
640 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
644 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
645 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
646 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
647 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
648 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
649 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
650 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
655 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
656 enum mlx4_res_tracker_free_type type)
658 struct mlx4_priv *priv = mlx4_priv(dev);
661 if (priv->mfunc.master.res_tracker.slave_list) {
662 if (type != RES_TR_FREE_STRUCTS_ONLY) {
663 for (i = 0; i < dev->num_slaves; i++) {
664 if (type == RES_TR_FREE_ALL ||
665 dev->caps.function != i)
666 mlx4_delete_all_resources_for_slave(dev, i);
668 /* free master's vlans */
669 i = dev->caps.function;
670 mlx4_reset_roce_gids(dev, i);
671 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
672 rem_slave_vlans(dev, i);
673 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
676 if (type != RES_TR_FREE_SLAVES_ONLY) {
677 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
678 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
679 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
680 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
681 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
682 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
683 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
685 kfree(priv->mfunc.master.res_tracker.slave_list);
686 priv->mfunc.master.res_tracker.slave_list = NULL;
691 static void update_pkey_index(struct mlx4_dev *dev, int slave,
692 struct mlx4_cmd_mailbox *inbox)
694 u8 sched = *(u8 *)(inbox->buf + 64);
695 u8 orig_index = *(u8 *)(inbox->buf + 35);
697 struct mlx4_priv *priv = mlx4_priv(dev);
700 port = (sched >> 6 & 1) + 1;
702 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
703 *(u8 *)(inbox->buf + 35) = new_index;
706 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
709 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
710 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
711 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
714 if (MLX4_QP_ST_UD == ts) {
715 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
716 if (mlx4_is_eth(dev, port))
717 qp_ctx->pri_path.mgid_index =
718 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
720 qp_ctx->pri_path.mgid_index = slave | 0x80;
722 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
723 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
724 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
725 if (mlx4_is_eth(dev, port)) {
726 qp_ctx->pri_path.mgid_index +=
727 mlx4_get_base_gid_ix(dev, slave, port);
728 qp_ctx->pri_path.mgid_index &= 0x7f;
730 qp_ctx->pri_path.mgid_index = slave & 0x7F;
733 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
734 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
735 if (mlx4_is_eth(dev, port)) {
736 qp_ctx->alt_path.mgid_index +=
737 mlx4_get_base_gid_ix(dev, slave, port);
738 qp_ctx->alt_path.mgid_index &= 0x7f;
740 qp_ctx->alt_path.mgid_index = slave & 0x7F;
746 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
749 static int update_vport_qp_param(struct mlx4_dev *dev,
750 struct mlx4_cmd_mailbox *inbox,
753 struct mlx4_qp_context *qpc = inbox->buf + 8;
754 struct mlx4_vport_oper_state *vp_oper;
755 struct mlx4_priv *priv;
759 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
760 priv = mlx4_priv(dev);
761 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
762 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
764 err = handle_counter(dev, qpc, slave, port);
768 if (MLX4_VGT != vp_oper->state.default_vlan) {
769 /* the reserved QPs (special, proxy, tunnel)
770 * do not operate over vlans
772 if (mlx4_is_qp_reserved(dev, qpn))
775 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
776 if (qp_type == MLX4_QP_ST_UD ||
777 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
778 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
779 *(__be32 *)inbox->buf =
780 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
781 MLX4_QP_OPTPAR_VLAN_STRIPPING);
782 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
784 struct mlx4_update_qp_params params = {.flags = 0};
786 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, ¶ms);
792 /* preserve IF_COUNTER flag */
793 qpc->pri_path.vlan_control &=
794 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
795 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
796 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
797 qpc->pri_path.vlan_control |=
798 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
799 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
800 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
801 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
802 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
803 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
804 } else if (0 != vp_oper->state.default_vlan) {
805 if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD)) {
806 /* vst QinQ should block untagged on TX,
807 * but cvlan is in payload and phv is set so
808 * hw see it as untagged. Block tagged instead.
810 qpc->pri_path.vlan_control |=
811 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
812 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
813 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
814 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
815 } else { /* vst 802.1Q */
816 qpc->pri_path.vlan_control |=
817 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
818 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
819 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
821 } else { /* priority tagged */
822 qpc->pri_path.vlan_control |=
823 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
824 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
827 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
828 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
829 qpc->pri_path.fl |= MLX4_FL_ETH_HIDE_CQE_VLAN;
830 if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD))
831 qpc->pri_path.fl |= MLX4_FL_SV;
833 qpc->pri_path.fl |= MLX4_FL_CV;
834 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
835 qpc->pri_path.sched_queue &= 0xC7;
836 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
837 qpc->qos_vport = vp_oper->state.qos_vport;
839 if (vp_oper->state.spoofchk) {
840 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
841 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
847 static int mpt_mask(struct mlx4_dev *dev)
849 return dev->caps.num_mpts - 1;
852 static const char *mlx4_resource_type_to_str(enum mlx4_resource t)
878 return "INVALID RESOURCE";
882 static void *find_res(struct mlx4_dev *dev, u64 res_id,
883 enum mlx4_resource type)
885 struct mlx4_priv *priv = mlx4_priv(dev);
887 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
891 static int _get_res(struct mlx4_dev *dev, int slave, u64 res_id,
892 enum mlx4_resource type,
893 void *res, const char *func_name)
895 struct res_common *r;
898 spin_lock_irq(mlx4_tlock(dev));
899 r = find_res(dev, res_id, type);
905 if (r->state == RES_ANY_BUSY) {
907 "%s(%d) trying to get resource %llx of type %s, but it's already taken by %s\n",
908 func_name, slave, res_id, mlx4_resource_type_to_str(type),
914 if (r->owner != slave) {
919 r->from_state = r->state;
920 r->state = RES_ANY_BUSY;
921 r->func_name = func_name;
924 *((struct res_common **)res) = r;
927 spin_unlock_irq(mlx4_tlock(dev));
931 #define get_res(dev, slave, res_id, type, res) \
932 _get_res((dev), (slave), (res_id), (type), (res), __func__)
934 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
935 enum mlx4_resource type,
936 u64 res_id, int *slave)
939 struct res_common *r;
945 spin_lock(mlx4_tlock(dev));
947 r = find_res(dev, id, type);
952 spin_unlock(mlx4_tlock(dev));
957 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
958 enum mlx4_resource type)
960 struct res_common *r;
962 spin_lock_irq(mlx4_tlock(dev));
963 r = find_res(dev, res_id, type);
965 r->state = r->from_state;
968 spin_unlock_irq(mlx4_tlock(dev));
971 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
972 u64 in_param, u64 *out_param, int port);
974 static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
977 struct res_common *r;
978 struct res_counter *counter;
981 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
984 spin_lock_irq(mlx4_tlock(dev));
985 r = find_res(dev, counter_index, RES_COUNTER);
986 if (!r || r->owner != slave) {
989 counter = container_of(r, struct res_counter, com);
991 counter->port = port;
994 spin_unlock_irq(mlx4_tlock(dev));
998 static int handle_unexisting_counter(struct mlx4_dev *dev,
999 struct mlx4_qp_context *qpc, u8 slave,
1002 struct mlx4_priv *priv = mlx4_priv(dev);
1003 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1004 struct res_common *tmp;
1005 struct res_counter *counter;
1006 u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
1009 spin_lock_irq(mlx4_tlock(dev));
1010 list_for_each_entry(tmp,
1011 &tracker->slave_list[slave].res_list[RES_COUNTER],
1013 counter = container_of(tmp, struct res_counter, com);
1014 if (port == counter->port) {
1015 qpc->pri_path.counter_index = counter->com.res_id;
1016 spin_unlock_irq(mlx4_tlock(dev));
1020 spin_unlock_irq(mlx4_tlock(dev));
1022 /* No existing counter, need to allocate a new counter */
1023 err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
1025 if (err == -ENOENT) {
1027 } else if (err && err != -ENOSPC) {
1028 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
1029 __func__, slave, err);
1031 qpc->pri_path.counter_index = counter_idx;
1032 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
1033 __func__, slave, qpc->pri_path.counter_index);
1040 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
1043 if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
1044 return handle_existing_counter(dev, slave, port,
1045 qpc->pri_path.counter_index);
1047 return handle_unexisting_counter(dev, qpc, slave, port);
1050 static struct res_common *alloc_qp_tr(int id)
1054 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1058 ret->com.res_id = id;
1059 ret->com.state = RES_QP_RESERVED;
1060 ret->local_qpn = id;
1061 INIT_LIST_HEAD(&ret->mcg_list);
1062 spin_lock_init(&ret->mcg_spl);
1063 atomic_set(&ret->ref_count, 0);
1068 static struct res_common *alloc_mtt_tr(int id, int order)
1070 struct res_mtt *ret;
1072 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1076 ret->com.res_id = id;
1078 ret->com.state = RES_MTT_ALLOCATED;
1079 atomic_set(&ret->ref_count, 0);
1084 static struct res_common *alloc_mpt_tr(int id, int key)
1086 struct res_mpt *ret;
1088 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1092 ret->com.res_id = id;
1093 ret->com.state = RES_MPT_RESERVED;
1099 static struct res_common *alloc_eq_tr(int id)
1103 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1107 ret->com.res_id = id;
1108 ret->com.state = RES_EQ_RESERVED;
1113 static struct res_common *alloc_cq_tr(int id)
1117 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1121 ret->com.res_id = id;
1122 ret->com.state = RES_CQ_ALLOCATED;
1123 atomic_set(&ret->ref_count, 0);
1128 static struct res_common *alloc_srq_tr(int id)
1130 struct res_srq *ret;
1132 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1136 ret->com.res_id = id;
1137 ret->com.state = RES_SRQ_ALLOCATED;
1138 atomic_set(&ret->ref_count, 0);
1143 static struct res_common *alloc_counter_tr(int id, int port)
1145 struct res_counter *ret;
1147 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1151 ret->com.res_id = id;
1152 ret->com.state = RES_COUNTER_ALLOCATED;
1158 static struct res_common *alloc_xrcdn_tr(int id)
1160 struct res_xrcdn *ret;
1162 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1166 ret->com.res_id = id;
1167 ret->com.state = RES_XRCD_ALLOCATED;
1172 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1174 struct res_fs_rule *ret;
1176 ret = kzalloc(sizeof(*ret), GFP_KERNEL);
1180 ret->com.res_id = id;
1181 ret->com.state = RES_FS_RULE_ALLOCATED;
1186 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
1189 struct res_common *ret;
1193 ret = alloc_qp_tr(id);
1196 ret = alloc_mpt_tr(id, extra);
1199 ret = alloc_mtt_tr(id, extra);
1202 ret = alloc_eq_tr(id);
1205 ret = alloc_cq_tr(id);
1208 ret = alloc_srq_tr(id);
1211 pr_err("implementation missing\n");
1214 ret = alloc_counter_tr(id, extra);
1217 ret = alloc_xrcdn_tr(id);
1220 ret = alloc_fs_rule_tr(id, extra);
1231 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1232 struct mlx4_counter *data)
1234 struct mlx4_priv *priv = mlx4_priv(dev);
1235 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1236 struct res_common *tmp;
1237 struct res_counter *counter;
1241 memset(data, 0, sizeof(*data));
1243 counters_arr = kmalloc_array(dev->caps.max_counters,
1244 sizeof(*counters_arr), GFP_KERNEL);
1248 spin_lock_irq(mlx4_tlock(dev));
1249 list_for_each_entry(tmp,
1250 &tracker->slave_list[slave].res_list[RES_COUNTER],
1252 counter = container_of(tmp, struct res_counter, com);
1253 if (counter->port == port) {
1254 counters_arr[i] = (int)tmp->res_id;
1258 spin_unlock_irq(mlx4_tlock(dev));
1259 counters_arr[i] = -1;
1263 while (counters_arr[i] != -1) {
1264 err = mlx4_get_counter_stats(dev, counters_arr[i], data,
1267 memset(data, 0, sizeof(*data));
1274 kfree(counters_arr);
1278 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1279 enum mlx4_resource type, int extra)
1283 struct mlx4_priv *priv = mlx4_priv(dev);
1284 struct res_common **res_arr;
1285 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1286 struct rb_root *root = &tracker->res_tree[type];
1288 res_arr = kcalloc(count, sizeof(*res_arr), GFP_KERNEL);
1292 for (i = 0; i < count; ++i) {
1293 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1295 for (--i; i >= 0; --i)
1303 spin_lock_irq(mlx4_tlock(dev));
1304 for (i = 0; i < count; ++i) {
1305 if (find_res(dev, base + i, type)) {
1309 err = res_tracker_insert(root, res_arr[i]);
1312 list_add_tail(&res_arr[i]->list,
1313 &tracker->slave_list[slave].res_list[type]);
1315 spin_unlock_irq(mlx4_tlock(dev));
1321 for (--i; i >= 0; --i) {
1322 rb_erase(&res_arr[i]->node, root);
1323 list_del_init(&res_arr[i]->list);
1326 spin_unlock_irq(mlx4_tlock(dev));
1328 for (i = 0; i < count; ++i)
1336 static int remove_qp_ok(struct res_qp *res)
1338 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1339 !list_empty(&res->mcg_list)) {
1340 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1341 res->com.state, atomic_read(&res->ref_count));
1343 } else if (res->com.state != RES_QP_RESERVED) {
1350 static int remove_mtt_ok(struct res_mtt *res, int order)
1352 if (res->com.state == RES_MTT_BUSY ||
1353 atomic_read(&res->ref_count)) {
1354 pr_devel("%s-%d: state %s, ref_count %d\n",
1356 mtt_states_str(res->com.state),
1357 atomic_read(&res->ref_count));
1359 } else if (res->com.state != RES_MTT_ALLOCATED)
1361 else if (res->order != order)
1367 static int remove_mpt_ok(struct res_mpt *res)
1369 if (res->com.state == RES_MPT_BUSY)
1371 else if (res->com.state != RES_MPT_RESERVED)
1377 static int remove_eq_ok(struct res_eq *res)
1379 if (res->com.state == RES_MPT_BUSY)
1381 else if (res->com.state != RES_MPT_RESERVED)
1387 static int remove_counter_ok(struct res_counter *res)
1389 if (res->com.state == RES_COUNTER_BUSY)
1391 else if (res->com.state != RES_COUNTER_ALLOCATED)
1397 static int remove_xrcdn_ok(struct res_xrcdn *res)
1399 if (res->com.state == RES_XRCD_BUSY)
1401 else if (res->com.state != RES_XRCD_ALLOCATED)
1407 static int remove_fs_rule_ok(struct res_fs_rule *res)
1409 if (res->com.state == RES_FS_RULE_BUSY)
1411 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1417 static int remove_cq_ok(struct res_cq *res)
1419 if (res->com.state == RES_CQ_BUSY)
1421 else if (res->com.state != RES_CQ_ALLOCATED)
1427 static int remove_srq_ok(struct res_srq *res)
1429 if (res->com.state == RES_SRQ_BUSY)
1431 else if (res->com.state != RES_SRQ_ALLOCATED)
1437 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1441 return remove_qp_ok((struct res_qp *)res);
1443 return remove_cq_ok((struct res_cq *)res);
1445 return remove_srq_ok((struct res_srq *)res);
1447 return remove_mpt_ok((struct res_mpt *)res);
1449 return remove_mtt_ok((struct res_mtt *)res, extra);
1453 return remove_eq_ok((struct res_eq *)res);
1455 return remove_counter_ok((struct res_counter *)res);
1457 return remove_xrcdn_ok((struct res_xrcdn *)res);
1459 return remove_fs_rule_ok((struct res_fs_rule *)res);
1465 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1466 enum mlx4_resource type, int extra)
1470 struct mlx4_priv *priv = mlx4_priv(dev);
1471 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1472 struct res_common *r;
1474 spin_lock_irq(mlx4_tlock(dev));
1475 for (i = base; i < base + count; ++i) {
1476 r = res_tracker_lookup(&tracker->res_tree[type], i);
1481 if (r->owner != slave) {
1485 err = remove_ok(r, type, extra);
1490 for (i = base; i < base + count; ++i) {
1491 r = res_tracker_lookup(&tracker->res_tree[type], i);
1492 rb_erase(&r->node, &tracker->res_tree[type]);
1499 spin_unlock_irq(mlx4_tlock(dev));
1504 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1505 enum res_qp_states state, struct res_qp **qp,
1508 struct mlx4_priv *priv = mlx4_priv(dev);
1509 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1513 spin_lock_irq(mlx4_tlock(dev));
1514 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
1517 else if (r->com.owner != slave)
1522 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
1523 __func__, r->com.res_id);
1527 case RES_QP_RESERVED:
1528 if (r->com.state == RES_QP_MAPPED && !alloc)
1531 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
1536 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1537 r->com.state == RES_QP_HW)
1540 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
1548 if (r->com.state != RES_QP_MAPPED)
1556 r->com.from_state = r->com.state;
1557 r->com.to_state = state;
1558 r->com.state = RES_QP_BUSY;
1564 spin_unlock_irq(mlx4_tlock(dev));
1569 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1570 enum res_mpt_states state, struct res_mpt **mpt)
1572 struct mlx4_priv *priv = mlx4_priv(dev);
1573 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1577 spin_lock_irq(mlx4_tlock(dev));
1578 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
1581 else if (r->com.owner != slave)
1589 case RES_MPT_RESERVED:
1590 if (r->com.state != RES_MPT_MAPPED)
1594 case RES_MPT_MAPPED:
1595 if (r->com.state != RES_MPT_RESERVED &&
1596 r->com.state != RES_MPT_HW)
1601 if (r->com.state != RES_MPT_MAPPED)
1609 r->com.from_state = r->com.state;
1610 r->com.to_state = state;
1611 r->com.state = RES_MPT_BUSY;
1617 spin_unlock_irq(mlx4_tlock(dev));
1622 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1623 enum res_eq_states state, struct res_eq **eq)
1625 struct mlx4_priv *priv = mlx4_priv(dev);
1626 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1630 spin_lock_irq(mlx4_tlock(dev));
1631 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1634 else if (r->com.owner != slave)
1642 case RES_EQ_RESERVED:
1643 if (r->com.state != RES_EQ_HW)
1648 if (r->com.state != RES_EQ_RESERVED)
1657 r->com.from_state = r->com.state;
1658 r->com.to_state = state;
1659 r->com.state = RES_EQ_BUSY;
1663 spin_unlock_irq(mlx4_tlock(dev));
1671 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1672 enum res_cq_states state, struct res_cq **cq)
1674 struct mlx4_priv *priv = mlx4_priv(dev);
1675 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1679 spin_lock_irq(mlx4_tlock(dev));
1680 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1683 } else if (r->com.owner != slave) {
1685 } else if (state == RES_CQ_ALLOCATED) {
1686 if (r->com.state != RES_CQ_HW)
1688 else if (atomic_read(&r->ref_count))
1692 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1699 r->com.from_state = r->com.state;
1700 r->com.to_state = state;
1701 r->com.state = RES_CQ_BUSY;
1706 spin_unlock_irq(mlx4_tlock(dev));
1711 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1712 enum res_srq_states state, struct res_srq **srq)
1714 struct mlx4_priv *priv = mlx4_priv(dev);
1715 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1719 spin_lock_irq(mlx4_tlock(dev));
1720 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1723 } else if (r->com.owner != slave) {
1725 } else if (state == RES_SRQ_ALLOCATED) {
1726 if (r->com.state != RES_SRQ_HW)
1728 else if (atomic_read(&r->ref_count))
1730 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1735 r->com.from_state = r->com.state;
1736 r->com.to_state = state;
1737 r->com.state = RES_SRQ_BUSY;
1742 spin_unlock_irq(mlx4_tlock(dev));
1747 static void res_abort_move(struct mlx4_dev *dev, int slave,
1748 enum mlx4_resource type, int id)
1750 struct mlx4_priv *priv = mlx4_priv(dev);
1751 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1752 struct res_common *r;
1754 spin_lock_irq(mlx4_tlock(dev));
1755 r = res_tracker_lookup(&tracker->res_tree[type], id);
1756 if (r && (r->owner == slave))
1757 r->state = r->from_state;
1758 spin_unlock_irq(mlx4_tlock(dev));
1761 static void res_end_move(struct mlx4_dev *dev, int slave,
1762 enum mlx4_resource type, int id)
1764 struct mlx4_priv *priv = mlx4_priv(dev);
1765 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1766 struct res_common *r;
1768 spin_lock_irq(mlx4_tlock(dev));
1769 r = res_tracker_lookup(&tracker->res_tree[type], id);
1770 if (r && (r->owner == slave))
1771 r->state = r->to_state;
1772 spin_unlock_irq(mlx4_tlock(dev));
1775 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1777 return mlx4_is_qp_reserved(dev, qpn) &&
1778 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1781 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1783 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1786 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1787 u64 in_param, u64 *out_param)
1797 case RES_OP_RESERVE:
1798 count = get_param_l(&in_param) & 0xffffff;
1799 /* Turn off all unsupported QP allocation flags that the
1800 * slave tries to set.
1802 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
1803 align = get_param_h(&in_param);
1804 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
1808 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
1810 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1814 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1816 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1817 __mlx4_qp_release_range(dev, base, count);
1820 set_param_l(out_param, base);
1822 case RES_OP_MAP_ICM:
1823 qpn = get_param_l(&in_param) & 0x7fffff;
1824 if (valid_reserved(dev, slave, qpn)) {
1825 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1830 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1835 if (!fw_reserved(dev, qpn)) {
1836 err = __mlx4_qp_alloc_icm(dev, qpn);
1838 res_abort_move(dev, slave, RES_QP, qpn);
1843 res_end_move(dev, slave, RES_QP, qpn);
1853 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1854 u64 in_param, u64 *out_param)
1860 if (op != RES_OP_RESERVE_AND_MAP)
1863 order = get_param_l(&in_param);
1865 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1869 base = __mlx4_alloc_mtt_range(dev, order);
1871 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1875 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1877 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1878 __mlx4_free_mtt_range(dev, base, order);
1880 set_param_l(out_param, base);
1886 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1887 u64 in_param, u64 *out_param)
1892 struct res_mpt *mpt;
1895 case RES_OP_RESERVE:
1896 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1900 index = __mlx4_mpt_reserve(dev);
1902 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1905 id = index & mpt_mask(dev);
1907 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1909 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1910 __mlx4_mpt_release(dev, index);
1913 set_param_l(out_param, index);
1915 case RES_OP_MAP_ICM:
1916 index = get_param_l(&in_param);
1917 id = index & mpt_mask(dev);
1918 err = mr_res_start_move_to(dev, slave, id,
1919 RES_MPT_MAPPED, &mpt);
1923 err = __mlx4_mpt_alloc_icm(dev, mpt->key);
1925 res_abort_move(dev, slave, RES_MPT, id);
1929 res_end_move(dev, slave, RES_MPT, id);
1935 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1936 u64 in_param, u64 *out_param)
1942 case RES_OP_RESERVE_AND_MAP:
1943 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
1947 err = __mlx4_cq_alloc_icm(dev, &cqn);
1949 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1953 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1955 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1956 __mlx4_cq_free_icm(dev, cqn);
1960 set_param_l(out_param, cqn);
1970 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1971 u64 in_param, u64 *out_param)
1977 case RES_OP_RESERVE_AND_MAP:
1978 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
1982 err = __mlx4_srq_alloc_icm(dev, &srqn);
1984 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1988 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1990 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1991 __mlx4_srq_free_icm(dev, srqn);
1995 set_param_l(out_param, srqn);
2005 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
2006 u8 smac_index, u64 *mac)
2008 struct mlx4_priv *priv = mlx4_priv(dev);
2009 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2010 struct list_head *mac_list =
2011 &tracker->slave_list[slave].res_list[RES_MAC];
2012 struct mac_res *res, *tmp;
2014 list_for_each_entry_safe(res, tmp, mac_list, list) {
2015 if (res->smac_index == smac_index && res->port == (u8) port) {
2023 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
2025 struct mlx4_priv *priv = mlx4_priv(dev);
2026 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2027 struct list_head *mac_list =
2028 &tracker->slave_list[slave].res_list[RES_MAC];
2029 struct mac_res *res, *tmp;
2031 list_for_each_entry_safe(res, tmp, mac_list, list) {
2032 if (res->mac == mac && res->port == (u8) port) {
2033 /* mac found. update ref count */
2039 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
2041 res = kzalloc(sizeof(*res), GFP_KERNEL);
2043 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
2047 res->port = (u8) port;
2048 res->smac_index = smac_index;
2050 list_add_tail(&res->list,
2051 &tracker->slave_list[slave].res_list[RES_MAC]);
2055 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
2058 struct mlx4_priv *priv = mlx4_priv(dev);
2059 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2060 struct list_head *mac_list =
2061 &tracker->slave_list[slave].res_list[RES_MAC];
2062 struct mac_res *res, *tmp;
2064 list_for_each_entry_safe(res, tmp, mac_list, list) {
2065 if (res->mac == mac && res->port == (u8) port) {
2066 if (!--res->ref_count) {
2067 list_del(&res->list);
2068 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
2076 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
2078 struct mlx4_priv *priv = mlx4_priv(dev);
2079 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2080 struct list_head *mac_list =
2081 &tracker->slave_list[slave].res_list[RES_MAC];
2082 struct mac_res *res, *tmp;
2085 list_for_each_entry_safe(res, tmp, mac_list, list) {
2086 list_del(&res->list);
2087 /* dereference the mac the num times the slave referenced it */
2088 for (i = 0; i < res->ref_count; i++)
2089 __mlx4_unregister_mac(dev, res->port, res->mac);
2090 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
2095 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2096 u64 in_param, u64 *out_param, int in_port)
2103 if (op != RES_OP_RESERVE_AND_MAP)
2106 port = !in_port ? get_param_l(out_param) : in_port;
2107 port = mlx4_slave_convert_port(
2114 err = __mlx4_register_mac(dev, port, mac);
2117 set_param_l(out_param, err);
2122 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
2124 __mlx4_unregister_mac(dev, port, mac);
2129 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2130 int port, int vlan_index)
2132 struct mlx4_priv *priv = mlx4_priv(dev);
2133 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2134 struct list_head *vlan_list =
2135 &tracker->slave_list[slave].res_list[RES_VLAN];
2136 struct vlan_res *res, *tmp;
2138 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2139 if (res->vlan == vlan && res->port == (u8) port) {
2140 /* vlan found. update ref count */
2146 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
2148 res = kzalloc(sizeof(*res), GFP_KERNEL);
2150 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
2154 res->port = (u8) port;
2155 res->vlan_index = vlan_index;
2157 list_add_tail(&res->list,
2158 &tracker->slave_list[slave].res_list[RES_VLAN]);
2163 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2166 struct mlx4_priv *priv = mlx4_priv(dev);
2167 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2168 struct list_head *vlan_list =
2169 &tracker->slave_list[slave].res_list[RES_VLAN];
2170 struct vlan_res *res, *tmp;
2172 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2173 if (res->vlan == vlan && res->port == (u8) port) {
2174 if (!--res->ref_count) {
2175 list_del(&res->list);
2176 mlx4_release_resource(dev, slave, RES_VLAN,
2185 static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
2187 struct mlx4_priv *priv = mlx4_priv(dev);
2188 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2189 struct list_head *vlan_list =
2190 &tracker->slave_list[slave].res_list[RES_VLAN];
2191 struct vlan_res *res, *tmp;
2194 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2195 list_del(&res->list);
2196 /* dereference the vlan the num times the slave referenced it */
2197 for (i = 0; i < res->ref_count; i++)
2198 __mlx4_unregister_vlan(dev, res->port, res->vlan);
2199 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
2204 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2205 u64 in_param, u64 *out_param, int in_port)
2207 struct mlx4_priv *priv = mlx4_priv(dev);
2208 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2214 port = !in_port ? get_param_l(out_param) : in_port;
2216 if (!port || op != RES_OP_RESERVE_AND_MAP)
2219 port = mlx4_slave_convert_port(
2224 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
2225 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
2226 slave_state[slave].old_vlan_api = true;
2230 vlan = (u16) in_param;
2232 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
2234 set_param_l(out_param, (u32) vlan_index);
2235 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2237 __mlx4_unregister_vlan(dev, port, vlan);
2242 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2243 u64 in_param, u64 *out_param, int port)
2248 if (op != RES_OP_RESERVE)
2251 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
2255 err = __mlx4_counter_alloc(dev, &index);
2257 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2261 err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
2263 __mlx4_counter_free(dev, index);
2264 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2266 set_param_l(out_param, index);
2272 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2273 u64 in_param, u64 *out_param)
2278 if (op != RES_OP_RESERVE)
2281 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2285 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2287 __mlx4_xrcd_free(dev, xrcdn);
2289 set_param_l(out_param, xrcdn);
2294 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2295 struct mlx4_vhcr *vhcr,
2296 struct mlx4_cmd_mailbox *inbox,
2297 struct mlx4_cmd_mailbox *outbox,
2298 struct mlx4_cmd_info *cmd)
2301 int alop = vhcr->op_modifier;
2303 switch (vhcr->in_modifier & 0xFF) {
2305 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2306 vhcr->in_param, &vhcr->out_param);
2310 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2311 vhcr->in_param, &vhcr->out_param);
2315 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2316 vhcr->in_param, &vhcr->out_param);
2320 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2321 vhcr->in_param, &vhcr->out_param);
2325 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2326 vhcr->in_param, &vhcr->out_param);
2330 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
2331 vhcr->in_param, &vhcr->out_param,
2332 (vhcr->in_modifier >> 8) & 0xFF);
2336 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
2337 vhcr->in_param, &vhcr->out_param,
2338 (vhcr->in_modifier >> 8) & 0xFF);
2342 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2343 vhcr->in_param, &vhcr->out_param, 0);
2347 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2348 vhcr->in_param, &vhcr->out_param);
2359 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2368 case RES_OP_RESERVE:
2369 base = get_param_l(&in_param) & 0x7fffff;
2370 count = get_param_h(&in_param);
2371 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2374 mlx4_release_resource(dev, slave, RES_QP, count, 0);
2375 __mlx4_qp_release_range(dev, base, count);
2377 case RES_OP_MAP_ICM:
2378 qpn = get_param_l(&in_param) & 0x7fffff;
2379 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2384 if (!fw_reserved(dev, qpn))
2385 __mlx4_qp_free_icm(dev, qpn);
2387 res_end_move(dev, slave, RES_QP, qpn);
2389 if (valid_reserved(dev, slave, qpn))
2390 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2399 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2400 u64 in_param, u64 *out_param)
2406 if (op != RES_OP_RESERVE_AND_MAP)
2409 base = get_param_l(&in_param);
2410 order = get_param_h(&in_param);
2411 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
2413 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
2414 __mlx4_free_mtt_range(dev, base, order);
2419 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2425 struct res_mpt *mpt;
2428 case RES_OP_RESERVE:
2429 index = get_param_l(&in_param);
2430 id = index & mpt_mask(dev);
2431 err = get_res(dev, slave, id, RES_MPT, &mpt);
2435 put_res(dev, slave, id, RES_MPT);
2437 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2440 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
2441 __mlx4_mpt_release(dev, index);
2443 case RES_OP_MAP_ICM:
2444 index = get_param_l(&in_param);
2445 id = index & mpt_mask(dev);
2446 err = mr_res_start_move_to(dev, slave, id,
2447 RES_MPT_RESERVED, &mpt);
2451 __mlx4_mpt_free_icm(dev, mpt->key);
2452 res_end_move(dev, slave, RES_MPT, id);
2461 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2462 u64 in_param, u64 *out_param)
2468 case RES_OP_RESERVE_AND_MAP:
2469 cqn = get_param_l(&in_param);
2470 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2474 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
2475 __mlx4_cq_free_icm(dev, cqn);
2486 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2487 u64 in_param, u64 *out_param)
2493 case RES_OP_RESERVE_AND_MAP:
2494 srqn = get_param_l(&in_param);
2495 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2499 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
2500 __mlx4_srq_free_icm(dev, srqn);
2511 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2512 u64 in_param, u64 *out_param, int in_port)
2518 case RES_OP_RESERVE_AND_MAP:
2519 port = !in_port ? get_param_l(out_param) : in_port;
2520 port = mlx4_slave_convert_port(
2525 mac_del_from_slave(dev, slave, in_param, port);
2526 __mlx4_unregister_mac(dev, port, in_param);
2537 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2538 u64 in_param, u64 *out_param, int port)
2540 struct mlx4_priv *priv = mlx4_priv(dev);
2541 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2544 port = mlx4_slave_convert_port(
2550 case RES_OP_RESERVE_AND_MAP:
2551 if (slave_state[slave].old_vlan_api)
2555 vlan_del_from_slave(dev, slave, in_param, port);
2556 __mlx4_unregister_vlan(dev, port, in_param);
2566 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2567 u64 in_param, u64 *out_param)
2572 if (op != RES_OP_RESERVE)
2575 index = get_param_l(&in_param);
2576 if (index == MLX4_SINK_COUNTER_INDEX(dev))
2579 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2583 __mlx4_counter_free(dev, index);
2584 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2589 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2590 u64 in_param, u64 *out_param)
2595 if (op != RES_OP_RESERVE)
2598 xrcdn = get_param_l(&in_param);
2599 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2603 __mlx4_xrcd_free(dev, xrcdn);
2608 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2609 struct mlx4_vhcr *vhcr,
2610 struct mlx4_cmd_mailbox *inbox,
2611 struct mlx4_cmd_mailbox *outbox,
2612 struct mlx4_cmd_info *cmd)
2615 int alop = vhcr->op_modifier;
2617 switch (vhcr->in_modifier & 0xFF) {
2619 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2624 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2625 vhcr->in_param, &vhcr->out_param);
2629 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2634 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2635 vhcr->in_param, &vhcr->out_param);
2639 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2640 vhcr->in_param, &vhcr->out_param);
2644 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
2645 vhcr->in_param, &vhcr->out_param,
2646 (vhcr->in_modifier >> 8) & 0xFF);
2650 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
2651 vhcr->in_param, &vhcr->out_param,
2652 (vhcr->in_modifier >> 8) & 0xFF);
2656 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2657 vhcr->in_param, &vhcr->out_param);
2661 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2662 vhcr->in_param, &vhcr->out_param);
2671 /* ugly but other choices are uglier */
2672 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2674 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2677 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
2679 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
2682 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2684 return be32_to_cpu(mpt->mtt_sz);
2687 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2689 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2692 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2694 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2697 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2699 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2702 static int mr_is_region(struct mlx4_mpt_entry *mpt)
2704 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2707 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
2709 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2712 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
2714 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2717 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2719 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2720 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2721 int log_sq_sride = qpc->sq_size_stride & 7;
2722 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2723 int log_rq_stride = qpc->rq_size_stride & 7;
2724 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2725 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
2726 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2727 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
2732 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2735 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2736 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2737 total_mem = sq_size + rq_size;
2738 tot = (total_mem + (page_offset << 6)) >> page_shift;
2739 total_pages = !tot ? 1 : roundup_pow_of_two(tot);
2744 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2745 int size, struct res_mtt *mtt)
2747 int res_start = mtt->com.res_id;
2748 int res_size = (1 << mtt->order);
2750 if (start < res_start || start + size > res_start + res_size)
2755 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2756 struct mlx4_vhcr *vhcr,
2757 struct mlx4_cmd_mailbox *inbox,
2758 struct mlx4_cmd_mailbox *outbox,
2759 struct mlx4_cmd_info *cmd)
2762 int index = vhcr->in_modifier;
2763 struct res_mtt *mtt;
2764 struct res_mpt *mpt = NULL;
2765 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
2771 id = index & mpt_mask(dev);
2772 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2776 /* Disable memory windows for VFs. */
2777 if (!mr_is_region(inbox->buf)) {
2782 /* Make sure that the PD bits related to the slave id are zeros. */
2783 pd = mr_get_pd(inbox->buf);
2784 pd_slave = (pd >> 17) & 0x7f;
2785 if (pd_slave != 0 && --pd_slave != slave) {
2790 if (mr_is_fmr(inbox->buf)) {
2791 /* FMR and Bind Enable are forbidden in slave devices. */
2792 if (mr_is_bind_enabled(inbox->buf)) {
2796 /* FMR and Memory Windows are also forbidden. */
2797 if (!mr_is_region(inbox->buf)) {
2803 phys = mr_phys_mpt(inbox->buf);
2805 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2809 err = check_mtt_range(dev, slave, mtt_base,
2810 mr_get_mtt_size(inbox->buf), mtt);
2817 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2822 atomic_inc(&mtt->ref_count);
2823 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2826 res_end_move(dev, slave, RES_MPT, id);
2831 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2833 res_abort_move(dev, slave, RES_MPT, id);
2838 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2839 struct mlx4_vhcr *vhcr,
2840 struct mlx4_cmd_mailbox *inbox,
2841 struct mlx4_cmd_mailbox *outbox,
2842 struct mlx4_cmd_info *cmd)
2845 int index = vhcr->in_modifier;
2846 struct res_mpt *mpt;
2849 id = index & mpt_mask(dev);
2850 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2854 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2859 atomic_dec(&mpt->mtt->ref_count);
2861 res_end_move(dev, slave, RES_MPT, id);
2865 res_abort_move(dev, slave, RES_MPT, id);
2870 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2871 struct mlx4_vhcr *vhcr,
2872 struct mlx4_cmd_mailbox *inbox,
2873 struct mlx4_cmd_mailbox *outbox,
2874 struct mlx4_cmd_info *cmd)
2877 int index = vhcr->in_modifier;
2878 struct res_mpt *mpt;
2881 id = index & mpt_mask(dev);
2882 err = get_res(dev, slave, id, RES_MPT, &mpt);
2886 if (mpt->com.from_state == RES_MPT_MAPPED) {
2887 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2888 * that, the VF must read the MPT. But since the MPT entry memory is not
2889 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2890 * entry contents. To guarantee that the MPT cannot be changed, the driver
2891 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2892 * ownership fofollowing the change. The change here allows the VF to
2893 * perform QUERY_MPT also when the entry is in SW ownership.
2895 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2896 &mlx4_priv(dev)->mr_table.dmpt_table,
2899 if (NULL == mpt_entry || NULL == outbox->buf) {
2904 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2907 } else if (mpt->com.from_state == RES_MPT_HW) {
2908 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2916 put_res(dev, slave, id, RES_MPT);
2920 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2922 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2925 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2927 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2930 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2932 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2935 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2936 struct mlx4_qp_context *context)
2938 u32 qpn = vhcr->in_modifier & 0xffffff;
2941 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2944 /* adjust qkey in qp context */
2945 context->qkey = cpu_to_be32(qkey);
2948 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
2949 struct mlx4_qp_context *qpc,
2950 struct mlx4_cmd_mailbox *inbox);
2952 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2953 struct mlx4_vhcr *vhcr,
2954 struct mlx4_cmd_mailbox *inbox,
2955 struct mlx4_cmd_mailbox *outbox,
2956 struct mlx4_cmd_info *cmd)
2959 int qpn = vhcr->in_modifier & 0x7fffff;
2960 struct res_mtt *mtt;
2962 struct mlx4_qp_context *qpc = inbox->buf + 8;
2963 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2964 int mtt_size = qp_get_mtt_size(qpc);
2967 int rcqn = qp_get_rcqn(qpc);
2968 int scqn = qp_get_scqn(qpc);
2969 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2970 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2971 struct res_srq *srq;
2972 int local_qpn = vhcr->in_modifier & 0xffffff;
2974 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
2978 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2981 qp->local_qpn = local_qpn;
2982 qp->sched_queue = 0;
2984 qp->vlan_control = 0;
2986 qp->pri_path_fl = 0;
2989 qp->qpc_flags = be32_to_cpu(qpc->flags);
2991 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2995 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2999 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
3004 err = get_res(dev, slave, scqn, RES_CQ, &scq);
3011 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3016 adjust_proxy_tun_qkey(dev, vhcr, qpc);
3017 update_pkey_index(dev, slave, inbox);
3018 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3021 atomic_inc(&mtt->ref_count);
3023 atomic_inc(&rcq->ref_count);
3025 atomic_inc(&scq->ref_count);
3029 put_res(dev, slave, scqn, RES_CQ);
3032 atomic_inc(&srq->ref_count);
3033 put_res(dev, slave, srqn, RES_SRQ);
3037 /* Save param3 for dynamic changes from VST back to VGT */
3038 qp->param3 = qpc->param3;
3039 put_res(dev, slave, rcqn, RES_CQ);
3040 put_res(dev, slave, mtt_base, RES_MTT);
3041 res_end_move(dev, slave, RES_QP, qpn);
3047 put_res(dev, slave, srqn, RES_SRQ);
3050 put_res(dev, slave, scqn, RES_CQ);
3052 put_res(dev, slave, rcqn, RES_CQ);
3054 put_res(dev, slave, mtt_base, RES_MTT);
3056 res_abort_move(dev, slave, RES_QP, qpn);
3061 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
3063 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
3066 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
3068 int log_eq_size = eqc->log_eq_size & 0x1f;
3069 int page_shift = (eqc->log_page_size & 0x3f) + 12;
3071 if (log_eq_size + 5 < page_shift)
3074 return 1 << (log_eq_size + 5 - page_shift);
3077 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
3079 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
3082 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
3084 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
3085 int page_shift = (cqc->log_page_size & 0x3f) + 12;
3087 if (log_cq_size + 5 < page_shift)
3090 return 1 << (log_cq_size + 5 - page_shift);
3093 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3094 struct mlx4_vhcr *vhcr,
3095 struct mlx4_cmd_mailbox *inbox,
3096 struct mlx4_cmd_mailbox *outbox,
3097 struct mlx4_cmd_info *cmd)
3100 int eqn = vhcr->in_modifier;
3101 int res_id = (slave << 10) | eqn;
3102 struct mlx4_eq_context *eqc = inbox->buf;
3103 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
3104 int mtt_size = eq_get_mtt_size(eqc);
3106 struct res_mtt *mtt;
3108 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3111 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
3115 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3119 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
3123 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3127 atomic_inc(&mtt->ref_count);
3129 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3130 res_end_move(dev, slave, RES_EQ, res_id);
3134 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3136 res_abort_move(dev, slave, RES_EQ, res_id);
3138 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3142 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
3143 struct mlx4_vhcr *vhcr,
3144 struct mlx4_cmd_mailbox *inbox,
3145 struct mlx4_cmd_mailbox *outbox,
3146 struct mlx4_cmd_info *cmd)
3149 u8 get = vhcr->op_modifier;
3154 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3159 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
3160 int len, struct res_mtt **res)
3162 struct mlx4_priv *priv = mlx4_priv(dev);
3163 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3164 struct res_mtt *mtt;
3167 spin_lock_irq(mlx4_tlock(dev));
3168 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
3170 if (!check_mtt_range(dev, slave, start, len, mtt)) {
3172 mtt->com.from_state = mtt->com.state;
3173 mtt->com.state = RES_MTT_BUSY;
3178 spin_unlock_irq(mlx4_tlock(dev));
3183 static int verify_qp_parameters(struct mlx4_dev *dev,
3184 struct mlx4_vhcr *vhcr,
3185 struct mlx4_cmd_mailbox *inbox,
3186 enum qp_transition transition, u8 slave)
3190 struct mlx4_qp_context *qp_ctx;
3191 enum mlx4_qp_optpar optpar;
3195 qp_ctx = inbox->buf + 8;
3196 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
3197 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
3199 if (slave != mlx4_master_func_num(dev)) {
3200 qp_ctx->params2 &= ~cpu_to_be32(MLX4_QP_BIT_FPP);
3201 /* setting QP rate-limit is disallowed for VFs */
3202 if (qp_ctx->rate_limit_params)
3208 case MLX4_QP_ST_XRC:
3210 switch (transition) {
3211 case QP_TRANS_INIT2RTR:
3212 case QP_TRANS_RTR2RTS:
3213 case QP_TRANS_RTS2RTS:
3214 case QP_TRANS_SQD2SQD:
3215 case QP_TRANS_SQD2RTS:
3216 if (slave != mlx4_master_func_num(dev)) {
3217 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
3218 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3219 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3220 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3223 if (qp_ctx->pri_path.mgid_index >= num_gids)
3226 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3227 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
3228 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3229 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3232 if (qp_ctx->alt_path.mgid_index >= num_gids)
3242 case MLX4_QP_ST_MLX:
3243 qpn = vhcr->in_modifier & 0x7fffff;
3244 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3245 if (transition == QP_TRANS_INIT2RTR &&
3246 slave != mlx4_master_func_num(dev) &&
3247 mlx4_is_qp_reserved(dev, qpn) &&
3248 !mlx4_vf_smi_enabled(dev, slave, port)) {
3249 /* only enabled VFs may create MLX proxy QPs */
3250 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
3251 __func__, slave, port);
3263 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3264 struct mlx4_vhcr *vhcr,
3265 struct mlx4_cmd_mailbox *inbox,
3266 struct mlx4_cmd_mailbox *outbox,
3267 struct mlx4_cmd_info *cmd)
3269 struct mlx4_mtt mtt;
3270 __be64 *page_list = inbox->buf;
3271 u64 *pg_list = (u64 *)page_list;
3273 struct res_mtt *rmtt = NULL;
3274 int start = be64_to_cpu(page_list[0]);
3275 int npages = vhcr->in_modifier;
3278 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3282 /* Call the SW implementation of write_mtt:
3283 * - Prepare a dummy mtt struct
3284 * - Translate inbox contents to simple addresses in host endianness */
3285 mtt.offset = 0; /* TBD this is broken but I don't handle it since
3286 we don't really use it */
3289 for (i = 0; i < npages; ++i)
3290 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3292 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3293 ((u64 *)page_list + 2));
3296 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3301 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3302 struct mlx4_vhcr *vhcr,
3303 struct mlx4_cmd_mailbox *inbox,
3304 struct mlx4_cmd_mailbox *outbox,
3305 struct mlx4_cmd_info *cmd)
3307 int eqn = vhcr->in_modifier;
3308 int res_id = eqn | (slave << 10);
3312 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3316 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3320 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3324 atomic_dec(&eq->mtt->ref_count);
3325 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3326 res_end_move(dev, slave, RES_EQ, res_id);
3327 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3332 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3334 res_abort_move(dev, slave, RES_EQ, res_id);
3339 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3341 struct mlx4_priv *priv = mlx4_priv(dev);
3342 struct mlx4_slave_event_eq_info *event_eq;
3343 struct mlx4_cmd_mailbox *mailbox;
3344 u32 in_modifier = 0;
3349 if (!priv->mfunc.master.slave_state)
3352 /* check for slave valid, slave not PF, and slave active */
3353 if (slave < 0 || slave > dev->persist->num_vfs ||
3354 slave == dev->caps.function ||
3355 !priv->mfunc.master.slave_state[slave].active)
3358 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
3360 /* Create the event only if the slave is registered */
3361 if (event_eq->eqn < 0)
3364 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3365 res_id = (slave << 10) | event_eq->eqn;
3366 err = get_res(dev, slave, res_id, RES_EQ, &req);
3370 if (req->com.from_state != RES_EQ_HW) {
3375 mailbox = mlx4_alloc_cmd_mailbox(dev);
3376 if (IS_ERR(mailbox)) {
3377 err = PTR_ERR(mailbox);
3381 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3383 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3386 memcpy(mailbox->buf, (u8 *) eqe, 28);
3388 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
3390 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3391 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3394 put_res(dev, slave, res_id, RES_EQ);
3395 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3396 mlx4_free_cmd_mailbox(dev, mailbox);
3400 put_res(dev, slave, res_id, RES_EQ);
3403 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3407 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3408 struct mlx4_vhcr *vhcr,
3409 struct mlx4_cmd_mailbox *inbox,
3410 struct mlx4_cmd_mailbox *outbox,
3411 struct mlx4_cmd_info *cmd)
3413 int eqn = vhcr->in_modifier;
3414 int res_id = eqn | (slave << 10);
3418 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3422 if (eq->com.from_state != RES_EQ_HW) {
3427 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3430 put_res(dev, slave, res_id, RES_EQ);
3434 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3435 struct mlx4_vhcr *vhcr,
3436 struct mlx4_cmd_mailbox *inbox,
3437 struct mlx4_cmd_mailbox *outbox,
3438 struct mlx4_cmd_info *cmd)
3441 int cqn = vhcr->in_modifier;
3442 struct mlx4_cq_context *cqc = inbox->buf;
3443 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3444 struct res_cq *cq = NULL;
3445 struct res_mtt *mtt;
3447 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3450 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3453 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3456 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3459 atomic_inc(&mtt->ref_count);
3461 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3462 res_end_move(dev, slave, RES_CQ, cqn);
3466 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3468 res_abort_move(dev, slave, RES_CQ, cqn);
3472 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3473 struct mlx4_vhcr *vhcr,
3474 struct mlx4_cmd_mailbox *inbox,
3475 struct mlx4_cmd_mailbox *outbox,
3476 struct mlx4_cmd_info *cmd)
3479 int cqn = vhcr->in_modifier;
3480 struct res_cq *cq = NULL;
3482 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3485 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3488 atomic_dec(&cq->mtt->ref_count);
3489 res_end_move(dev, slave, RES_CQ, cqn);
3493 res_abort_move(dev, slave, RES_CQ, cqn);
3497 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3498 struct mlx4_vhcr *vhcr,
3499 struct mlx4_cmd_mailbox *inbox,
3500 struct mlx4_cmd_mailbox *outbox,
3501 struct mlx4_cmd_info *cmd)
3503 int cqn = vhcr->in_modifier;
3507 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3511 if (cq->com.from_state != RES_CQ_HW)
3514 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3516 put_res(dev, slave, cqn, RES_CQ);
3521 static int handle_resize(struct mlx4_dev *dev, int slave,
3522 struct mlx4_vhcr *vhcr,
3523 struct mlx4_cmd_mailbox *inbox,
3524 struct mlx4_cmd_mailbox *outbox,
3525 struct mlx4_cmd_info *cmd,
3529 struct res_mtt *orig_mtt;
3530 struct res_mtt *mtt;
3531 struct mlx4_cq_context *cqc = inbox->buf;
3532 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3534 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3538 if (orig_mtt != cq->mtt) {
3543 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3547 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3550 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3553 atomic_dec(&orig_mtt->ref_count);
3554 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3555 atomic_inc(&mtt->ref_count);
3557 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3561 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3563 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3569 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3570 struct mlx4_vhcr *vhcr,
3571 struct mlx4_cmd_mailbox *inbox,
3572 struct mlx4_cmd_mailbox *outbox,
3573 struct mlx4_cmd_info *cmd)
3575 int cqn = vhcr->in_modifier;
3579 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3583 if (cq->com.from_state != RES_CQ_HW)
3586 if (vhcr->op_modifier == 0) {
3587 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
3591 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3593 put_res(dev, slave, cqn, RES_CQ);
3598 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3600 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3601 int log_rq_stride = srqc->logstride & 7;
3602 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3604 if (log_srq_size + log_rq_stride + 4 < page_shift)
3607 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3610 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3611 struct mlx4_vhcr *vhcr,
3612 struct mlx4_cmd_mailbox *inbox,
3613 struct mlx4_cmd_mailbox *outbox,
3614 struct mlx4_cmd_info *cmd)
3617 int srqn = vhcr->in_modifier;
3618 struct res_mtt *mtt;
3619 struct res_srq *srq = NULL;
3620 struct mlx4_srq_context *srqc = inbox->buf;
3621 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
3623 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3626 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3629 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3632 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3637 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3641 atomic_inc(&mtt->ref_count);
3643 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3644 res_end_move(dev, slave, RES_SRQ, srqn);
3648 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3650 res_abort_move(dev, slave, RES_SRQ, srqn);
3655 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3656 struct mlx4_vhcr *vhcr,
3657 struct mlx4_cmd_mailbox *inbox,
3658 struct mlx4_cmd_mailbox *outbox,
3659 struct mlx4_cmd_info *cmd)
3662 int srqn = vhcr->in_modifier;
3663 struct res_srq *srq = NULL;
3665 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3668 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3671 atomic_dec(&srq->mtt->ref_count);
3673 atomic_dec(&srq->cq->ref_count);
3674 res_end_move(dev, slave, RES_SRQ, srqn);
3679 res_abort_move(dev, slave, RES_SRQ, srqn);
3684 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3685 struct mlx4_vhcr *vhcr,
3686 struct mlx4_cmd_mailbox *inbox,
3687 struct mlx4_cmd_mailbox *outbox,
3688 struct mlx4_cmd_info *cmd)
3691 int srqn = vhcr->in_modifier;
3692 struct res_srq *srq;
3694 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3697 if (srq->com.from_state != RES_SRQ_HW) {
3701 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3703 put_res(dev, slave, srqn, RES_SRQ);
3707 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3708 struct mlx4_vhcr *vhcr,
3709 struct mlx4_cmd_mailbox *inbox,
3710 struct mlx4_cmd_mailbox *outbox,
3711 struct mlx4_cmd_info *cmd)
3714 int srqn = vhcr->in_modifier;
3715 struct res_srq *srq;
3717 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3721 if (srq->com.from_state != RES_SRQ_HW) {
3726 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3728 put_res(dev, slave, srqn, RES_SRQ);
3732 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3733 struct mlx4_vhcr *vhcr,
3734 struct mlx4_cmd_mailbox *inbox,
3735 struct mlx4_cmd_mailbox *outbox,
3736 struct mlx4_cmd_info *cmd)
3739 int qpn = vhcr->in_modifier & 0x7fffff;
3742 err = get_res(dev, slave, qpn, RES_QP, &qp);
3745 if (qp->com.from_state != RES_QP_HW) {
3750 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3752 put_res(dev, slave, qpn, RES_QP);
3756 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3757 struct mlx4_vhcr *vhcr,
3758 struct mlx4_cmd_mailbox *inbox,
3759 struct mlx4_cmd_mailbox *outbox,
3760 struct mlx4_cmd_info *cmd)
3762 struct mlx4_qp_context *context = inbox->buf + 8;
3763 adjust_proxy_tun_qkey(dev, vhcr, context);
3764 update_pkey_index(dev, slave, inbox);
3765 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3768 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3769 struct mlx4_qp_context *qpc,
3770 struct mlx4_cmd_mailbox *inbox)
3772 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3774 int port = mlx4_slave_convert_port(
3775 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3780 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3783 if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
3784 qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
3785 qpc->pri_path.sched_queue = pri_sched_queue;
3788 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3789 port = mlx4_slave_convert_port(
3790 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3794 qpc->alt_path.sched_queue =
3795 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3801 static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3802 struct mlx4_qp_context *qpc,
3803 struct mlx4_cmd_mailbox *inbox)
3807 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3808 u8 sched = *(u8 *)(inbox->buf + 64);
3811 port = (sched >> 6 & 1) + 1;
3812 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3813 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3814 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3820 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3821 struct mlx4_vhcr *vhcr,
3822 struct mlx4_cmd_mailbox *inbox,
3823 struct mlx4_cmd_mailbox *outbox,
3824 struct mlx4_cmd_info *cmd)
3827 struct mlx4_qp_context *qpc = inbox->buf + 8;
3828 int qpn = vhcr->in_modifier & 0x7fffff;
3830 u8 orig_sched_queue;
3831 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3832 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3833 u8 orig_pri_path_fl = qpc->pri_path.fl;
3834 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3835 u8 orig_feup = qpc->pri_path.feup;
3837 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3840 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
3844 if (roce_verify_mac(dev, slave, qpc, inbox))
3847 update_pkey_index(dev, slave, inbox);
3848 update_gid(dev, inbox, (u8)slave);
3849 adjust_proxy_tun_qkey(dev, vhcr, qpc);
3850 orig_sched_queue = qpc->pri_path.sched_queue;
3852 err = get_res(dev, slave, qpn, RES_QP, &qp);
3855 if (qp->com.from_state != RES_QP_HW) {
3860 err = update_vport_qp_param(dev, inbox, slave, qpn);
3864 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3866 /* if no error, save sched queue value passed in by VF. This is
3867 * essentially the QOS value provided by the VF. This will be useful
3868 * if we allow dynamic changes from VST back to VGT
3871 qp->sched_queue = orig_sched_queue;
3872 qp->vlan_control = orig_vlan_control;
3873 qp->fvl_rx = orig_fvl_rx;
3874 qp->pri_path_fl = orig_pri_path_fl;
3875 qp->vlan_index = orig_vlan_index;
3876 qp->feup = orig_feup;
3878 put_res(dev, slave, qpn, RES_QP);
3882 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3883 struct mlx4_vhcr *vhcr,
3884 struct mlx4_cmd_mailbox *inbox,
3885 struct mlx4_cmd_mailbox *outbox,
3886 struct mlx4_cmd_info *cmd)
3889 struct mlx4_qp_context *context = inbox->buf + 8;
3891 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3894 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
3898 update_pkey_index(dev, slave, inbox);
3899 update_gid(dev, inbox, (u8)slave);
3900 adjust_proxy_tun_qkey(dev, vhcr, context);
3901 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3904 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3905 struct mlx4_vhcr *vhcr,
3906 struct mlx4_cmd_mailbox *inbox,
3907 struct mlx4_cmd_mailbox *outbox,
3908 struct mlx4_cmd_info *cmd)
3911 struct mlx4_qp_context *context = inbox->buf + 8;
3913 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3916 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
3920 update_pkey_index(dev, slave, inbox);
3921 update_gid(dev, inbox, (u8)slave);
3922 adjust_proxy_tun_qkey(dev, vhcr, context);
3923 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3927 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3928 struct mlx4_vhcr *vhcr,
3929 struct mlx4_cmd_mailbox *inbox,
3930 struct mlx4_cmd_mailbox *outbox,
3931 struct mlx4_cmd_info *cmd)
3933 struct mlx4_qp_context *context = inbox->buf + 8;
3934 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3937 adjust_proxy_tun_qkey(dev, vhcr, context);
3938 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3941 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3942 struct mlx4_vhcr *vhcr,
3943 struct mlx4_cmd_mailbox *inbox,
3944 struct mlx4_cmd_mailbox *outbox,
3945 struct mlx4_cmd_info *cmd)
3948 struct mlx4_qp_context *context = inbox->buf + 8;
3950 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3953 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
3957 adjust_proxy_tun_qkey(dev, vhcr, context);
3958 update_gid(dev, inbox, (u8)slave);
3959 update_pkey_index(dev, slave, inbox);
3960 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3963 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3964 struct mlx4_vhcr *vhcr,
3965 struct mlx4_cmd_mailbox *inbox,
3966 struct mlx4_cmd_mailbox *outbox,
3967 struct mlx4_cmd_info *cmd)
3970 struct mlx4_qp_context *context = inbox->buf + 8;
3972 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3975 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
3979 adjust_proxy_tun_qkey(dev, vhcr, context);
3980 update_gid(dev, inbox, (u8)slave);
3981 update_pkey_index(dev, slave, inbox);
3982 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3985 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3986 struct mlx4_vhcr *vhcr,
3987 struct mlx4_cmd_mailbox *inbox,
3988 struct mlx4_cmd_mailbox *outbox,
3989 struct mlx4_cmd_info *cmd)
3992 int qpn = vhcr->in_modifier & 0x7fffff;
3995 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3998 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4002 atomic_dec(&qp->mtt->ref_count);
4003 atomic_dec(&qp->rcq->ref_count);
4004 atomic_dec(&qp->scq->ref_count);
4006 atomic_dec(&qp->srq->ref_count);
4007 res_end_move(dev, slave, RES_QP, qpn);
4011 res_abort_move(dev, slave, RES_QP, qpn);
4016 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
4017 struct res_qp *rqp, u8 *gid)
4019 struct res_gid *res;
4021 list_for_each_entry(res, &rqp->mcg_list, list) {
4022 if (!memcmp(res->gid, gid, 16))
4028 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
4029 u8 *gid, enum mlx4_protocol prot,
4030 enum mlx4_steer_type steer, u64 reg_id)
4032 struct res_gid *res;
4035 res = kzalloc(sizeof(*res), GFP_KERNEL);
4039 spin_lock_irq(&rqp->mcg_spl);
4040 if (find_gid(dev, slave, rqp, gid)) {
4044 memcpy(res->gid, gid, 16);
4047 res->reg_id = reg_id;
4048 list_add_tail(&res->list, &rqp->mcg_list);
4051 spin_unlock_irq(&rqp->mcg_spl);
4056 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
4057 u8 *gid, enum mlx4_protocol prot,
4058 enum mlx4_steer_type steer, u64 *reg_id)
4060 struct res_gid *res;
4063 spin_lock_irq(&rqp->mcg_spl);
4064 res = find_gid(dev, slave, rqp, gid);
4065 if (!res || res->prot != prot || res->steer != steer)
4068 *reg_id = res->reg_id;
4069 list_del(&res->list);
4073 spin_unlock_irq(&rqp->mcg_spl);
4078 static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
4079 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
4080 enum mlx4_steer_type type, u64 *reg_id)
4082 switch (dev->caps.steering_mode) {
4083 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
4084 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4087 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
4088 block_loopback, prot,
4091 case MLX4_STEERING_MODE_B0:
4092 if (prot == MLX4_PROT_ETH) {
4093 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4098 return mlx4_qp_attach_common(dev, qp, gid,
4099 block_loopback, prot, type);
4105 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
4106 u8 gid[16], enum mlx4_protocol prot,
4107 enum mlx4_steer_type type, u64 reg_id)
4109 switch (dev->caps.steering_mode) {
4110 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4111 return mlx4_flow_detach(dev, reg_id);
4112 case MLX4_STEERING_MODE_B0:
4113 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
4119 static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
4120 u8 *gid, enum mlx4_protocol prot)
4124 if (prot != MLX4_PROT_ETH)
4127 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
4128 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
4129 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
4138 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4139 struct mlx4_vhcr *vhcr,
4140 struct mlx4_cmd_mailbox *inbox,
4141 struct mlx4_cmd_mailbox *outbox,
4142 struct mlx4_cmd_info *cmd)
4144 struct mlx4_qp qp; /* dummy for calling attach/detach */
4145 u8 *gid = inbox->buf;
4146 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
4151 int attach = vhcr->op_modifier;
4152 int block_loopback = vhcr->in_modifier >> 31;
4153 u8 steer_type_mask = 2;
4154 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
4156 qpn = vhcr->in_modifier & 0xffffff;
4157 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4163 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
4166 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
4169 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
4173 err = mlx4_adjust_port(dev, slave, gid, prot);
4177 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, ®_id);
4181 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
4183 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
4186 put_res(dev, slave, qpn, RES_QP);
4190 qp_detach(dev, &qp, gid, prot, type, reg_id);
4192 put_res(dev, slave, qpn, RES_QP);
4197 * MAC validation for Flow Steering rules.
4198 * VF can attach rules only with a mac address which is assigned to it.
4200 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
4201 struct list_head *rlist)
4203 struct mac_res *res, *tmp;
4206 /* make sure it isn't multicast or broadcast mac*/
4207 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
4208 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4209 list_for_each_entry_safe(res, tmp, rlist, list) {
4210 be_mac = cpu_to_be64(res->mac << 16);
4211 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
4214 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
4215 eth_header->eth.dst_mac, slave);
4222 * In case of missing eth header, append eth header with a MAC address
4223 * assigned to the VF.
4225 static int add_eth_header(struct mlx4_dev *dev, int slave,
4226 struct mlx4_cmd_mailbox *inbox,
4227 struct list_head *rlist, int header_id)
4229 struct mac_res *res, *tmp;
4231 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4232 struct mlx4_net_trans_rule_hw_eth *eth_header;
4233 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
4234 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
4236 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
4238 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4240 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
4242 /* Clear a space in the inbox for eth header */
4243 switch (header_id) {
4244 case MLX4_NET_TRANS_RULE_ID_IPV4:
4246 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
4247 memmove(ip_header, eth_header,
4248 sizeof(*ip_header) + sizeof(*l4_header));
4250 case MLX4_NET_TRANS_RULE_ID_TCP:
4251 case MLX4_NET_TRANS_RULE_ID_UDP:
4252 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
4254 memmove(l4_header, eth_header, sizeof(*l4_header));
4259 list_for_each_entry_safe(res, tmp, rlist, list) {
4260 if (port == res->port) {
4261 be_mac = cpu_to_be64(res->mac << 16);
4266 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
4271 memset(eth_header, 0, sizeof(*eth_header));
4272 eth_header->size = sizeof(*eth_header) >> 2;
4273 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4274 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4275 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4281 #define MLX4_UPD_QP_PATH_MASK_SUPPORTED ( \
4282 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\
4283 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
4284 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4285 struct mlx4_vhcr *vhcr,
4286 struct mlx4_cmd_mailbox *inbox,
4287 struct mlx4_cmd_mailbox *outbox,
4288 struct mlx4_cmd_info *cmd_info)
4291 u32 qpn = vhcr->in_modifier & 0xffffff;
4295 u64 pri_addr_path_mask;
4296 struct mlx4_update_qp_context *cmd;
4299 cmd = (struct mlx4_update_qp_context *)inbox->buf;
4301 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4302 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4303 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4306 if ((pri_addr_path_mask &
4307 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
4308 !(dev->caps.flags2 &
4309 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
4310 mlx4_warn(dev, "Src check LB for slave %d isn't supported\n",
4315 /* Just change the smac for the QP */
4316 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4318 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4322 port = (rqp->sched_queue >> 6 & 1) + 1;
4324 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4325 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4326 err = mac_find_smac_ix_in_slave(dev, slave, port,
4330 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4336 err = mlx4_cmd(dev, inbox->dma,
4337 vhcr->in_modifier, 0,
4338 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4341 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4346 put_res(dev, slave, qpn, RES_QP);
4350 static u32 qp_attach_mbox_size(void *mbox)
4352 u32 size = sizeof(struct mlx4_net_trans_rule_hw_ctrl);
4353 struct _rule_hw *rule_header;
4355 rule_header = (struct _rule_hw *)(mbox + size);
4357 while (rule_header->size) {
4358 size += rule_header->size * sizeof(u32);
4364 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule);
4366 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4367 struct mlx4_vhcr *vhcr,
4368 struct mlx4_cmd_mailbox *inbox,
4369 struct mlx4_cmd_mailbox *outbox,
4370 struct mlx4_cmd_info *cmd)
4373 struct mlx4_priv *priv = mlx4_priv(dev);
4374 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4375 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
4379 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4380 struct _rule_hw *rule_header;
4382 struct res_fs_rule *rrule;
4385 if (dev->caps.steering_mode !=
4386 MLX4_STEERING_MODE_DEVICE_MANAGED)
4389 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4390 err = mlx4_slave_convert_port(dev, slave, ctrl->port);
4394 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
4395 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4397 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
4400 rule_header = (struct _rule_hw *)(ctrl + 1);
4401 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4403 if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
4404 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
4406 switch (header_id) {
4407 case MLX4_NET_TRANS_RULE_ID_ETH:
4408 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4413 case MLX4_NET_TRANS_RULE_ID_IB:
4415 case MLX4_NET_TRANS_RULE_ID_IPV4:
4416 case MLX4_NET_TRANS_RULE_ID_TCP:
4417 case MLX4_NET_TRANS_RULE_ID_UDP:
4418 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
4419 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4423 vhcr->in_modifier +=
4424 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4427 pr_err("Corrupted mailbox\n");
4432 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4433 vhcr->in_modifier, 0,
4434 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4440 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
4442 mlx4_err(dev, "Fail to add flow steering resources\n");
4446 err = get_res(dev, slave, vhcr->out_param, RES_FS_RULE, &rrule);
4450 mbox_size = qp_attach_mbox_size(inbox->buf);
4451 rrule->mirr_mbox = kmalloc(mbox_size, GFP_KERNEL);
4452 if (!rrule->mirr_mbox) {
4456 rrule->mirr_mbox_size = mbox_size;
4457 rrule->mirr_rule_id = 0;
4458 memcpy(rrule->mirr_mbox, inbox->buf, mbox_size);
4460 /* set different port */
4461 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox;
4462 if (ctrl->port == 1)
4467 if (mlx4_is_bonded(dev))
4468 mlx4_do_mirror_rule(dev, rrule);
4470 atomic_inc(&rqp->ref_count);
4473 put_res(dev, slave, vhcr->out_param, RES_FS_RULE);
4475 /* detach rule on error */
4477 mlx4_cmd(dev, vhcr->out_param, 0, 0,
4478 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4481 put_res(dev, slave, qpn, RES_QP);
4485 static int mlx4_undo_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4489 err = rem_res_range(dev, fs_rule->com.owner, fs_rule->com.res_id, 1, RES_FS_RULE, 0);
4491 mlx4_err(dev, "Fail to remove flow steering resources\n");
4495 mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4496 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
4500 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4501 struct mlx4_vhcr *vhcr,
4502 struct mlx4_cmd_mailbox *inbox,
4503 struct mlx4_cmd_mailbox *outbox,
4504 struct mlx4_cmd_info *cmd)
4508 struct res_fs_rule *rrule;
4512 if (dev->caps.steering_mode !=
4513 MLX4_STEERING_MODE_DEVICE_MANAGED)
4516 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4520 if (!rrule->mirr_mbox) {
4521 mlx4_err(dev, "Mirror rules cannot be removed explicitly\n");
4522 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4525 mirr_reg_id = rrule->mirr_rule_id;
4526 kfree(rrule->mirr_mbox);
4529 /* Release the rule form busy state before removal */
4530 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4531 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4535 if (mirr_reg_id && mlx4_is_bonded(dev)) {
4536 err = get_res(dev, slave, mirr_reg_id, RES_FS_RULE, &rrule);
4538 mlx4_err(dev, "Fail to get resource of mirror rule\n");
4540 put_res(dev, slave, mirr_reg_id, RES_FS_RULE);
4541 mlx4_undo_mirror_rule(dev, rrule);
4544 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4546 mlx4_err(dev, "Fail to remove flow steering resources\n");
4550 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4551 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4554 atomic_dec(&rqp->ref_count);
4556 put_res(dev, slave, qpn, RES_QP);
4561 BUSY_MAX_RETRIES = 10
4564 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4565 struct mlx4_vhcr *vhcr,
4566 struct mlx4_cmd_mailbox *inbox,
4567 struct mlx4_cmd_mailbox *outbox,
4568 struct mlx4_cmd_info *cmd)
4571 int index = vhcr->in_modifier & 0xffff;
4573 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4577 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4578 put_res(dev, slave, index, RES_COUNTER);
4582 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4584 struct res_gid *rgid;
4585 struct res_gid *tmp;
4586 struct mlx4_qp qp; /* dummy for calling attach/detach */
4588 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
4589 switch (dev->caps.steering_mode) {
4590 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4591 mlx4_flow_detach(dev, rgid->reg_id);
4593 case MLX4_STEERING_MODE_B0:
4594 qp.qpn = rqp->local_qpn;
4595 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4596 rgid->prot, rgid->steer);
4599 list_del(&rgid->list);
4604 static int _move_all_busy(struct mlx4_dev *dev, int slave,
4605 enum mlx4_resource type, int print)
4607 struct mlx4_priv *priv = mlx4_priv(dev);
4608 struct mlx4_resource_tracker *tracker =
4609 &priv->mfunc.master.res_tracker;
4610 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4611 struct res_common *r;
4612 struct res_common *tmp;
4616 spin_lock_irq(mlx4_tlock(dev));
4617 list_for_each_entry_safe(r, tmp, rlist, list) {
4618 if (r->owner == slave) {
4620 if (r->state == RES_ANY_BUSY) {
4623 "%s id 0x%llx is busy\n",
4628 r->from_state = r->state;
4629 r->state = RES_ANY_BUSY;
4635 spin_unlock_irq(mlx4_tlock(dev));
4640 static int move_all_busy(struct mlx4_dev *dev, int slave,
4641 enum mlx4_resource type)
4643 unsigned long begin;
4648 busy = _move_all_busy(dev, slave, type, 0);
4649 if (time_after(jiffies, begin + 5 * HZ))
4656 busy = _move_all_busy(dev, slave, type, 1);
4660 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4662 struct mlx4_priv *priv = mlx4_priv(dev);
4663 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4664 struct list_head *qp_list =
4665 &tracker->slave_list[slave].res_list[RES_QP];
4673 err = move_all_busy(dev, slave, RES_QP);
4675 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4678 spin_lock_irq(mlx4_tlock(dev));
4679 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4680 spin_unlock_irq(mlx4_tlock(dev));
4681 if (qp->com.owner == slave) {
4682 qpn = qp->com.res_id;
4683 detach_qp(dev, slave, qp);
4684 state = qp->com.from_state;
4685 while (state != 0) {
4687 case RES_QP_RESERVED:
4688 spin_lock_irq(mlx4_tlock(dev));
4689 rb_erase(&qp->com.node,
4690 &tracker->res_tree[RES_QP]);
4691 list_del(&qp->com.list);
4692 spin_unlock_irq(mlx4_tlock(dev));
4693 if (!valid_reserved(dev, slave, qpn)) {
4694 __mlx4_qp_release_range(dev, qpn, 1);
4695 mlx4_release_resource(dev, slave,
4702 if (!valid_reserved(dev, slave, qpn))
4703 __mlx4_qp_free_icm(dev, qpn);
4704 state = RES_QP_RESERVED;
4708 err = mlx4_cmd(dev, in_param,
4711 MLX4_CMD_TIME_CLASS_A,
4714 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4715 slave, qp->local_qpn);
4716 atomic_dec(&qp->rcq->ref_count);
4717 atomic_dec(&qp->scq->ref_count);
4718 atomic_dec(&qp->mtt->ref_count);
4720 atomic_dec(&qp->srq->ref_count);
4721 state = RES_QP_MAPPED;
4728 spin_lock_irq(mlx4_tlock(dev));
4730 spin_unlock_irq(mlx4_tlock(dev));
4733 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4735 struct mlx4_priv *priv = mlx4_priv(dev);
4736 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4737 struct list_head *srq_list =
4738 &tracker->slave_list[slave].res_list[RES_SRQ];
4739 struct res_srq *srq;
4740 struct res_srq *tmp;
4746 err = move_all_busy(dev, slave, RES_SRQ);
4748 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4751 spin_lock_irq(mlx4_tlock(dev));
4752 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4753 spin_unlock_irq(mlx4_tlock(dev));
4754 if (srq->com.owner == slave) {
4755 srqn = srq->com.res_id;
4756 state = srq->com.from_state;
4757 while (state != 0) {
4759 case RES_SRQ_ALLOCATED:
4760 __mlx4_srq_free_icm(dev, srqn);
4761 spin_lock_irq(mlx4_tlock(dev));
4762 rb_erase(&srq->com.node,
4763 &tracker->res_tree[RES_SRQ]);
4764 list_del(&srq->com.list);
4765 spin_unlock_irq(mlx4_tlock(dev));
4766 mlx4_release_resource(dev, slave,
4774 err = mlx4_cmd(dev, in_param, srqn, 1,
4776 MLX4_CMD_TIME_CLASS_A,
4779 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
4782 atomic_dec(&srq->mtt->ref_count);
4784 atomic_dec(&srq->cq->ref_count);
4785 state = RES_SRQ_ALLOCATED;
4793 spin_lock_irq(mlx4_tlock(dev));
4795 spin_unlock_irq(mlx4_tlock(dev));
4798 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4800 struct mlx4_priv *priv = mlx4_priv(dev);
4801 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4802 struct list_head *cq_list =
4803 &tracker->slave_list[slave].res_list[RES_CQ];
4811 err = move_all_busy(dev, slave, RES_CQ);
4813 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4816 spin_lock_irq(mlx4_tlock(dev));
4817 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4818 spin_unlock_irq(mlx4_tlock(dev));
4819 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4820 cqn = cq->com.res_id;
4821 state = cq->com.from_state;
4822 while (state != 0) {
4824 case RES_CQ_ALLOCATED:
4825 __mlx4_cq_free_icm(dev, cqn);
4826 spin_lock_irq(mlx4_tlock(dev));
4827 rb_erase(&cq->com.node,
4828 &tracker->res_tree[RES_CQ]);
4829 list_del(&cq->com.list);
4830 spin_unlock_irq(mlx4_tlock(dev));
4831 mlx4_release_resource(dev, slave,
4839 err = mlx4_cmd(dev, in_param, cqn, 1,
4841 MLX4_CMD_TIME_CLASS_A,
4844 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
4846 atomic_dec(&cq->mtt->ref_count);
4847 state = RES_CQ_ALLOCATED;
4855 spin_lock_irq(mlx4_tlock(dev));
4857 spin_unlock_irq(mlx4_tlock(dev));
4860 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4862 struct mlx4_priv *priv = mlx4_priv(dev);
4863 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4864 struct list_head *mpt_list =
4865 &tracker->slave_list[slave].res_list[RES_MPT];
4866 struct res_mpt *mpt;
4867 struct res_mpt *tmp;
4873 err = move_all_busy(dev, slave, RES_MPT);
4875 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4878 spin_lock_irq(mlx4_tlock(dev));
4879 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4880 spin_unlock_irq(mlx4_tlock(dev));
4881 if (mpt->com.owner == slave) {
4882 mptn = mpt->com.res_id;
4883 state = mpt->com.from_state;
4884 while (state != 0) {
4886 case RES_MPT_RESERVED:
4887 __mlx4_mpt_release(dev, mpt->key);
4888 spin_lock_irq(mlx4_tlock(dev));
4889 rb_erase(&mpt->com.node,
4890 &tracker->res_tree[RES_MPT]);
4891 list_del(&mpt->com.list);
4892 spin_unlock_irq(mlx4_tlock(dev));
4893 mlx4_release_resource(dev, slave,
4899 case RES_MPT_MAPPED:
4900 __mlx4_mpt_free_icm(dev, mpt->key);
4901 state = RES_MPT_RESERVED;
4906 err = mlx4_cmd(dev, in_param, mptn, 0,
4908 MLX4_CMD_TIME_CLASS_A,
4911 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
4914 atomic_dec(&mpt->mtt->ref_count);
4915 state = RES_MPT_MAPPED;
4922 spin_lock_irq(mlx4_tlock(dev));
4924 spin_unlock_irq(mlx4_tlock(dev));
4927 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4929 struct mlx4_priv *priv = mlx4_priv(dev);
4930 struct mlx4_resource_tracker *tracker =
4931 &priv->mfunc.master.res_tracker;
4932 struct list_head *mtt_list =
4933 &tracker->slave_list[slave].res_list[RES_MTT];
4934 struct res_mtt *mtt;
4935 struct res_mtt *tmp;
4940 err = move_all_busy(dev, slave, RES_MTT);
4942 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4945 spin_lock_irq(mlx4_tlock(dev));
4946 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4947 spin_unlock_irq(mlx4_tlock(dev));
4948 if (mtt->com.owner == slave) {
4949 base = mtt->com.res_id;
4950 state = mtt->com.from_state;
4951 while (state != 0) {
4953 case RES_MTT_ALLOCATED:
4954 __mlx4_free_mtt_range(dev, base,
4956 spin_lock_irq(mlx4_tlock(dev));
4957 rb_erase(&mtt->com.node,
4958 &tracker->res_tree[RES_MTT]);
4959 list_del(&mtt->com.list);
4960 spin_unlock_irq(mlx4_tlock(dev));
4961 mlx4_release_resource(dev, slave, RES_MTT,
4962 1 << mtt->order, 0);
4972 spin_lock_irq(mlx4_tlock(dev));
4974 spin_unlock_irq(mlx4_tlock(dev));
4977 static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
4979 struct mlx4_cmd_mailbox *mailbox;
4981 struct res_fs_rule *mirr_rule;
4984 mailbox = mlx4_alloc_cmd_mailbox(dev);
4985 if (IS_ERR(mailbox))
4986 return PTR_ERR(mailbox);
4988 if (!fs_rule->mirr_mbox) {
4989 mlx4_err(dev, "rule mirroring mailbox is null\n");
4990 mlx4_free_cmd_mailbox(dev, mailbox);
4993 memcpy(mailbox->buf, fs_rule->mirr_mbox, fs_rule->mirr_mbox_size);
4994 err = mlx4_cmd_imm(dev, mailbox->dma, ®_id, fs_rule->mirr_mbox_size >> 2, 0,
4995 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4997 mlx4_free_cmd_mailbox(dev, mailbox);
5002 err = add_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, fs_rule->qpn);
5006 err = get_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE, &mirr_rule);
5010 fs_rule->mirr_rule_id = reg_id;
5011 mirr_rule->mirr_rule_id = 0;
5012 mirr_rule->mirr_mbox_size = 0;
5013 mirr_rule->mirr_mbox = NULL;
5014 put_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE);
5018 rem_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, 0);
5020 mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
5021 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
5026 static int mlx4_mirror_fs_rules(struct mlx4_dev *dev, bool bond)
5028 struct mlx4_priv *priv = mlx4_priv(dev);
5029 struct mlx4_resource_tracker *tracker =
5030 &priv->mfunc.master.res_tracker;
5031 struct rb_root *root = &tracker->res_tree[RES_FS_RULE];
5033 struct res_fs_rule *fs_rule;
5035 LIST_HEAD(mirr_list);
5037 for (p = rb_first(root); p; p = rb_next(p)) {
5038 fs_rule = rb_entry(p, struct res_fs_rule, com.node);
5039 if ((bond && fs_rule->mirr_mbox_size) ||
5040 (!bond && !fs_rule->mirr_mbox_size))
5041 list_add_tail(&fs_rule->mirr_list, &mirr_list);
5044 list_for_each_entry(fs_rule, &mirr_list, mirr_list) {
5046 err += mlx4_do_mirror_rule(dev, fs_rule);
5048 err += mlx4_undo_mirror_rule(dev, fs_rule);
5053 int mlx4_bond_fs_rules(struct mlx4_dev *dev)
5055 return mlx4_mirror_fs_rules(dev, true);
5058 int mlx4_unbond_fs_rules(struct mlx4_dev *dev)
5060 return mlx4_mirror_fs_rules(dev, false);
5063 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
5065 struct mlx4_priv *priv = mlx4_priv(dev);
5066 struct mlx4_resource_tracker *tracker =
5067 &priv->mfunc.master.res_tracker;
5068 struct list_head *fs_rule_list =
5069 &tracker->slave_list[slave].res_list[RES_FS_RULE];
5070 struct res_fs_rule *fs_rule;
5071 struct res_fs_rule *tmp;
5076 err = move_all_busy(dev, slave, RES_FS_RULE);
5078 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
5081 spin_lock_irq(mlx4_tlock(dev));
5082 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
5083 spin_unlock_irq(mlx4_tlock(dev));
5084 if (fs_rule->com.owner == slave) {
5085 base = fs_rule->com.res_id;
5086 state = fs_rule->com.from_state;
5087 while (state != 0) {
5089 case RES_FS_RULE_ALLOCATED:
5091 err = mlx4_cmd(dev, base, 0, 0,
5092 MLX4_QP_FLOW_STEERING_DETACH,
5093 MLX4_CMD_TIME_CLASS_A,
5096 spin_lock_irq(mlx4_tlock(dev));
5097 rb_erase(&fs_rule->com.node,
5098 &tracker->res_tree[RES_FS_RULE]);
5099 list_del(&fs_rule->com.list);
5100 spin_unlock_irq(mlx4_tlock(dev));
5101 kfree(fs_rule->mirr_mbox);
5111 spin_lock_irq(mlx4_tlock(dev));
5113 spin_unlock_irq(mlx4_tlock(dev));
5116 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
5118 struct mlx4_priv *priv = mlx4_priv(dev);
5119 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5120 struct list_head *eq_list =
5121 &tracker->slave_list[slave].res_list[RES_EQ];
5128 err = move_all_busy(dev, slave, RES_EQ);
5130 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
5133 spin_lock_irq(mlx4_tlock(dev));
5134 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
5135 spin_unlock_irq(mlx4_tlock(dev));
5136 if (eq->com.owner == slave) {
5137 eqn = eq->com.res_id;
5138 state = eq->com.from_state;
5139 while (state != 0) {
5141 case RES_EQ_RESERVED:
5142 spin_lock_irq(mlx4_tlock(dev));
5143 rb_erase(&eq->com.node,
5144 &tracker->res_tree[RES_EQ]);
5145 list_del(&eq->com.list);
5146 spin_unlock_irq(mlx4_tlock(dev));
5152 err = mlx4_cmd(dev, slave, eqn & 0x3ff,
5153 1, MLX4_CMD_HW2SW_EQ,
5154 MLX4_CMD_TIME_CLASS_A,
5157 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
5158 slave, eqn & 0x3ff);
5159 atomic_dec(&eq->mtt->ref_count);
5160 state = RES_EQ_RESERVED;
5168 spin_lock_irq(mlx4_tlock(dev));
5170 spin_unlock_irq(mlx4_tlock(dev));
5173 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
5175 struct mlx4_priv *priv = mlx4_priv(dev);
5176 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5177 struct list_head *counter_list =
5178 &tracker->slave_list[slave].res_list[RES_COUNTER];
5179 struct res_counter *counter;
5180 struct res_counter *tmp;
5182 int *counters_arr = NULL;
5185 err = move_all_busy(dev, slave, RES_COUNTER);
5187 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
5190 counters_arr = kmalloc_array(dev->caps.max_counters,
5191 sizeof(*counters_arr), GFP_KERNEL);
5198 spin_lock_irq(mlx4_tlock(dev));
5199 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
5200 if (counter->com.owner == slave) {
5201 counters_arr[i++] = counter->com.res_id;
5202 rb_erase(&counter->com.node,
5203 &tracker->res_tree[RES_COUNTER]);
5204 list_del(&counter->com.list);
5208 spin_unlock_irq(mlx4_tlock(dev));
5211 __mlx4_counter_free(dev, counters_arr[j++]);
5212 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
5216 kfree(counters_arr);
5219 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
5221 struct mlx4_priv *priv = mlx4_priv(dev);
5222 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5223 struct list_head *xrcdn_list =
5224 &tracker->slave_list[slave].res_list[RES_XRCD];
5225 struct res_xrcdn *xrcd;
5226 struct res_xrcdn *tmp;
5230 err = move_all_busy(dev, slave, RES_XRCD);
5232 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
5235 spin_lock_irq(mlx4_tlock(dev));
5236 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
5237 if (xrcd->com.owner == slave) {
5238 xrcdn = xrcd->com.res_id;
5239 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
5240 list_del(&xrcd->com.list);
5242 __mlx4_xrcd_free(dev, xrcdn);
5245 spin_unlock_irq(mlx4_tlock(dev));
5248 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
5250 struct mlx4_priv *priv = mlx4_priv(dev);
5251 mlx4_reset_roce_gids(dev, slave);
5252 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5253 rem_slave_vlans(dev, slave);
5254 rem_slave_macs(dev, slave);
5255 rem_slave_fs_rule(dev, slave);
5256 rem_slave_qps(dev, slave);
5257 rem_slave_srqs(dev, slave);
5258 rem_slave_cqs(dev, slave);
5259 rem_slave_mrs(dev, slave);
5260 rem_slave_eqs(dev, slave);
5261 rem_slave_mtts(dev, slave);
5262 rem_slave_counters(dev, slave);
5263 rem_slave_xrcdns(dev, slave);
5264 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5267 static void update_qos_vpp(struct mlx4_update_qp_context *ctx,
5268 struct mlx4_vf_immed_vlan_work *work)
5270 ctx->qp_mask |= cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_QOS_VPP);
5271 ctx->qp_context.qos_vport = work->qos_vport;
5274 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
5276 struct mlx4_vf_immed_vlan_work *work =
5277 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
5278 struct mlx4_cmd_mailbox *mailbox;
5279 struct mlx4_update_qp_context *upd_context;
5280 struct mlx4_dev *dev = &work->priv->dev;
5281 struct mlx4_resource_tracker *tracker =
5282 &work->priv->mfunc.master.res_tracker;
5283 struct list_head *qp_list =
5284 &tracker->slave_list[work->slave].res_list[RES_QP];
5287 u64 qp_path_mask_vlan_ctrl =
5288 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
5289 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
5290 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
5291 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
5292 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
5293 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
5295 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
5296 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
5297 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
5298 (1ULL << MLX4_UPD_QP_PATH_MASK_SV) |
5299 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
5300 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
5301 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
5302 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
5305 int port, errors = 0;
5308 if (mlx4_is_slave(dev)) {
5309 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
5314 mailbox = mlx4_alloc_cmd_mailbox(dev);
5315 if (IS_ERR(mailbox))
5317 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
5318 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5319 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5320 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
5321 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5322 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
5323 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5324 else if (!work->vlan_id)
5325 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5326 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5327 else if (work->vlan_proto == htons(ETH_P_8021AD))
5328 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5329 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5330 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5331 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5332 else /* vst 802.1Q */
5333 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5334 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5335 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5337 upd_context = mailbox->buf;
5338 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
5340 spin_lock_irq(mlx4_tlock(dev));
5341 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
5342 spin_unlock_irq(mlx4_tlock(dev));
5343 if (qp->com.owner == work->slave) {
5344 if (qp->com.from_state != RES_QP_HW ||
5345 !qp->sched_queue || /* no INIT2RTR trans yet */
5346 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
5347 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
5348 spin_lock_irq(mlx4_tlock(dev));
5351 port = (qp->sched_queue >> 6 & 1) + 1;
5352 if (port != work->port) {
5353 spin_lock_irq(mlx4_tlock(dev));
5356 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
5357 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
5359 upd_context->primary_addr_path_mask =
5360 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
5361 if (work->vlan_id == MLX4_VGT) {
5362 upd_context->qp_context.param3 = qp->param3;
5363 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
5364 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
5365 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
5366 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
5367 upd_context->qp_context.pri_path.feup = qp->feup;
5368 upd_context->qp_context.pri_path.sched_queue =
5371 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
5372 upd_context->qp_context.pri_path.vlan_control = vlan_control;
5373 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
5374 upd_context->qp_context.pri_path.fvl_rx =
5375 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
5376 upd_context->qp_context.pri_path.fl =
5377 qp->pri_path_fl | MLX4_FL_ETH_HIDE_CQE_VLAN;
5378 if (work->vlan_proto == htons(ETH_P_8021AD))
5379 upd_context->qp_context.pri_path.fl |= MLX4_FL_SV;
5381 upd_context->qp_context.pri_path.fl |= MLX4_FL_CV;
5382 upd_context->qp_context.pri_path.feup =
5383 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
5384 upd_context->qp_context.pri_path.sched_queue =
5385 qp->sched_queue & 0xC7;
5386 upd_context->qp_context.pri_path.sched_queue |=
5387 ((work->qos & 0x7) << 3);
5389 if (dev->caps.flags2 &
5390 MLX4_DEV_CAP_FLAG2_QOS_VPP)
5391 update_qos_vpp(upd_context, work);
5394 err = mlx4_cmd(dev, mailbox->dma,
5395 qp->local_qpn & 0xffffff,
5396 0, MLX4_CMD_UPDATE_QP,
5397 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
5399 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
5400 work->slave, port, qp->local_qpn, err);
5404 spin_lock_irq(mlx4_tlock(dev));
5406 spin_unlock_irq(mlx4_tlock(dev));
5407 mlx4_free_cmd_mailbox(dev, mailbox);
5410 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
5411 errors, work->slave, work->port);
5413 /* unregister previous vlan_id if needed and we had no errors
5414 * while updating the QPs
5416 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
5417 NO_INDX != work->orig_vlan_ix)
5418 __mlx4_unregister_vlan(&work->priv->dev, work->port,
5419 work->orig_vlan_id);