2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/sched.h>
37 #include <linux/pci.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/mlx4/cmd.h>
43 #include <linux/mlx4/qp.h>
44 #include <linux/if_ether.h>
45 #include <linux/etherdevice.h>
49 #include "mlx4_stats.h"
51 #define MLX4_MAC_VALID (1ull << 63)
52 #define MLX4_PF_COUNTERS_PER_PORT 2
53 #define MLX4_VF_COUNTERS_PER_PORT 1
56 struct list_head list;
64 struct list_head list;
72 struct list_head list;
87 struct list_head list;
89 enum mlx4_protocol prot;
90 enum mlx4_steer_type steer;
95 RES_QP_BUSY = RES_ANY_BUSY,
97 /* QP number was allocated */
100 /* ICM memory for QP context was mapped */
103 /* QP is in hw ownership */
108 struct res_common com;
113 struct list_head mcg_list;
118 /* saved qp params before VST enforcement in order to restore on VGT */
128 enum res_mtt_states {
129 RES_MTT_BUSY = RES_ANY_BUSY,
133 static inline const char *mtt_states_str(enum res_mtt_states state)
136 case RES_MTT_BUSY: return "RES_MTT_BUSY";
137 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
138 default: return "Unknown";
143 struct res_common com;
148 enum res_mpt_states {
149 RES_MPT_BUSY = RES_ANY_BUSY,
156 struct res_common com;
162 RES_EQ_BUSY = RES_ANY_BUSY,
168 struct res_common com;
173 RES_CQ_BUSY = RES_ANY_BUSY,
179 struct res_common com;
184 enum res_srq_states {
185 RES_SRQ_BUSY = RES_ANY_BUSY,
191 struct res_common com;
197 enum res_counter_states {
198 RES_COUNTER_BUSY = RES_ANY_BUSY,
199 RES_COUNTER_ALLOCATED,
203 struct res_common com;
207 enum res_xrcdn_states {
208 RES_XRCD_BUSY = RES_ANY_BUSY,
213 struct res_common com;
217 enum res_fs_rule_states {
218 RES_FS_RULE_BUSY = RES_ANY_BUSY,
219 RES_FS_RULE_ALLOCATED,
223 struct res_common com;
227 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
229 struct rb_node *node = root->rb_node;
232 struct res_common *res = container_of(node, struct res_common,
235 if (res_id < res->res_id)
236 node = node->rb_left;
237 else if (res_id > res->res_id)
238 node = node->rb_right;
245 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
247 struct rb_node **new = &(root->rb_node), *parent = NULL;
249 /* Figure out where to put new node */
251 struct res_common *this = container_of(*new, struct res_common,
255 if (res->res_id < this->res_id)
256 new = &((*new)->rb_left);
257 else if (res->res_id > this->res_id)
258 new = &((*new)->rb_right);
263 /* Add new node and rebalance tree. */
264 rb_link_node(&res->node, parent, new);
265 rb_insert_color(&res->node, root);
280 static const char *resource_str(enum mlx4_resource rt)
283 case RES_QP: return "RES_QP";
284 case RES_CQ: return "RES_CQ";
285 case RES_SRQ: return "RES_SRQ";
286 case RES_MPT: return "RES_MPT";
287 case RES_MTT: return "RES_MTT";
288 case RES_MAC: return "RES_MAC";
289 case RES_VLAN: return "RES_VLAN";
290 case RES_EQ: return "RES_EQ";
291 case RES_COUNTER: return "RES_COUNTER";
292 case RES_FS_RULE: return "RES_FS_RULE";
293 case RES_XRCD: return "RES_XRCD";
294 default: return "Unknown resource type !!!";
298 static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
299 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
300 enum mlx4_resource res_type, int count,
303 struct mlx4_priv *priv = mlx4_priv(dev);
304 struct resource_allocator *res_alloc =
305 &priv->mfunc.master.res_tracker.res_alloc[res_type];
307 int allocated, free, reserved, guaranteed, from_free;
310 if (slave > dev->persist->num_vfs)
313 spin_lock(&res_alloc->alloc_lock);
314 allocated = (port > 0) ?
315 res_alloc->allocated[(port - 1) *
316 (dev->persist->num_vfs + 1) + slave] :
317 res_alloc->allocated[slave];
318 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
320 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
321 res_alloc->res_reserved;
322 guaranteed = res_alloc->guaranteed[slave];
324 if (allocated + count > res_alloc->quota[slave]) {
325 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
326 slave, port, resource_str(res_type), count,
327 allocated, res_alloc->quota[slave]);
331 if (allocated + count <= guaranteed) {
335 /* portion may need to be obtained from free area */
336 if (guaranteed - allocated > 0)
337 from_free = count - (guaranteed - allocated);
341 from_rsvd = count - from_free;
343 if (free - from_free >= reserved)
346 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
347 slave, port, resource_str(res_type), free,
348 from_free, reserved);
352 /* grant the request */
354 res_alloc->allocated[(port - 1) *
355 (dev->persist->num_vfs + 1) + slave] += count;
356 res_alloc->res_port_free[port - 1] -= count;
357 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
359 res_alloc->allocated[slave] += count;
360 res_alloc->res_free -= count;
361 res_alloc->res_reserved -= from_rsvd;
366 spin_unlock(&res_alloc->alloc_lock);
370 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
371 enum mlx4_resource res_type, int count,
374 struct mlx4_priv *priv = mlx4_priv(dev);
375 struct resource_allocator *res_alloc =
376 &priv->mfunc.master.res_tracker.res_alloc[res_type];
377 int allocated, guaranteed, from_rsvd;
379 if (slave > dev->persist->num_vfs)
382 spin_lock(&res_alloc->alloc_lock);
384 allocated = (port > 0) ?
385 res_alloc->allocated[(port - 1) *
386 (dev->persist->num_vfs + 1) + slave] :
387 res_alloc->allocated[slave];
388 guaranteed = res_alloc->guaranteed[slave];
390 if (allocated - count >= guaranteed) {
393 /* portion may need to be returned to reserved area */
394 if (allocated - guaranteed > 0)
395 from_rsvd = count - (allocated - guaranteed);
401 res_alloc->allocated[(port - 1) *
402 (dev->persist->num_vfs + 1) + slave] -= count;
403 res_alloc->res_port_free[port - 1] += count;
404 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
406 res_alloc->allocated[slave] -= count;
407 res_alloc->res_free += count;
408 res_alloc->res_reserved += from_rsvd;
411 spin_unlock(&res_alloc->alloc_lock);
415 static inline void initialize_res_quotas(struct mlx4_dev *dev,
416 struct resource_allocator *res_alloc,
417 enum mlx4_resource res_type,
418 int vf, int num_instances)
420 res_alloc->guaranteed[vf] = num_instances /
421 (2 * (dev->persist->num_vfs + 1));
422 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
423 if (vf == mlx4_master_func_num(dev)) {
424 res_alloc->res_free = num_instances;
425 if (res_type == RES_MTT) {
426 /* reserved mtts will be taken out of the PF allocation */
427 res_alloc->res_free += dev->caps.reserved_mtts;
428 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
429 res_alloc->quota[vf] += dev->caps.reserved_mtts;
434 void mlx4_init_quotas(struct mlx4_dev *dev)
436 struct mlx4_priv *priv = mlx4_priv(dev);
439 /* quotas for VFs are initialized in mlx4_slave_cap */
440 if (mlx4_is_slave(dev))
443 if (!mlx4_is_mfunc(dev)) {
444 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
445 mlx4_num_reserved_sqps(dev);
446 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
447 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
448 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
449 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
453 pf = mlx4_master_func_num(dev);
455 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
457 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
459 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
461 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
463 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
467 mlx4_calc_res_counter_guaranteed(struct mlx4_dev *dev,
468 struct resource_allocator *res_alloc,
471 struct mlx4_active_ports actv_ports;
472 int ports, counters_guaranteed;
474 /* For master, only allocate according to the number of phys ports */
475 if (vf == mlx4_master_func_num(dev))
476 return MLX4_PF_COUNTERS_PER_PORT * dev->caps.num_ports;
478 /* calculate real number of ports for the VF */
479 actv_ports = mlx4_get_active_ports(dev, vf);
480 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
481 counters_guaranteed = ports * MLX4_VF_COUNTERS_PER_PORT;
483 /* If we do not have enough counters for this VF, do not
484 * allocate any for it. '-1' to reduce the sink counter.
486 if ((res_alloc->res_reserved + counters_guaranteed) >
487 (dev->caps.max_counters - 1))
490 return counters_guaranteed;
493 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
495 struct mlx4_priv *priv = mlx4_priv(dev);
499 priv->mfunc.master.res_tracker.slave_list =
500 kzalloc(dev->num_slaves * sizeof(struct slave_list),
502 if (!priv->mfunc.master.res_tracker.slave_list)
505 for (i = 0 ; i < dev->num_slaves; i++) {
506 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
507 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
508 slave_list[i].res_list[t]);
509 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
512 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
514 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
515 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
517 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
518 struct resource_allocator *res_alloc =
519 &priv->mfunc.master.res_tracker.res_alloc[i];
520 res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
521 sizeof(int), GFP_KERNEL);
522 res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
523 sizeof(int), GFP_KERNEL);
524 if (i == RES_MAC || i == RES_VLAN)
525 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
526 (dev->persist->num_vfs
528 sizeof(int), GFP_KERNEL);
530 res_alloc->allocated = kzalloc((dev->persist->
532 sizeof(int), GFP_KERNEL);
533 /* Reduce the sink counter */
534 if (i == RES_COUNTER)
535 res_alloc->res_free = dev->caps.max_counters - 1;
537 if (!res_alloc->quota || !res_alloc->guaranteed ||
538 !res_alloc->allocated)
541 spin_lock_init(&res_alloc->alloc_lock);
542 for (t = 0; t < dev->persist->num_vfs + 1; t++) {
543 struct mlx4_active_ports actv_ports =
544 mlx4_get_active_ports(dev, t);
547 initialize_res_quotas(dev, res_alloc, RES_QP,
548 t, dev->caps.num_qps -
549 dev->caps.reserved_qps -
550 mlx4_num_reserved_sqps(dev));
553 initialize_res_quotas(dev, res_alloc, RES_CQ,
554 t, dev->caps.num_cqs -
555 dev->caps.reserved_cqs);
558 initialize_res_quotas(dev, res_alloc, RES_SRQ,
559 t, dev->caps.num_srqs -
560 dev->caps.reserved_srqs);
563 initialize_res_quotas(dev, res_alloc, RES_MPT,
564 t, dev->caps.num_mpts -
565 dev->caps.reserved_mrws);
568 initialize_res_quotas(dev, res_alloc, RES_MTT,
569 t, dev->caps.num_mtts -
570 dev->caps.reserved_mtts);
573 if (t == mlx4_master_func_num(dev)) {
574 int max_vfs_pport = 0;
575 /* Calculate the max vfs per port for */
577 for (j = 0; j < dev->caps.num_ports;
579 struct mlx4_slaves_pport slaves_pport =
580 mlx4_phys_to_slaves_pport(dev, j + 1);
581 unsigned current_slaves =
582 bitmap_weight(slaves_pport.slaves,
583 dev->caps.num_ports) - 1;
584 if (max_vfs_pport < current_slaves)
588 res_alloc->quota[t] =
591 res_alloc->guaranteed[t] = 2;
592 for (j = 0; j < MLX4_MAX_PORTS; j++)
593 res_alloc->res_port_free[j] =
596 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
597 res_alloc->guaranteed[t] = 2;
601 if (t == mlx4_master_func_num(dev)) {
602 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
603 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
604 for (j = 0; j < MLX4_MAX_PORTS; j++)
605 res_alloc->res_port_free[j] =
608 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
609 res_alloc->guaranteed[t] = 0;
613 res_alloc->quota[t] = dev->caps.max_counters;
614 res_alloc->guaranteed[t] =
615 mlx4_calc_res_counter_guaranteed(dev, res_alloc, t);
616 res_alloc->res_free -= res_alloc->guaranteed[t];
621 if (i == RES_MAC || i == RES_VLAN) {
622 for (j = 0; j < dev->caps.num_ports; j++)
623 if (test_bit(j, actv_ports.ports))
624 res_alloc->res_port_rsvd[j] +=
625 res_alloc->guaranteed[t];
627 res_alloc->res_reserved += res_alloc->guaranteed[t];
631 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
635 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
636 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
637 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
638 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
639 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
640 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
641 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
646 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
647 enum mlx4_res_tracker_free_type type)
649 struct mlx4_priv *priv = mlx4_priv(dev);
652 if (priv->mfunc.master.res_tracker.slave_list) {
653 if (type != RES_TR_FREE_STRUCTS_ONLY) {
654 for (i = 0; i < dev->num_slaves; i++) {
655 if (type == RES_TR_FREE_ALL ||
656 dev->caps.function != i)
657 mlx4_delete_all_resources_for_slave(dev, i);
659 /* free master's vlans */
660 i = dev->caps.function;
661 mlx4_reset_roce_gids(dev, i);
662 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
663 rem_slave_vlans(dev, i);
664 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
667 if (type != RES_TR_FREE_SLAVES_ONLY) {
668 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
669 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
670 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
671 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
672 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
673 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
674 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
676 kfree(priv->mfunc.master.res_tracker.slave_list);
677 priv->mfunc.master.res_tracker.slave_list = NULL;
682 static void update_pkey_index(struct mlx4_dev *dev, int slave,
683 struct mlx4_cmd_mailbox *inbox)
685 u8 sched = *(u8 *)(inbox->buf + 64);
686 u8 orig_index = *(u8 *)(inbox->buf + 35);
688 struct mlx4_priv *priv = mlx4_priv(dev);
691 port = (sched >> 6 & 1) + 1;
693 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
694 *(u8 *)(inbox->buf + 35) = new_index;
697 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
700 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
701 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
702 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
705 if (MLX4_QP_ST_UD == ts) {
706 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
707 if (mlx4_is_eth(dev, port))
708 qp_ctx->pri_path.mgid_index =
709 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
711 qp_ctx->pri_path.mgid_index = slave | 0x80;
713 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
714 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
715 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
716 if (mlx4_is_eth(dev, port)) {
717 qp_ctx->pri_path.mgid_index +=
718 mlx4_get_base_gid_ix(dev, slave, port);
719 qp_ctx->pri_path.mgid_index &= 0x7f;
721 qp_ctx->pri_path.mgid_index = slave & 0x7F;
724 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
725 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
726 if (mlx4_is_eth(dev, port)) {
727 qp_ctx->alt_path.mgid_index +=
728 mlx4_get_base_gid_ix(dev, slave, port);
729 qp_ctx->alt_path.mgid_index &= 0x7f;
731 qp_ctx->alt_path.mgid_index = slave & 0x7F;
737 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
740 static int update_vport_qp_param(struct mlx4_dev *dev,
741 struct mlx4_cmd_mailbox *inbox,
744 struct mlx4_qp_context *qpc = inbox->buf + 8;
745 struct mlx4_vport_oper_state *vp_oper;
746 struct mlx4_priv *priv;
750 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
751 priv = mlx4_priv(dev);
752 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
753 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
755 err = handle_counter(dev, qpc, slave, port);
759 if (MLX4_VGT != vp_oper->state.default_vlan) {
760 /* the reserved QPs (special, proxy, tunnel)
761 * do not operate over vlans
763 if (mlx4_is_qp_reserved(dev, qpn))
766 /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
767 if (qp_type == MLX4_QP_ST_UD ||
768 (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
769 if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
770 *(__be32 *)inbox->buf =
771 cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
772 MLX4_QP_OPTPAR_VLAN_STRIPPING);
773 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
775 struct mlx4_update_qp_params params = {.flags = 0};
777 err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, ¶ms);
783 /* preserve IF_COUNTER flag */
784 qpc->pri_path.vlan_control &=
785 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
786 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
787 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
788 qpc->pri_path.vlan_control |=
789 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
790 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
791 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
792 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
793 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
794 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
795 } else if (0 != vp_oper->state.default_vlan) {
796 qpc->pri_path.vlan_control |=
797 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
798 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
799 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
800 } else { /* priority tagged */
801 qpc->pri_path.vlan_control |=
802 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
803 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
806 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
807 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
808 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
809 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
810 qpc->pri_path.sched_queue &= 0xC7;
811 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
812 qpc->qos_vport = vp_oper->state.qos_vport;
814 if (vp_oper->state.spoofchk) {
815 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
816 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
822 static int mpt_mask(struct mlx4_dev *dev)
824 return dev->caps.num_mpts - 1;
827 static void *find_res(struct mlx4_dev *dev, u64 res_id,
828 enum mlx4_resource type)
830 struct mlx4_priv *priv = mlx4_priv(dev);
832 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
836 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
837 enum mlx4_resource type,
840 struct res_common *r;
843 spin_lock_irq(mlx4_tlock(dev));
844 r = find_res(dev, res_id, type);
850 if (r->state == RES_ANY_BUSY) {
855 if (r->owner != slave) {
860 r->from_state = r->state;
861 r->state = RES_ANY_BUSY;
864 *((struct res_common **)res) = r;
867 spin_unlock_irq(mlx4_tlock(dev));
871 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
872 enum mlx4_resource type,
873 u64 res_id, int *slave)
876 struct res_common *r;
882 spin_lock(mlx4_tlock(dev));
884 r = find_res(dev, id, type);
889 spin_unlock(mlx4_tlock(dev));
894 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
895 enum mlx4_resource type)
897 struct res_common *r;
899 spin_lock_irq(mlx4_tlock(dev));
900 r = find_res(dev, res_id, type);
902 r->state = r->from_state;
903 spin_unlock_irq(mlx4_tlock(dev));
906 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
907 u64 in_param, u64 *out_param, int port);
909 static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
912 struct res_common *r;
913 struct res_counter *counter;
916 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
919 spin_lock_irq(mlx4_tlock(dev));
920 r = find_res(dev, counter_index, RES_COUNTER);
921 if (!r || r->owner != slave) {
924 counter = container_of(r, struct res_counter, com);
926 counter->port = port;
929 spin_unlock_irq(mlx4_tlock(dev));
933 static int handle_unexisting_counter(struct mlx4_dev *dev,
934 struct mlx4_qp_context *qpc, u8 slave,
937 struct mlx4_priv *priv = mlx4_priv(dev);
938 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
939 struct res_common *tmp;
940 struct res_counter *counter;
941 u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
944 spin_lock_irq(mlx4_tlock(dev));
945 list_for_each_entry(tmp,
946 &tracker->slave_list[slave].res_list[RES_COUNTER],
948 counter = container_of(tmp, struct res_counter, com);
949 if (port == counter->port) {
950 qpc->pri_path.counter_index = counter->com.res_id;
951 spin_unlock_irq(mlx4_tlock(dev));
955 spin_unlock_irq(mlx4_tlock(dev));
957 /* No existing counter, need to allocate a new counter */
958 err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
960 if (err == -ENOENT) {
962 } else if (err && err != -ENOSPC) {
963 mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
964 __func__, slave, err);
966 qpc->pri_path.counter_index = counter_idx;
967 mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
968 __func__, slave, qpc->pri_path.counter_index);
975 static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
978 if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
979 return handle_existing_counter(dev, slave, port,
980 qpc->pri_path.counter_index);
982 return handle_unexisting_counter(dev, qpc, slave, port);
985 static struct res_common *alloc_qp_tr(int id)
989 ret = kzalloc(sizeof *ret, GFP_KERNEL);
993 ret->com.res_id = id;
994 ret->com.state = RES_QP_RESERVED;
996 INIT_LIST_HEAD(&ret->mcg_list);
997 spin_lock_init(&ret->mcg_spl);
998 atomic_set(&ret->ref_count, 0);
1003 static struct res_common *alloc_mtt_tr(int id, int order)
1005 struct res_mtt *ret;
1007 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1011 ret->com.res_id = id;
1013 ret->com.state = RES_MTT_ALLOCATED;
1014 atomic_set(&ret->ref_count, 0);
1019 static struct res_common *alloc_mpt_tr(int id, int key)
1021 struct res_mpt *ret;
1023 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1027 ret->com.res_id = id;
1028 ret->com.state = RES_MPT_RESERVED;
1034 static struct res_common *alloc_eq_tr(int id)
1038 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1042 ret->com.res_id = id;
1043 ret->com.state = RES_EQ_RESERVED;
1048 static struct res_common *alloc_cq_tr(int id)
1052 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1056 ret->com.res_id = id;
1057 ret->com.state = RES_CQ_ALLOCATED;
1058 atomic_set(&ret->ref_count, 0);
1063 static struct res_common *alloc_srq_tr(int id)
1065 struct res_srq *ret;
1067 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1071 ret->com.res_id = id;
1072 ret->com.state = RES_SRQ_ALLOCATED;
1073 atomic_set(&ret->ref_count, 0);
1078 static struct res_common *alloc_counter_tr(int id, int port)
1080 struct res_counter *ret;
1082 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1086 ret->com.res_id = id;
1087 ret->com.state = RES_COUNTER_ALLOCATED;
1093 static struct res_common *alloc_xrcdn_tr(int id)
1095 struct res_xrcdn *ret;
1097 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1101 ret->com.res_id = id;
1102 ret->com.state = RES_XRCD_ALLOCATED;
1107 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1109 struct res_fs_rule *ret;
1111 ret = kzalloc(sizeof *ret, GFP_KERNEL);
1115 ret->com.res_id = id;
1116 ret->com.state = RES_FS_RULE_ALLOCATED;
1121 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
1124 struct res_common *ret;
1128 ret = alloc_qp_tr(id);
1131 ret = alloc_mpt_tr(id, extra);
1134 ret = alloc_mtt_tr(id, extra);
1137 ret = alloc_eq_tr(id);
1140 ret = alloc_cq_tr(id);
1143 ret = alloc_srq_tr(id);
1146 pr_err("implementation missing\n");
1149 ret = alloc_counter_tr(id, extra);
1152 ret = alloc_xrcdn_tr(id);
1155 ret = alloc_fs_rule_tr(id, extra);
1166 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1167 struct mlx4_counter *data)
1169 struct mlx4_priv *priv = mlx4_priv(dev);
1170 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1171 struct res_common *tmp;
1172 struct res_counter *counter;
1176 memset(data, 0, sizeof(*data));
1178 counters_arr = kmalloc_array(dev->caps.max_counters,
1179 sizeof(*counters_arr), GFP_KERNEL);
1183 spin_lock_irq(mlx4_tlock(dev));
1184 list_for_each_entry(tmp,
1185 &tracker->slave_list[slave].res_list[RES_COUNTER],
1187 counter = container_of(tmp, struct res_counter, com);
1188 if (counter->port == port) {
1189 counters_arr[i] = (int)tmp->res_id;
1193 spin_unlock_irq(mlx4_tlock(dev));
1194 counters_arr[i] = -1;
1198 while (counters_arr[i] != -1) {
1199 err = mlx4_get_counter_stats(dev, counters_arr[i], data,
1202 memset(data, 0, sizeof(*data));
1209 kfree(counters_arr);
1213 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1214 enum mlx4_resource type, int extra)
1218 struct mlx4_priv *priv = mlx4_priv(dev);
1219 struct res_common **res_arr;
1220 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1221 struct rb_root *root = &tracker->res_tree[type];
1223 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1227 for (i = 0; i < count; ++i) {
1228 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1230 for (--i; i >= 0; --i)
1238 spin_lock_irq(mlx4_tlock(dev));
1239 for (i = 0; i < count; ++i) {
1240 if (find_res(dev, base + i, type)) {
1244 err = res_tracker_insert(root, res_arr[i]);
1247 list_add_tail(&res_arr[i]->list,
1248 &tracker->slave_list[slave].res_list[type]);
1250 spin_unlock_irq(mlx4_tlock(dev));
1256 for (--i; i >= 0; --i) {
1257 rb_erase(&res_arr[i]->node, root);
1258 list_del_init(&res_arr[i]->list);
1261 spin_unlock_irq(mlx4_tlock(dev));
1263 for (i = 0; i < count; ++i)
1271 static int remove_qp_ok(struct res_qp *res)
1273 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1274 !list_empty(&res->mcg_list)) {
1275 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1276 res->com.state, atomic_read(&res->ref_count));
1278 } else if (res->com.state != RES_QP_RESERVED) {
1285 static int remove_mtt_ok(struct res_mtt *res, int order)
1287 if (res->com.state == RES_MTT_BUSY ||
1288 atomic_read(&res->ref_count)) {
1289 pr_devel("%s-%d: state %s, ref_count %d\n",
1291 mtt_states_str(res->com.state),
1292 atomic_read(&res->ref_count));
1294 } else if (res->com.state != RES_MTT_ALLOCATED)
1296 else if (res->order != order)
1302 static int remove_mpt_ok(struct res_mpt *res)
1304 if (res->com.state == RES_MPT_BUSY)
1306 else if (res->com.state != RES_MPT_RESERVED)
1312 static int remove_eq_ok(struct res_eq *res)
1314 if (res->com.state == RES_MPT_BUSY)
1316 else if (res->com.state != RES_MPT_RESERVED)
1322 static int remove_counter_ok(struct res_counter *res)
1324 if (res->com.state == RES_COUNTER_BUSY)
1326 else if (res->com.state != RES_COUNTER_ALLOCATED)
1332 static int remove_xrcdn_ok(struct res_xrcdn *res)
1334 if (res->com.state == RES_XRCD_BUSY)
1336 else if (res->com.state != RES_XRCD_ALLOCATED)
1342 static int remove_fs_rule_ok(struct res_fs_rule *res)
1344 if (res->com.state == RES_FS_RULE_BUSY)
1346 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1352 static int remove_cq_ok(struct res_cq *res)
1354 if (res->com.state == RES_CQ_BUSY)
1356 else if (res->com.state != RES_CQ_ALLOCATED)
1362 static int remove_srq_ok(struct res_srq *res)
1364 if (res->com.state == RES_SRQ_BUSY)
1366 else if (res->com.state != RES_SRQ_ALLOCATED)
1372 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1376 return remove_qp_ok((struct res_qp *)res);
1378 return remove_cq_ok((struct res_cq *)res);
1380 return remove_srq_ok((struct res_srq *)res);
1382 return remove_mpt_ok((struct res_mpt *)res);
1384 return remove_mtt_ok((struct res_mtt *)res, extra);
1388 return remove_eq_ok((struct res_eq *)res);
1390 return remove_counter_ok((struct res_counter *)res);
1392 return remove_xrcdn_ok((struct res_xrcdn *)res);
1394 return remove_fs_rule_ok((struct res_fs_rule *)res);
1400 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1401 enum mlx4_resource type, int extra)
1405 struct mlx4_priv *priv = mlx4_priv(dev);
1406 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1407 struct res_common *r;
1409 spin_lock_irq(mlx4_tlock(dev));
1410 for (i = base; i < base + count; ++i) {
1411 r = res_tracker_lookup(&tracker->res_tree[type], i);
1416 if (r->owner != slave) {
1420 err = remove_ok(r, type, extra);
1425 for (i = base; i < base + count; ++i) {
1426 r = res_tracker_lookup(&tracker->res_tree[type], i);
1427 rb_erase(&r->node, &tracker->res_tree[type]);
1434 spin_unlock_irq(mlx4_tlock(dev));
1439 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1440 enum res_qp_states state, struct res_qp **qp,
1443 struct mlx4_priv *priv = mlx4_priv(dev);
1444 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1448 spin_lock_irq(mlx4_tlock(dev));
1449 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
1452 else if (r->com.owner != slave)
1457 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
1458 __func__, r->com.res_id);
1462 case RES_QP_RESERVED:
1463 if (r->com.state == RES_QP_MAPPED && !alloc)
1466 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
1471 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1472 r->com.state == RES_QP_HW)
1475 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
1483 if (r->com.state != RES_QP_MAPPED)
1491 r->com.from_state = r->com.state;
1492 r->com.to_state = state;
1493 r->com.state = RES_QP_BUSY;
1499 spin_unlock_irq(mlx4_tlock(dev));
1504 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1505 enum res_mpt_states state, struct res_mpt **mpt)
1507 struct mlx4_priv *priv = mlx4_priv(dev);
1508 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1512 spin_lock_irq(mlx4_tlock(dev));
1513 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
1516 else if (r->com.owner != slave)
1524 case RES_MPT_RESERVED:
1525 if (r->com.state != RES_MPT_MAPPED)
1529 case RES_MPT_MAPPED:
1530 if (r->com.state != RES_MPT_RESERVED &&
1531 r->com.state != RES_MPT_HW)
1536 if (r->com.state != RES_MPT_MAPPED)
1544 r->com.from_state = r->com.state;
1545 r->com.to_state = state;
1546 r->com.state = RES_MPT_BUSY;
1552 spin_unlock_irq(mlx4_tlock(dev));
1557 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1558 enum res_eq_states state, struct res_eq **eq)
1560 struct mlx4_priv *priv = mlx4_priv(dev);
1561 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1565 spin_lock_irq(mlx4_tlock(dev));
1566 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1569 else if (r->com.owner != slave)
1577 case RES_EQ_RESERVED:
1578 if (r->com.state != RES_EQ_HW)
1583 if (r->com.state != RES_EQ_RESERVED)
1592 r->com.from_state = r->com.state;
1593 r->com.to_state = state;
1594 r->com.state = RES_EQ_BUSY;
1600 spin_unlock_irq(mlx4_tlock(dev));
1605 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1606 enum res_cq_states state, struct res_cq **cq)
1608 struct mlx4_priv *priv = mlx4_priv(dev);
1609 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1613 spin_lock_irq(mlx4_tlock(dev));
1614 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1617 } else if (r->com.owner != slave) {
1619 } else if (state == RES_CQ_ALLOCATED) {
1620 if (r->com.state != RES_CQ_HW)
1622 else if (atomic_read(&r->ref_count))
1626 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1633 r->com.from_state = r->com.state;
1634 r->com.to_state = state;
1635 r->com.state = RES_CQ_BUSY;
1640 spin_unlock_irq(mlx4_tlock(dev));
1645 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1646 enum res_srq_states state, struct res_srq **srq)
1648 struct mlx4_priv *priv = mlx4_priv(dev);
1649 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1653 spin_lock_irq(mlx4_tlock(dev));
1654 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1657 } else if (r->com.owner != slave) {
1659 } else if (state == RES_SRQ_ALLOCATED) {
1660 if (r->com.state != RES_SRQ_HW)
1662 else if (atomic_read(&r->ref_count))
1664 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1669 r->com.from_state = r->com.state;
1670 r->com.to_state = state;
1671 r->com.state = RES_SRQ_BUSY;
1676 spin_unlock_irq(mlx4_tlock(dev));
1681 static void res_abort_move(struct mlx4_dev *dev, int slave,
1682 enum mlx4_resource type, int id)
1684 struct mlx4_priv *priv = mlx4_priv(dev);
1685 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1686 struct res_common *r;
1688 spin_lock_irq(mlx4_tlock(dev));
1689 r = res_tracker_lookup(&tracker->res_tree[type], id);
1690 if (r && (r->owner == slave))
1691 r->state = r->from_state;
1692 spin_unlock_irq(mlx4_tlock(dev));
1695 static void res_end_move(struct mlx4_dev *dev, int slave,
1696 enum mlx4_resource type, int id)
1698 struct mlx4_priv *priv = mlx4_priv(dev);
1699 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1700 struct res_common *r;
1702 spin_lock_irq(mlx4_tlock(dev));
1703 r = res_tracker_lookup(&tracker->res_tree[type], id);
1704 if (r && (r->owner == slave))
1705 r->state = r->to_state;
1706 spin_unlock_irq(mlx4_tlock(dev));
1709 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1711 return mlx4_is_qp_reserved(dev, qpn) &&
1712 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1715 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1717 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1720 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1721 u64 in_param, u64 *out_param)
1731 case RES_OP_RESERVE:
1732 count = get_param_l(&in_param) & 0xffffff;
1733 /* Turn off all unsupported QP allocation flags that the
1734 * slave tries to set.
1736 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
1737 align = get_param_h(&in_param);
1738 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
1742 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
1744 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1748 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1750 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1751 __mlx4_qp_release_range(dev, base, count);
1754 set_param_l(out_param, base);
1756 case RES_OP_MAP_ICM:
1757 qpn = get_param_l(&in_param) & 0x7fffff;
1758 if (valid_reserved(dev, slave, qpn)) {
1759 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1764 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1769 if (!fw_reserved(dev, qpn)) {
1770 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
1772 res_abort_move(dev, slave, RES_QP, qpn);
1777 res_end_move(dev, slave, RES_QP, qpn);
1787 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1788 u64 in_param, u64 *out_param)
1794 if (op != RES_OP_RESERVE_AND_MAP)
1797 order = get_param_l(&in_param);
1799 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1803 base = __mlx4_alloc_mtt_range(dev, order);
1805 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1809 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1811 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1812 __mlx4_free_mtt_range(dev, base, order);
1814 set_param_l(out_param, base);
1820 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1821 u64 in_param, u64 *out_param)
1826 struct res_mpt *mpt;
1829 case RES_OP_RESERVE:
1830 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1834 index = __mlx4_mpt_reserve(dev);
1836 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1839 id = index & mpt_mask(dev);
1841 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1843 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1844 __mlx4_mpt_release(dev, index);
1847 set_param_l(out_param, index);
1849 case RES_OP_MAP_ICM:
1850 index = get_param_l(&in_param);
1851 id = index & mpt_mask(dev);
1852 err = mr_res_start_move_to(dev, slave, id,
1853 RES_MPT_MAPPED, &mpt);
1857 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
1859 res_abort_move(dev, slave, RES_MPT, id);
1863 res_end_move(dev, slave, RES_MPT, id);
1869 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1870 u64 in_param, u64 *out_param)
1876 case RES_OP_RESERVE_AND_MAP:
1877 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
1881 err = __mlx4_cq_alloc_icm(dev, &cqn);
1883 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1887 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1889 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1890 __mlx4_cq_free_icm(dev, cqn);
1894 set_param_l(out_param, cqn);
1904 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1905 u64 in_param, u64 *out_param)
1911 case RES_OP_RESERVE_AND_MAP:
1912 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
1916 err = __mlx4_srq_alloc_icm(dev, &srqn);
1918 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1922 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1924 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1925 __mlx4_srq_free_icm(dev, srqn);
1929 set_param_l(out_param, srqn);
1939 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1940 u8 smac_index, u64 *mac)
1942 struct mlx4_priv *priv = mlx4_priv(dev);
1943 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1944 struct list_head *mac_list =
1945 &tracker->slave_list[slave].res_list[RES_MAC];
1946 struct mac_res *res, *tmp;
1948 list_for_each_entry_safe(res, tmp, mac_list, list) {
1949 if (res->smac_index == smac_index && res->port == (u8) port) {
1957 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
1959 struct mlx4_priv *priv = mlx4_priv(dev);
1960 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1961 struct list_head *mac_list =
1962 &tracker->slave_list[slave].res_list[RES_MAC];
1963 struct mac_res *res, *tmp;
1965 list_for_each_entry_safe(res, tmp, mac_list, list) {
1966 if (res->mac == mac && res->port == (u8) port) {
1967 /* mac found. update ref count */
1973 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1975 res = kzalloc(sizeof *res, GFP_KERNEL);
1977 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1981 res->port = (u8) port;
1982 res->smac_index = smac_index;
1984 list_add_tail(&res->list,
1985 &tracker->slave_list[slave].res_list[RES_MAC]);
1989 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1992 struct mlx4_priv *priv = mlx4_priv(dev);
1993 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1994 struct list_head *mac_list =
1995 &tracker->slave_list[slave].res_list[RES_MAC];
1996 struct mac_res *res, *tmp;
1998 list_for_each_entry_safe(res, tmp, mac_list, list) {
1999 if (res->mac == mac && res->port == (u8) port) {
2000 if (!--res->ref_count) {
2001 list_del(&res->list);
2002 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
2010 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
2012 struct mlx4_priv *priv = mlx4_priv(dev);
2013 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2014 struct list_head *mac_list =
2015 &tracker->slave_list[slave].res_list[RES_MAC];
2016 struct mac_res *res, *tmp;
2019 list_for_each_entry_safe(res, tmp, mac_list, list) {
2020 list_del(&res->list);
2021 /* dereference the mac the num times the slave referenced it */
2022 for (i = 0; i < res->ref_count; i++)
2023 __mlx4_unregister_mac(dev, res->port, res->mac);
2024 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
2029 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2030 u64 in_param, u64 *out_param, int in_port)
2037 if (op != RES_OP_RESERVE_AND_MAP)
2040 port = !in_port ? get_param_l(out_param) : in_port;
2041 port = mlx4_slave_convert_port(
2048 err = __mlx4_register_mac(dev, port, mac);
2051 set_param_l(out_param, err);
2056 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
2058 __mlx4_unregister_mac(dev, port, mac);
2063 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2064 int port, int vlan_index)
2066 struct mlx4_priv *priv = mlx4_priv(dev);
2067 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2068 struct list_head *vlan_list =
2069 &tracker->slave_list[slave].res_list[RES_VLAN];
2070 struct vlan_res *res, *tmp;
2072 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2073 if (res->vlan == vlan && res->port == (u8) port) {
2074 /* vlan found. update ref count */
2080 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
2082 res = kzalloc(sizeof(*res), GFP_KERNEL);
2084 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
2088 res->port = (u8) port;
2089 res->vlan_index = vlan_index;
2091 list_add_tail(&res->list,
2092 &tracker->slave_list[slave].res_list[RES_VLAN]);
2097 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
2100 struct mlx4_priv *priv = mlx4_priv(dev);
2101 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2102 struct list_head *vlan_list =
2103 &tracker->slave_list[slave].res_list[RES_VLAN];
2104 struct vlan_res *res, *tmp;
2106 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2107 if (res->vlan == vlan && res->port == (u8) port) {
2108 if (!--res->ref_count) {
2109 list_del(&res->list);
2110 mlx4_release_resource(dev, slave, RES_VLAN,
2119 static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
2121 struct mlx4_priv *priv = mlx4_priv(dev);
2122 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2123 struct list_head *vlan_list =
2124 &tracker->slave_list[slave].res_list[RES_VLAN];
2125 struct vlan_res *res, *tmp;
2128 list_for_each_entry_safe(res, tmp, vlan_list, list) {
2129 list_del(&res->list);
2130 /* dereference the vlan the num times the slave referenced it */
2131 for (i = 0; i < res->ref_count; i++)
2132 __mlx4_unregister_vlan(dev, res->port, res->vlan);
2133 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
2138 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2139 u64 in_param, u64 *out_param, int in_port)
2141 struct mlx4_priv *priv = mlx4_priv(dev);
2142 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2148 port = !in_port ? get_param_l(out_param) : in_port;
2150 if (!port || op != RES_OP_RESERVE_AND_MAP)
2153 port = mlx4_slave_convert_port(
2158 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
2159 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
2160 slave_state[slave].old_vlan_api = true;
2164 vlan = (u16) in_param;
2166 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
2168 set_param_l(out_param, (u32) vlan_index);
2169 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
2171 __mlx4_unregister_vlan(dev, port, vlan);
2176 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2177 u64 in_param, u64 *out_param, int port)
2182 if (op != RES_OP_RESERVE)
2185 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
2189 err = __mlx4_counter_alloc(dev, &index);
2191 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2195 err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
2197 __mlx4_counter_free(dev, index);
2198 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2200 set_param_l(out_param, index);
2206 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2207 u64 in_param, u64 *out_param)
2212 if (op != RES_OP_RESERVE)
2215 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2219 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2221 __mlx4_xrcd_free(dev, xrcdn);
2223 set_param_l(out_param, xrcdn);
2228 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2229 struct mlx4_vhcr *vhcr,
2230 struct mlx4_cmd_mailbox *inbox,
2231 struct mlx4_cmd_mailbox *outbox,
2232 struct mlx4_cmd_info *cmd)
2235 int alop = vhcr->op_modifier;
2237 switch (vhcr->in_modifier & 0xFF) {
2239 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2240 vhcr->in_param, &vhcr->out_param);
2244 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2245 vhcr->in_param, &vhcr->out_param);
2249 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2250 vhcr->in_param, &vhcr->out_param);
2254 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2255 vhcr->in_param, &vhcr->out_param);
2259 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2260 vhcr->in_param, &vhcr->out_param);
2264 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
2265 vhcr->in_param, &vhcr->out_param,
2266 (vhcr->in_modifier >> 8) & 0xFF);
2270 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
2271 vhcr->in_param, &vhcr->out_param,
2272 (vhcr->in_modifier >> 8) & 0xFF);
2276 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2277 vhcr->in_param, &vhcr->out_param, 0);
2281 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2282 vhcr->in_param, &vhcr->out_param);
2293 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2302 case RES_OP_RESERVE:
2303 base = get_param_l(&in_param) & 0x7fffff;
2304 count = get_param_h(&in_param);
2305 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2308 mlx4_release_resource(dev, slave, RES_QP, count, 0);
2309 __mlx4_qp_release_range(dev, base, count);
2311 case RES_OP_MAP_ICM:
2312 qpn = get_param_l(&in_param) & 0x7fffff;
2313 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2318 if (!fw_reserved(dev, qpn))
2319 __mlx4_qp_free_icm(dev, qpn);
2321 res_end_move(dev, slave, RES_QP, qpn);
2323 if (valid_reserved(dev, slave, qpn))
2324 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2333 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2334 u64 in_param, u64 *out_param)
2340 if (op != RES_OP_RESERVE_AND_MAP)
2343 base = get_param_l(&in_param);
2344 order = get_param_h(&in_param);
2345 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
2347 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
2348 __mlx4_free_mtt_range(dev, base, order);
2353 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2359 struct res_mpt *mpt;
2362 case RES_OP_RESERVE:
2363 index = get_param_l(&in_param);
2364 id = index & mpt_mask(dev);
2365 err = get_res(dev, slave, id, RES_MPT, &mpt);
2369 put_res(dev, slave, id, RES_MPT);
2371 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2374 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
2375 __mlx4_mpt_release(dev, index);
2377 case RES_OP_MAP_ICM:
2378 index = get_param_l(&in_param);
2379 id = index & mpt_mask(dev);
2380 err = mr_res_start_move_to(dev, slave, id,
2381 RES_MPT_RESERVED, &mpt);
2385 __mlx4_mpt_free_icm(dev, mpt->key);
2386 res_end_move(dev, slave, RES_MPT, id);
2396 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2397 u64 in_param, u64 *out_param)
2403 case RES_OP_RESERVE_AND_MAP:
2404 cqn = get_param_l(&in_param);
2405 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2409 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
2410 __mlx4_cq_free_icm(dev, cqn);
2421 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2422 u64 in_param, u64 *out_param)
2428 case RES_OP_RESERVE_AND_MAP:
2429 srqn = get_param_l(&in_param);
2430 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2434 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
2435 __mlx4_srq_free_icm(dev, srqn);
2446 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2447 u64 in_param, u64 *out_param, int in_port)
2453 case RES_OP_RESERVE_AND_MAP:
2454 port = !in_port ? get_param_l(out_param) : in_port;
2455 port = mlx4_slave_convert_port(
2460 mac_del_from_slave(dev, slave, in_param, port);
2461 __mlx4_unregister_mac(dev, port, in_param);
2472 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2473 u64 in_param, u64 *out_param, int port)
2475 struct mlx4_priv *priv = mlx4_priv(dev);
2476 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2479 port = mlx4_slave_convert_port(
2485 case RES_OP_RESERVE_AND_MAP:
2486 if (slave_state[slave].old_vlan_api)
2490 vlan_del_from_slave(dev, slave, in_param, port);
2491 __mlx4_unregister_vlan(dev, port, in_param);
2501 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2502 u64 in_param, u64 *out_param)
2507 if (op != RES_OP_RESERVE)
2510 index = get_param_l(&in_param);
2511 if (index == MLX4_SINK_COUNTER_INDEX(dev))
2514 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2518 __mlx4_counter_free(dev, index);
2519 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
2524 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2525 u64 in_param, u64 *out_param)
2530 if (op != RES_OP_RESERVE)
2533 xrcdn = get_param_l(&in_param);
2534 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2538 __mlx4_xrcd_free(dev, xrcdn);
2543 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2544 struct mlx4_vhcr *vhcr,
2545 struct mlx4_cmd_mailbox *inbox,
2546 struct mlx4_cmd_mailbox *outbox,
2547 struct mlx4_cmd_info *cmd)
2550 int alop = vhcr->op_modifier;
2552 switch (vhcr->in_modifier & 0xFF) {
2554 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2559 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2560 vhcr->in_param, &vhcr->out_param);
2564 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2569 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2570 vhcr->in_param, &vhcr->out_param);
2574 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2575 vhcr->in_param, &vhcr->out_param);
2579 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
2580 vhcr->in_param, &vhcr->out_param,
2581 (vhcr->in_modifier >> 8) & 0xFF);
2585 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
2586 vhcr->in_param, &vhcr->out_param,
2587 (vhcr->in_modifier >> 8) & 0xFF);
2591 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2592 vhcr->in_param, &vhcr->out_param);
2596 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2597 vhcr->in_param, &vhcr->out_param);
2605 /* ugly but other choices are uglier */
2606 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2608 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2611 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
2613 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
2616 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2618 return be32_to_cpu(mpt->mtt_sz);
2621 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2623 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2626 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2628 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2631 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2633 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2636 static int mr_is_region(struct mlx4_mpt_entry *mpt)
2638 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2641 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
2643 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2646 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
2648 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2651 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2653 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2654 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2655 int log_sq_sride = qpc->sq_size_stride & 7;
2656 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2657 int log_rq_stride = qpc->rq_size_stride & 7;
2658 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2659 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
2660 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2661 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
2666 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2669 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2670 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2671 total_mem = sq_size + rq_size;
2672 tot = (total_mem + (page_offset << 6)) >> page_shift;
2673 total_pages = !tot ? 1 : roundup_pow_of_two(tot);
2678 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2679 int size, struct res_mtt *mtt)
2681 int res_start = mtt->com.res_id;
2682 int res_size = (1 << mtt->order);
2684 if (start < res_start || start + size > res_start + res_size)
2689 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2690 struct mlx4_vhcr *vhcr,
2691 struct mlx4_cmd_mailbox *inbox,
2692 struct mlx4_cmd_mailbox *outbox,
2693 struct mlx4_cmd_info *cmd)
2696 int index = vhcr->in_modifier;
2697 struct res_mtt *mtt;
2698 struct res_mpt *mpt;
2699 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
2705 id = index & mpt_mask(dev);
2706 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2710 /* Disable memory windows for VFs. */
2711 if (!mr_is_region(inbox->buf)) {
2716 /* Make sure that the PD bits related to the slave id are zeros. */
2717 pd = mr_get_pd(inbox->buf);
2718 pd_slave = (pd >> 17) & 0x7f;
2719 if (pd_slave != 0 && --pd_slave != slave) {
2724 if (mr_is_fmr(inbox->buf)) {
2725 /* FMR and Bind Enable are forbidden in slave devices. */
2726 if (mr_is_bind_enabled(inbox->buf)) {
2730 /* FMR and Memory Windows are also forbidden. */
2731 if (!mr_is_region(inbox->buf)) {
2737 phys = mr_phys_mpt(inbox->buf);
2739 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2743 err = check_mtt_range(dev, slave, mtt_base,
2744 mr_get_mtt_size(inbox->buf), mtt);
2751 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2756 atomic_inc(&mtt->ref_count);
2757 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2760 res_end_move(dev, slave, RES_MPT, id);
2765 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2767 res_abort_move(dev, slave, RES_MPT, id);
2772 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2773 struct mlx4_vhcr *vhcr,
2774 struct mlx4_cmd_mailbox *inbox,
2775 struct mlx4_cmd_mailbox *outbox,
2776 struct mlx4_cmd_info *cmd)
2779 int index = vhcr->in_modifier;
2780 struct res_mpt *mpt;
2783 id = index & mpt_mask(dev);
2784 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2788 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2793 atomic_dec(&mpt->mtt->ref_count);
2795 res_end_move(dev, slave, RES_MPT, id);
2799 res_abort_move(dev, slave, RES_MPT, id);
2804 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2805 struct mlx4_vhcr *vhcr,
2806 struct mlx4_cmd_mailbox *inbox,
2807 struct mlx4_cmd_mailbox *outbox,
2808 struct mlx4_cmd_info *cmd)
2811 int index = vhcr->in_modifier;
2812 struct res_mpt *mpt;
2815 id = index & mpt_mask(dev);
2816 err = get_res(dev, slave, id, RES_MPT, &mpt);
2820 if (mpt->com.from_state == RES_MPT_MAPPED) {
2821 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2822 * that, the VF must read the MPT. But since the MPT entry memory is not
2823 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2824 * entry contents. To guarantee that the MPT cannot be changed, the driver
2825 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2826 * ownership fofollowing the change. The change here allows the VF to
2827 * perform QUERY_MPT also when the entry is in SW ownership.
2829 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2830 &mlx4_priv(dev)->mr_table.dmpt_table,
2833 if (NULL == mpt_entry || NULL == outbox->buf) {
2838 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2841 } else if (mpt->com.from_state == RES_MPT_HW) {
2842 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2850 put_res(dev, slave, id, RES_MPT);
2854 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2856 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2859 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2861 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2864 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2866 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2869 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2870 struct mlx4_qp_context *context)
2872 u32 qpn = vhcr->in_modifier & 0xffffff;
2875 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2878 /* adjust qkey in qp context */
2879 context->qkey = cpu_to_be32(qkey);
2882 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
2883 struct mlx4_qp_context *qpc,
2884 struct mlx4_cmd_mailbox *inbox);
2886 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2887 struct mlx4_vhcr *vhcr,
2888 struct mlx4_cmd_mailbox *inbox,
2889 struct mlx4_cmd_mailbox *outbox,
2890 struct mlx4_cmd_info *cmd)
2893 int qpn = vhcr->in_modifier & 0x7fffff;
2894 struct res_mtt *mtt;
2896 struct mlx4_qp_context *qpc = inbox->buf + 8;
2897 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2898 int mtt_size = qp_get_mtt_size(qpc);
2901 int rcqn = qp_get_rcqn(qpc);
2902 int scqn = qp_get_scqn(qpc);
2903 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2904 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2905 struct res_srq *srq;
2906 int local_qpn = vhcr->in_modifier & 0xffffff;
2908 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
2912 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2915 qp->local_qpn = local_qpn;
2916 qp->sched_queue = 0;
2918 qp->vlan_control = 0;
2920 qp->pri_path_fl = 0;
2923 qp->qpc_flags = be32_to_cpu(qpc->flags);
2925 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2929 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2933 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2938 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2945 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2950 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2951 update_pkey_index(dev, slave, inbox);
2952 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2955 atomic_inc(&mtt->ref_count);
2957 atomic_inc(&rcq->ref_count);
2959 atomic_inc(&scq->ref_count);
2963 put_res(dev, slave, scqn, RES_CQ);
2966 atomic_inc(&srq->ref_count);
2967 put_res(dev, slave, srqn, RES_SRQ);
2971 /* Save param3 for dynamic changes from VST back to VGT */
2972 qp->param3 = qpc->param3;
2973 put_res(dev, slave, rcqn, RES_CQ);
2974 put_res(dev, slave, mtt_base, RES_MTT);
2975 res_end_move(dev, slave, RES_QP, qpn);
2981 put_res(dev, slave, srqn, RES_SRQ);
2984 put_res(dev, slave, scqn, RES_CQ);
2986 put_res(dev, slave, rcqn, RES_CQ);
2988 put_res(dev, slave, mtt_base, RES_MTT);
2990 res_abort_move(dev, slave, RES_QP, qpn);
2995 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
2997 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
3000 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
3002 int log_eq_size = eqc->log_eq_size & 0x1f;
3003 int page_shift = (eqc->log_page_size & 0x3f) + 12;
3005 if (log_eq_size + 5 < page_shift)
3008 return 1 << (log_eq_size + 5 - page_shift);
3011 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
3013 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
3016 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
3018 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
3019 int page_shift = (cqc->log_page_size & 0x3f) + 12;
3021 if (log_cq_size + 5 < page_shift)
3024 return 1 << (log_cq_size + 5 - page_shift);
3027 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3028 struct mlx4_vhcr *vhcr,
3029 struct mlx4_cmd_mailbox *inbox,
3030 struct mlx4_cmd_mailbox *outbox,
3031 struct mlx4_cmd_info *cmd)
3034 int eqn = vhcr->in_modifier;
3035 int res_id = (slave << 10) | eqn;
3036 struct mlx4_eq_context *eqc = inbox->buf;
3037 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
3038 int mtt_size = eq_get_mtt_size(eqc);
3040 struct res_mtt *mtt;
3042 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3045 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
3049 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3053 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
3057 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3061 atomic_inc(&mtt->ref_count);
3063 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3064 res_end_move(dev, slave, RES_EQ, res_id);
3068 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3070 res_abort_move(dev, slave, RES_EQ, res_id);
3072 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3076 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
3077 struct mlx4_vhcr *vhcr,
3078 struct mlx4_cmd_mailbox *inbox,
3079 struct mlx4_cmd_mailbox *outbox,
3080 struct mlx4_cmd_info *cmd)
3083 u8 get = vhcr->op_modifier;
3088 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3093 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
3094 int len, struct res_mtt **res)
3096 struct mlx4_priv *priv = mlx4_priv(dev);
3097 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3098 struct res_mtt *mtt;
3101 spin_lock_irq(mlx4_tlock(dev));
3102 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
3104 if (!check_mtt_range(dev, slave, start, len, mtt)) {
3106 mtt->com.from_state = mtt->com.state;
3107 mtt->com.state = RES_MTT_BUSY;
3112 spin_unlock_irq(mlx4_tlock(dev));
3117 static int verify_qp_parameters(struct mlx4_dev *dev,
3118 struct mlx4_vhcr *vhcr,
3119 struct mlx4_cmd_mailbox *inbox,
3120 enum qp_transition transition, u8 slave)
3124 struct mlx4_qp_context *qp_ctx;
3125 enum mlx4_qp_optpar optpar;
3129 qp_ctx = inbox->buf + 8;
3130 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
3131 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
3133 if (slave != mlx4_master_func_num(dev)) {
3134 qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
3135 /* setting QP rate-limit is disallowed for VFs */
3136 if (qp_ctx->rate_limit_params)
3142 case MLX4_QP_ST_XRC:
3144 switch (transition) {
3145 case QP_TRANS_INIT2RTR:
3146 case QP_TRANS_RTR2RTS:
3147 case QP_TRANS_RTS2RTS:
3148 case QP_TRANS_SQD2SQD:
3149 case QP_TRANS_SQD2RTS:
3150 if (slave != mlx4_master_func_num(dev)) {
3151 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
3152 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3153 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3154 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3157 if (qp_ctx->pri_path.mgid_index >= num_gids)
3160 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3161 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
3162 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
3163 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
3166 if (qp_ctx->alt_path.mgid_index >= num_gids)
3176 case MLX4_QP_ST_MLX:
3177 qpn = vhcr->in_modifier & 0x7fffff;
3178 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
3179 if (transition == QP_TRANS_INIT2RTR &&
3180 slave != mlx4_master_func_num(dev) &&
3181 mlx4_is_qp_reserved(dev, qpn) &&
3182 !mlx4_vf_smi_enabled(dev, slave, port)) {
3183 /* only enabled VFs may create MLX proxy QPs */
3184 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
3185 __func__, slave, port);
3197 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
3198 struct mlx4_vhcr *vhcr,
3199 struct mlx4_cmd_mailbox *inbox,
3200 struct mlx4_cmd_mailbox *outbox,
3201 struct mlx4_cmd_info *cmd)
3203 struct mlx4_mtt mtt;
3204 __be64 *page_list = inbox->buf;
3205 u64 *pg_list = (u64 *)page_list;
3207 struct res_mtt *rmtt = NULL;
3208 int start = be64_to_cpu(page_list[0]);
3209 int npages = vhcr->in_modifier;
3212 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
3216 /* Call the SW implementation of write_mtt:
3217 * - Prepare a dummy mtt struct
3218 * - Translate inbox contents to simple addresses in host endianness */
3219 mtt.offset = 0; /* TBD this is broken but I don't handle it since
3220 we don't really use it */
3223 for (i = 0; i < npages; ++i)
3224 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
3226 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
3227 ((u64 *)page_list + 2));
3230 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
3235 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
3236 struct mlx4_vhcr *vhcr,
3237 struct mlx4_cmd_mailbox *inbox,
3238 struct mlx4_cmd_mailbox *outbox,
3239 struct mlx4_cmd_info *cmd)
3241 int eqn = vhcr->in_modifier;
3242 int res_id = eqn | (slave << 10);
3246 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3250 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3254 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3258 atomic_dec(&eq->mtt->ref_count);
3259 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3260 res_end_move(dev, slave, RES_EQ, res_id);
3261 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3266 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3268 res_abort_move(dev, slave, RES_EQ, res_id);
3273 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3275 struct mlx4_priv *priv = mlx4_priv(dev);
3276 struct mlx4_slave_event_eq_info *event_eq;
3277 struct mlx4_cmd_mailbox *mailbox;
3278 u32 in_modifier = 0;
3283 if (!priv->mfunc.master.slave_state)
3286 /* check for slave valid, slave not PF, and slave active */
3287 if (slave < 0 || slave > dev->persist->num_vfs ||
3288 slave == dev->caps.function ||
3289 !priv->mfunc.master.slave_state[slave].active)
3292 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
3294 /* Create the event only if the slave is registered */
3295 if (event_eq->eqn < 0)
3298 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3299 res_id = (slave << 10) | event_eq->eqn;
3300 err = get_res(dev, slave, res_id, RES_EQ, &req);
3304 if (req->com.from_state != RES_EQ_HW) {
3309 mailbox = mlx4_alloc_cmd_mailbox(dev);
3310 if (IS_ERR(mailbox)) {
3311 err = PTR_ERR(mailbox);
3315 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3317 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3320 memcpy(mailbox->buf, (u8 *) eqe, 28);
3322 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
3324 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3325 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3328 put_res(dev, slave, res_id, RES_EQ);
3329 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3330 mlx4_free_cmd_mailbox(dev, mailbox);
3334 put_res(dev, slave, res_id, RES_EQ);
3337 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3341 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3342 struct mlx4_vhcr *vhcr,
3343 struct mlx4_cmd_mailbox *inbox,
3344 struct mlx4_cmd_mailbox *outbox,
3345 struct mlx4_cmd_info *cmd)
3347 int eqn = vhcr->in_modifier;
3348 int res_id = eqn | (slave << 10);
3352 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3356 if (eq->com.from_state != RES_EQ_HW) {
3361 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3364 put_res(dev, slave, res_id, RES_EQ);
3368 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3369 struct mlx4_vhcr *vhcr,
3370 struct mlx4_cmd_mailbox *inbox,
3371 struct mlx4_cmd_mailbox *outbox,
3372 struct mlx4_cmd_info *cmd)
3375 int cqn = vhcr->in_modifier;
3376 struct mlx4_cq_context *cqc = inbox->buf;
3377 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3378 struct res_cq *cq = NULL;
3379 struct res_mtt *mtt;
3381 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3384 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3387 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3390 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3393 atomic_inc(&mtt->ref_count);
3395 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3396 res_end_move(dev, slave, RES_CQ, cqn);
3400 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3402 res_abort_move(dev, slave, RES_CQ, cqn);
3406 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3407 struct mlx4_vhcr *vhcr,
3408 struct mlx4_cmd_mailbox *inbox,
3409 struct mlx4_cmd_mailbox *outbox,
3410 struct mlx4_cmd_info *cmd)
3413 int cqn = vhcr->in_modifier;
3414 struct res_cq *cq = NULL;
3416 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3419 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3422 atomic_dec(&cq->mtt->ref_count);
3423 res_end_move(dev, slave, RES_CQ, cqn);
3427 res_abort_move(dev, slave, RES_CQ, cqn);
3431 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3432 struct mlx4_vhcr *vhcr,
3433 struct mlx4_cmd_mailbox *inbox,
3434 struct mlx4_cmd_mailbox *outbox,
3435 struct mlx4_cmd_info *cmd)
3437 int cqn = vhcr->in_modifier;
3441 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3445 if (cq->com.from_state != RES_CQ_HW)
3448 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3450 put_res(dev, slave, cqn, RES_CQ);
3455 static int handle_resize(struct mlx4_dev *dev, int slave,
3456 struct mlx4_vhcr *vhcr,
3457 struct mlx4_cmd_mailbox *inbox,
3458 struct mlx4_cmd_mailbox *outbox,
3459 struct mlx4_cmd_info *cmd,
3463 struct res_mtt *orig_mtt;
3464 struct res_mtt *mtt;
3465 struct mlx4_cq_context *cqc = inbox->buf;
3466 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3468 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3472 if (orig_mtt != cq->mtt) {
3477 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3481 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3484 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3487 atomic_dec(&orig_mtt->ref_count);
3488 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3489 atomic_inc(&mtt->ref_count);
3491 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3495 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3497 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3503 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3504 struct mlx4_vhcr *vhcr,
3505 struct mlx4_cmd_mailbox *inbox,
3506 struct mlx4_cmd_mailbox *outbox,
3507 struct mlx4_cmd_info *cmd)
3509 int cqn = vhcr->in_modifier;
3513 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3517 if (cq->com.from_state != RES_CQ_HW)
3520 if (vhcr->op_modifier == 0) {
3521 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
3525 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3527 put_res(dev, slave, cqn, RES_CQ);
3532 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3534 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3535 int log_rq_stride = srqc->logstride & 7;
3536 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3538 if (log_srq_size + log_rq_stride + 4 < page_shift)
3541 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3544 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3545 struct mlx4_vhcr *vhcr,
3546 struct mlx4_cmd_mailbox *inbox,
3547 struct mlx4_cmd_mailbox *outbox,
3548 struct mlx4_cmd_info *cmd)
3551 int srqn = vhcr->in_modifier;
3552 struct res_mtt *mtt;
3553 struct res_srq *srq = NULL;
3554 struct mlx4_srq_context *srqc = inbox->buf;
3555 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
3557 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3560 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3563 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3566 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3571 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3575 atomic_inc(&mtt->ref_count);
3577 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3578 res_end_move(dev, slave, RES_SRQ, srqn);
3582 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3584 res_abort_move(dev, slave, RES_SRQ, srqn);
3589 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3590 struct mlx4_vhcr *vhcr,
3591 struct mlx4_cmd_mailbox *inbox,
3592 struct mlx4_cmd_mailbox *outbox,
3593 struct mlx4_cmd_info *cmd)
3596 int srqn = vhcr->in_modifier;
3597 struct res_srq *srq = NULL;
3599 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3602 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3605 atomic_dec(&srq->mtt->ref_count);
3607 atomic_dec(&srq->cq->ref_count);
3608 res_end_move(dev, slave, RES_SRQ, srqn);
3613 res_abort_move(dev, slave, RES_SRQ, srqn);
3618 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3619 struct mlx4_vhcr *vhcr,
3620 struct mlx4_cmd_mailbox *inbox,
3621 struct mlx4_cmd_mailbox *outbox,
3622 struct mlx4_cmd_info *cmd)
3625 int srqn = vhcr->in_modifier;
3626 struct res_srq *srq;
3628 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3631 if (srq->com.from_state != RES_SRQ_HW) {
3635 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3637 put_res(dev, slave, srqn, RES_SRQ);
3641 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3642 struct mlx4_vhcr *vhcr,
3643 struct mlx4_cmd_mailbox *inbox,
3644 struct mlx4_cmd_mailbox *outbox,
3645 struct mlx4_cmd_info *cmd)
3648 int srqn = vhcr->in_modifier;
3649 struct res_srq *srq;
3651 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3655 if (srq->com.from_state != RES_SRQ_HW) {
3660 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3662 put_res(dev, slave, srqn, RES_SRQ);
3666 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3667 struct mlx4_vhcr *vhcr,
3668 struct mlx4_cmd_mailbox *inbox,
3669 struct mlx4_cmd_mailbox *outbox,
3670 struct mlx4_cmd_info *cmd)
3673 int qpn = vhcr->in_modifier & 0x7fffff;
3676 err = get_res(dev, slave, qpn, RES_QP, &qp);
3679 if (qp->com.from_state != RES_QP_HW) {
3684 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3686 put_res(dev, slave, qpn, RES_QP);
3690 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3691 struct mlx4_vhcr *vhcr,
3692 struct mlx4_cmd_mailbox *inbox,
3693 struct mlx4_cmd_mailbox *outbox,
3694 struct mlx4_cmd_info *cmd)
3696 struct mlx4_qp_context *context = inbox->buf + 8;
3697 adjust_proxy_tun_qkey(dev, vhcr, context);
3698 update_pkey_index(dev, slave, inbox);
3699 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3702 static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3703 struct mlx4_qp_context *qpc,
3704 struct mlx4_cmd_mailbox *inbox)
3706 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3708 int port = mlx4_slave_convert_port(
3709 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3714 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3717 if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
3718 qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
3719 qpc->pri_path.sched_queue = pri_sched_queue;
3722 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3723 port = mlx4_slave_convert_port(
3724 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3728 qpc->alt_path.sched_queue =
3729 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3735 static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3736 struct mlx4_qp_context *qpc,
3737 struct mlx4_cmd_mailbox *inbox)
3741 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3742 u8 sched = *(u8 *)(inbox->buf + 64);
3745 port = (sched >> 6 & 1) + 1;
3746 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3747 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3748 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3754 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3755 struct mlx4_vhcr *vhcr,
3756 struct mlx4_cmd_mailbox *inbox,
3757 struct mlx4_cmd_mailbox *outbox,
3758 struct mlx4_cmd_info *cmd)
3761 struct mlx4_qp_context *qpc = inbox->buf + 8;
3762 int qpn = vhcr->in_modifier & 0x7fffff;
3764 u8 orig_sched_queue;
3765 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3766 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3767 u8 orig_pri_path_fl = qpc->pri_path.fl;
3768 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3769 u8 orig_feup = qpc->pri_path.feup;
3771 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3774 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
3778 if (roce_verify_mac(dev, slave, qpc, inbox))
3781 update_pkey_index(dev, slave, inbox);
3782 update_gid(dev, inbox, (u8)slave);
3783 adjust_proxy_tun_qkey(dev, vhcr, qpc);
3784 orig_sched_queue = qpc->pri_path.sched_queue;
3786 err = get_res(dev, slave, qpn, RES_QP, &qp);
3789 if (qp->com.from_state != RES_QP_HW) {
3794 err = update_vport_qp_param(dev, inbox, slave, qpn);
3798 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3800 /* if no error, save sched queue value passed in by VF. This is
3801 * essentially the QOS value provided by the VF. This will be useful
3802 * if we allow dynamic changes from VST back to VGT
3805 qp->sched_queue = orig_sched_queue;
3806 qp->vlan_control = orig_vlan_control;
3807 qp->fvl_rx = orig_fvl_rx;
3808 qp->pri_path_fl = orig_pri_path_fl;
3809 qp->vlan_index = orig_vlan_index;
3810 qp->feup = orig_feup;
3812 put_res(dev, slave, qpn, RES_QP);
3816 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3817 struct mlx4_vhcr *vhcr,
3818 struct mlx4_cmd_mailbox *inbox,
3819 struct mlx4_cmd_mailbox *outbox,
3820 struct mlx4_cmd_info *cmd)
3823 struct mlx4_qp_context *context = inbox->buf + 8;
3825 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3828 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
3832 update_pkey_index(dev, slave, inbox);
3833 update_gid(dev, inbox, (u8)slave);
3834 adjust_proxy_tun_qkey(dev, vhcr, context);
3835 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3838 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3839 struct mlx4_vhcr *vhcr,
3840 struct mlx4_cmd_mailbox *inbox,
3841 struct mlx4_cmd_mailbox *outbox,
3842 struct mlx4_cmd_info *cmd)
3845 struct mlx4_qp_context *context = inbox->buf + 8;
3847 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3850 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
3854 update_pkey_index(dev, slave, inbox);
3855 update_gid(dev, inbox, (u8)slave);
3856 adjust_proxy_tun_qkey(dev, vhcr, context);
3857 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3861 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3862 struct mlx4_vhcr *vhcr,
3863 struct mlx4_cmd_mailbox *inbox,
3864 struct mlx4_cmd_mailbox *outbox,
3865 struct mlx4_cmd_info *cmd)
3867 struct mlx4_qp_context *context = inbox->buf + 8;
3868 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3871 adjust_proxy_tun_qkey(dev, vhcr, context);
3872 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3875 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3876 struct mlx4_vhcr *vhcr,
3877 struct mlx4_cmd_mailbox *inbox,
3878 struct mlx4_cmd_mailbox *outbox,
3879 struct mlx4_cmd_info *cmd)
3882 struct mlx4_qp_context *context = inbox->buf + 8;
3884 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3887 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
3891 adjust_proxy_tun_qkey(dev, vhcr, context);
3892 update_gid(dev, inbox, (u8)slave);
3893 update_pkey_index(dev, slave, inbox);
3894 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3897 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3898 struct mlx4_vhcr *vhcr,
3899 struct mlx4_cmd_mailbox *inbox,
3900 struct mlx4_cmd_mailbox *outbox,
3901 struct mlx4_cmd_info *cmd)
3904 struct mlx4_qp_context *context = inbox->buf + 8;
3906 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3909 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
3913 adjust_proxy_tun_qkey(dev, vhcr, context);
3914 update_gid(dev, inbox, (u8)slave);
3915 update_pkey_index(dev, slave, inbox);
3916 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3919 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3920 struct mlx4_vhcr *vhcr,
3921 struct mlx4_cmd_mailbox *inbox,
3922 struct mlx4_cmd_mailbox *outbox,
3923 struct mlx4_cmd_info *cmd)
3926 int qpn = vhcr->in_modifier & 0x7fffff;
3929 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3932 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3936 atomic_dec(&qp->mtt->ref_count);
3937 atomic_dec(&qp->rcq->ref_count);
3938 atomic_dec(&qp->scq->ref_count);
3940 atomic_dec(&qp->srq->ref_count);
3941 res_end_move(dev, slave, RES_QP, qpn);
3945 res_abort_move(dev, slave, RES_QP, qpn);
3950 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3951 struct res_qp *rqp, u8 *gid)
3953 struct res_gid *res;
3955 list_for_each_entry(res, &rqp->mcg_list, list) {
3956 if (!memcmp(res->gid, gid, 16))
3962 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3963 u8 *gid, enum mlx4_protocol prot,
3964 enum mlx4_steer_type steer, u64 reg_id)
3966 struct res_gid *res;
3969 res = kzalloc(sizeof *res, GFP_KERNEL);
3973 spin_lock_irq(&rqp->mcg_spl);
3974 if (find_gid(dev, slave, rqp, gid)) {
3978 memcpy(res->gid, gid, 16);
3981 res->reg_id = reg_id;
3982 list_add_tail(&res->list, &rqp->mcg_list);
3985 spin_unlock_irq(&rqp->mcg_spl);
3990 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3991 u8 *gid, enum mlx4_protocol prot,
3992 enum mlx4_steer_type steer, u64 *reg_id)
3994 struct res_gid *res;
3997 spin_lock_irq(&rqp->mcg_spl);
3998 res = find_gid(dev, slave, rqp, gid);
3999 if (!res || res->prot != prot || res->steer != steer)
4002 *reg_id = res->reg_id;
4003 list_del(&res->list);
4007 spin_unlock_irq(&rqp->mcg_spl);
4012 static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
4013 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
4014 enum mlx4_steer_type type, u64 *reg_id)
4016 switch (dev->caps.steering_mode) {
4017 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
4018 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4021 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
4022 block_loopback, prot,
4025 case MLX4_STEERING_MODE_B0:
4026 if (prot == MLX4_PROT_ETH) {
4027 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
4032 return mlx4_qp_attach_common(dev, qp, gid,
4033 block_loopback, prot, type);
4039 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
4040 u8 gid[16], enum mlx4_protocol prot,
4041 enum mlx4_steer_type type, u64 reg_id)
4043 switch (dev->caps.steering_mode) {
4044 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4045 return mlx4_flow_detach(dev, reg_id);
4046 case MLX4_STEERING_MODE_B0:
4047 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
4053 static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
4054 u8 *gid, enum mlx4_protocol prot)
4058 if (prot != MLX4_PROT_ETH)
4061 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
4062 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
4063 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
4072 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4073 struct mlx4_vhcr *vhcr,
4074 struct mlx4_cmd_mailbox *inbox,
4075 struct mlx4_cmd_mailbox *outbox,
4076 struct mlx4_cmd_info *cmd)
4078 struct mlx4_qp qp; /* dummy for calling attach/detach */
4079 u8 *gid = inbox->buf;
4080 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
4085 int attach = vhcr->op_modifier;
4086 int block_loopback = vhcr->in_modifier >> 31;
4087 u8 steer_type_mask = 2;
4088 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
4090 qpn = vhcr->in_modifier & 0xffffff;
4091 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4097 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
4100 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
4103 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
4107 err = mlx4_adjust_port(dev, slave, gid, prot);
4111 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, ®_id);
4115 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
4117 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
4120 put_res(dev, slave, qpn, RES_QP);
4124 qp_detach(dev, &qp, gid, prot, type, reg_id);
4126 put_res(dev, slave, qpn, RES_QP);
4131 * MAC validation for Flow Steering rules.
4132 * VF can attach rules only with a mac address which is assigned to it.
4134 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
4135 struct list_head *rlist)
4137 struct mac_res *res, *tmp;
4140 /* make sure it isn't multicast or broadcast mac*/
4141 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
4142 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4143 list_for_each_entry_safe(res, tmp, rlist, list) {
4144 be_mac = cpu_to_be64(res->mac << 16);
4145 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
4148 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
4149 eth_header->eth.dst_mac, slave);
4155 static void handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
4156 struct _rule_hw *eth_header)
4158 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
4159 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
4160 struct mlx4_net_trans_rule_hw_eth *eth =
4161 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
4162 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
4163 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
4164 next_rule->rsvd == 0;
4167 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
4172 * In case of missing eth header, append eth header with a MAC address
4173 * assigned to the VF.
4175 static int add_eth_header(struct mlx4_dev *dev, int slave,
4176 struct mlx4_cmd_mailbox *inbox,
4177 struct list_head *rlist, int header_id)
4179 struct mac_res *res, *tmp;
4181 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4182 struct mlx4_net_trans_rule_hw_eth *eth_header;
4183 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
4184 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
4186 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
4188 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4190 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
4192 /* Clear a space in the inbox for eth header */
4193 switch (header_id) {
4194 case MLX4_NET_TRANS_RULE_ID_IPV4:
4196 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
4197 memmove(ip_header, eth_header,
4198 sizeof(*ip_header) + sizeof(*l4_header));
4200 case MLX4_NET_TRANS_RULE_ID_TCP:
4201 case MLX4_NET_TRANS_RULE_ID_UDP:
4202 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
4204 memmove(l4_header, eth_header, sizeof(*l4_header));
4209 list_for_each_entry_safe(res, tmp, rlist, list) {
4210 if (port == res->port) {
4211 be_mac = cpu_to_be64(res->mac << 16);
4216 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
4221 memset(eth_header, 0, sizeof(*eth_header));
4222 eth_header->size = sizeof(*eth_header) >> 2;
4223 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
4224 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
4225 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
4231 #define MLX4_UPD_QP_PATH_MASK_SUPPORTED ( \
4232 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\
4233 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
4234 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
4235 struct mlx4_vhcr *vhcr,
4236 struct mlx4_cmd_mailbox *inbox,
4237 struct mlx4_cmd_mailbox *outbox,
4238 struct mlx4_cmd_info *cmd_info)
4241 u32 qpn = vhcr->in_modifier & 0xffffff;
4245 u64 pri_addr_path_mask;
4246 struct mlx4_update_qp_context *cmd;
4249 cmd = (struct mlx4_update_qp_context *)inbox->buf;
4251 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
4252 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
4253 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
4256 if ((pri_addr_path_mask &
4257 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
4258 !(dev->caps.flags2 &
4259 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
4261 "Src check LB for slave %d isn't supported\n",
4266 /* Just change the smac for the QP */
4267 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4269 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
4273 port = (rqp->sched_queue >> 6 & 1) + 1;
4275 if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
4276 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4277 err = mac_find_smac_ix_in_slave(dev, slave, port,
4281 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4287 err = mlx4_cmd(dev, inbox->dma,
4288 vhcr->in_modifier, 0,
4289 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4292 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4297 put_res(dev, slave, qpn, RES_QP);
4301 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4302 struct mlx4_vhcr *vhcr,
4303 struct mlx4_cmd_mailbox *inbox,
4304 struct mlx4_cmd_mailbox *outbox,
4305 struct mlx4_cmd_info *cmd)
4308 struct mlx4_priv *priv = mlx4_priv(dev);
4309 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4310 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
4314 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4315 struct _rule_hw *rule_header;
4318 if (dev->caps.steering_mode !=
4319 MLX4_STEERING_MODE_DEVICE_MANAGED)
4322 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
4323 err = mlx4_slave_convert_port(dev, slave, ctrl->port);
4327 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
4328 err = get_res(dev, slave, qpn, RES_QP, &rqp);
4330 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
4333 rule_header = (struct _rule_hw *)(ctrl + 1);
4334 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4336 if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
4337 handle_eth_header_mcast_prio(ctrl, rule_header);
4339 if (slave == dev->caps.function)
4342 switch (header_id) {
4343 case MLX4_NET_TRANS_RULE_ID_ETH:
4344 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4349 case MLX4_NET_TRANS_RULE_ID_IB:
4351 case MLX4_NET_TRANS_RULE_ID_IPV4:
4352 case MLX4_NET_TRANS_RULE_ID_TCP:
4353 case MLX4_NET_TRANS_RULE_ID_UDP:
4354 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
4355 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4359 vhcr->in_modifier +=
4360 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4363 pr_err("Corrupted mailbox\n");
4369 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4370 vhcr->in_modifier, 0,
4371 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4376 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
4378 mlx4_err(dev, "Fail to add flow steering resources\n");
4380 mlx4_cmd(dev, vhcr->out_param, 0, 0,
4381 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4385 atomic_inc(&rqp->ref_count);
4387 put_res(dev, slave, qpn, RES_QP);
4391 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4392 struct mlx4_vhcr *vhcr,
4393 struct mlx4_cmd_mailbox *inbox,
4394 struct mlx4_cmd_mailbox *outbox,
4395 struct mlx4_cmd_info *cmd)
4399 struct res_fs_rule *rrule;
4401 if (dev->caps.steering_mode !=
4402 MLX4_STEERING_MODE_DEVICE_MANAGED)
4405 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4408 /* Release the rule form busy state before removal */
4409 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4410 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4414 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4416 mlx4_err(dev, "Fail to remove flow steering resources\n");
4420 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4421 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4424 atomic_dec(&rqp->ref_count);
4426 put_res(dev, slave, rrule->qpn, RES_QP);
4431 BUSY_MAX_RETRIES = 10
4434 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4435 struct mlx4_vhcr *vhcr,
4436 struct mlx4_cmd_mailbox *inbox,
4437 struct mlx4_cmd_mailbox *outbox,
4438 struct mlx4_cmd_info *cmd)
4441 int index = vhcr->in_modifier & 0xffff;
4443 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4447 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4448 put_res(dev, slave, index, RES_COUNTER);
4452 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4454 struct res_gid *rgid;
4455 struct res_gid *tmp;
4456 struct mlx4_qp qp; /* dummy for calling attach/detach */
4458 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
4459 switch (dev->caps.steering_mode) {
4460 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4461 mlx4_flow_detach(dev, rgid->reg_id);
4463 case MLX4_STEERING_MODE_B0:
4464 qp.qpn = rqp->local_qpn;
4465 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4466 rgid->prot, rgid->steer);
4469 list_del(&rgid->list);
4474 static int _move_all_busy(struct mlx4_dev *dev, int slave,
4475 enum mlx4_resource type, int print)
4477 struct mlx4_priv *priv = mlx4_priv(dev);
4478 struct mlx4_resource_tracker *tracker =
4479 &priv->mfunc.master.res_tracker;
4480 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4481 struct res_common *r;
4482 struct res_common *tmp;
4486 spin_lock_irq(mlx4_tlock(dev));
4487 list_for_each_entry_safe(r, tmp, rlist, list) {
4488 if (r->owner == slave) {
4490 if (r->state == RES_ANY_BUSY) {
4493 "%s id 0x%llx is busy\n",
4498 r->from_state = r->state;
4499 r->state = RES_ANY_BUSY;
4505 spin_unlock_irq(mlx4_tlock(dev));
4510 static int move_all_busy(struct mlx4_dev *dev, int slave,
4511 enum mlx4_resource type)
4513 unsigned long begin;
4518 busy = _move_all_busy(dev, slave, type, 0);
4519 if (time_after(jiffies, begin + 5 * HZ))
4526 busy = _move_all_busy(dev, slave, type, 1);
4530 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4532 struct mlx4_priv *priv = mlx4_priv(dev);
4533 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4534 struct list_head *qp_list =
4535 &tracker->slave_list[slave].res_list[RES_QP];
4543 err = move_all_busy(dev, slave, RES_QP);
4545 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4548 spin_lock_irq(mlx4_tlock(dev));
4549 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4550 spin_unlock_irq(mlx4_tlock(dev));
4551 if (qp->com.owner == slave) {
4552 qpn = qp->com.res_id;
4553 detach_qp(dev, slave, qp);
4554 state = qp->com.from_state;
4555 while (state != 0) {
4557 case RES_QP_RESERVED:
4558 spin_lock_irq(mlx4_tlock(dev));
4559 rb_erase(&qp->com.node,
4560 &tracker->res_tree[RES_QP]);
4561 list_del(&qp->com.list);
4562 spin_unlock_irq(mlx4_tlock(dev));
4563 if (!valid_reserved(dev, slave, qpn)) {
4564 __mlx4_qp_release_range(dev, qpn, 1);
4565 mlx4_release_resource(dev, slave,
4572 if (!valid_reserved(dev, slave, qpn))
4573 __mlx4_qp_free_icm(dev, qpn);
4574 state = RES_QP_RESERVED;
4578 err = mlx4_cmd(dev, in_param,
4581 MLX4_CMD_TIME_CLASS_A,
4584 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4585 slave, qp->local_qpn);
4586 atomic_dec(&qp->rcq->ref_count);
4587 atomic_dec(&qp->scq->ref_count);
4588 atomic_dec(&qp->mtt->ref_count);
4590 atomic_dec(&qp->srq->ref_count);
4591 state = RES_QP_MAPPED;
4598 spin_lock_irq(mlx4_tlock(dev));
4600 spin_unlock_irq(mlx4_tlock(dev));
4603 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4605 struct mlx4_priv *priv = mlx4_priv(dev);
4606 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4607 struct list_head *srq_list =
4608 &tracker->slave_list[slave].res_list[RES_SRQ];
4609 struct res_srq *srq;
4610 struct res_srq *tmp;
4617 err = move_all_busy(dev, slave, RES_SRQ);
4619 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4622 spin_lock_irq(mlx4_tlock(dev));
4623 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4624 spin_unlock_irq(mlx4_tlock(dev));
4625 if (srq->com.owner == slave) {
4626 srqn = srq->com.res_id;
4627 state = srq->com.from_state;
4628 while (state != 0) {
4630 case RES_SRQ_ALLOCATED:
4631 __mlx4_srq_free_icm(dev, srqn);
4632 spin_lock_irq(mlx4_tlock(dev));
4633 rb_erase(&srq->com.node,
4634 &tracker->res_tree[RES_SRQ]);
4635 list_del(&srq->com.list);
4636 spin_unlock_irq(mlx4_tlock(dev));
4637 mlx4_release_resource(dev, slave,
4645 err = mlx4_cmd(dev, in_param, srqn, 1,
4647 MLX4_CMD_TIME_CLASS_A,
4650 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
4653 atomic_dec(&srq->mtt->ref_count);
4655 atomic_dec(&srq->cq->ref_count);
4656 state = RES_SRQ_ALLOCATED;
4664 spin_lock_irq(mlx4_tlock(dev));
4666 spin_unlock_irq(mlx4_tlock(dev));
4669 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4671 struct mlx4_priv *priv = mlx4_priv(dev);
4672 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4673 struct list_head *cq_list =
4674 &tracker->slave_list[slave].res_list[RES_CQ];
4683 err = move_all_busy(dev, slave, RES_CQ);
4685 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4688 spin_lock_irq(mlx4_tlock(dev));
4689 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4690 spin_unlock_irq(mlx4_tlock(dev));
4691 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4692 cqn = cq->com.res_id;
4693 state = cq->com.from_state;
4694 while (state != 0) {
4696 case RES_CQ_ALLOCATED:
4697 __mlx4_cq_free_icm(dev, cqn);
4698 spin_lock_irq(mlx4_tlock(dev));
4699 rb_erase(&cq->com.node,
4700 &tracker->res_tree[RES_CQ]);
4701 list_del(&cq->com.list);
4702 spin_unlock_irq(mlx4_tlock(dev));
4703 mlx4_release_resource(dev, slave,
4711 err = mlx4_cmd(dev, in_param, cqn, 1,
4713 MLX4_CMD_TIME_CLASS_A,
4716 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
4718 atomic_dec(&cq->mtt->ref_count);
4719 state = RES_CQ_ALLOCATED;
4727 spin_lock_irq(mlx4_tlock(dev));
4729 spin_unlock_irq(mlx4_tlock(dev));
4732 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4734 struct mlx4_priv *priv = mlx4_priv(dev);
4735 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4736 struct list_head *mpt_list =
4737 &tracker->slave_list[slave].res_list[RES_MPT];
4738 struct res_mpt *mpt;
4739 struct res_mpt *tmp;
4746 err = move_all_busy(dev, slave, RES_MPT);
4748 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4751 spin_lock_irq(mlx4_tlock(dev));
4752 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4753 spin_unlock_irq(mlx4_tlock(dev));
4754 if (mpt->com.owner == slave) {
4755 mptn = mpt->com.res_id;
4756 state = mpt->com.from_state;
4757 while (state != 0) {
4759 case RES_MPT_RESERVED:
4760 __mlx4_mpt_release(dev, mpt->key);
4761 spin_lock_irq(mlx4_tlock(dev));
4762 rb_erase(&mpt->com.node,
4763 &tracker->res_tree[RES_MPT]);
4764 list_del(&mpt->com.list);
4765 spin_unlock_irq(mlx4_tlock(dev));
4766 mlx4_release_resource(dev, slave,
4772 case RES_MPT_MAPPED:
4773 __mlx4_mpt_free_icm(dev, mpt->key);
4774 state = RES_MPT_RESERVED;
4779 err = mlx4_cmd(dev, in_param, mptn, 0,
4781 MLX4_CMD_TIME_CLASS_A,
4784 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
4787 atomic_dec(&mpt->mtt->ref_count);
4788 state = RES_MPT_MAPPED;
4795 spin_lock_irq(mlx4_tlock(dev));
4797 spin_unlock_irq(mlx4_tlock(dev));
4800 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4802 struct mlx4_priv *priv = mlx4_priv(dev);
4803 struct mlx4_resource_tracker *tracker =
4804 &priv->mfunc.master.res_tracker;
4805 struct list_head *mtt_list =
4806 &tracker->slave_list[slave].res_list[RES_MTT];
4807 struct res_mtt *mtt;
4808 struct res_mtt *tmp;
4814 err = move_all_busy(dev, slave, RES_MTT);
4816 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4819 spin_lock_irq(mlx4_tlock(dev));
4820 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4821 spin_unlock_irq(mlx4_tlock(dev));
4822 if (mtt->com.owner == slave) {
4823 base = mtt->com.res_id;
4824 state = mtt->com.from_state;
4825 while (state != 0) {
4827 case RES_MTT_ALLOCATED:
4828 __mlx4_free_mtt_range(dev, base,
4830 spin_lock_irq(mlx4_tlock(dev));
4831 rb_erase(&mtt->com.node,
4832 &tracker->res_tree[RES_MTT]);
4833 list_del(&mtt->com.list);
4834 spin_unlock_irq(mlx4_tlock(dev));
4835 mlx4_release_resource(dev, slave, RES_MTT,
4836 1 << mtt->order, 0);
4846 spin_lock_irq(mlx4_tlock(dev));
4848 spin_unlock_irq(mlx4_tlock(dev));
4851 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
4853 struct mlx4_priv *priv = mlx4_priv(dev);
4854 struct mlx4_resource_tracker *tracker =
4855 &priv->mfunc.master.res_tracker;
4856 struct list_head *fs_rule_list =
4857 &tracker->slave_list[slave].res_list[RES_FS_RULE];
4858 struct res_fs_rule *fs_rule;
4859 struct res_fs_rule *tmp;
4864 err = move_all_busy(dev, slave, RES_FS_RULE);
4866 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
4869 spin_lock_irq(mlx4_tlock(dev));
4870 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
4871 spin_unlock_irq(mlx4_tlock(dev));
4872 if (fs_rule->com.owner == slave) {
4873 base = fs_rule->com.res_id;
4874 state = fs_rule->com.from_state;
4875 while (state != 0) {
4877 case RES_FS_RULE_ALLOCATED:
4879 err = mlx4_cmd(dev, base, 0, 0,
4880 MLX4_QP_FLOW_STEERING_DETACH,
4881 MLX4_CMD_TIME_CLASS_A,
4884 spin_lock_irq(mlx4_tlock(dev));
4885 rb_erase(&fs_rule->com.node,
4886 &tracker->res_tree[RES_FS_RULE]);
4887 list_del(&fs_rule->com.list);
4888 spin_unlock_irq(mlx4_tlock(dev));
4898 spin_lock_irq(mlx4_tlock(dev));
4900 spin_unlock_irq(mlx4_tlock(dev));
4903 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
4905 struct mlx4_priv *priv = mlx4_priv(dev);
4906 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4907 struct list_head *eq_list =
4908 &tracker->slave_list[slave].res_list[RES_EQ];
4916 err = move_all_busy(dev, slave, RES_EQ);
4918 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
4921 spin_lock_irq(mlx4_tlock(dev));
4922 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
4923 spin_unlock_irq(mlx4_tlock(dev));
4924 if (eq->com.owner == slave) {
4925 eqn = eq->com.res_id;
4926 state = eq->com.from_state;
4927 while (state != 0) {
4929 case RES_EQ_RESERVED:
4930 spin_lock_irq(mlx4_tlock(dev));
4931 rb_erase(&eq->com.node,
4932 &tracker->res_tree[RES_EQ]);
4933 list_del(&eq->com.list);
4934 spin_unlock_irq(mlx4_tlock(dev));
4940 err = mlx4_cmd(dev, slave, eqn & 0x3ff,
4941 1, MLX4_CMD_HW2SW_EQ,
4942 MLX4_CMD_TIME_CLASS_A,
4945 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
4946 slave, eqn & 0x3ff);
4947 atomic_dec(&eq->mtt->ref_count);
4948 state = RES_EQ_RESERVED;
4956 spin_lock_irq(mlx4_tlock(dev));
4958 spin_unlock_irq(mlx4_tlock(dev));
4961 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
4963 struct mlx4_priv *priv = mlx4_priv(dev);
4964 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4965 struct list_head *counter_list =
4966 &tracker->slave_list[slave].res_list[RES_COUNTER];
4967 struct res_counter *counter;
4968 struct res_counter *tmp;
4970 int *counters_arr = NULL;
4973 err = move_all_busy(dev, slave, RES_COUNTER);
4975 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
4978 counters_arr = kmalloc_array(dev->caps.max_counters,
4979 sizeof(*counters_arr), GFP_KERNEL);
4986 spin_lock_irq(mlx4_tlock(dev));
4987 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
4988 if (counter->com.owner == slave) {
4989 counters_arr[i++] = counter->com.res_id;
4990 rb_erase(&counter->com.node,
4991 &tracker->res_tree[RES_COUNTER]);
4992 list_del(&counter->com.list);
4996 spin_unlock_irq(mlx4_tlock(dev));
4999 __mlx4_counter_free(dev, counters_arr[j++]);
5000 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
5004 kfree(counters_arr);
5007 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
5009 struct mlx4_priv *priv = mlx4_priv(dev);
5010 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
5011 struct list_head *xrcdn_list =
5012 &tracker->slave_list[slave].res_list[RES_XRCD];
5013 struct res_xrcdn *xrcd;
5014 struct res_xrcdn *tmp;
5018 err = move_all_busy(dev, slave, RES_XRCD);
5020 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
5023 spin_lock_irq(mlx4_tlock(dev));
5024 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
5025 if (xrcd->com.owner == slave) {
5026 xrcdn = xrcd->com.res_id;
5027 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
5028 list_del(&xrcd->com.list);
5030 __mlx4_xrcd_free(dev, xrcdn);
5033 spin_unlock_irq(mlx4_tlock(dev));
5036 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
5038 struct mlx4_priv *priv = mlx4_priv(dev);
5039 mlx4_reset_roce_gids(dev, slave);
5040 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5041 rem_slave_vlans(dev, slave);
5042 rem_slave_macs(dev, slave);
5043 rem_slave_fs_rule(dev, slave);
5044 rem_slave_qps(dev, slave);
5045 rem_slave_srqs(dev, slave);
5046 rem_slave_cqs(dev, slave);
5047 rem_slave_mrs(dev, slave);
5048 rem_slave_eqs(dev, slave);
5049 rem_slave_mtts(dev, slave);
5050 rem_slave_counters(dev, slave);
5051 rem_slave_xrcdns(dev, slave);
5052 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
5055 static void update_qos_vpp(struct mlx4_update_qp_context *ctx,
5056 struct mlx4_vf_immed_vlan_work *work)
5058 ctx->qp_mask |= cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_QOS_VPP);
5059 ctx->qp_context.qos_vport = work->qos_vport;
5062 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
5064 struct mlx4_vf_immed_vlan_work *work =
5065 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
5066 struct mlx4_cmd_mailbox *mailbox;
5067 struct mlx4_update_qp_context *upd_context;
5068 struct mlx4_dev *dev = &work->priv->dev;
5069 struct mlx4_resource_tracker *tracker =
5070 &work->priv->mfunc.master.res_tracker;
5071 struct list_head *qp_list =
5072 &tracker->slave_list[work->slave].res_list[RES_QP];
5075 u64 qp_path_mask_vlan_ctrl =
5076 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
5077 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
5078 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
5079 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
5080 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
5081 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
5083 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
5084 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
5085 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
5086 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
5087 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
5088 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
5089 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
5092 int port, errors = 0;
5095 if (mlx4_is_slave(dev)) {
5096 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
5101 mailbox = mlx4_alloc_cmd_mailbox(dev);
5102 if (IS_ERR(mailbox))
5104 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
5105 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5106 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
5107 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
5108 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5109 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
5110 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5111 else if (!work->vlan_id)
5112 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5113 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
5115 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
5116 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
5117 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
5119 upd_context = mailbox->buf;
5120 upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
5122 spin_lock_irq(mlx4_tlock(dev));
5123 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
5124 spin_unlock_irq(mlx4_tlock(dev));
5125 if (qp->com.owner == work->slave) {
5126 if (qp->com.from_state != RES_QP_HW ||
5127 !qp->sched_queue || /* no INIT2RTR trans yet */
5128 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
5129 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
5130 spin_lock_irq(mlx4_tlock(dev));
5133 port = (qp->sched_queue >> 6 & 1) + 1;
5134 if (port != work->port) {
5135 spin_lock_irq(mlx4_tlock(dev));
5138 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
5139 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
5141 upd_context->primary_addr_path_mask =
5142 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
5143 if (work->vlan_id == MLX4_VGT) {
5144 upd_context->qp_context.param3 = qp->param3;
5145 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
5146 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
5147 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
5148 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
5149 upd_context->qp_context.pri_path.feup = qp->feup;
5150 upd_context->qp_context.pri_path.sched_queue =
5153 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
5154 upd_context->qp_context.pri_path.vlan_control = vlan_control;
5155 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
5156 upd_context->qp_context.pri_path.fvl_rx =
5157 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
5158 upd_context->qp_context.pri_path.fl =
5159 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
5160 upd_context->qp_context.pri_path.feup =
5161 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
5162 upd_context->qp_context.pri_path.sched_queue =
5163 qp->sched_queue & 0xC7;
5164 upd_context->qp_context.pri_path.sched_queue |=
5165 ((work->qos & 0x7) << 3);
5167 if (dev->caps.flags2 &
5168 MLX4_DEV_CAP_FLAG2_QOS_VPP)
5169 update_qos_vpp(upd_context, work);
5172 err = mlx4_cmd(dev, mailbox->dma,
5173 qp->local_qpn & 0xffffff,
5174 0, MLX4_CMD_UPDATE_QP,
5175 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
5177 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
5178 work->slave, port, qp->local_qpn, err);
5182 spin_lock_irq(mlx4_tlock(dev));
5184 spin_unlock_irq(mlx4_tlock(dev));
5185 mlx4_free_cmd_mailbox(dev, mailbox);
5188 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
5189 errors, work->slave, work->port);
5191 /* unregister previous vlan_id if needed and we had no errors
5192 * while updating the QPs
5194 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
5195 NO_INDX != work->orig_vlan_ix)
5196 __mlx4_unregister_vlan(&work->priv->dev, work->port,
5197 work->orig_vlan_id);