drivers/net/ethernet/mellanox/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/gfp.h>
  37 #include <linux/export.h>
  38
  39 #include <linux/mlx4/cmd.h>
  40 #include <linux/mlx4/qp.h>
  41
  42 #include "mlx4.h"
  43 #include "icm.h"
  44
  45 /* QP to support BF should have bits 6,7 cleared */
  46 #define MLX4_BF_QP_SKIP_MASK    0xc0
  47 #define MLX4_MAX_BF_QP_RANGE    0x40
  48
  49 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
  50 {
  51         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
  52         struct mlx4_qp *qp;
  53
  54         spin_lock(&qp_table->lock);
  55
  56         qp = __mlx4_qp_lookup(dev, qpn);
  57         if (qp)
  58                 atomic_inc(&qp->refcount);
  59
  60         spin_unlock(&qp_table->lock);
  61
  62         if (!qp) {
  63                 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
  64                 return;
  65         }
  66
  67         qp->event(qp, event_type);
  68
  69         if (atomic_dec_and_test(&qp->refcount))
  70                 complete(&qp->free);
  71 }
  72
  73 /* used for INIT/CLOSE port logic */
  74 static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
  75 {
  76         /* this procedure is called after we already know we are on the master */
  77         /* qp0 is either the proxy qp0, or the real qp0 */
  78         u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
  79         *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
  80
  81         *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
  82                 qp->qpn <= dev->phys_caps.base_sqpn + 1;
  83
  84         return *real_qp0 || *proxy_qp0;
  85 }
  86
  87 static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  88                      enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
  89                      struct mlx4_qp_context *context,
  90                      enum mlx4_qp_optpar optpar,
  91                      int sqd_event, struct mlx4_qp *qp, int native)
  92 {
  93         static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
  94                 [MLX4_QP_STATE_RST] = {
  95                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
  96                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
  97                         [MLX4_QP_STATE_INIT]    = MLX4_CMD_RST2INIT_QP,
  98                 },
  99                 [MLX4_QP_STATE_INIT]  = {
 100                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 101                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 102                         [MLX4_QP_STATE_INIT]    = MLX4_CMD_INIT2INIT_QP,
 103                         [MLX4_QP_STATE_RTR]     = MLX4_CMD_INIT2RTR_QP,
 104                 },
 105                 [MLX4_QP_STATE_RTR]   = {
 106                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 107                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 108                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_RTR2RTS_QP,
 109                 },
 110                 [MLX4_QP_STATE_RTS]   = {
 111                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 112                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 113                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_RTS2RTS_QP,
 114                         [MLX4_QP_STATE_SQD]     = MLX4_CMD_RTS2SQD_QP,
 115                 },
 116                 [MLX4_QP_STATE_SQD] = {
 117                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 118                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 119                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_SQD2RTS_QP,
 120                         [MLX4_QP_STATE_SQD]     = MLX4_CMD_SQD2SQD_QP,
 121                 },
 122                 [MLX4_QP_STATE_SQER] = {
 123                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 124                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 125                         [MLX4_QP_STATE_RTS]     = MLX4_CMD_SQERR2RTS_QP,
 126                 },
 127                 [MLX4_QP_STATE_ERR] = {
 128                         [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 129                         [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 130                 }
 131         };
 132
 133         struct mlx4_priv *priv = mlx4_priv(dev);
 134         struct mlx4_cmd_mailbox *mailbox;
 135         int ret = 0;
 136         int real_qp0 = 0;
 137         int proxy_qp0 = 0;
 138         u8 port;
 139
 140         if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
 141             !op[cur_state][new_state])
 142                 return -EINVAL;
 143
 144         if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
 145                 ret = mlx4_cmd(dev, 0, qp->qpn, 2,
 146                         MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
 147                 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
 148                     cur_state != MLX4_QP_STATE_RST &&
 149                     is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
 150                         port = (qp->qpn & 1) + 1;
 151                         if (proxy_qp0)
 152                                 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
 153                         else
 154                                 priv->mfunc.master.qp0_state[port].qp0_active = 0;
 155                 }
 156                 return ret;
 157         }
 158
 159         mailbox = mlx4_alloc_cmd_mailbox(dev);
 160         if (IS_ERR(mailbox))
 161                 return PTR_ERR(mailbox);
 162
 163         if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
 164                 u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
 165                 context->mtt_base_addr_h = mtt_addr >> 32;
 166                 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 167                 context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 168         }
 169
 170         *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
 171         memcpy(mailbox->buf + 8, context, sizeof *context);
 172
 173         ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
 174                 cpu_to_be32(qp->qpn);
 175
 176         ret = mlx4_cmd(dev, mailbox->dma,
 177                        qp->qpn | (!!sqd_event << 31),
 178                        new_state == MLX4_QP_STATE_RST ? 2 : 0,
 179                        op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
 180
 181         if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
 182                 port = (qp->qpn & 1) + 1;
 183                 if (cur_state != MLX4_QP_STATE_ERR &&
 184                     cur_state != MLX4_QP_STATE_RST &&
 185                     new_state == MLX4_QP_STATE_ERR) {
 186                         if (proxy_qp0)
 187                                 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
 188                         else
 189                                 priv->mfunc.master.qp0_state[port].qp0_active = 0;
 190                 } else if (new_state == MLX4_QP_STATE_RTR) {
 191                         if (proxy_qp0)
 192                                 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
 193                         else
 194                                 priv->mfunc.master.qp0_state[port].qp0_active = 1;
 195                 }
 196         }
 197
 198         mlx4_free_cmd_mailbox(dev, mailbox);
 199         return ret;
 200 }
 201
 202 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 203                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 204                    struct mlx4_qp_context *context,
 205                    enum mlx4_qp_optpar optpar,
 206                    int sqd_event, struct mlx4_qp *qp)
 207 {
 208         return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
 209                                 optpar, sqd_event, qp, 0);
 210 }
 211 EXPORT_SYMBOL_GPL(mlx4_qp_modify);
 212
 213 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 214                             int *base, u8 flags)
 215 {
 216         u32 uid;
 217         int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP);
 218
 219         struct mlx4_priv *priv = mlx4_priv(dev);
 220         struct mlx4_qp_table *qp_table = &priv->qp_table;
 221
 222         if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
 223                 return -ENOMEM;
 224
 225         uid = MLX4_QP_TABLE_ZONE_GENERAL;
 226         if (flags & (u8)MLX4_RESERVE_A0_QP) {
 227                 if (bf_qp)
 228                         uid = MLX4_QP_TABLE_ZONE_RAW_ETH;
 229                 else
 230                         uid = MLX4_QP_TABLE_ZONE_RSS;
 231         }
 232
 233         *base = mlx4_zone_alloc_entries(qp_table->zones, uid, cnt, align,
 234                                         bf_qp ? MLX4_BF_QP_SKIP_MASK : 0, NULL);
 235         if (*base == -1)
 236                 return -ENOMEM;
 237
 238         return 0;
 239 }
 240
 241 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 242                           int *base, u8 flags)
 243 {
 244         u64 in_param = 0;
 245         u64 out_param;
 246         int err;
 247
 248         /* Turn off all unsupported QP allocation flags */
 249         flags &= dev->caps.alloc_res_qp_mask;
 250
 251         if (mlx4_is_mfunc(dev)) {
 252                 set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt);
 253                 set_param_h(&in_param, align);
 254                 err = mlx4_cmd_imm(dev, in_param, &out_param,
 255                                    RES_QP, RES_OP_RESERVE,
 256                                    MLX4_CMD_ALLOC_RES,
 257                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 258                 if (err)
 259                         return err;
 260
 261                 *base = get_param_l(&out_param);
 262                 return 0;
 263         }
 264         return __mlx4_qp_reserve_range(dev, cnt, align, base, flags);
 265 }
 266 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
 267
 268 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
 269 {
 270         struct mlx4_priv *priv = mlx4_priv(dev);
 271         struct mlx4_qp_table *qp_table = &priv->qp_table;
 272
 273         if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
 274                 return;
 275         mlx4_zone_free_entries_unique(qp_table->zones, base_qpn, cnt);
 276 }
 277
 278 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
 279 {
 280         u64 in_param = 0;
 281         int err;
 282
 283         if (!cnt)
 284                 return;
 285
 286         if (mlx4_is_mfunc(dev)) {
 287                 set_param_l(&in_param, base_qpn);
 288                 set_param_h(&in_param, cnt);
 289                 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
 290                                MLX4_CMD_FREE_RES,
 291                                MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 292                 if (err) {
 293                         mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n",
 294                                   base_qpn, cnt);
 295                 }
 296         } else
 297                  __mlx4_qp_release_range(dev, base_qpn, cnt);
 298 }
 299 EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
 300
 301 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp)
 302 {
 303         struct mlx4_priv *priv = mlx4_priv(dev);
 304         struct mlx4_qp_table *qp_table = &priv->qp_table;
 305         int err;
 306
 307         err = mlx4_table_get(dev, &qp_table->qp_table, qpn, gfp);
 308         if (err)
 309                 goto err_out;
 310
 311         err = mlx4_table_get(dev, &qp_table->auxc_table, qpn, gfp);
 312         if (err)
 313                 goto err_put_qp;
 314
 315         err = mlx4_table_get(dev, &qp_table->altc_table, qpn, gfp);
 316         if (err)
 317                 goto err_put_auxc;
 318
 319         err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn, gfp);
 320         if (err)
 321                 goto err_put_altc;
 322
 323         err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn, gfp);
 324         if (err)
 325                 goto err_put_rdmarc;
 326
 327         return 0;
 328
 329 err_put_rdmarc:
 330         mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
 331
 332 err_put_altc:
 333         mlx4_table_put(dev, &qp_table->altc_table, qpn);
 334
 335 err_put_auxc:
 336         mlx4_table_put(dev, &qp_table->auxc_table, qpn);
 337
 338 err_put_qp:
 339         mlx4_table_put(dev, &qp_table->qp_table, qpn);
 340
 341 err_out:
 342         return err;
 343 }
 344
 345 static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp)
 346 {
 347         u64 param = 0;
 348
 349         if (mlx4_is_mfunc(dev)) {
 350                 set_param_l(&param, qpn);
 351                 return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
 352                                     MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
 353                                     MLX4_CMD_WRAPPED);
 354         }
 355         return __mlx4_qp_alloc_icm(dev, qpn, gfp);
 356 }
 357
 358 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
 359 {
 360         struct mlx4_priv *priv = mlx4_priv(dev);
 361         struct mlx4_qp_table *qp_table = &priv->qp_table;
 362
 363         mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
 364         mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
 365         mlx4_table_put(dev, &qp_table->altc_table, qpn);
 366         mlx4_table_put(dev, &qp_table->auxc_table, qpn);
 367         mlx4_table_put(dev, &qp_table->qp_table, qpn);
 368 }
 369
 370 static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
 371 {
 372         u64 in_param = 0;
 373
 374         if (mlx4_is_mfunc(dev)) {
 375                 set_param_l(&in_param, qpn);
 376                 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
 377                              MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
 378                              MLX4_CMD_WRAPPED))
 379                         mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
 380         } else
 381                 __mlx4_qp_free_icm(dev, qpn);
 382 }
 383
 384 struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 385 {
 386         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 387         struct mlx4_qp *qp;
 388
 389         spin_lock_irq(&qp_table->lock);
 390
 391         qp = __mlx4_qp_lookup(dev, qpn);
 392
 393         spin_unlock_irq(&qp_table->lock);
 394         return qp;
 395 }
 396
 397 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, gfp_t gfp)
 398 {
 399         struct mlx4_priv *priv = mlx4_priv(dev);
 400         struct mlx4_qp_table *qp_table = &priv->qp_table;
 401         int err;
 402
 403         if (!qpn)
 404                 return -EINVAL;
 405
 406         qp->qpn = qpn;
 407
 408         err = mlx4_qp_alloc_icm(dev, qpn, gfp);
 409         if (err)
 410                 return err;
 411
 412         spin_lock_irq(&qp_table->lock);
 413         err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
 414                                 (dev->caps.num_qps - 1), qp);
 415         spin_unlock_irq(&qp_table->lock);
 416         if (err)
 417                 goto err_icm;
 418
 419         atomic_set(&qp->refcount, 1);
 420         init_completion(&qp->free);
 421
 422         return 0;
 423
 424 err_icm:
 425         mlx4_qp_free_icm(dev, qpn);
 426         return err;
 427 }
 428
 429 EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
 430
 431 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
 432                    enum mlx4_update_qp_attr attr,
 433                    struct mlx4_update_qp_params *params)
 434 {
 435         struct mlx4_cmd_mailbox *mailbox;
 436         struct mlx4_update_qp_context *cmd;
 437         u64 pri_addr_path_mask = 0;
 438         u64 qp_mask = 0;
 439         int err = 0;
 440
 441         if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS))
 442                 return -EINVAL;
 443
 444         mailbox = mlx4_alloc_cmd_mailbox(dev);
 445         if (IS_ERR(mailbox))
 446                 return PTR_ERR(mailbox);
 447
 448         cmd = (struct mlx4_update_qp_context *)mailbox->buf;
 449
 450         if (attr & MLX4_UPDATE_QP_SMAC) {
 451                 pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX;
 452                 cmd->qp_context.pri_path.grh_mylmc = params->smac_index;
 453         }
 454
 455         if (attr & MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB) {
 456                 if (!(dev->caps.flags2
 457                       & MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
 458                         mlx4_warn(dev,
 459                                   "Trying to set src check LB, but it isn't supported\n");
 460                         err = -ENOTSUPP;
 461                         goto out;
 462                 }
 463                 pri_addr_path_mask |=
 464                         1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB;
 465                 if (params->flags &
 466                     MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB) {
 467                         cmd->qp_context.pri_path.fl |=
 468                                 MLX4_FL_ETH_SRC_CHECK_MC_LB;
 469                 }
 470         }
 471
 472         if (attr & MLX4_UPDATE_QP_VSD) {
 473                 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD;
 474                 if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE)
 475                         cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN);
 476         }
 477
 478         if (attr & MLX4_UPDATE_QP_RATE_LIMIT) {
 479                 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_RATE_LIMIT;
 480                 cmd->qp_context.rate_limit_params = cpu_to_be16((params->rate_unit << 14) | params->rate_val);
 481         }
 482
 483         if (attr & MLX4_UPDATE_QP_QOS_VPORT) {
 484                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) {
 485                         mlx4_warn(dev, "Granular QoS per VF is not enabled\n");
 486                         err = -EOPNOTSUPP;
 487                         goto out;
 488                 }
 489
 490                 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;
 491                 cmd->qp_context.qos_vport = params->qos_vport;
 492         }
 493
 494         cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask);
 495         cmd->qp_mask = cpu_to_be64(qp_mask);
 496
 497         err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
 498                        MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
 499                        MLX4_CMD_NATIVE);
 500 out:
 501         mlx4_free_cmd_mailbox(dev, mailbox);
 502         return err;
 503 }
 504 EXPORT_SYMBOL_GPL(mlx4_update_qp);
 505
 506 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
 507 {
 508         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 509         unsigned long flags;
 510
 511         spin_lock_irqsave(&qp_table->lock, flags);
 512         radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
 513         spin_unlock_irqrestore(&qp_table->lock, flags);
 514 }
 515 EXPORT_SYMBOL_GPL(mlx4_qp_remove);
 516
 517 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
 518 {
 519         if (atomic_dec_and_test(&qp->refcount))
 520                 complete(&qp->free);
 521         wait_for_completion(&qp->free);
 522
 523         mlx4_qp_free_icm(dev, qp->qpn);
 524 }
 525 EXPORT_SYMBOL_GPL(mlx4_qp_free);
 526
 527 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
 528 {
 529         return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
 530                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 531 }
 532
 533 #define MLX4_QP_TABLE_RSS_ETH_PRIORITY 2
 534 #define MLX4_QP_TABLE_RAW_ETH_PRIORITY 1
 535 #define MLX4_QP_TABLE_RAW_ETH_SIZE     256
 536
 537 static int mlx4_create_zones(struct mlx4_dev *dev,
 538                              u32 reserved_bottom_general,
 539                              u32 reserved_top_general,
 540                              u32 reserved_bottom_rss,
 541                              u32 start_offset_rss,
 542                              u32 max_table_offset)
 543 {
 544         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 545         struct mlx4_bitmap (*bitmap)[MLX4_QP_TABLE_ZONE_NUM] = NULL;
 546         int bitmap_initialized = 0;
 547         u32 last_offset;
 548         int k;
 549         int err;
 550
 551         qp_table->zones = mlx4_zone_allocator_create(MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP);
 552
 553         if (NULL == qp_table->zones)
 554                 return -ENOMEM;
 555
 556         bitmap = kmalloc(sizeof(*bitmap), GFP_KERNEL);
 557
 558         if (NULL == bitmap) {
 559                 err = -ENOMEM;
 560                 goto free_zone;
 561         }
 562
 563         err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps,
 564                                (1 << 23) - 1, reserved_bottom_general,
 565                                reserved_top_general);
 566
 567         if (err)
 568                 goto free_bitmap;
 569
 570         ++bitmap_initialized;
 571
 572         err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_GENERAL,
 573                                 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO |
 574                                 MLX4_ZONE_USE_RR, 0,
 575                                 0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_GENERAL);
 576
 577         if (err)
 578                 goto free_bitmap;
 579
 580         err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_RSS,
 581                                reserved_bottom_rss,
 582                                reserved_bottom_rss - 1,
 583                                dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 584                                reserved_bottom_rss - start_offset_rss);
 585
 586         if (err)
 587                 goto free_bitmap;
 588
 589         ++bitmap_initialized;
 590
 591         err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_RSS,
 592                                 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
 593                                 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
 594                                 MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RSS_ETH_PRIORITY,
 595                                 0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_RSS);
 596
 597         if (err)
 598                 goto free_bitmap;
 599
 600         last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 601         /*  We have a single zone for the A0 steering QPs area of the FW. This area
 602          *  needs to be split into subareas. One set of subareas is for RSS QPs
 603          *  (in which qp number bits 6 and/or 7 are set); the other set of subareas
 604          *  is for RAW_ETH QPs, which require that both bits 6 and 7 are zero.
 605          *  Currently, the values returned by the FW (A0 steering area starting qp number
 606          *  and A0 steering area size) are such that there are only two subareas -- one
 607          *  for RSS and one for RAW_ETH.
 608          */
 609         for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]);
 610              k++) {
 611                 int size;
 612                 u32 offset = start_offset_rss;
 613                 u32 bf_mask;
 614                 u32 requested_size;
 615
 616                 /* Assuming MLX4_BF_QP_SKIP_MASK is consecutive ones, this calculates
 617                  * a mask of all LSB bits set until (and not including) the first
 618                  * set bit of  MLX4_BF_QP_SKIP_MASK. For example, if MLX4_BF_QP_SKIP_MASK
 619                  * is 0xc0, bf_mask will be 0x3f.
 620                  */
 621                 bf_mask = (MLX4_BF_QP_SKIP_MASK & ~(MLX4_BF_QP_SKIP_MASK - 1)) - 1;
 622                 requested_size = min((u32)MLX4_QP_TABLE_RAW_ETH_SIZE, bf_mask + 1);
 623
 624                 if (((last_offset & MLX4_BF_QP_SKIP_MASK) &&
 625                      ((int)(max_table_offset - last_offset)) >=
 626                      roundup_pow_of_two(MLX4_BF_QP_SKIP_MASK)) ||
 627                     (!(last_offset & MLX4_BF_QP_SKIP_MASK) &&
 628                      !((last_offset + requested_size - 1) &
 629                        MLX4_BF_QP_SKIP_MASK)))
 630                         size = requested_size;
 631                 else {
 632                         u32 candidate_offset =
 633                                 (last_offset | MLX4_BF_QP_SKIP_MASK | bf_mask) + 1;
 634
 635                         if (last_offset & MLX4_BF_QP_SKIP_MASK)
 636                                 last_offset = candidate_offset;
 637
 638                         /* From this point, the BF bits are 0 */
 639
 640                         if (last_offset > max_table_offset) {
 641                                 /* need to skip */
 642                                 size = -1;
 643                         } else {
 644                                 size = min3(max_table_offset - last_offset,
 645                                             bf_mask - (last_offset & bf_mask),
 646                                             requested_size);
 647                                 if (size < requested_size) {
 648                                         int candidate_size;
 649
 650                                         candidate_size = min3(
 651                                                 max_table_offset - candidate_offset,
 652                                                 bf_mask - (last_offset & bf_mask),
 653                                                 requested_size);
 654
 655                                         /*  We will not take this path if last_offset was
 656                                          *  already set above to candidate_offset
 657                                          */
 658                                         if (candidate_size > size) {
 659                                                 last_offset = candidate_offset;
 660                                                 size = candidate_size;
 661                                         }
 662                                 }
 663                         }
 664                 }
 665
 666                 if (size > 0) {
 667                         /* mlx4_bitmap_alloc_range will find a contiguous range of "size"
 668                          * QPs in which both bits 6 and 7 are zero, because we pass it the
 669                          * MLX4_BF_SKIP_MASK).
 670                          */
 671                         offset = mlx4_bitmap_alloc_range(
 672                                         *bitmap + MLX4_QP_TABLE_ZONE_RSS,
 673                                         size, 1,
 674                                         MLX4_BF_QP_SKIP_MASK);
 675
 676                         if (offset == (u32)-1) {
 677                                 err = -ENOMEM;
 678                                 break;
 679                         }
 680
 681                         last_offset = offset + size;
 682
 683                         err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size),
 684                                                roundup_pow_of_two(size) - 1, 0,
 685                                                roundup_pow_of_two(size) - size);
 686                 } else {
 687                         /* Add an empty bitmap, we'll allocate from different zones (since
 688                          * at least one is reserved)
 689                          */
 690                         err = mlx4_bitmap_init(*bitmap + k, 1,
 691                                                MLX4_QP_TABLE_RAW_ETH_SIZE - 1, 0,
 692                                                0);
 693                         mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0);
 694                 }
 695
 696                 if (err)
 697                         break;
 698
 699                 ++bitmap_initialized;
 700
 701                 err = mlx4_zone_add_one(qp_table->zones, *bitmap + k,
 702                                         MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
 703                                         MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
 704                                         MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RAW_ETH_PRIORITY,
 705                                         offset, qp_table->zones_uids + k);
 706
 707                 if (err)
 708                         break;
 709         }
 710
 711         if (err)
 712                 goto free_bitmap;
 713
 714         qp_table->bitmap_gen = *bitmap;
 715
 716         return err;
 717
 718 free_bitmap:
 719         for (k = 0; k < bitmap_initialized; k++)
 720                 mlx4_bitmap_cleanup(*bitmap + k);
 721         kfree(bitmap);
 722 free_zone:
 723         mlx4_zone_allocator_destroy(qp_table->zones);
 724         return err;
 725 }
 726
 727 static void mlx4_cleanup_qp_zones(struct mlx4_dev *dev)
 728 {
 729         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 730
 731         if (qp_table->zones) {
 732                 int i;
 733
 734                 for (i = 0;
 735                      i < sizeof(qp_table->zones_uids)/sizeof(qp_table->zones_uids[0]);
 736                      i++) {
 737                         struct mlx4_bitmap *bitmap =
 738                                 mlx4_zone_get_bitmap(qp_table->zones,
 739                                                      qp_table->zones_uids[i]);
 740
 741                         mlx4_zone_remove_one(qp_table->zones, qp_table->zones_uids[i]);
 742                         if (NULL == bitmap)
 743                                 continue;
 744
 745                         mlx4_bitmap_cleanup(bitmap);
 746                 }
 747                 mlx4_zone_allocator_destroy(qp_table->zones);
 748                 kfree(qp_table->bitmap_gen);
 749                 qp_table->bitmap_gen = NULL;
 750                 qp_table->zones = NULL;
 751         }
 752 }
 753
 754 int mlx4_init_qp_table(struct mlx4_dev *dev)
 755 {
 756         struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 757         int err;
 758         int reserved_from_top = 0;
 759         int reserved_from_bot;
 760         int k;
 761         int fixed_reserved_from_bot_rv = 0;
 762         int bottom_reserved_for_rss_bitmap;
 763         u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base +
 764                         dev->caps.dmfs_high_rate_qpn_range;
 765
 766         spin_lock_init(&qp_table->lock);
 767         INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
 768         if (mlx4_is_slave(dev))
 769                 return 0;
 770
 771         /* We reserve 2 extra QPs per port for the special QPs.  The
 772          * block of special QPs must be aligned to a multiple of 8, so
 773          * round up.
 774          *
 775          * We also reserve the MSB of the 24-bit QP number to indicate
 776          * that a QP is an XRC QP.
 777          */
 778         for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++)
 779                 fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k];
 780
 781         if (fixed_reserved_from_bot_rv < max_table_offset)
 782                 fixed_reserved_from_bot_rv = max_table_offset;
 783
 784         /* We reserve at least 1 extra for bitmaps that we don't have enough space for*/
 785         bottom_reserved_for_rss_bitmap =
 786                 roundup_pow_of_two(fixed_reserved_from_bot_rv + 1);
 787         dev->phys_caps.base_sqpn = ALIGN(bottom_reserved_for_rss_bitmap, 8);
 788
 789         {
 790                 int sort[MLX4_NUM_QP_REGION];
 791                 int i, j;
 792                 int last_base = dev->caps.num_qps;
 793
 794                 for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
 795                         sort[i] = i;
 796
 797                 for (i = MLX4_NUM_QP_REGION; i > MLX4_QP_REGION_BOTTOM; --i) {
 798                         for (j = MLX4_QP_REGION_BOTTOM + 2; j < i; ++j) {
 799                                 if (dev->caps.reserved_qps_cnt[sort[j]] >
 800                                     dev->caps.reserved_qps_cnt[sort[j - 1]])
 801                                         swap(sort[j], sort[j - 1]);
 802                         }
 803                 }
 804
 805                 for (i = MLX4_QP_REGION_BOTTOM + 1; i < MLX4_NUM_QP_REGION; ++i) {
 806                         last_base -= dev->caps.reserved_qps_cnt[sort[i]];
 807                         dev->caps.reserved_qps_base[sort[i]] = last_base;
 808                         reserved_from_top +=
 809                                 dev->caps.reserved_qps_cnt[sort[i]];
 810                 }
 811         }
 812
 813        /* Reserve 8 real SQPs in both native and SRIOV modes.
 814         * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
 815         * (for all PFs and VFs), and 8 corresponding tunnel QPs.
 816         * Each proxy SQP works opposite its own tunnel QP.
 817         *
 818         * The QPs are arranged as follows:
 819         * a. 8 real SQPs
 820         * b. All the proxy SQPs (8 per function)
 821         * c. All the tunnel QPs (8 per function)
 822         */
 823         reserved_from_bot = mlx4_num_reserved_sqps(dev);
 824         if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) {
 825                 mlx4_err(dev, "Number of reserved QPs is higher than number of QPs\n");
 826                 return -EINVAL;
 827         }
 828
 829         err = mlx4_create_zones(dev, reserved_from_bot, reserved_from_bot,
 830                                 bottom_reserved_for_rss_bitmap,
 831                                 fixed_reserved_from_bot_rv,
 832                                 max_table_offset);
 833
 834         if (err)
 835                 return err;
 836
 837         if (mlx4_is_mfunc(dev)) {
 838                 /* for PPF use */
 839                 dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
 840                 dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
 841
 842                 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
 843                  * since the PF does not call mlx4_slave_caps */
 844                 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 845                 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 846                 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 847                 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
 848
 849                 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
 850                     !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
 851                         err = -ENOMEM;
 852                         goto err_mem;
 853                 }
 854
 855                 for (k = 0; k < dev->caps.num_ports; k++) {
 856                         dev->caps.qp0_proxy[k] = dev->phys_caps.base_proxy_sqpn +
 857                                 8 * mlx4_master_func_num(dev) + k;
 858                         dev->caps.qp0_tunnel[k] = dev->caps.qp0_proxy[k] + 8 * MLX4_MFUNC_MAX;
 859                         dev->caps.qp1_proxy[k] = dev->phys_caps.base_proxy_sqpn +
 860                                 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
 861                         dev->caps.qp1_tunnel[k] = dev->caps.qp1_proxy[k] + 8 * MLX4_MFUNC_MAX;
 862                 }
 863         }
 864
 865
 866         err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
 867         if (err)
 868                 goto err_mem;
 869
 870         return err;
 871
 872 err_mem:
 873         kfree(dev->caps.qp0_tunnel);
 874         kfree(dev->caps.qp0_proxy);
 875         kfree(dev->caps.qp1_tunnel);
 876         kfree(dev->caps.qp1_proxy);
 877         dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
 878                 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
 879         mlx4_cleanup_qp_zones(dev);
 880         return err;
 881 }
 882
 883 void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
 884 {
 885         if (mlx4_is_slave(dev))
 886                 return;
 887
 888         mlx4_CONF_SPECIAL_QP(dev, 0);
 889
 890         mlx4_cleanup_qp_zones(dev);
 891 }
 892
 893 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 894                   struct mlx4_qp_context *context)
 895 {
 896         struct mlx4_cmd_mailbox *mailbox;
 897         int err;
 898
 899         mailbox = mlx4_alloc_cmd_mailbox(dev);
 900         if (IS_ERR(mailbox))
 901                 return PTR_ERR(mailbox);
 902
 903         err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
 904                            MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
 905                            MLX4_CMD_WRAPPED);
 906         if (!err)
 907                 memcpy(context, mailbox->buf + 8, sizeof *context);
 908
 909         mlx4_free_cmd_mailbox(dev, mailbox);
 910         return err;
 911 }
 912 EXPORT_SYMBOL_GPL(mlx4_qp_query);
 913
 914 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 915                      struct mlx4_qp_context *context,
 916                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
 917 {
 918         int err;
 919         int i;
 920         enum mlx4_qp_state states[] = {
 921                 MLX4_QP_STATE_RST,
 922                 MLX4_QP_STATE_INIT,
 923                 MLX4_QP_STATE_RTR,
 924                 MLX4_QP_STATE_RTS
 925         };
 926
 927         for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
 928                 context->flags &= cpu_to_be32(~(0xf << 28));
 929                 context->flags |= cpu_to_be32(states[i + 1] << 28);
 930                 if (states[i + 1] != MLX4_QP_STATE_RTR)
 931                         context->params2 &= ~MLX4_QP_BIT_FPP;
 932                 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
 933                                      context, 0, 0, qp);
 934                 if (err) {
 935                         mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n",
 936                                  states[i + 1], err);
 937                         return err;
 938                 }
 939
 940                 *qp_state = states[i + 1];
 941         }
 942
 943         return 0;
 944 }
 945 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);