2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/errno.h>
36 #include <linux/export.h>
37 #include <linux/slab.h>
38 #include <linux/kernel.h>
39 #include <linux/vmalloc.h>
41 #include <linux/mlx4/cmd.h>
46 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
52 spin_lock(&buddy->lock);
54 for (o = order; o <= buddy->max_order; ++o)
55 if (buddy->num_free[o]) {
56 m = 1 << (buddy->max_order - o);
57 seg = find_first_bit(buddy->bits[o], m);
62 spin_unlock(&buddy->lock);
66 clear_bit(seg, buddy->bits[o]);
72 set_bit(seg ^ 1, buddy->bits[o]);
76 spin_unlock(&buddy->lock);
83 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
87 spin_lock(&buddy->lock);
89 while (test_bit(seg ^ 1, buddy->bits[order])) {
90 clear_bit(seg ^ 1, buddy->bits[order]);
91 --buddy->num_free[order];
96 set_bit(seg, buddy->bits[order]);
97 ++buddy->num_free[order];
99 spin_unlock(&buddy->lock);
102 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
106 buddy->max_order = max_order;
107 spin_lock_init(&buddy->lock);
109 buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *),
111 buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
113 if (!buddy->bits || !buddy->num_free)
116 for (i = 0; i <= buddy->max_order; ++i) {
117 s = BITS_TO_LONGS(1UL << (buddy->max_order - i));
118 buddy->bits[i] = kcalloc(s, sizeof (long), GFP_KERNEL | __GFP_NOWARN);
119 if (!buddy->bits[i]) {
120 buddy->bits[i] = vzalloc(s * sizeof(long));
126 set_bit(0, buddy->bits[buddy->max_order]);
127 buddy->num_free[buddy->max_order] = 1;
132 for (i = 0; i <= buddy->max_order; ++i)
133 kvfree(buddy->bits[i]);
137 kfree(buddy->num_free);
142 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
146 for (i = 0; i <= buddy->max_order; ++i)
147 kvfree(buddy->bits[i]);
150 kfree(buddy->num_free);
153 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
155 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
160 seg_order = max_t(int, order - log_mtts_per_seg, 0);
162 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order);
166 offset = seg * (1 << log_mtts_per_seg);
168 if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset,
169 offset + (1 << order) - 1)) {
170 mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order);
177 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
183 if (mlx4_is_mfunc(dev)) {
184 set_param_l(&in_param, order);
185 err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT,
186 RES_OP_RESERVE_AND_MAP,
188 MLX4_CMD_TIME_CLASS_A,
192 return get_param_l(&out_param);
194 return __mlx4_alloc_mtt_range(dev, order);
197 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
198 struct mlx4_mtt *mtt)
204 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
207 mtt->page_shift = page_shift;
209 for (mtt->order = 0, i = 1; i < npages; i <<= 1)
212 mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order);
213 if (mtt->offset == -1)
218 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
220 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
224 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
226 seg_order = max_t(int, order - log_mtts_per_seg, 0);
227 first_seg = offset / (1 << log_mtts_per_seg);
229 mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order);
230 mlx4_table_put_range(dev, &mr_table->mtt_table, offset,
231 offset + (1 << order) - 1);
234 static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
239 if (mlx4_is_mfunc(dev)) {
240 set_param_l(&in_param, offset);
241 set_param_h(&in_param, order);
242 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
244 MLX4_CMD_TIME_CLASS_A,
247 mlx4_warn(dev, "Failed to free mtt range at:%d order:%d\n",
251 __mlx4_free_mtt_range(dev, offset, order);
254 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
259 mlx4_free_mtt_range(dev, mtt->offset, mtt->order);
261 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
263 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
265 return (u64) mtt->offset * dev->caps.mtt_entry_sz;
267 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
269 static u32 hw_index_to_key(u32 ind)
271 return (ind >> 24) | (ind << 8);
274 static u32 key_to_hw_index(u32 key)
276 return (key << 24) | (key >> 8);
279 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
282 return mlx4_cmd(dev, mailbox->dma, mpt_index,
283 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B,
287 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
290 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
291 !mailbox, MLX4_CMD_HW2SW_MPT,
292 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
295 /* Must protect against concurrent access */
296 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
297 struct mlx4_mpt_entry ***mpt_entry)
300 int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1);
301 struct mlx4_cmd_mailbox *mailbox = NULL;
303 if (mmr->enabled != MLX4_MPT_EN_HW)
306 err = mlx4_HW2SW_MPT(dev, NULL, key);
308 mlx4_warn(dev, "HW2SW_MPT failed (%d).", err);
309 mlx4_warn(dev, "Most likely the MR has MWs bound to it.\n");
313 mmr->enabled = MLX4_MPT_EN_SW;
315 if (!mlx4_is_mfunc(dev)) {
316 **mpt_entry = mlx4_table_find(
317 &mlx4_priv(dev)->mr_table.dmpt_table,
320 mailbox = mlx4_alloc_cmd_mailbox(dev);
322 return PTR_ERR(mailbox);
324 err = mlx4_cmd_box(dev, 0, mailbox->dma, key,
325 0, MLX4_CMD_QUERY_MPT,
326 MLX4_CMD_TIME_CLASS_B,
331 *mpt_entry = (struct mlx4_mpt_entry **)&mailbox->buf;
334 if (!(*mpt_entry) || !(**mpt_entry)) {
342 mlx4_free_cmd_mailbox(dev, mailbox);
345 EXPORT_SYMBOL_GPL(mlx4_mr_hw_get_mpt);
347 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
348 struct mlx4_mpt_entry **mpt_entry)
352 if (!mlx4_is_mfunc(dev)) {
353 /* Make sure any changes to this entry are flushed */
356 *(u8 *)(*mpt_entry) = MLX4_MPT_STATUS_HW;
358 /* Make sure the new status is written */
361 err = mlx4_SYNC_TPT(dev);
363 int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1);
365 struct mlx4_cmd_mailbox *mailbox =
366 container_of((void *)mpt_entry, struct mlx4_cmd_mailbox,
369 (*mpt_entry)->lkey = 0;
370 err = mlx4_SW2HW_MPT(dev, mailbox, key);
374 mmr->pd = be32_to_cpu((*mpt_entry)->pd_flags) & MLX4_MPT_PD_MASK;
375 mmr->enabled = MLX4_MPT_EN_HW;
379 EXPORT_SYMBOL_GPL(mlx4_mr_hw_write_mpt);
381 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
382 struct mlx4_mpt_entry **mpt_entry)
384 if (mlx4_is_mfunc(dev)) {
385 struct mlx4_cmd_mailbox *mailbox =
386 container_of((void *)mpt_entry, struct mlx4_cmd_mailbox,
388 mlx4_free_cmd_mailbox(dev, mailbox);
391 EXPORT_SYMBOL_GPL(mlx4_mr_hw_put_mpt);
393 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
396 u32 pd_flags = be32_to_cpu(mpt_entry->pd_flags) & ~MLX4_MPT_PD_MASK;
397 /* The wrapper function will put the slave's id here */
398 if (mlx4_is_mfunc(dev))
399 pd_flags &= ~MLX4_MPT_PD_VF_MASK;
401 mpt_entry->pd_flags = cpu_to_be32(pd_flags |
402 (pdn & MLX4_MPT_PD_MASK)
403 | MLX4_MPT_PD_FLAG_EN_INV);
406 EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_pd);
408 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
409 struct mlx4_mpt_entry *mpt_entry,
412 u32 flags = (be32_to_cpu(mpt_entry->flags) & ~MLX4_PERM_MASK) |
413 (access & MLX4_PERM_MASK);
415 mpt_entry->flags = cpu_to_be32(flags);
418 EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_access);
420 static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
421 u64 iova, u64 size, u32 access, int npages,
422 int page_shift, struct mlx4_mr *mr)
428 mr->enabled = MLX4_MPT_DISABLED;
429 mr->key = hw_index_to_key(mridx);
431 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
434 static int mlx4_WRITE_MTT(struct mlx4_dev *dev,
435 struct mlx4_cmd_mailbox *mailbox,
438 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
439 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
442 int __mlx4_mpt_reserve(struct mlx4_dev *dev)
444 struct mlx4_priv *priv = mlx4_priv(dev);
446 return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
449 static int mlx4_mpt_reserve(struct mlx4_dev *dev)
453 if (mlx4_is_mfunc(dev)) {
454 if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE,
456 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
458 return get_param_l(&out_param);
460 return __mlx4_mpt_reserve(dev);
463 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index)
465 struct mlx4_priv *priv = mlx4_priv(dev);
467 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index, MLX4_NO_RR);
470 static void mlx4_mpt_release(struct mlx4_dev *dev, u32 index)
474 if (mlx4_is_mfunc(dev)) {
475 set_param_l(&in_param, index);
476 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
478 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
479 mlx4_warn(dev, "Failed to release mr index:%d\n",
483 __mlx4_mpt_release(dev, index);
486 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp)
488 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
490 return mlx4_table_get(dev, &mr_table->dmpt_table, index, gfp);
493 static int mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp)
497 if (mlx4_is_mfunc(dev)) {
498 set_param_l(¶m, index);
499 return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM,
501 MLX4_CMD_TIME_CLASS_A,
504 return __mlx4_mpt_alloc_icm(dev, index, gfp);
507 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index)
509 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
511 mlx4_table_put(dev, &mr_table->dmpt_table, index);
514 static void mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index)
518 if (mlx4_is_mfunc(dev)) {
519 set_param_l(&in_param, index);
520 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
521 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
523 mlx4_warn(dev, "Failed to free icm of mr index:%d\n",
527 return __mlx4_mpt_free_icm(dev, index);
530 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
531 int npages, int page_shift, struct mlx4_mr *mr)
536 index = mlx4_mpt_reserve(dev);
540 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
541 access, npages, page_shift, mr);
543 mlx4_mpt_release(dev, index);
547 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
549 static int mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
553 if (mr->enabled == MLX4_MPT_EN_HW) {
554 err = mlx4_HW2SW_MPT(dev, NULL,
555 key_to_hw_index(mr->key) &
556 (dev->caps.num_mpts - 1));
558 mlx4_warn(dev, "HW2SW_MPT failed (%d), MR has MWs bound to it\n",
563 mr->enabled = MLX4_MPT_EN_SW;
565 mlx4_mtt_cleanup(dev, &mr->mtt);
570 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
574 ret = mlx4_mr_free_reserved(dev, mr);
578 mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key));
579 mlx4_mpt_release(dev, key_to_hw_index(mr->key));
583 EXPORT_SYMBOL_GPL(mlx4_mr_free);
585 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr)
587 mlx4_mtt_cleanup(dev, &mr->mtt);
590 EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_cleanup);
592 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
593 u64 iova, u64 size, int npages,
594 int page_shift, struct mlx4_mpt_entry *mpt_entry)
598 err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
602 mpt_entry->start = cpu_to_be64(iova);
603 mpt_entry->length = cpu_to_be64(size);
604 mpt_entry->entity_size = cpu_to_be32(page_shift);
605 mpt_entry->flags &= ~(cpu_to_be32(MLX4_MPT_FLAG_FREE |
606 MLX4_MPT_FLAG_SW_OWNS));
607 if (mr->mtt.order < 0) {
608 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
609 mpt_entry->mtt_addr = 0;
611 mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev,
613 if (mr->mtt.page_shift == 0)
614 mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order);
616 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
617 /* fast register MR in free state */
618 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
619 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
620 MLX4_MPT_PD_FLAG_RAE);
622 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
624 mr->enabled = MLX4_MPT_EN_SW;
628 EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_write);
630 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
632 struct mlx4_cmd_mailbox *mailbox;
633 struct mlx4_mpt_entry *mpt_entry;
636 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mr->key), GFP_KERNEL);
640 mailbox = mlx4_alloc_cmd_mailbox(dev);
641 if (IS_ERR(mailbox)) {
642 err = PTR_ERR(mailbox);
645 mpt_entry = mailbox->buf;
646 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
647 MLX4_MPT_FLAG_REGION |
650 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
651 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
652 mpt_entry->start = cpu_to_be64(mr->iova);
653 mpt_entry->length = cpu_to_be64(mr->size);
654 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
656 if (mr->mtt.order < 0) {
657 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
658 mpt_entry->mtt_addr = 0;
660 mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev,
664 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
665 /* fast register MR in free state */
666 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
667 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
668 MLX4_MPT_PD_FLAG_RAE);
669 mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order);
671 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
674 err = mlx4_SW2HW_MPT(dev, mailbox,
675 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
677 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
680 mr->enabled = MLX4_MPT_EN_HW;
682 mlx4_free_cmd_mailbox(dev, mailbox);
687 mlx4_free_cmd_mailbox(dev, mailbox);
690 mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key));
693 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
695 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
696 int start_index, int npages, u64 *page_list)
698 struct mlx4_priv *priv = mlx4_priv(dev);
700 dma_addr_t dma_handle;
703 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset +
704 start_index, &dma_handle);
709 dma_sync_single_for_cpu(&dev->persist->pdev->dev, dma_handle,
710 npages * sizeof (u64), DMA_TO_DEVICE);
712 for (i = 0; i < npages; ++i)
713 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
715 dma_sync_single_for_device(&dev->persist->pdev->dev, dma_handle,
716 npages * sizeof (u64), DMA_TO_DEVICE);
721 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
722 int start_index, int npages, u64 *page_list)
727 int max_mtts_first_page;
729 /* compute how may mtts fit in the first page */
730 mtts_per_page = PAGE_SIZE / sizeof(u64);
731 max_mtts_first_page = mtts_per_page - (mtt->offset + start_index)
734 chunk = min_t(int, max_mtts_first_page, npages);
737 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
741 start_index += chunk;
744 chunk = min_t(int, mtts_per_page, npages);
749 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
750 int start_index, int npages, u64 *page_list)
752 struct mlx4_cmd_mailbox *mailbox = NULL;
753 __be64 *inbox = NULL;
761 if (mlx4_is_mfunc(dev)) {
762 mailbox = mlx4_alloc_cmd_mailbox(dev);
764 return PTR_ERR(mailbox);
765 inbox = mailbox->buf;
768 chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2,
770 inbox[0] = cpu_to_be64(mtt->offset + start_index);
772 for (i = 0; i < chunk; ++i)
773 inbox[i + 2] = cpu_to_be64(page_list[i] |
774 MLX4_MTT_FLAG_PRESENT);
775 err = mlx4_WRITE_MTT(dev, mailbox, chunk);
777 mlx4_free_cmd_mailbox(dev, mailbox);
782 start_index += chunk;
785 mlx4_free_cmd_mailbox(dev, mailbox);
789 return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list);
791 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
793 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
794 struct mlx4_buf *buf, gfp_t gfp)
800 page_list = kmalloc(buf->npages * sizeof *page_list,
805 for (i = 0; i < buf->npages; ++i)
807 page_list[i] = buf->direct.map + (i << buf->page_shift);
809 page_list[i] = buf->page_list[i].map;
811 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
816 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
818 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
823 if ((type == MLX4_MW_TYPE_1 &&
824 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)) ||
825 (type == MLX4_MW_TYPE_2 &&
826 !(dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)))
829 index = mlx4_mpt_reserve(dev);
833 mw->key = hw_index_to_key(index);
836 mw->enabled = MLX4_MPT_DISABLED;
840 EXPORT_SYMBOL_GPL(mlx4_mw_alloc);
842 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw)
844 struct mlx4_cmd_mailbox *mailbox;
845 struct mlx4_mpt_entry *mpt_entry;
848 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key), GFP_KERNEL);
852 mailbox = mlx4_alloc_cmd_mailbox(dev);
853 if (IS_ERR(mailbox)) {
854 err = PTR_ERR(mailbox);
857 mpt_entry = mailbox->buf;
859 /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned
860 * off, thus creating a memory window and not a memory region.
862 mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key));
863 mpt_entry->pd_flags = cpu_to_be32(mw->pd);
864 if (mw->type == MLX4_MW_TYPE_2) {
865 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
866 mpt_entry->qpn = cpu_to_be32(MLX4_MPT_QP_FLAG_BOUND_QP);
867 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_EN_INV);
870 err = mlx4_SW2HW_MPT(dev, mailbox,
871 key_to_hw_index(mw->key) &
872 (dev->caps.num_mpts - 1));
874 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
877 mw->enabled = MLX4_MPT_EN_HW;
879 mlx4_free_cmd_mailbox(dev, mailbox);
884 mlx4_free_cmd_mailbox(dev, mailbox);
887 mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key));
890 EXPORT_SYMBOL_GPL(mlx4_mw_enable);
892 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw)
896 if (mw->enabled == MLX4_MPT_EN_HW) {
897 err = mlx4_HW2SW_MPT(dev, NULL,
898 key_to_hw_index(mw->key) &
899 (dev->caps.num_mpts - 1));
901 mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err);
903 mw->enabled = MLX4_MPT_EN_SW;
906 mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key));
907 mlx4_mpt_release(dev, key_to_hw_index(mw->key));
909 EXPORT_SYMBOL_GPL(mlx4_mw_free);
911 int mlx4_init_mr_table(struct mlx4_dev *dev)
913 struct mlx4_priv *priv = mlx4_priv(dev);
914 struct mlx4_mr_table *mr_table = &priv->mr_table;
917 /* Nothing to do for slaves - all MR handling is forwarded
919 if (mlx4_is_slave(dev))
922 if (!is_power_of_2(dev->caps.num_mpts))
925 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
926 ~0, dev->caps.reserved_mrws, 0);
930 err = mlx4_buddy_init(&mr_table->mtt_buddy,
931 ilog2((u32)dev->caps.num_mtts /
932 (1 << log_mtts_per_seg)));
936 if (dev->caps.reserved_mtts) {
937 priv->reserved_mtts =
938 mlx4_alloc_mtt_range(dev,
939 fls(dev->caps.reserved_mtts - 1));
940 if (priv->reserved_mtts < 0) {
941 mlx4_warn(dev, "MTT table of order %u is too small\n",
942 mr_table->mtt_buddy.max_order);
944 goto err_reserve_mtts;
951 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
954 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
959 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
961 struct mlx4_priv *priv = mlx4_priv(dev);
962 struct mlx4_mr_table *mr_table = &priv->mr_table;
964 if (mlx4_is_slave(dev))
966 if (priv->reserved_mtts >= 0)
967 mlx4_free_mtt_range(dev, priv->reserved_mtts,
968 fls(dev->caps.reserved_mtts - 1));
969 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
970 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
973 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
974 int npages, u64 iova)
978 if (npages > fmr->max_pages)
981 page_mask = (1 << fmr->page_shift) - 1;
983 /* We are getting page lists, so va must be page aligned. */
984 if (iova & page_mask)
987 /* Trust the user not to pass misaligned data in page_list */
989 for (i = 0; i < npages; ++i) {
990 if (page_list[i] & ~page_mask)
994 if (fmr->maps >= fmr->max_maps)
1000 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1001 int npages, u64 iova, u32 *lkey, u32 *rkey)
1006 err = mlx4_check_fmr(fmr, page_list, npages, iova);
1012 key = key_to_hw_index(fmr->mr.key);
1013 key += dev->caps.num_mpts;
1014 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
1016 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
1018 /* Make sure MPT status is visible before writing MTT entries */
1021 dma_sync_single_for_cpu(&dev->persist->pdev->dev, fmr->dma_handle,
1022 npages * sizeof(u64), DMA_TO_DEVICE);
1024 for (i = 0; i < npages; ++i)
1025 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
1027 dma_sync_single_for_device(&dev->persist->pdev->dev, fmr->dma_handle,
1028 npages * sizeof(u64), DMA_TO_DEVICE);
1030 fmr->mpt->key = cpu_to_be32(key);
1031 fmr->mpt->lkey = cpu_to_be32(key);
1032 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
1033 fmr->mpt->start = cpu_to_be64(iova);
1035 /* Make MTT entries are visible before setting MPT status */
1038 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
1040 /* Make sure MPT status is visible before consumer can use FMR */
1045 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
1047 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1048 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
1050 struct mlx4_priv *priv = mlx4_priv(dev);
1053 if (max_maps > dev->caps.max_fmr_maps)
1056 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
1059 /* All MTTs must fit in the same page */
1060 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
1063 fmr->page_shift = page_shift;
1064 fmr->max_pages = max_pages;
1065 fmr->max_maps = max_maps;
1068 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
1069 page_shift, &fmr->mr);
1073 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
1085 (void) mlx4_mr_free(dev, &fmr->mr);
1088 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
1090 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
1092 struct mlx4_priv *priv = mlx4_priv(dev);
1095 err = mlx4_mr_enable(dev, &fmr->mr);
1099 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
1100 key_to_hw_index(fmr->mr.key), NULL);
1106 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
1108 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1109 u32 *lkey, u32 *rkey)
1111 struct mlx4_cmd_mailbox *mailbox;
1119 mailbox = mlx4_alloc_cmd_mailbox(dev);
1120 if (IS_ERR(mailbox)) {
1121 err = PTR_ERR(mailbox);
1122 pr_warn("mlx4_ib: mlx4_alloc_cmd_mailbox failed (%d)\n", err);
1126 err = mlx4_HW2SW_MPT(dev, NULL,
1127 key_to_hw_index(fmr->mr.key) &
1128 (dev->caps.num_mpts - 1));
1129 mlx4_free_cmd_mailbox(dev, mailbox);
1131 pr_warn("mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n", err);
1134 fmr->mr.enabled = MLX4_MPT_EN_SW;
1136 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
1138 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
1145 ret = mlx4_mr_free(dev, &fmr->mr);
1148 fmr->mr.enabled = MLX4_MPT_DISABLED;
1152 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
1154 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
1156 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT,
1157 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1159 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);