2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
58 #include "mlx4_stats.h"
60 #define DRV_NAME "mlx4_en"
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
77 #define HEADROOM (2048 / TXBB_SIZE + 1)
78 #define STAMP_STRIDE 64
79 #define STAMP_DWORDS (STAMP_STRIDE / 4)
80 #define STAMP_SHIFT 31
81 #define STAMP_VAL 0x7fffffff
82 #define STATS_DELAY (HZ / 4)
83 #define SERVICE_TASK_DELAY (HZ / 4)
84 #define MAX_NUM_OF_FS_RULES 256
86 #define MLX4_EN_FILTER_HASH_SHIFT 4
87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
90 #define MAX_DESC_SIZE 512
91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
94 * OS related constants and tunables
97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_PRIV_FLAGS_PHV 2
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102 /* Use the maximum between 16384 and a single page */
103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
108 * and 4K allocations) */
110 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
115 #define MLX4_EN_MAX_RX_FRAGS 4
117 /* Maximum ring sizes */
118 #define MLX4_EN_MAX_TX_SIZE 8192
119 #define MLX4_EN_MAX_RX_SIZE 8192
121 /* Minimum ring size for our page-allocation scheme to work */
122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
125 #define MLX4_EN_SMALL_PKT_SIZE 64
126 #define MLX4_EN_MIN_TX_RING_P_UP 1
127 #define MLX4_EN_MAX_TX_RING_P_UP 32
128 #define MLX4_EN_NUM_UP 8
129 #define MLX4_EN_DEF_TX_RING_SIZE 512
130 #define MLX4_EN_DEF_RX_RING_SIZE 1024
131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
134 #define MLX4_EN_DEFAULT_TX_WORK 256
135 #define MLX4_EN_DOORBELL_BUDGET 8
137 /* Target number of packets to coalesce with interrupt moderation */
138 #define MLX4_EN_RX_COAL_TARGET 44
139 #define MLX4_EN_RX_COAL_TIME 0x10
141 #define MLX4_EN_TX_COAL_PKTS 16
142 #define MLX4_EN_TX_COAL_TIME 0x10
144 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
145 #define MLX4_EN_MAX_COAL_TIME U16_MAX
147 #define MLX4_EN_RX_RATE_LOW 400000
148 #define MLX4_EN_RX_COAL_TIME_LOW 0
149 #define MLX4_EN_RX_RATE_HIGH 450000
150 #define MLX4_EN_RX_COAL_TIME_HIGH 128
151 #define MLX4_EN_RX_SIZE_THRESH 1024
152 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
153 #define MLX4_EN_SAMPLE_INTERVAL 0
154 #define MLX4_EN_AVG_PKT_SMALL 256
156 #define MLX4_EN_AUTO_CONF 0xffff
158 #define MLX4_EN_DEF_RX_PAUSE 1
159 #define MLX4_EN_DEF_TX_PAUSE 1
161 /* Interval between successive polls in the Tx routine when polling is used
162 instead of interrupts (in per-core Tx rings) - should be power of 2 */
163 #define MLX4_EN_TX_POLL_MODER 16
164 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
166 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
167 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
168 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
170 #define MLX4_EN_MIN_MTU 46
171 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
172 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
174 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
175 #define ETH_BCAST 0xffffffffffffULL
177 #define MLX4_EN_LOOPBACK_RETRIES 5
178 #define MLX4_EN_LOOPBACK_TIMEOUT 100
180 #ifdef MLX4_EN_PERF_STAT
181 /* Number of samples to 'average' */
183 #define AVG_FACTOR 1024
185 #define INC_PERF_COUNTER(cnt) (++(cnt))
186 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
187 #define AVG_PERF_COUNTER(cnt, sample) \
188 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
189 #define GET_PERF_COUNTER(cnt) (cnt)
190 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
194 #define INC_PERF_COUNTER(cnt) do {} while (0)
195 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
196 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
197 #define GET_PERF_COUNTER(cnt) (0)
198 #define GET_AVG_PERF_COUNTER(cnt) (0)
199 #endif /* MLX4_EN_PERF_STAT */
201 /* Constants for TX flow */
203 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
221 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
222 #define XNOR(x, y) (!(x) == !(y))
225 struct mlx4_en_tx_info {
239 } ____cacheline_aligned_in_smp;
242 #define MLX4_EN_BIT_DESC_OWN 0x80000000
243 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
244 #define MLX4_EN_MEMTYPE_PAD 0x100
245 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
248 struct mlx4_en_tx_desc {
249 struct mlx4_wqe_ctrl_seg ctrl;
251 struct mlx4_wqe_data_seg data; /* at least one data segment */
252 struct mlx4_wqe_lso_seg lso;
253 struct mlx4_wqe_inline_seg inl;
257 #define MLX4_EN_USE_SRQ 0x01000000
259 #define MLX4_EN_CX3_LOW_ID 0x1000
260 #define MLX4_EN_CX3_HIGH_ID 0x1005
262 struct mlx4_en_rx_alloc {
269 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
270 struct mlx4_en_page_cache {
272 struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE];
277 struct mlx4_en_tx_ring {
278 /* cache line used and dirtied in tx completion
279 * (mlx4_en_free_tx_buf())
283 unsigned long wake_queue;
285 /* cache line used and dirtied in mlx4_en_xmit() */
286 u32 prod ____cacheline_aligned_in_smp;
288 unsigned long packets;
289 unsigned long tx_csum;
290 unsigned long tso_packets;
291 unsigned long xmit_more;
292 unsigned int tx_dropped;
294 unsigned long queue_stopped;
296 /* Following part should be mostly read */
297 cpumask_t affinity_mask;
299 struct mlx4_hwq_resources wqres;
300 u32 size; /* number of TXBBs */
304 u16 cqn; /* index of port CQ associated with this ring */
309 struct mlx4_en_tx_info *tx_info;
310 struct mlx4_en_rx_ring *recycle_ring;
311 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
312 struct mlx4_en_tx_ring *ring,
314 u64 timestamp, int napi_mode);
316 struct mlx4_qp_context context;
318 enum mlx4_qp_state qp_state;
322 struct netdev_queue *tx_queue;
323 int hwtstamp_tx_type;
324 } ____cacheline_aligned_in_smp;
326 struct mlx4_en_rx_desc {
327 /* actual number of entries depends on rx ring stride */
328 struct mlx4_wqe_data_seg data[0];
331 struct mlx4_en_rx_ring {
332 struct mlx4_hwq_resources wqres;
333 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
334 u32 size ; /* number of Rx descs*/
339 u16 cqn; /* index of port CQ associated with this ring */
346 struct bpf_prog __rcu *xdp_prog;
347 struct mlx4_en_page_cache page_cache;
349 unsigned long packets;
350 unsigned long csum_ok;
351 unsigned long csum_none;
352 unsigned long csum_complete;
353 unsigned long dropped;
354 int hwtstamp_rx_filter;
355 cpumask_var_t affinity_mask;
360 struct mlx4_hwq_resources wqres;
362 struct net_device *dev;
363 struct napi_struct napi;
370 struct mlx4_cqe *buf;
371 #define MLX4_EN_OPCODE_ERROR 0x1e
373 struct irq_desc *irq_desc;
376 struct mlx4_en_port_profile {
382 u8 num_tx_rings_p_up;
389 struct hwtstamp_config hwtstamp_config;
392 struct mlx4_en_profile {
398 u8 num_tx_rings_p_up;
399 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
403 struct mlx4_dev *dev;
404 struct pci_dev *pdev;
405 struct mutex state_lock;
406 struct net_device *pndev[MLX4_MAX_PORTS + 1];
407 struct net_device *upper[MLX4_MAX_PORTS + 1];
410 struct mlx4_en_profile profile;
412 struct workqueue_struct *workqueue;
413 struct device *dma_device;
414 void __iomem *uar_map;
415 struct mlx4_uar priv_uar;
419 u8 mac_removed[MLX4_MAX_PORTS + 1];
422 struct cyclecounter cycles;
423 struct timecounter clock;
424 unsigned long last_overflow_check;
425 struct ptp_clock *ptp_clock;
426 struct ptp_clock_info ptp_clock_info;
427 struct notifier_block nb;
431 struct mlx4_en_rss_map {
433 struct mlx4_qp qps[MAX_RX_RINGS];
434 enum mlx4_qp_state state[MAX_RX_RINGS];
435 struct mlx4_qp indir_qp;
436 enum mlx4_qp_state indir_state;
439 enum mlx4_en_port_flag {
440 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
441 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
444 struct mlx4_en_port_state {
451 enum mlx4_en_mclist_act {
457 struct mlx4_en_mc_list {
458 struct list_head list;
459 enum mlx4_en_mclist_act action;
465 struct mlx4_en_frag_info {
467 u16 frag_prefix_size;
469 enum dma_data_direction dma_dir;
473 #ifdef CONFIG_MLX4_EN_DCB
474 /* Minimal TC BW - setting to 0 will block traffic */
475 #define MLX4_EN_BW_MIN 1
476 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
478 #define MLX4_EN_TC_VENDOR 0
479 #define MLX4_EN_TC_ETS 7
488 struct mlx4_en_cee_config {
490 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
494 struct ethtool_flow_id {
495 struct list_head list;
496 struct ethtool_rx_flow_spec flow_spec;
501 MLX4_EN_FLAG_PROMISC = (1 << 0),
502 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
503 /* whether we need to enable hardware loopback by putting dmac
506 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
507 /* whether we need to drop packets that hardware loopback-ed */
508 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
509 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
510 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
511 #ifdef CONFIG_MLX4_EN_DCB
512 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
516 #define PORT_BEACON_MAX_LIMIT (65535)
517 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
518 #define MLX4_EN_MAC_HASH_IDX 5
520 struct mlx4_en_stats_bitmap {
521 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
522 struct mutex mutex; /* for mutual access to stats bitmap */
526 MLX4_EN_STATE_FLAG_RESTARTING,
529 struct mlx4_en_priv {
530 struct mlx4_en_dev *mdev;
531 struct mlx4_en_port_profile *prof;
532 struct net_device *dev;
533 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
534 struct mlx4_en_port_state port_state;
535 spinlock_t stats_lock;
536 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
537 /* To allow rules removal while port is going down */
538 struct list_head ethtool_list;
540 unsigned long last_moder_packets[MAX_RX_RINGS];
541 unsigned long last_moder_tx_packets;
542 unsigned long last_moder_bytes[MAX_RX_RINGS];
543 unsigned long last_moder_jiffies;
544 int last_moder_time[MAX_RX_RINGS];
554 u32 adaptive_rx_coal;
557 u32 validate_loopback;
559 struct mlx4_hwq_resources res;
567 unsigned char current_mac[ETH_ALEN + 2];
574 struct mlx4_en_rss_map rss_map;
577 u8 num_tx_rings_p_up;
582 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
587 struct mlx4_en_tx_ring **tx_ring;
588 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
589 struct mlx4_en_cq **tx_cq;
590 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
591 struct mlx4_qp drop_qp;
592 struct work_struct rx_mode_task;
593 struct work_struct restart_task;
594 struct work_struct linkstate_task;
595 struct delayed_work stats_task;
596 struct delayed_work service_task;
597 struct work_struct vxlan_add_task;
598 struct work_struct vxlan_del_task;
599 struct mlx4_en_perf_stats pstats;
600 struct mlx4_en_pkt_stats pkstats;
601 struct mlx4_en_counter_stats pf_stats;
602 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
603 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
604 struct mlx4_en_flow_stats_rx rx_flowstats;
605 struct mlx4_en_flow_stats_tx tx_flowstats;
606 struct mlx4_en_port_stats port_stats;
607 struct mlx4_en_stats_bitmap stats_bitmap;
608 struct list_head mc_list;
609 struct list_head curr_list;
611 struct mlx4_en_stat_out_mbox hw_stats;
615 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
616 struct hwtstamp_config hwtstamp_config;
619 #ifdef CONFIG_MLX4_EN_DCB
620 #define MLX4_EN_DCB_ENABLED 0x3
622 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
623 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
624 struct mlx4_en_cee_config cee_config;
627 #ifdef CONFIG_RFS_ACCEL
628 spinlock_t filters_lock;
630 struct list_head filters;
631 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
637 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
643 MLX4_EN_WOL_MAGIC = (1ULL << 61),
644 MLX4_EN_WOL_ENABLED = (1ULL << 62),
647 struct mlx4_mac_entry {
648 struct hlist_node hlist;
649 unsigned char mac[ETH_ALEN + 2];
654 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
656 return buf + idx * cqe_sz;
659 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
661 void mlx4_en_init_ptys2ethtool_map(void);
662 void mlx4_en_update_loopback_state(struct net_device *dev,
663 netdev_features_t features);
665 void mlx4_en_destroy_netdev(struct net_device *dev);
666 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
667 struct mlx4_en_port_profile *prof);
669 int mlx4_en_start_port(struct net_device *dev);
670 void mlx4_en_stop_port(struct net_device *dev, int detach);
672 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
673 struct mlx4_en_stats_bitmap *stats_bitmap,
674 u8 rx_ppp, u8 rx_pause,
675 u8 tx_ppp, u8 tx_pause);
677 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
678 struct mlx4_en_priv *tmp,
679 struct mlx4_en_port_profile *prof);
680 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
681 struct mlx4_en_priv *tmp);
683 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
684 int entries, int ring, enum cq_type mode, int node);
685 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
686 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
688 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
689 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
690 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
692 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
693 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
694 void *accel_priv, select_queue_fallback_t fallback);
695 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
696 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_alloc *frame,
697 struct net_device *dev, unsigned int length,
698 int tx_ind, int *doorbell_pending);
699 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
700 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
701 struct mlx4_en_rx_alloc *frame);
703 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
704 struct mlx4_en_tx_ring **pring,
705 u32 size, u16 stride,
706 int node, int queue_index);
707 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
708 struct mlx4_en_tx_ring **pring);
709 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
710 struct mlx4_en_tx_ring *ring,
711 int cq, int user_prio);
712 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
713 struct mlx4_en_tx_ring *ring);
714 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
715 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
716 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
717 struct mlx4_en_rx_ring **pring,
718 u32 size, u16 stride, int node);
719 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
720 struct mlx4_en_rx_ring **pring,
721 u32 size, u16 stride);
722 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
723 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
724 struct mlx4_en_rx_ring *ring);
725 int mlx4_en_process_rx_cq(struct net_device *dev,
726 struct mlx4_en_cq *cq,
728 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
729 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
730 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
731 struct mlx4_en_tx_ring *ring,
732 int index, u8 owner, u64 timestamp,
734 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
735 struct mlx4_en_tx_ring *ring,
736 int index, u8 owner, u64 timestamp,
738 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
739 int is_tx, int rss, int qpn, int cqn, int user_prio,
740 struct mlx4_qp_context *context);
741 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
742 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
744 void mlx4_en_calc_rx_buf(struct net_device *dev);
745 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
746 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
747 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
748 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
749 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
750 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
752 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
753 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
755 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
756 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
758 #ifdef CONFIG_MLX4_EN_DCB
759 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
760 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
763 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
765 #ifdef CONFIG_RFS_ACCEL
766 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
769 #define MLX4_EN_NUM_SELF_TEST 5
770 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
771 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
773 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
774 ((dev->features & feature) ^ (new_features & feature))
776 int mlx4_en_moderation_update(struct mlx4_en_priv *priv);
777 int mlx4_en_reset_config(struct net_device *dev,
778 struct hwtstamp_config ts_config,
779 netdev_features_t new_features);
780 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
781 struct mlx4_en_stats_bitmap *stats_bitmap,
782 u8 rx_ppp, u8 rx_pause,
783 u8 tx_ppp, u8 tx_pause);
784 int mlx4_en_netdev_event(struct notifier_block *this,
785 unsigned long event, void *ptr);
788 * Functions for time stamping
790 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
791 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
792 struct skb_shared_hwtstamps *hwts,
794 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
795 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
799 extern const struct ethtool_ops mlx4_en_ethtool_ops;
804 * printk / logging functions
808 void en_print(const char *level, const struct mlx4_en_priv *priv,
809 const char *format, ...);
811 #define en_dbg(mlevel, priv, format, ...) \
813 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
814 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
816 #define en_warn(priv, format, ...) \
817 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
818 #define en_err(priv, format, ...) \
819 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
820 #define en_info(priv, format, ...) \
821 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
823 #define mlx4_err(mdev, format, ...) \
824 pr_err(DRV_NAME " %s: " format, \
825 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
826 #define mlx4_info(mdev, format, ...) \
827 pr_info(DRV_NAME " %s: " format, \
828 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
829 #define mlx4_warn(mdev, format, ...) \
830 pr_warn(DRV_NAME " %s: " format, \
831 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)