2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
37 #include <linux/mlx4/cmd.h>
38 #include <linux/mlx4/qp.h>
39 #include <linux/export.h>
43 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
45 return 1 << dev->oper_log_mgm_entry_size;
48 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
50 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
53 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
54 struct mlx4_cmd_mailbox *mailbox,
61 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
62 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
71 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
75 err = mlx4_cmd(dev, regid, 0, 0,
76 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
82 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
83 struct mlx4_cmd_mailbox *mailbox)
85 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
86 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
89 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
90 struct mlx4_cmd_mailbox *mailbox)
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
93 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
96 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
97 struct mlx4_cmd_mailbox *mailbox)
101 in_mod = (u32) port << 16 | steer << 1;
102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
103 MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
107 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
108 u16 *hash, u8 op_mod)
113 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
114 MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
123 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
124 enum mlx4_steer_type steer,
127 struct mlx4_steer *s_steer;
128 struct mlx4_promisc_qp *pqp;
130 if (port < 1 || port > dev->caps.num_ports)
133 s_steer = &mlx4_priv(dev)->steer[port - 1];
135 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
144 * Add new entry to steering data structure.
145 * All promisc QPs should be added as well
147 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
148 enum mlx4_steer_type steer,
149 unsigned int index, u32 qpn)
151 struct mlx4_steer *s_steer;
152 struct mlx4_cmd_mailbox *mailbox;
153 struct mlx4_mgm *mgm;
155 struct mlx4_steer_index *new_entry;
156 struct mlx4_promisc_qp *pqp;
157 struct mlx4_promisc_qp *dqp = NULL;
161 if (port < 1 || port > dev->caps.num_ports)
164 s_steer = &mlx4_priv(dev)->steer[port - 1];
165 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
169 INIT_LIST_HEAD(&new_entry->duplicates);
170 new_entry->index = index;
171 list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
173 /* If the given qpn is also a promisc qp,
174 * it should be inserted to duplicates list
176 pqp = get_promisc_qp(dev, port, steer, qpn);
178 dqp = kmalloc(sizeof(*dqp), GFP_KERNEL);
184 list_add_tail(&dqp->list, &new_entry->duplicates);
187 /* if no promisc qps for this vep, we are done */
188 if (list_empty(&s_steer->promisc_qps[steer]))
191 /* now need to add all the promisc qps to the new
192 * steering entry, as they should also receive the packets
193 * destined to this address */
194 mailbox = mlx4_alloc_cmd_mailbox(dev);
195 if (IS_ERR(mailbox)) {
201 err = mlx4_READ_ENTRY(dev, index, mailbox);
205 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
206 prot = be32_to_cpu(mgm->members_count) >> 30;
207 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
208 /* don't add already existing qpn */
211 if (members_count == dev->caps.num_qp_per_mgm) {
218 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
220 /* update the qps count and update the entry with all the promisc qps*/
221 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
222 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
225 mlx4_free_cmd_mailbox(dev, mailbox);
230 list_del(&dqp->list);
233 list_del(&new_entry->list);
238 /* update the data structures with existing steering entry */
239 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
240 enum mlx4_steer_type steer,
241 unsigned int index, u32 qpn)
243 struct mlx4_steer *s_steer;
244 struct mlx4_steer_index *tmp_entry, *entry = NULL;
245 struct mlx4_promisc_qp *pqp;
246 struct mlx4_promisc_qp *dqp;
248 if (port < 1 || port > dev->caps.num_ports)
251 s_steer = &mlx4_priv(dev)->steer[port - 1];
253 pqp = get_promisc_qp(dev, port, steer, qpn);
255 return 0; /* nothing to do */
257 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
258 if (tmp_entry->index == index) {
263 if (unlikely(!entry)) {
264 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
268 /* the given qpn is listed as a promisc qpn
269 * we need to add it as a duplicate to this entry
270 * for future references */
271 list_for_each_entry(dqp, &entry->duplicates, list) {
273 return 0; /* qp is already duplicated */
276 /* add the qp as a duplicate on this index */
277 dqp = kmalloc(sizeof(*dqp), GFP_KERNEL);
281 list_add_tail(&dqp->list, &entry->duplicates);
286 /* Check whether a qpn is a duplicate on steering entry
287 * If so, it should not be removed from mgm */
288 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
289 enum mlx4_steer_type steer,
290 unsigned int index, u32 qpn)
292 struct mlx4_steer *s_steer;
293 struct mlx4_steer_index *tmp_entry, *entry = NULL;
294 struct mlx4_promisc_qp *dqp, *tmp_dqp;
296 if (port < 1 || port > dev->caps.num_ports)
299 s_steer = &mlx4_priv(dev)->steer[port - 1];
301 /* if qp is not promisc, it cannot be duplicated */
302 if (!get_promisc_qp(dev, port, steer, qpn))
305 /* The qp is promisc qp so it is a duplicate on this index
306 * Find the index entry, and remove the duplicate */
307 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
308 if (tmp_entry->index == index) {
313 if (unlikely(!entry)) {
314 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
317 list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
318 if (dqp->qpn == qpn) {
319 list_del(&dqp->list);
326 /* Returns true if all the QPs != tqpn contained in this entry
327 * are Promisc QPs. Returns false otherwise.
329 static bool promisc_steering_entry(struct mlx4_dev *dev, u8 port,
330 enum mlx4_steer_type steer,
331 unsigned int index, u32 tqpn,
334 struct mlx4_cmd_mailbox *mailbox;
335 struct mlx4_mgm *mgm;
340 if (port < 1 || port > dev->caps.num_ports)
343 mailbox = mlx4_alloc_cmd_mailbox(dev);
348 if (mlx4_READ_ENTRY(dev, index, mailbox))
350 m_count = be32_to_cpu(mgm->members_count) & 0xffffff;
352 *members_count = m_count;
354 for (i = 0; i < m_count; i++) {
355 u32 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
356 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
357 /* the qp is not promisc, the entry can't be removed */
363 mlx4_free_cmd_mailbox(dev, mailbox);
367 /* IF a steering entry contains only promisc QPs, it can be removed. */
368 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
369 enum mlx4_steer_type steer,
370 unsigned int index, u32 tqpn)
372 struct mlx4_steer *s_steer;
373 struct mlx4_steer_index *entry = NULL, *tmp_entry;
377 if (port < 1 || port > dev->caps.num_ports)
380 s_steer = &mlx4_priv(dev)->steer[port - 1];
382 if (!promisc_steering_entry(dev, port, steer, index,
383 tqpn, &members_count))
386 /* All the qps currently registered for this entry are promiscuous,
387 * Checking for duplicates */
389 list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
390 if (entry->index == index) {
391 if (list_empty(&entry->duplicates) ||
392 members_count == 1) {
393 struct mlx4_promisc_qp *pqp, *tmp_pqp;
394 /* If there is only 1 entry in duplicates then
395 * this is the QP we want to delete, going over
396 * the list and deleting the entry.
398 list_del(&entry->list);
399 list_for_each_entry_safe(pqp, tmp_pqp,
402 list_del(&pqp->list);
407 /* This entry contains duplicates so it shouldn't be removed */
418 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
419 enum mlx4_steer_type steer, u32 qpn)
421 struct mlx4_steer *s_steer;
422 struct mlx4_cmd_mailbox *mailbox;
423 struct mlx4_mgm *mgm;
424 struct mlx4_steer_index *entry;
425 struct mlx4_promisc_qp *pqp;
426 struct mlx4_promisc_qp *dqp;
432 struct mlx4_priv *priv = mlx4_priv(dev);
434 if (port < 1 || port > dev->caps.num_ports)
437 s_steer = &mlx4_priv(dev)->steer[port - 1];
439 mutex_lock(&priv->mcg_table.mutex);
441 if (get_promisc_qp(dev, port, steer, qpn)) {
442 err = 0; /* Noting to do, already exists */
446 pqp = kmalloc(sizeof(*pqp), GFP_KERNEL);
453 mailbox = mlx4_alloc_cmd_mailbox(dev);
454 if (IS_ERR(mailbox)) {
460 if (!(mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)) {
461 /* The promisc QP needs to be added for each one of the steering
462 * entries. If it already exists, needs to be added as
463 * a duplicate for this entry.
465 list_for_each_entry(entry,
466 &s_steer->steer_entries[steer],
468 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
472 members_count = be32_to_cpu(mgm->members_count) &
474 prot = be32_to_cpu(mgm->members_count) >> 30;
476 for (i = 0; i < members_count; i++) {
477 if ((be32_to_cpu(mgm->qp[i]) &
478 MGM_QPN_MASK) == qpn) {
479 /* Entry already exists.
482 dqp = kmalloc(sizeof(*dqp), GFP_KERNEL);
488 list_add_tail(&dqp->list,
494 /* Need to add the qpn to mgm */
496 dev->caps.num_qp_per_mgm) {
501 mgm->qp[members_count++] =
502 cpu_to_be32(qpn & MGM_QPN_MASK);
504 cpu_to_be32(members_count |
506 err = mlx4_WRITE_ENTRY(dev, entry->index,
514 /* add the new qpn to list of promisc qps */
515 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
516 /* now need to add all the promisc qps to default entry */
517 memset(mgm, 0, sizeof(*mgm));
519 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) {
520 if (members_count == dev->caps.num_qp_per_mgm) {
525 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
527 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
529 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
533 mlx4_free_cmd_mailbox(dev, mailbox);
534 mutex_unlock(&priv->mcg_table.mutex);
538 list_del(&pqp->list);
540 mlx4_free_cmd_mailbox(dev, mailbox);
544 mutex_unlock(&priv->mcg_table.mutex);
548 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
549 enum mlx4_steer_type steer, u32 qpn)
551 struct mlx4_priv *priv = mlx4_priv(dev);
552 struct mlx4_steer *s_steer;
553 struct mlx4_cmd_mailbox *mailbox;
554 struct mlx4_mgm *mgm;
555 struct mlx4_steer_index *entry, *tmp_entry;
556 struct mlx4_promisc_qp *pqp;
557 struct mlx4_promisc_qp *dqp;
560 bool back_to_list = false;
564 if (port < 1 || port > dev->caps.num_ports)
567 s_steer = &mlx4_priv(dev)->steer[port - 1];
568 mutex_lock(&priv->mcg_table.mutex);
570 pqp = get_promisc_qp(dev, port, steer, qpn);
571 if (unlikely(!pqp)) {
572 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
578 /*remove from list of promisc qps */
579 list_del(&pqp->list);
581 /* set the default entry not to include the removed one */
582 mailbox = mlx4_alloc_cmd_mailbox(dev);
583 if (IS_ERR(mailbox)) {
590 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
591 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
592 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
594 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
598 if (!(mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)) {
599 /* Remove the QP from all the steering entries */
600 list_for_each_entry_safe(entry, tmp_entry,
601 &s_steer->steer_entries[steer],
604 list_for_each_entry(dqp, &entry->duplicates, list) {
605 if (dqp->qpn == qpn) {
611 /* A duplicate, no need to change the MGM,
612 * only update the duplicates list
614 list_del(&dqp->list);
619 err = mlx4_READ_ENTRY(dev,
625 be32_to_cpu(mgm->members_count) &
627 if (!members_count) {
628 mlx4_warn(dev, "QP %06x wasn't found in entry %x mcount=0. deleting entry...\n",
630 list_del(&entry->list);
635 for (i = 0; i < members_count; ++i)
636 if ((be32_to_cpu(mgm->qp[i]) &
637 MGM_QPN_MASK) == qpn) {
643 mlx4_err(dev, "QP %06x wasn't found in entry %d\n",
649 /* Copy the last QP in this MGM
652 mgm->qp[loc] = mgm->qp[members_count - 1];
653 mgm->qp[members_count - 1] = 0;
655 cpu_to_be32(--members_count |
656 (MLX4_PROT_ETH << 30));
658 err = mlx4_WRITE_ENTRY(dev,
668 mlx4_free_cmd_mailbox(dev, mailbox);
671 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
675 mutex_unlock(&priv->mcg_table.mutex);
680 * Caller must hold MCG table semaphore. gid and mgm parameters must
681 * be properly aligned for command interface.
683 * Returns 0 unless a firmware command error occurs.
685 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
686 * and *mgm holds MGM entry.
688 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
689 * previous entry in hash chain and *mgm holds AMGM entry.
691 * If no AMGM exists for given gid, *index = -1, *prev = index of last
692 * entry in hash chain and *mgm holds end of hash chain.
694 static int find_entry(struct mlx4_dev *dev, u8 port,
695 u8 *gid, enum mlx4_protocol prot,
696 struct mlx4_cmd_mailbox *mgm_mailbox,
697 int *prev, int *index)
699 struct mlx4_cmd_mailbox *mailbox;
700 struct mlx4_mgm *mgm = mgm_mailbox->buf;
704 u8 op_mod = (prot == MLX4_PROT_ETH) ?
705 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
707 mailbox = mlx4_alloc_cmd_mailbox(dev);
712 memcpy(mgid, gid, 16);
714 err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
715 mlx4_free_cmd_mailbox(dev, mailbox);
720 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
726 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
730 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
731 if (*index != hash) {
732 mlx4_err(dev, "Found zero MGID in AMGM\n");
738 if (!memcmp(mgm->gid, gid, 16) &&
739 be32_to_cpu(mgm->members_count) >> 30 == prot)
743 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
750 static const u8 __promisc_mode[] = {
751 [MLX4_FS_REGULAR] = 0x0,
752 [MLX4_FS_ALL_DEFAULT] = 0x1,
753 [MLX4_FS_MC_DEFAULT] = 0x3,
754 [MLX4_FS_MIRROR_RX_PORT] = 0x4,
755 [MLX4_FS_MIRROR_SX_PORT] = 0x5,
756 [MLX4_FS_UC_SNIFFER] = 0x6,
757 [MLX4_FS_MC_SNIFFER] = 0x7,
760 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
761 enum mlx4_net_trans_promisc_mode flow_type)
763 if (flow_type >= MLX4_FS_MODE_NUM) {
764 mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type);
767 return __promisc_mode[flow_type];
769 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode);
771 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
772 struct mlx4_net_trans_rule_hw_ctrl *hw)
776 flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
777 flags |= ctrl->exclusive ? (1 << 2) : 0;
778 flags |= ctrl->allow_loopback ? (1 << 3) : 0;
781 hw->type = __promisc_mode[ctrl->promisc_mode];
782 hw->prio = cpu_to_be16(ctrl->priority);
783 hw->port = ctrl->port;
784 hw->qpn = cpu_to_be32(ctrl->qpn);
787 const u16 __sw_id_hw[] = {
788 [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001,
789 [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005,
790 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003,
791 [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002,
792 [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004,
793 [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006,
794 [MLX4_NET_TRANS_RULE_ID_VXLAN] = 0xE008
797 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
798 enum mlx4_net_trans_rule_id id)
800 if (id >= MLX4_NET_TRANS_RULE_NUM) {
801 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
804 return __sw_id_hw[id];
806 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id);
808 static const int __rule_hw_sz[] = {
809 [MLX4_NET_TRANS_RULE_ID_ETH] =
810 sizeof(struct mlx4_net_trans_rule_hw_eth),
811 [MLX4_NET_TRANS_RULE_ID_IB] =
812 sizeof(struct mlx4_net_trans_rule_hw_ib),
813 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
814 [MLX4_NET_TRANS_RULE_ID_IPV4] =
815 sizeof(struct mlx4_net_trans_rule_hw_ipv4),
816 [MLX4_NET_TRANS_RULE_ID_TCP] =
817 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
818 [MLX4_NET_TRANS_RULE_ID_UDP] =
819 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
820 [MLX4_NET_TRANS_RULE_ID_VXLAN] =
821 sizeof(struct mlx4_net_trans_rule_hw_vxlan)
824 int mlx4_hw_rule_sz(struct mlx4_dev *dev,
825 enum mlx4_net_trans_rule_id id)
827 if (id >= MLX4_NET_TRANS_RULE_NUM) {
828 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
832 return __rule_hw_sz[id];
834 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz);
836 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
837 struct _rule_hw *rule_hw)
839 if (mlx4_hw_rule_sz(dev, spec->id) < 0)
841 memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id));
842 rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
843 rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2;
846 case MLX4_NET_TRANS_RULE_ID_ETH:
847 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
848 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
850 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
851 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
853 if (spec->eth.ether_type_enable) {
854 rule_hw->eth.ether_type_enable = 1;
855 rule_hw->eth.ether_type = spec->eth.ether_type;
857 rule_hw->eth.vlan_tag = spec->eth.vlan_id;
858 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk;
861 case MLX4_NET_TRANS_RULE_ID_IB:
862 rule_hw->ib.l3_qpn = spec->ib.l3_qpn;
863 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
864 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
865 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
868 case MLX4_NET_TRANS_RULE_ID_IPV6:
871 case MLX4_NET_TRANS_RULE_ID_IPV4:
872 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
873 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
874 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
875 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
878 case MLX4_NET_TRANS_RULE_ID_TCP:
879 case MLX4_NET_TRANS_RULE_ID_UDP:
880 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
881 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
882 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
883 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
886 case MLX4_NET_TRANS_RULE_ID_VXLAN:
888 cpu_to_be32(be32_to_cpu(spec->vxlan.vni) << 8);
889 rule_hw->vxlan.vni_mask =
890 cpu_to_be32(be32_to_cpu(spec->vxlan.vni_mask) << 8);
897 return __rule_hw_sz[spec->id];
900 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
901 struct mlx4_net_trans_rule *rule)
904 struct mlx4_spec_list *cur;
908 mlx4_err(dev, "%s", str);
909 len += scnprintf(buf + len, BUF_SIZE - len,
910 "port = %d prio = 0x%x qp = 0x%x ",
911 rule->port, rule->priority, rule->qpn);
913 list_for_each_entry(cur, &rule->list, list) {
915 case MLX4_NET_TRANS_RULE_ID_ETH:
916 len += scnprintf(buf + len, BUF_SIZE - len,
917 "dmac = %pM ", &cur->eth.dst_mac);
918 if (cur->eth.ether_type)
919 len += scnprintf(buf + len, BUF_SIZE - len,
921 be16_to_cpu(cur->eth.ether_type));
922 if (cur->eth.vlan_id)
923 len += scnprintf(buf + len, BUF_SIZE - len,
925 be16_to_cpu(cur->eth.vlan_id));
928 case MLX4_NET_TRANS_RULE_ID_IPV4:
929 if (cur->ipv4.src_ip)
930 len += scnprintf(buf + len, BUF_SIZE - len,
933 if (cur->ipv4.dst_ip)
934 len += scnprintf(buf + len, BUF_SIZE - len,
939 case MLX4_NET_TRANS_RULE_ID_TCP:
940 case MLX4_NET_TRANS_RULE_ID_UDP:
941 if (cur->tcp_udp.src_port)
942 len += scnprintf(buf + len, BUF_SIZE - len,
944 be16_to_cpu(cur->tcp_udp.src_port));
945 if (cur->tcp_udp.dst_port)
946 len += scnprintf(buf + len, BUF_SIZE - len,
948 be16_to_cpu(cur->tcp_udp.dst_port));
951 case MLX4_NET_TRANS_RULE_ID_IB:
952 len += scnprintf(buf + len, BUF_SIZE - len,
953 "dst-gid = %pI6\n", cur->ib.dst_gid);
954 len += scnprintf(buf + len, BUF_SIZE - len,
955 "dst-gid-mask = %pI6\n",
956 cur->ib.dst_gid_msk);
959 case MLX4_NET_TRANS_RULE_ID_VXLAN:
960 len += scnprintf(buf + len, BUF_SIZE - len,
961 "VNID = %d ", be32_to_cpu(cur->vxlan.vni));
963 case MLX4_NET_TRANS_RULE_ID_IPV6:
970 len += scnprintf(buf + len, BUF_SIZE - len, "\n");
971 mlx4_err(dev, "%s", buf);
974 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small\n");
977 int mlx4_flow_attach(struct mlx4_dev *dev,
978 struct mlx4_net_trans_rule *rule, u64 *reg_id)
980 struct mlx4_cmd_mailbox *mailbox;
981 struct mlx4_spec_list *cur;
985 mailbox = mlx4_alloc_cmd_mailbox(dev);
987 return PTR_ERR(mailbox);
989 if (!mlx4_qp_lookup(dev, rule->qpn)) {
990 mlx4_err_rule(dev, "QP doesn't exist\n", rule);
995 trans_rule_ctrl_to_hw(rule, mailbox->buf);
997 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
999 list_for_each_entry(cur, &rule->list, list) {
1000 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
1007 ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
1008 if (ret == -ENOMEM) {
1010 "mcg table is full. Fail to register network rule\n",
1013 if (ret == -ENXIO) {
1014 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED)
1016 "DMFS is not enabled, "
1017 "failed to register network rule.\n",
1021 "Rule exceeds the dmfs_high_rate_mode limitations, "
1022 "failed to register network rule.\n",
1026 mlx4_err_rule(dev, "Fail to register network rule.\n", rule);
1031 mlx4_free_cmd_mailbox(dev, mailbox);
1035 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
1037 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
1041 err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
1043 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
1047 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
1049 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, const unsigned char *addr,
1050 int port, int qpn, u16 prio, u64 *reg_id)
1053 struct mlx4_spec_list spec_eth_outer = { {NULL} };
1054 struct mlx4_spec_list spec_vxlan = { {NULL} };
1055 struct mlx4_spec_list spec_eth_inner = { {NULL} };
1057 struct mlx4_net_trans_rule rule = {
1058 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1060 .allow_loopback = 1,
1061 .promisc_mode = MLX4_FS_REGULAR,
1064 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1068 rule.priority = prio;
1069 INIT_LIST_HEAD(&rule.list);
1071 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
1072 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
1073 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1075 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
1076 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
1078 list_add_tail(&spec_eth_outer.list, &rule.list);
1079 list_add_tail(&spec_vxlan.list, &rule.list);
1080 list_add_tail(&spec_eth_inner.list, &rule.list);
1082 err = mlx4_flow_attach(dev, &rule, reg_id);
1085 EXPORT_SYMBOL(mlx4_tunnel_steer_add);
1087 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1093 in_param = ((u64) min_range_qpn) << 32;
1094 in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF;
1096 err = mlx4_cmd(dev, in_param, 0, 0,
1097 MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1098 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1102 EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE);
1104 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1105 int block_mcast_loopback, enum mlx4_protocol prot,
1106 enum mlx4_steer_type steer)
1108 struct mlx4_priv *priv = mlx4_priv(dev);
1109 struct mlx4_cmd_mailbox *mailbox;
1110 struct mlx4_mgm *mgm;
1112 int index = -1, prev;
1119 mailbox = mlx4_alloc_cmd_mailbox(dev);
1120 if (IS_ERR(mailbox))
1121 return PTR_ERR(mailbox);
1124 mutex_lock(&priv->mcg_table.mutex);
1125 err = find_entry(dev, port, gid, prot,
1126 mailbox, &prev, &index);
1131 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
1133 memcpy(mgm->gid, gid, 16);
1138 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
1140 mlx4_err(dev, "No AMGM entries left\n");
1144 index += dev->caps.num_mgms;
1147 memset(mgm, 0, sizeof(*mgm));
1148 memcpy(mgm->gid, gid, 16);
1151 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1152 if (members_count == dev->caps.num_qp_per_mgm) {
1153 mlx4_err(dev, "MGM at index %x is full\n", index);
1158 for (i = 0; i < members_count; ++i)
1159 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1160 mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
1165 if (block_mcast_loopback)
1166 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
1167 (1U << MGM_BLCK_LB_BIT));
1169 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
1171 mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
1173 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1180 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1184 mgm->next_gid_index = cpu_to_be32(index << 6);
1186 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1191 if (prot == MLX4_PROT_ETH && index != -1) {
1192 /* manage the steering entry for promisc mode */
1194 err = new_steering_entry(dev, port, steer,
1197 err = existing_steering_entry(dev, port, steer,
1200 if (err && link && index != -1) {
1201 if (index < dev->caps.num_mgms)
1202 mlx4_warn(dev, "Got AMGM index %d < %d\n",
1203 index, dev->caps.num_mgms);
1205 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1206 index - dev->caps.num_mgms, MLX4_USE_RR);
1208 mutex_unlock(&priv->mcg_table.mutex);
1210 mlx4_free_cmd_mailbox(dev, mailbox);
1214 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1215 enum mlx4_protocol prot, enum mlx4_steer_type steer)
1217 struct mlx4_priv *priv = mlx4_priv(dev);
1218 struct mlx4_cmd_mailbox *mailbox;
1219 struct mlx4_mgm *mgm;
1225 bool removed_entry = false;
1227 mailbox = mlx4_alloc_cmd_mailbox(dev);
1228 if (IS_ERR(mailbox))
1229 return PTR_ERR(mailbox);
1232 mutex_lock(&priv->mcg_table.mutex);
1234 err = find_entry(dev, port, gid, prot,
1235 mailbox, &prev, &index);
1240 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1245 /* If this QP is also a promisc QP, it shouldn't be removed only if
1246 * at least one none promisc QP is also attached to this MCG
1248 if (prot == MLX4_PROT_ETH &&
1249 check_duplicate_entry(dev, port, steer, index, qp->qpn) &&
1250 !promisc_steering_entry(dev, port, steer, index, qp->qpn, NULL))
1253 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1254 for (i = 0; i < members_count; ++i)
1255 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1261 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1266 /* copy the last QP in this MGM over removed QP */
1267 mgm->qp[loc] = mgm->qp[members_count - 1];
1268 mgm->qp[members_count - 1] = 0;
1269 mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1271 if (prot == MLX4_PROT_ETH)
1272 removed_entry = can_remove_steering_entry(dev, port, steer,
1274 if (members_count && (prot != MLX4_PROT_ETH || !removed_entry)) {
1275 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1279 /* We are going to delete the entry, members count should be 0 */
1280 mgm->members_count = cpu_to_be32((u32) prot << 30);
1283 /* Remove entry from MGM */
1284 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1286 err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1290 memset(mgm->gid, 0, 16);
1292 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1297 if (amgm_index < dev->caps.num_mgms)
1298 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d\n",
1299 index, amgm_index, dev->caps.num_mgms);
1301 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1302 amgm_index - dev->caps.num_mgms, MLX4_USE_RR);
1305 /* Remove entry from AMGM */
1306 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1307 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1311 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1313 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1317 if (index < dev->caps.num_mgms)
1318 mlx4_warn(dev, "entry %d had next AMGM index %d < %d\n",
1319 prev, index, dev->caps.num_mgms);
1321 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1322 index - dev->caps.num_mgms, MLX4_USE_RR);
1326 mutex_unlock(&priv->mcg_table.mutex);
1328 mlx4_free_cmd_mailbox(dev, mailbox);
1329 if (err && dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
1330 /* In case device is under an error, return success as a closing command */
1335 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1336 u8 gid[16], u8 attach, u8 block_loopback,
1337 enum mlx4_protocol prot)
1339 struct mlx4_cmd_mailbox *mailbox;
1343 if (!mlx4_is_mfunc(dev))
1346 mailbox = mlx4_alloc_cmd_mailbox(dev);
1347 if (IS_ERR(mailbox))
1348 return PTR_ERR(mailbox);
1350 memcpy(mailbox->buf, gid, 16);
1352 qpn |= (prot << 28);
1353 if (attach && block_loopback)
1356 err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1357 MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1360 mlx4_free_cmd_mailbox(dev, mailbox);
1361 if (err && !attach &&
1362 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
1367 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1368 u8 gid[16], u8 port,
1369 int block_mcast_loopback,
1370 enum mlx4_protocol prot, u64 *reg_id)
1372 struct mlx4_spec_list spec = { {NULL} };
1373 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1375 struct mlx4_net_trans_rule rule = {
1376 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1378 .promisc_mode = MLX4_FS_REGULAR,
1379 .priority = MLX4_DOMAIN_NIC,
1382 rule.allow_loopback = !block_mcast_loopback;
1385 INIT_LIST_HEAD(&rule.list);
1389 spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1390 memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1391 memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1394 case MLX4_PROT_IB_IPV6:
1395 spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1396 memcpy(spec.ib.dst_gid, gid, 16);
1397 memset(&spec.ib.dst_gid_msk, 0xff, 16);
1402 list_add_tail(&spec.list, &rule.list);
1404 return mlx4_flow_attach(dev, &rule, reg_id);
1407 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1408 u8 port, int block_mcast_loopback,
1409 enum mlx4_protocol prot, u64 *reg_id)
1411 switch (dev->caps.steering_mode) {
1412 case MLX4_STEERING_MODE_A0:
1413 if (prot == MLX4_PROT_ETH)
1417 case MLX4_STEERING_MODE_B0:
1418 if (prot == MLX4_PROT_ETH)
1419 gid[7] |= (MLX4_MC_STEER << 1);
1421 if (mlx4_is_mfunc(dev))
1422 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1423 block_mcast_loopback, prot);
1424 return mlx4_qp_attach_common(dev, qp, gid,
1425 block_mcast_loopback, prot,
1428 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1429 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
1430 block_mcast_loopback,
1436 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1438 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1439 enum mlx4_protocol prot, u64 reg_id)
1441 switch (dev->caps.steering_mode) {
1442 case MLX4_STEERING_MODE_A0:
1443 if (prot == MLX4_PROT_ETH)
1447 case MLX4_STEERING_MODE_B0:
1448 if (prot == MLX4_PROT_ETH)
1449 gid[7] |= (MLX4_MC_STEER << 1);
1451 if (mlx4_is_mfunc(dev))
1452 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1454 return mlx4_qp_detach_common(dev, qp, gid, prot,
1457 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1458 return mlx4_flow_detach(dev, reg_id);
1464 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1466 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1467 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1469 struct mlx4_net_trans_rule rule = {
1470 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1472 .allow_loopback = 1,
1478 case MLX4_FS_ALL_DEFAULT:
1479 regid_p = &dev->regid_promisc_array[port];
1481 case MLX4_FS_MC_DEFAULT:
1482 regid_p = &dev->regid_allmulti_array[port];
1491 rule.promisc_mode = mode;
1494 INIT_LIST_HEAD(&rule.list);
1495 mlx4_info(dev, "going promisc on %x\n", port);
1497 return mlx4_flow_attach(dev, &rule, regid_p);
1499 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1501 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1502 enum mlx4_net_trans_promisc_mode mode)
1508 case MLX4_FS_ALL_DEFAULT:
1509 regid_p = &dev->regid_promisc_array[port];
1511 case MLX4_FS_MC_DEFAULT:
1512 regid_p = &dev->regid_allmulti_array[port];
1521 ret = mlx4_flow_detach(dev, *regid_p);
1527 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1529 int mlx4_unicast_attach(struct mlx4_dev *dev,
1530 struct mlx4_qp *qp, u8 gid[16],
1531 int block_mcast_loopback, enum mlx4_protocol prot)
1533 if (prot == MLX4_PROT_ETH)
1534 gid[7] |= (MLX4_UC_STEER << 1);
1536 if (mlx4_is_mfunc(dev))
1537 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1538 block_mcast_loopback, prot);
1540 return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1541 prot, MLX4_UC_STEER);
1543 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1545 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1546 u8 gid[16], enum mlx4_protocol prot)
1548 if (prot == MLX4_PROT_ETH)
1549 gid[7] |= (MLX4_UC_STEER << 1);
1551 if (mlx4_is_mfunc(dev))
1552 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1554 return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1556 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1558 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1559 struct mlx4_vhcr *vhcr,
1560 struct mlx4_cmd_mailbox *inbox,
1561 struct mlx4_cmd_mailbox *outbox,
1562 struct mlx4_cmd_info *cmd)
1564 u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1565 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_param >> 62);
1566 enum mlx4_steer_type steer = vhcr->in_modifier;
1571 /* Promiscuous unicast is not allowed in mfunc */
1572 if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1575 if (vhcr->op_modifier)
1576 return add_promisc_qp(dev, port, steer, qpn);
1578 return remove_promisc_qp(dev, port, steer, qpn);
1581 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1582 enum mlx4_steer_type steer, u8 add, u8 port)
1584 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1585 MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1589 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1591 if (mlx4_is_mfunc(dev))
1592 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1594 return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1596 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1598 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1600 if (mlx4_is_mfunc(dev))
1601 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1603 return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1605 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1607 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1609 if (mlx4_is_mfunc(dev))
1610 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1612 return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1614 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1616 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1618 if (mlx4_is_mfunc(dev))
1619 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1621 return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1623 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1625 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1627 struct mlx4_priv *priv = mlx4_priv(dev);
1630 /* No need for mcg_table when fw managed the mcg table*/
1631 if (dev->caps.steering_mode ==
1632 MLX4_STEERING_MODE_DEVICE_MANAGED)
1634 err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1635 dev->caps.num_amgms - 1, 0, 0);
1639 mutex_init(&priv->mcg_table.mutex);
1644 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1646 if (dev->caps.steering_mode !=
1647 MLX4_STEERING_MODE_DEVICE_MANAGED)
1648 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);