drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/errno.h>
  40 #include <linux/pci.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/slab.h>
  43 #include <linux/io-mapping.h>
  44 #include <linux/delay.h>
  45 #include <linux/kmod.h>
  46 #include <linux/etherdevice.h>
  47 #include <net/devlink.h>
  48
  49 #include <linux/mlx4/device.h>
  50 #include <linux/mlx4/doorbell.h>
  51
  52 #include "mlx4.h"
  53 #include "fw.h"
  54 #include "icm.h"
  55
  56 MODULE_AUTHOR("Roland Dreier");
  57 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  58 MODULE_LICENSE("Dual BSD/GPL");
  59 MODULE_VERSION(DRV_VERSION);
  60
  61 struct workqueue_struct *mlx4_wq;
  62
  63 #ifdef CONFIG_MLX4_DEBUG
  64
  65 int mlx4_debug_level = 0;
  66 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  67 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  68
  69 #endif /* CONFIG_MLX4_DEBUG */
  70
  71 #ifdef CONFIG_PCI_MSI
  72
  73 static int msi_x = 1;
  74 module_param(msi_x, int, 0444);
  75 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  76
  77 #else /* CONFIG_PCI_MSI */
  78
  79 #define msi_x (0)
  80
  81 #endif /* CONFIG_PCI_MSI */
  82
  83 static uint8_t num_vfs[3] = {0, 0, 0};
  84 static int num_vfs_argc;
  85 module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
  86 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
  87                           "num_vfs=port1,port2,port1+2");
  88
  89 static uint8_t probe_vf[3] = {0, 0, 0};
  90 static int probe_vfs_argc;
  91 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
  92 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
  93                            "probe_vf=port1,port2,port1+2");
  94
  95 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
  96 module_param_named(log_num_mgm_entry_size,
  97                         mlx4_log_num_mgm_entry_size, int, 0444);
  98 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  99                                          " of qp per mcg, for example:"
 100                                          " 10 gives 248.range: 7 <="
 101                                          " log_num_mgm_entry_size <= 12."
 102                                          " To activate device managed"
 103                                          " flow steering when available, set to -1");
 104
 105 static bool enable_64b_cqe_eqe = true;
 106 module_param(enable_64b_cqe_eqe, bool, 0444);
 107 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 108                  "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
 109
 110 static bool enable_4k_uar;
 111 module_param(enable_4k_uar, bool, 0444);
 112 MODULE_PARM_DESC(enable_4k_uar,
 113                  "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
 114
 115 #define PF_CONTEXT_BEHAVIOUR_MASK       (MLX4_FUNC_CAP_64B_EQE_CQE | \
 116                                          MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
 117                                          MLX4_FUNC_CAP_DMFS_A0_STATIC)
 118
 119 #define RESET_PERSIST_MASK_FLAGS        (MLX4_FLAG_SRIOV)
 120
 121 static char mlx4_version[] =
 122         DRV_NAME ": Mellanox ConnectX core driver v"
 123         DRV_VERSION "\n";
 124
 125 static const struct mlx4_profile default_profile = {
 126         .num_qp         = 1 << 18,
 127         .num_srq        = 1 << 16,
 128         .rdmarc_per_qp  = 1 << 4,
 129         .num_cq         = 1 << 16,
 130         .num_mcg        = 1 << 13,
 131         .num_mpt        = 1 << 19,
 132         .num_mtt        = 1 << 20, /* It is really num mtt segements */
 133 };
 134
 135 static const struct mlx4_profile low_mem_profile = {
 136         .num_qp         = 1 << 17,
 137         .num_srq        = 1 << 6,
 138         .rdmarc_per_qp  = 1 << 4,
 139         .num_cq         = 1 << 8,
 140         .num_mcg        = 1 << 8,
 141         .num_mpt        = 1 << 9,
 142         .num_mtt        = 1 << 7,
 143 };
 144
 145 static int log_num_mac = 7;
 146 module_param_named(log_num_mac, log_num_mac, int, 0444);
 147 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 148
 149 static int log_num_vlan;
 150 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 151 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 152 /* Log2 max number of VLANs per ETH port (0-7) */
 153 #define MLX4_LOG_NUM_VLANS 7
 154 #define MLX4_MIN_LOG_NUM_VLANS 0
 155 #define MLX4_MIN_LOG_NUM_MAC 1
 156
 157 static bool use_prio;
 158 module_param_named(use_prio, use_prio, bool, 0444);
 159 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
 160
 161 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 162 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 163 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 164
 165 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
 166 static int arr_argc = 2;
 167 module_param_array(port_type_array, int, &arr_argc, 0444);
 168 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
 169                                 "1 for IB, 2 for Ethernet");
 170
 171 struct mlx4_port_config {
 172         struct list_head list;
 173         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 174         struct pci_dev *pdev;
 175 };
 176
 177 static atomic_t pf_loading = ATOMIC_INIT(0);
 178
 179 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
 180                                               struct mlx4_dev_cap *dev_cap)
 181 {
 182         /* The reserved_uars is calculated by system page size unit.
 183          * Therefore, adjustment is added when the uar page size is less
 184          * than the system page size
 185          */
 186         dev->caps.reserved_uars =
 187                 max_t(int,
 188                       mlx4_get_num_reserved_uar(dev),
 189                       dev_cap->reserved_uars /
 190                         (1 << (PAGE_SHIFT - dev->uar_page_shift)));
 191 }
 192
 193 int mlx4_check_port_params(struct mlx4_dev *dev,
 194                            enum mlx4_port_type *port_type)
 195 {
 196         int i;
 197
 198         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 199                 for (i = 0; i < dev->caps.num_ports - 1; i++) {
 200                         if (port_type[i] != port_type[i + 1]) {
 201                                 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
 202                                 return -EOPNOTSUPP;
 203                         }
 204                 }
 205         }
 206
 207         for (i = 0; i < dev->caps.num_ports; i++) {
 208                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 209                         mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
 210                                  i + 1);
 211                         return -EOPNOTSUPP;
 212                 }
 213         }
 214         return 0;
 215 }
 216
 217 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 218 {
 219         int i;
 220
 221         for (i = 1; i <= dev->caps.num_ports; ++i)
 222                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 223 }
 224
 225 enum {
 226         MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
 227 };
 228
 229 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 230 {
 231         int err = 0;
 232         struct mlx4_func func;
 233
 234         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
 235                 err = mlx4_QUERY_FUNC(dev, &func, 0);
 236                 if (err) {
 237                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 238                         return err;
 239                 }
 240                 dev_cap->max_eqs = func.max_eq;
 241                 dev_cap->reserved_eqs = func.rsvd_eqs;
 242                 dev_cap->reserved_uars = func.rsvd_uars;
 243                 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
 244         }
 245         return err;
 246 }
 247
 248 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
 249 {
 250         struct mlx4_caps *dev_cap = &dev->caps;
 251
 252         /* FW not supporting or cancelled by user */
 253         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
 254             !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
 255                 return;
 256
 257         /* Must have 64B CQE_EQE enabled by FW to use bigger stride
 258          * When FW has NCSI it may decide not to report 64B CQE/EQEs
 259          */
 260         if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
 261             !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
 262                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 263                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 264                 return;
 265         }
 266
 267         if (cache_line_size() == 128 || cache_line_size() == 256) {
 268                 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
 269                 /* Changing the real data inside CQE size to 32B */
 270                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 271                 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 272
 273                 if (mlx4_is_master(dev))
 274                         dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
 275         } else {
 276                 if (cache_line_size() != 32  && cache_line_size() != 64)
 277                         mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
 278                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 279                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 280         }
 281 }
 282
 283 static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
 284                           struct mlx4_port_cap *port_cap)
 285 {
 286         dev->caps.vl_cap[port]      = port_cap->max_vl;
 287         dev->caps.ib_mtu_cap[port]          = port_cap->ib_mtu;
 288         dev->phys_caps.gid_phys_table_len[port]  = port_cap->max_gids;
 289         dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
 290         /* set gid and pkey table operating lengths by default
 291          * to non-sriov values
 292          */
 293         dev->caps.gid_table_len[port]  = port_cap->max_gids;
 294         dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
 295         dev->caps.port_width_cap[port] = port_cap->max_port_width;
 296         dev->caps.eth_mtu_cap[port]    = port_cap->eth_mtu;
 297         dev->caps.max_tc_eth           = port_cap->max_tc_eth;
 298         dev->caps.def_mac[port]        = port_cap->def_mac;
 299         dev->caps.supported_type[port] = port_cap->supported_port_types;
 300         dev->caps.suggested_type[port] = port_cap->suggested_type;
 301         dev->caps.default_sense[port] = port_cap->default_sense;
 302         dev->caps.trans_type[port]          = port_cap->trans_type;
 303         dev->caps.vendor_oui[port]     = port_cap->vendor_oui;
 304         dev->caps.wavelength[port]     = port_cap->wavelength;
 305         dev->caps.trans_code[port]     = port_cap->trans_code;
 306
 307         return 0;
 308 }
 309
 310 static int mlx4_dev_port(struct mlx4_dev *dev, int port,
 311                          struct mlx4_port_cap *port_cap)
 312 {
 313         int err = 0;
 314
 315         err = mlx4_QUERY_PORT(dev, port, port_cap);
 316
 317         if (err)
 318                 mlx4_err(dev, "QUERY_PORT command failed.\n");
 319
 320         return err;
 321 }
 322
 323 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
 324 {
 325         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
 326                 return;
 327
 328         if (mlx4_is_mfunc(dev)) {
 329                 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
 330                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 331                 return;
 332         }
 333
 334         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
 335                 mlx4_dbg(dev,
 336                          "Keep FCS is not supported - Disabling Ignore FCS");
 337                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
 338                 return;
 339         }
 340 }
 341
 342 #define MLX4_A0_STEERING_TABLE_SIZE     256
 343 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 344 {
 345         int err;
 346         int i;
 347
 348         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 349         if (err) {
 350                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 351                 return err;
 352         }
 353         mlx4_dev_cap_dump(dev, dev_cap);
 354
 355         if (dev_cap->min_page_sz > PAGE_SIZE) {
 356                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 357                          dev_cap->min_page_sz, PAGE_SIZE);
 358                 return -ENODEV;
 359         }
 360         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 361                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 362                          dev_cap->num_ports, MLX4_MAX_PORTS);
 363                 return -ENODEV;
 364         }
 365
 366         if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
 367                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 368                          dev_cap->uar_size,
 369                          (unsigned long long)
 370                          pci_resource_len(dev->persist->pdev, 2));
 371                 return -ENODEV;
 372         }
 373
 374         dev->caps.num_ports          = dev_cap->num_ports;
 375         dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
 376         dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
 377                                       dev->caps.num_sys_eqs :
 378                                       MLX4_MAX_EQ_NUM;
 379         for (i = 1; i <= dev->caps.num_ports; ++i) {
 380                 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
 381                 if (err) {
 382                         mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
 383                         return err;
 384                 }
 385         }
 386
 387         dev->caps.uar_page_size      = PAGE_SIZE;
 388         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 389         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 390         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 391         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 392         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 393         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 394         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 395         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 396         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 397         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 398         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 399         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 400         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 401         /*
 402          * Subtract 1 from the limit because we need to allocate a
 403          * spare CQE so the HCA HW can tell the difference between an
 404          * empty CQ and a full CQ.
 405          */
 406         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 407         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 408         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 409         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 410         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 411
 412         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 413         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 414                                         dev_cap->reserved_xrcds : 0;
 415         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 416                                         dev_cap->max_xrcds : 0;
 417         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 418
 419         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 420         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 421         dev->caps.flags              = dev_cap->flags;
 422         dev->caps.flags2             = dev_cap->flags2;
 423         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 424         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 425         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 426         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 427         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 428         dev->caps.wol_port[1]          = dev_cap->wol_port[1];
 429         dev->caps.wol_port[2]          = dev_cap->wol_port[2];
 430
 431         /* Save uar page shift */
 432         if (!mlx4_is_slave(dev)) {
 433                 /* Virtual PCI function needs to determine UAR page size from
 434                  * firmware. Only master PCI function can set the uar page size
 435                  */
 436                 if (enable_4k_uar || !dev->persist->num_vfs)
 437                         dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
 438                 else
 439                         dev->uar_page_shift = PAGE_SHIFT;
 440
 441                 mlx4_set_num_reserved_uars(dev, dev_cap);
 442         }
 443
 444         if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
 445                 struct mlx4_init_hca_param hca_param;
 446
 447                 memset(&hca_param, 0, sizeof(hca_param));
 448                 err = mlx4_QUERY_HCA(dev, &hca_param);
 449                 /* Turn off PHV_EN flag in case phv_check_en is set.
 450                  * phv_check_en is a HW check that parse the packet and verify
 451                  * phv bit was reported correctly in the wqe. To allow QinQ
 452                  * PHV_EN flag should be set and phv_check_en must be cleared
 453                  * otherwise QinQ packets will be drop by the HW.
 454                  */
 455                 if (err || hca_param.phv_check_en)
 456                         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
 457         }
 458
 459         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 460         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 461                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 462         /* Don't do sense port on multifunction devices (for now at least) */
 463         if (mlx4_is_mfunc(dev))
 464                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 465
 466         if (mlx4_low_memory_profile()) {
 467                 dev->caps.log_num_macs  = MLX4_MIN_LOG_NUM_MAC;
 468                 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
 469         } else {
 470                 dev->caps.log_num_macs  = log_num_mac;
 471                 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 472         }
 473
 474         for (i = 1; i <= dev->caps.num_ports; ++i) {
 475                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 476                 if (dev->caps.supported_type[i]) {
 477                         /* if only ETH is supported - assign ETH */
 478                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 479                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 480                         /* if only IB is supported, assign IB */
 481                         else if (dev->caps.supported_type[i] ==
 482                                  MLX4_PORT_TYPE_IB)
 483                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 484                         else {
 485                                 /* if IB and ETH are supported, we set the port
 486                                  * type according to user selection of port type;
 487                                  * if user selected none, take the FW hint */
 488                                 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
 489                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 490                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 491                                 else
 492                                         dev->caps.port_type[i] = port_type_array[i - 1];
 493                         }
 494                 }
 495                 /*
 496                  * Link sensing is allowed on the port if 3 conditions are true:
 497                  * 1. Both protocols are supported on the port.
 498                  * 2. Different types are supported on the port
 499                  * 3. FW declared that it supports link sensing
 500                  */
 501                 mlx4_priv(dev)->sense.sense_allowed[i] =
 502                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 503                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 504                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 505
 506                 /*
 507                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 508                  * and perform sense_port FW command to try and set the correct
 509                  * port type from beginning
 510                  */
 511                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 512                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 513                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 514                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 515                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 516                                 dev->caps.port_type[i] = sensed_port;
 517                 } else {
 518                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 519                 }
 520
 521                 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
 522                         dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
 523                         mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
 524                                   i, 1 << dev->caps.log_num_macs);
 525                 }
 526                 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
 527                         dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
 528                         mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
 529                                   i, 1 << dev->caps.log_num_vlans);
 530                 }
 531         }
 532
 533         if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
 534             (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
 535             (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
 536                 mlx4_warn(dev,
 537                           "Granular QoS per VF not supported with IB/Eth configuration\n");
 538                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
 539         }
 540
 541         dev->caps.max_counters = dev_cap->max_counters;
 542
 543         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 544         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 545                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 546                 (1 << dev->caps.log_num_macs) *
 547                 (1 << dev->caps.log_num_vlans) *
 548                 dev->caps.num_ports;
 549         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 550
 551         if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
 552             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
 553                 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
 554         else
 555                 dev->caps.dmfs_high_rate_qpn_base =
 556                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 557
 558         if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
 559             dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
 560                 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
 561                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
 562                 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
 563         } else {
 564                 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
 565                 dev->caps.dmfs_high_rate_qpn_base =
 566                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 567                 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
 568         }
 569
 570         dev->caps.rl_caps = dev_cap->rl_caps;
 571
 572         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
 573                 dev->caps.dmfs_high_rate_qpn_range;
 574
 575         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 576                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 577                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 578                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 579
 580         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 581
 582         if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 583                 if (dev_cap->flags &
 584                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 585                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 586                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 587                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 588                 }
 589
 590                 if (dev_cap->flags2 &
 591                     (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
 592                      MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
 593                         mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
 594                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
 595                         dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
 596                 }
 597         }
 598
 599         if ((dev->caps.flags &
 600             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 601             mlx4_is_master(dev))
 602                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 603
 604         if (!mlx4_is_slave(dev)) {
 605                 mlx4_enable_cqe_eqe_stride(dev);
 606                 dev->caps.alloc_res_qp_mask =
 607                         (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
 608                         MLX4_RESERVE_A0_QP;
 609
 610                 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
 611                     dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
 612                         mlx4_warn(dev, "Old device ETS support detected\n");
 613                         mlx4_warn(dev, "Consider upgrading device FW.\n");
 614                         dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
 615                 }
 616
 617         } else {
 618                 dev->caps.alloc_res_qp_mask = 0;
 619         }
 620
 621         mlx4_enable_ignore_fcs(dev);
 622
 623         return 0;
 624 }
 625
 626 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
 627                                        enum pci_bus_speed *speed,
 628                                        enum pcie_link_width *width)
 629 {
 630         u32 lnkcap1, lnkcap2;
 631         int err1, err2;
 632
 633 #define  PCIE_MLW_CAP_SHIFT 4   /* start of MLW mask in link capabilities */
 634
 635         *speed = PCI_SPEED_UNKNOWN;
 636         *width = PCIE_LNK_WIDTH_UNKNOWN;
 637
 638         err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
 639                                           &lnkcap1);
 640         err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
 641                                           &lnkcap2);
 642         if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
 643                 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
 644                         *speed = PCIE_SPEED_8_0GT;
 645                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
 646                         *speed = PCIE_SPEED_5_0GT;
 647                 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
 648                         *speed = PCIE_SPEED_2_5GT;
 649         }
 650         if (!err1) {
 651                 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
 652                 if (!lnkcap2) { /* pre-r3.0 */
 653                         if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
 654                                 *speed = PCIE_SPEED_5_0GT;
 655                         else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
 656                                 *speed = PCIE_SPEED_2_5GT;
 657                 }
 658         }
 659
 660         if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
 661                 return err1 ? err1 :
 662                         err2 ? err2 : -EINVAL;
 663         }
 664         return 0;
 665 }
 666
 667 static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
 668 {
 669         enum pcie_link_width width, width_cap;
 670         enum pci_bus_speed speed, speed_cap;
 671         int err;
 672
 673 #define PCIE_SPEED_STR(speed) \
 674         (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
 675          speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
 676          speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
 677          "Unknown")
 678
 679         err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
 680         if (err) {
 681                 mlx4_warn(dev,
 682                           "Unable to determine PCIe device BW capabilities\n");
 683                 return;
 684         }
 685
 686         err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
 687         if (err || speed == PCI_SPEED_UNKNOWN ||
 688             width == PCIE_LNK_WIDTH_UNKNOWN) {
 689                 mlx4_warn(dev,
 690                           "Unable to determine PCI device chain minimum BW\n");
 691                 return;
 692         }
 693
 694         if (width != width_cap || speed != speed_cap)
 695                 mlx4_warn(dev,
 696                           "PCIe BW is different than device's capability\n");
 697
 698         mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
 699                   PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
 700         mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
 701                   width, width_cap);
 702         return;
 703 }
 704
 705 /*The function checks if there are live vf, return the num of them*/
 706 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 707 {
 708         struct mlx4_priv *priv = mlx4_priv(dev);
 709         struct mlx4_slave_state *s_state;
 710         int i;
 711         int ret = 0;
 712
 713         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 714                 s_state = &priv->mfunc.master.slave_state[i];
 715                 if (s_state->active && s_state->last_cmd !=
 716                     MLX4_COMM_CMD_RESET) {
 717                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 718                                   __func__, i);
 719                         ret++;
 720                 }
 721         }
 722         return ret;
 723 }
 724
 725 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 726 {
 727         u32 qk = MLX4_RESERVED_QKEY_BASE;
 728
 729         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 730             qpn < dev->phys_caps.base_proxy_sqpn)
 731                 return -EINVAL;
 732
 733         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 734                 /* tunnel qp */
 735                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 736         else
 737                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 738         *qkey = qk;
 739         return 0;
 740 }
 741 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 742
 743 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 744 {
 745         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 746
 747         if (!mlx4_is_master(dev))
 748                 return;
 749
 750         priv->virt2phys_pkey[slave][port - 1][i] = val;
 751 }
 752 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 753
 754 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 755 {
 756         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 757
 758         if (!mlx4_is_master(dev))
 759                 return;
 760
 761         priv->slave_node_guids[slave] = guid;
 762 }
 763 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 764
 765 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 766 {
 767         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 768
 769         if (!mlx4_is_master(dev))
 770                 return 0;
 771
 772         return priv->slave_node_guids[slave];
 773 }
 774 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 775
 776 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 777 {
 778         struct mlx4_priv *priv = mlx4_priv(dev);
 779         struct mlx4_slave_state *s_slave;
 780
 781         if (!mlx4_is_master(dev))
 782                 return 0;
 783
 784         s_slave = &priv->mfunc.master.slave_state[slave];
 785         return !!s_slave->active;
 786 }
 787 EXPORT_SYMBOL(mlx4_is_slave_active);
 788
 789 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
 790                                        struct _rule_hw *eth_header)
 791 {
 792         if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
 793             is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
 794                 struct mlx4_net_trans_rule_hw_eth *eth =
 795                         (struct mlx4_net_trans_rule_hw_eth *)eth_header;
 796                 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
 797                 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
 798                         next_rule->rsvd == 0;
 799
 800                 if (last_rule)
 801                         ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
 802         }
 803 }
 804 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
 805
 806 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 807                                        struct mlx4_dev_cap *dev_cap,
 808                                        struct mlx4_init_hca_param *hca_param)
 809 {
 810         dev->caps.steering_mode = hca_param->steering_mode;
 811         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
 812                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 813                 dev->caps.fs_log_max_ucast_qp_range_size =
 814                         dev_cap->fs_log_max_ucast_qp_range_size;
 815         } else
 816                 dev->caps.num_qp_per_mgm =
 817                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 818
 819         mlx4_dbg(dev, "Steering mode is: %s\n",
 820                  mlx4_steering_mode_str(dev->caps.steering_mode));
 821 }
 822
 823 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
 824 {
 825         kfree(dev->caps.spec_qps);
 826         dev->caps.spec_qps = NULL;
 827 }
 828
 829 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
 830 {
 831         struct mlx4_func_cap *func_cap = NULL;
 832         struct mlx4_caps *caps = &dev->caps;
 833         int i, err = 0;
 834
 835         func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
 836         caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
 837
 838         if (!func_cap || !caps->spec_qps) {
 839                 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
 840                 err = -ENOMEM;
 841                 goto err_mem;
 842         }
 843
 844         for (i = 1; i <= caps->num_ports; ++i) {
 845                 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
 846                 if (err) {
 847                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
 848                                  i, err);
 849                         goto err_mem;
 850                 }
 851                 caps->spec_qps[i - 1] = func_cap->spec_qps;
 852                 caps->port_mask[i] = caps->port_type[i];
 853                 caps->phys_port_id[i] = func_cap->phys_port_id;
 854                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
 855                                                       &caps->gid_table_len[i],
 856                                                       &caps->pkey_table_len[i]);
 857                 if (err) {
 858                         mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
 859                                  i, err);
 860                         goto err_mem;
 861                 }
 862         }
 863
 864 err_mem:
 865         if (err)
 866                 mlx4_slave_destroy_special_qp_cap(dev);
 867         kfree(func_cap);
 868         return err;
 869 }
 870
 871 static int mlx4_slave_cap(struct mlx4_dev *dev)
 872 {
 873         int                        err;
 874         u32                        page_size;
 875         struct mlx4_dev_cap        *dev_cap = NULL;
 876         struct mlx4_func_cap       *func_cap = NULL;
 877         struct mlx4_init_hca_param *hca_param = NULL;
 878
 879         hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
 880         func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
 881         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
 882         if (!hca_param || !func_cap || !dev_cap) {
 883                 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
 884                 err = -ENOMEM;
 885                 goto free_mem;
 886         }
 887
 888         err = mlx4_QUERY_HCA(dev, hca_param);
 889         if (err) {
 890                 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
 891                 goto free_mem;
 892         }
 893
 894         /* fail if the hca has an unknown global capability
 895          * at this time global_caps should be always zeroed
 896          */
 897         if (hca_param->global_caps) {
 898                 mlx4_err(dev, "Unknown hca global capabilities\n");
 899                 err = -EINVAL;
 900                 goto free_mem;
 901         }
 902
 903         dev->caps.hca_core_clock = hca_param->hca_core_clock;
 904
 905         dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
 906         err = mlx4_dev_cap(dev, dev_cap);
 907         if (err) {
 908                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
 909                 goto free_mem;
 910         }
 911
 912         err = mlx4_QUERY_FW(dev);
 913         if (err)
 914                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
 915
 916         page_size = ~dev->caps.page_size_cap + 1;
 917         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 918         if (page_size > PAGE_SIZE) {
 919                 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
 920                          page_size, PAGE_SIZE);
 921                 err = -ENODEV;
 922                 goto free_mem;
 923         }
 924
 925         /* Set uar_page_shift for VF */
 926         dev->uar_page_shift = hca_param->uar_page_sz + 12;
 927
 928         /* Make sure the master uar page size is valid */
 929         if (dev->uar_page_shift > PAGE_SHIFT) {
 930                 mlx4_err(dev,
 931                          "Invalid configuration: uar page size is larger than system page size\n");
 932                 err = -ENODEV;
 933                 goto free_mem;
 934         }
 935
 936         /* Set reserved_uars based on the uar_page_shift */
 937         mlx4_set_num_reserved_uars(dev, dev_cap);
 938
 939         /* Although uar page size in FW differs from system page size,
 940          * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
 941          * still works with assumption that uar page size == system page size
 942          */
 943         dev->caps.uar_page_size = PAGE_SIZE;
 944
 945         err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
 946         if (err) {
 947                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
 948                          err);
 949                 goto free_mem;
 950         }
 951
 952         if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
 953             PF_CONTEXT_BEHAVIOUR_MASK) {
 954                 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
 955                          func_cap->pf_context_behaviour,
 956                          PF_CONTEXT_BEHAVIOUR_MASK);
 957                 err = -EINVAL;
 958                 goto free_mem;
 959         }
 960
 961         dev->caps.num_ports             = func_cap->num_ports;
 962         dev->quotas.qp                  = func_cap->qp_quota;
 963         dev->quotas.srq                 = func_cap->srq_quota;
 964         dev->quotas.cq                  = func_cap->cq_quota;
 965         dev->quotas.mpt                 = func_cap->mpt_quota;
 966         dev->quotas.mtt                 = func_cap->mtt_quota;
 967         dev->caps.num_qps               = 1 << hca_param->log_num_qps;
 968         dev->caps.num_srqs              = 1 << hca_param->log_num_srqs;
 969         dev->caps.num_cqs               = 1 << hca_param->log_num_cqs;
 970         dev->caps.num_mpts              = 1 << hca_param->log_mpt_sz;
 971         dev->caps.num_eqs               = func_cap->max_eq;
 972         dev->caps.reserved_eqs          = func_cap->reserved_eq;
 973         dev->caps.reserved_lkey         = func_cap->reserved_lkey;
 974         dev->caps.num_pds               = MLX4_NUM_PDS;
 975         dev->caps.num_mgms              = 0;
 976         dev->caps.num_amgms             = 0;
 977
 978         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
 979                 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
 980                          dev->caps.num_ports, MLX4_MAX_PORTS);
 981                 err = -ENODEV;
 982                 goto free_mem;
 983         }
 984
 985         mlx4_replace_zero_macs(dev);
 986
 987         err = mlx4_slave_special_qp_cap(dev);
 988         if (err) {
 989                 mlx4_err(dev, "Set special QP caps failed. aborting\n");
 990                 goto free_mem;
 991         }
 992
 993         if (dev->caps.uar_page_size * (dev->caps.num_uars -
 994                                        dev->caps.reserved_uars) >
 995                                        pci_resource_len(dev->persist->pdev,
 996                                                         2)) {
 997                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
 998                          dev->caps.uar_page_size * dev->caps.num_uars,
 999                          (unsigned long long)
1000                          pci_resource_len(dev->persist->pdev, 2));
1001                 err = -ENOMEM;
1002                 goto err_mem;
1003         }
1004
1005         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
1006                 dev->caps.eqe_size   = 64;
1007                 dev->caps.eqe_factor = 1;
1008         } else {
1009                 dev->caps.eqe_size   = 32;
1010                 dev->caps.eqe_factor = 0;
1011         }
1012
1013         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
1014                 dev->caps.cqe_size   = 64;
1015                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1016         } else {
1017                 dev->caps.cqe_size   = 32;
1018         }
1019
1020         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
1021                 dev->caps.eqe_size = hca_param->eqe_size;
1022                 dev->caps.eqe_factor = 0;
1023         }
1024
1025         if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
1026                 dev->caps.cqe_size = hca_param->cqe_size;
1027                 /* User still need to know when CQE > 32B */
1028                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1029         }
1030
1031         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1032         mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
1033
1034         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1035         mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
1036
1037         slave_adjust_steering_mode(dev, dev_cap, hca_param);
1038         mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
1039                  hca_param->rss_ip_frags ? "on" : "off");
1040
1041         if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
1042             dev->caps.bf_reg_size)
1043                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1044
1045         if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
1046                 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1047
1048 err_mem:
1049         if (err)
1050                 mlx4_slave_destroy_special_qp_cap(dev);
1051 free_mem:
1052         kfree(hca_param);
1053         kfree(func_cap);
1054         kfree(dev_cap);
1055         return err;
1056 }
1057
1058 static void mlx4_request_modules(struct mlx4_dev *dev)
1059 {
1060         int port;
1061         int has_ib_port = false;
1062         int has_eth_port = false;
1063 #define EN_DRV_NAME     "mlx4_en"
1064 #define IB_DRV_NAME     "mlx4_ib"
1065
1066         for (port = 1; port <= dev->caps.num_ports; port++) {
1067                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1068                         has_ib_port = true;
1069                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1070                         has_eth_port = true;
1071         }
1072
1073         if (has_eth_port)
1074                 request_module_nowait(EN_DRV_NAME);
1075         if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1076                 request_module_nowait(IB_DRV_NAME);
1077 }
1078
1079 /*
1080  * Change the port configuration of the device.
1081  * Every user of this function must hold the port mutex.
1082  */
1083 int mlx4_change_port_types(struct mlx4_dev *dev,
1084                            enum mlx4_port_type *port_types)
1085 {
1086         int err = 0;
1087         int change = 0;
1088         int port;
1089
1090         for (port = 0; port <  dev->caps.num_ports; port++) {
1091                 /* Change the port type only if the new type is different
1092                  * from the current, and not set to Auto */
1093                 if (port_types[port] != dev->caps.port_type[port + 1])
1094                         change = 1;
1095         }
1096         if (change) {
1097                 mlx4_unregister_device(dev);
1098                 for (port = 1; port <= dev->caps.num_ports; port++) {
1099                         mlx4_CLOSE_PORT(dev, port);
1100                         dev->caps.port_type[port] = port_types[port - 1];
1101                         err = mlx4_SET_PORT(dev, port, -1);
1102                         if (err) {
1103                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
1104                                          port);
1105                                 goto out;
1106                         }
1107                 }
1108                 mlx4_set_port_mask(dev);
1109                 err = mlx4_register_device(dev);
1110                 if (err) {
1111                         mlx4_err(dev, "Failed to register device\n");
1112                         goto out;
1113                 }
1114                 mlx4_request_modules(dev);
1115         }
1116
1117 out:
1118         return err;
1119 }
1120
1121 static ssize_t show_port_type(struct device *dev,
1122                               struct device_attribute *attr,
1123                               char *buf)
1124 {
1125         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1126                                                    port_attr);
1127         struct mlx4_dev *mdev = info->dev;
1128         char type[8];
1129
1130         sprintf(type, "%s",
1131                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1132                 "ib" : "eth");
1133         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1134                 sprintf(buf, "auto (%s)\n", type);
1135         else
1136                 sprintf(buf, "%s\n", type);
1137
1138         return strlen(buf);
1139 }
1140
1141 static int __set_port_type(struct mlx4_port_info *info,
1142                            enum mlx4_port_type port_type)
1143 {
1144         struct mlx4_dev *mdev = info->dev;
1145         struct mlx4_priv *priv = mlx4_priv(mdev);
1146         enum mlx4_port_type types[MLX4_MAX_PORTS];
1147         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1148         int i;
1149         int err = 0;
1150
1151         if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1152                 mlx4_err(mdev,
1153                          "Requested port type for port %d is not supported on this HCA\n",
1154                          info->port);
1155                 return -EOPNOTSUPP;
1156         }
1157
1158         mlx4_stop_sense(mdev);
1159         mutex_lock(&priv->port_mutex);
1160         info->tmp_type = port_type;
1161
1162         /* Possible type is always the one that was delivered */
1163         mdev->caps.possible_type[info->port] = info->tmp_type;
1164
1165         for (i = 0; i < mdev->caps.num_ports; i++) {
1166                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1167                                         mdev->caps.possible_type[i+1];
1168                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1169                         types[i] = mdev->caps.port_type[i+1];
1170         }
1171
1172         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1173             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1174                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1175                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1176                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1177                                 err = -EOPNOTSUPP;
1178                         }
1179                 }
1180         }
1181         if (err) {
1182                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1183                 goto out;
1184         }
1185
1186         mlx4_do_sense_ports(mdev, new_types, types);
1187
1188         err = mlx4_check_port_params(mdev, new_types);
1189         if (err)
1190                 goto out;
1191
1192         /* We are about to apply the changes after the configuration
1193          * was verified, no need to remember the temporary types
1194          * any more */
1195         for (i = 0; i < mdev->caps.num_ports; i++)
1196                 priv->port[i + 1].tmp_type = 0;
1197
1198         err = mlx4_change_port_types(mdev, new_types);
1199
1200 out:
1201         mlx4_start_sense(mdev);
1202         mutex_unlock(&priv->port_mutex);
1203
1204         return err;
1205 }
1206
1207 static ssize_t set_port_type(struct device *dev,
1208                              struct device_attribute *attr,
1209                              const char *buf, size_t count)
1210 {
1211         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1212                                                    port_attr);
1213         struct mlx4_dev *mdev = info->dev;
1214         enum mlx4_port_type port_type;
1215         static DEFINE_MUTEX(set_port_type_mutex);
1216         int err;
1217
1218         mutex_lock(&set_port_type_mutex);
1219
1220         if (!strcmp(buf, "ib\n")) {
1221                 port_type = MLX4_PORT_TYPE_IB;
1222         } else if (!strcmp(buf, "eth\n")) {
1223                 port_type = MLX4_PORT_TYPE_ETH;
1224         } else if (!strcmp(buf, "auto\n")) {
1225                 port_type = MLX4_PORT_TYPE_AUTO;
1226         } else {
1227                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1228                 err = -EINVAL;
1229                 goto err_out;
1230         }
1231
1232         err = __set_port_type(info, port_type);
1233
1234 err_out:
1235         mutex_unlock(&set_port_type_mutex);
1236
1237         return err ? err : count;
1238 }
1239
1240 enum ibta_mtu {
1241         IB_MTU_256  = 1,
1242         IB_MTU_512  = 2,
1243         IB_MTU_1024 = 3,
1244         IB_MTU_2048 = 4,
1245         IB_MTU_4096 = 5
1246 };
1247
1248 static inline int int_to_ibta_mtu(int mtu)
1249 {
1250         switch (mtu) {
1251         case 256:  return IB_MTU_256;
1252         case 512:  return IB_MTU_512;
1253         case 1024: return IB_MTU_1024;
1254         case 2048: return IB_MTU_2048;
1255         case 4096: return IB_MTU_4096;
1256         default: return -1;
1257         }
1258 }
1259
1260 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1261 {
1262         switch (mtu) {
1263         case IB_MTU_256:  return  256;
1264         case IB_MTU_512:  return  512;
1265         case IB_MTU_1024: return 1024;
1266         case IB_MTU_2048: return 2048;
1267         case IB_MTU_4096: return 4096;
1268         default: return -1;
1269         }
1270 }
1271
1272 static ssize_t show_port_ib_mtu(struct device *dev,
1273                              struct device_attribute *attr,
1274                              char *buf)
1275 {
1276         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1277                                                    port_mtu_attr);
1278         struct mlx4_dev *mdev = info->dev;
1279
1280         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1281                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1282
1283         sprintf(buf, "%d\n",
1284                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1285         return strlen(buf);
1286 }
1287
1288 static ssize_t set_port_ib_mtu(struct device *dev,
1289                              struct device_attribute *attr,
1290                              const char *buf, size_t count)
1291 {
1292         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1293                                                    port_mtu_attr);
1294         struct mlx4_dev *mdev = info->dev;
1295         struct mlx4_priv *priv = mlx4_priv(mdev);
1296         int err, port, mtu, ibta_mtu = -1;
1297
1298         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1299                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1300                 return -EINVAL;
1301         }
1302
1303         err = kstrtoint(buf, 0, &mtu);
1304         if (!err)
1305                 ibta_mtu = int_to_ibta_mtu(mtu);
1306
1307         if (err || ibta_mtu < 0) {
1308                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1309                 return -EINVAL;
1310         }
1311
1312         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1313
1314         mlx4_stop_sense(mdev);
1315         mutex_lock(&priv->port_mutex);
1316         mlx4_unregister_device(mdev);
1317         for (port = 1; port <= mdev->caps.num_ports; port++) {
1318                 mlx4_CLOSE_PORT(mdev, port);
1319                 err = mlx4_SET_PORT(mdev, port, -1);
1320                 if (err) {
1321                         mlx4_err(mdev, "Failed to set port %d, aborting\n",
1322                                  port);
1323                         goto err_set_port;
1324                 }
1325         }
1326         err = mlx4_register_device(mdev);
1327 err_set_port:
1328         mutex_unlock(&priv->port_mutex);
1329         mlx4_start_sense(mdev);
1330         return err ? err : count;
1331 }
1332
1333 /* bond for multi-function device */
1334 #define MAX_MF_BOND_ALLOWED_SLAVES 63
1335 static int mlx4_mf_bond(struct mlx4_dev *dev)
1336 {
1337         int err = 0;
1338         int nvfs;
1339         struct mlx4_slaves_pport slaves_port1;
1340         struct mlx4_slaves_pport slaves_port2;
1341         DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1342
1343         slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1344         slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1345         bitmap_and(slaves_port_1_2,
1346                    slaves_port1.slaves, slaves_port2.slaves,
1347                    dev->persist->num_vfs + 1);
1348
1349         /* only single port vfs are allowed */
1350         if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1351                 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1352                 return -EINVAL;
1353         }
1354
1355         /* number of virtual functions is number of total functions minus one
1356          * physical function for each port.
1357          */
1358         nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1359                 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1360
1361         /* limit on maximum allowed VFs */
1362         if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1363                 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1364                           nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1365                 return -EINVAL;
1366         }
1367
1368         if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1369                 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1370                 return -EINVAL;
1371         }
1372
1373         err = mlx4_bond_mac_table(dev);
1374         if (err)
1375                 return err;
1376         err = mlx4_bond_vlan_table(dev);
1377         if (err)
1378                 goto err1;
1379         err = mlx4_bond_fs_rules(dev);
1380         if (err)
1381                 goto err2;
1382
1383         return 0;
1384 err2:
1385         (void)mlx4_unbond_vlan_table(dev);
1386 err1:
1387         (void)mlx4_unbond_mac_table(dev);
1388         return err;
1389 }
1390
1391 static int mlx4_mf_unbond(struct mlx4_dev *dev)
1392 {
1393         int ret, ret1;
1394
1395         ret = mlx4_unbond_fs_rules(dev);
1396         if (ret)
1397                 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1398         ret1 = mlx4_unbond_mac_table(dev);
1399         if (ret1) {
1400                 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1401                 ret = ret1;
1402         }
1403         ret1 = mlx4_unbond_vlan_table(dev);
1404         if (ret1) {
1405                 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1406                 ret = ret1;
1407         }
1408         return ret;
1409 }
1410
1411 int mlx4_bond(struct mlx4_dev *dev)
1412 {
1413         int ret = 0;
1414         struct mlx4_priv *priv = mlx4_priv(dev);
1415
1416         mutex_lock(&priv->bond_mutex);
1417
1418         if (!mlx4_is_bonded(dev)) {
1419                 ret = mlx4_do_bond(dev, true);
1420                 if (ret)
1421                         mlx4_err(dev, "Failed to bond device: %d\n", ret);
1422                 if (!ret && mlx4_is_master(dev)) {
1423                         ret = mlx4_mf_bond(dev);
1424                         if (ret) {
1425                                 mlx4_err(dev, "bond for multifunction failed\n");
1426                                 mlx4_do_bond(dev, false);
1427                         }
1428                 }
1429         }
1430
1431         mutex_unlock(&priv->bond_mutex);
1432         if (!ret)
1433                 mlx4_dbg(dev, "Device is bonded\n");
1434
1435         return ret;
1436 }
1437 EXPORT_SYMBOL_GPL(mlx4_bond);
1438
1439 int mlx4_unbond(struct mlx4_dev *dev)
1440 {
1441         int ret = 0;
1442         struct mlx4_priv *priv = mlx4_priv(dev);
1443
1444         mutex_lock(&priv->bond_mutex);
1445
1446         if (mlx4_is_bonded(dev)) {
1447                 int ret2 = 0;
1448
1449                 ret = mlx4_do_bond(dev, false);
1450                 if (ret)
1451                         mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1452                 if (mlx4_is_master(dev))
1453                         ret2 = mlx4_mf_unbond(dev);
1454                 if (ret2) {
1455                         mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1456                         ret = ret2;
1457                 }
1458         }
1459
1460         mutex_unlock(&priv->bond_mutex);
1461         if (!ret)
1462                 mlx4_dbg(dev, "Device is unbonded\n");
1463
1464         return ret;
1465 }
1466 EXPORT_SYMBOL_GPL(mlx4_unbond);
1467
1468
1469 int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1470 {
1471         u8 port1 = v2p->port1;
1472         u8 port2 = v2p->port2;
1473         struct mlx4_priv *priv = mlx4_priv(dev);
1474         int err;
1475
1476         if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1477                 return -EOPNOTSUPP;
1478
1479         mutex_lock(&priv->bond_mutex);
1480
1481         /* zero means keep current mapping for this port */
1482         if (port1 == 0)
1483                 port1 = priv->v2p.port1;
1484         if (port2 == 0)
1485                 port2 = priv->v2p.port2;
1486
1487         if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1488             (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1489             (port1 == 2 && port2 == 1)) {
1490                 /* besides boundary checks cross mapping makes
1491                  * no sense and therefore not allowed */
1492                 err = -EINVAL;
1493         } else if ((port1 == priv->v2p.port1) &&
1494                  (port2 == priv->v2p.port2)) {
1495                 err = 0;
1496         } else {
1497                 err = mlx4_virt2phy_port_map(dev, port1, port2);
1498                 if (!err) {
1499                         mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1500                                  port1, port2);
1501                         priv->v2p.port1 = port1;
1502                         priv->v2p.port2 = port2;
1503                 } else {
1504                         mlx4_err(dev, "Failed to change port mape: %d\n", err);
1505                 }
1506         }
1507
1508         mutex_unlock(&priv->bond_mutex);
1509         return err;
1510 }
1511 EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1512
1513 static int mlx4_load_fw(struct mlx4_dev *dev)
1514 {
1515         struct mlx4_priv *priv = mlx4_priv(dev);
1516         int err;
1517
1518         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1519                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1520         if (!priv->fw.fw_icm) {
1521                 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1522                 return -ENOMEM;
1523         }
1524
1525         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1526         if (err) {
1527                 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1528                 goto err_free;
1529         }
1530
1531         err = mlx4_RUN_FW(dev);
1532         if (err) {
1533                 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1534                 goto err_unmap_fa;
1535         }
1536
1537         return 0;
1538
1539 err_unmap_fa:
1540         mlx4_UNMAP_FA(dev);
1541
1542 err_free:
1543         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1544         return err;
1545 }
1546
1547 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1548                                 int cmpt_entry_sz)
1549 {
1550         struct mlx4_priv *priv = mlx4_priv(dev);
1551         int err;
1552         int num_eqs;
1553
1554         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1555                                   cmpt_base +
1556                                   ((u64) (MLX4_CMPT_TYPE_QP *
1557                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1558                                   cmpt_entry_sz, dev->caps.num_qps,
1559                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1560                                   0, 0);
1561         if (err)
1562                 goto err;
1563
1564         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1565                                   cmpt_base +
1566                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1567                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1568                                   cmpt_entry_sz, dev->caps.num_srqs,
1569                                   dev->caps.reserved_srqs, 0, 0);
1570         if (err)
1571                 goto err_qp;
1572
1573         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1574                                   cmpt_base +
1575                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1576                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1577                                   cmpt_entry_sz, dev->caps.num_cqs,
1578                                   dev->caps.reserved_cqs, 0, 0);
1579         if (err)
1580                 goto err_srq;
1581
1582         num_eqs = dev->phys_caps.num_phys_eqs;
1583         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1584                                   cmpt_base +
1585                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1586                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1587                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1588         if (err)
1589                 goto err_cq;
1590
1591         return 0;
1592
1593 err_cq:
1594         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1595
1596 err_srq:
1597         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1598
1599 err_qp:
1600         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1601
1602 err:
1603         return err;
1604 }
1605
1606 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1607                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1608 {
1609         struct mlx4_priv *priv = mlx4_priv(dev);
1610         u64 aux_pages;
1611         int num_eqs;
1612         int err;
1613
1614         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1615         if (err) {
1616                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1617                 return err;
1618         }
1619
1620         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1621                  (unsigned long long) icm_size >> 10,
1622                  (unsigned long long) aux_pages << 2);
1623
1624         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1625                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1626         if (!priv->fw.aux_icm) {
1627                 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1628                 return -ENOMEM;
1629         }
1630
1631         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1632         if (err) {
1633                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1634                 goto err_free_aux;
1635         }
1636
1637         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1638         if (err) {
1639                 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1640                 goto err_unmap_aux;
1641         }
1642
1643
1644         num_eqs = dev->phys_caps.num_phys_eqs;
1645         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1646                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1647                                   num_eqs, num_eqs, 0, 0);
1648         if (err) {
1649                 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1650                 goto err_unmap_cmpt;
1651         }
1652
1653         /*
1654          * Reserved MTT entries must be aligned up to a cacheline
1655          * boundary, since the FW will write to them, while the driver
1656          * writes to all other MTT entries. (The variable
1657          * dev->caps.mtt_entry_sz below is really the MTT segment
1658          * size, not the raw entry size)
1659          */
1660         dev->caps.reserved_mtts =
1661                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1662                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1663
1664         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1665                                   init_hca->mtt_base,
1666                                   dev->caps.mtt_entry_sz,
1667                                   dev->caps.num_mtts,
1668                                   dev->caps.reserved_mtts, 1, 0);
1669         if (err) {
1670                 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1671                 goto err_unmap_eq;
1672         }
1673
1674         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1675                                   init_hca->dmpt_base,
1676                                   dev_cap->dmpt_entry_sz,
1677                                   dev->caps.num_mpts,
1678                                   dev->caps.reserved_mrws, 1, 1);
1679         if (err) {
1680                 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1681                 goto err_unmap_mtt;
1682         }
1683
1684         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1685                                   init_hca->qpc_base,
1686                                   dev_cap->qpc_entry_sz,
1687                                   dev->caps.num_qps,
1688                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1689                                   0, 0);
1690         if (err) {
1691                 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1692                 goto err_unmap_dmpt;
1693         }
1694
1695         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1696                                   init_hca->auxc_base,
1697                                   dev_cap->aux_entry_sz,
1698                                   dev->caps.num_qps,
1699                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1700                                   0, 0);
1701         if (err) {
1702                 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1703                 goto err_unmap_qp;
1704         }
1705
1706         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1707                                   init_hca->altc_base,
1708                                   dev_cap->altc_entry_sz,
1709                                   dev->caps.num_qps,
1710                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1711                                   0, 0);
1712         if (err) {
1713                 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1714                 goto err_unmap_auxc;
1715         }
1716
1717         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1718                                   init_hca->rdmarc_base,
1719                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1720                                   dev->caps.num_qps,
1721                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1722                                   0, 0);
1723         if (err) {
1724                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1725                 goto err_unmap_altc;
1726         }
1727
1728         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1729                                   init_hca->cqc_base,
1730                                   dev_cap->cqc_entry_sz,
1731                                   dev->caps.num_cqs,
1732                                   dev->caps.reserved_cqs, 0, 0);
1733         if (err) {
1734                 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1735                 goto err_unmap_rdmarc;
1736         }
1737
1738         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1739                                   init_hca->srqc_base,
1740                                   dev_cap->srq_entry_sz,
1741                                   dev->caps.num_srqs,
1742                                   dev->caps.reserved_srqs, 0, 0);
1743         if (err) {
1744                 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1745                 goto err_unmap_cq;
1746         }
1747
1748         /*
1749          * For flow steering device managed mode it is required to use
1750          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1751          * required, but for simplicity just map the whole multicast
1752          * group table now.  The table isn't very big and it's a lot
1753          * easier than trying to track ref counts.
1754          */
1755         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1756                                   init_hca->mc_base,
1757                                   mlx4_get_mgm_entry_size(dev),
1758                                   dev->caps.num_mgms + dev->caps.num_amgms,
1759                                   dev->caps.num_mgms + dev->caps.num_amgms,
1760                                   0, 0);
1761         if (err) {
1762                 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1763                 goto err_unmap_srq;
1764         }
1765
1766         return 0;
1767
1768 err_unmap_srq:
1769         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1770
1771 err_unmap_cq:
1772         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1773
1774 err_unmap_rdmarc:
1775         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1776
1777 err_unmap_altc:
1778         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1779
1780 err_unmap_auxc:
1781         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1782
1783 err_unmap_qp:
1784         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1785
1786 err_unmap_dmpt:
1787         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1788
1789 err_unmap_mtt:
1790         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1791
1792 err_unmap_eq:
1793         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1794
1795 err_unmap_cmpt:
1796         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1797         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1798         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1799         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1800
1801 err_unmap_aux:
1802         mlx4_UNMAP_ICM_AUX(dev);
1803
1804 err_free_aux:
1805         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1806
1807         return err;
1808 }
1809
1810 static void mlx4_free_icms(struct mlx4_dev *dev)
1811 {
1812         struct mlx4_priv *priv = mlx4_priv(dev);
1813
1814         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1815         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1816         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1817         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1818         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1819         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1820         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1821         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1822         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1823         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1824         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1825         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1826         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1827         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1828
1829         mlx4_UNMAP_ICM_AUX(dev);
1830         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1831 }
1832
1833 static void mlx4_slave_exit(struct mlx4_dev *dev)
1834 {
1835         struct mlx4_priv *priv = mlx4_priv(dev);
1836
1837         mutex_lock(&priv->cmd.slave_cmd_mutex);
1838         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1839                           MLX4_COMM_TIME))
1840                 mlx4_warn(dev, "Failed to close slave function\n");
1841         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1842 }
1843
1844 static int map_bf_area(struct mlx4_dev *dev)
1845 {
1846         struct mlx4_priv *priv = mlx4_priv(dev);
1847         resource_size_t bf_start;
1848         resource_size_t bf_len;
1849         int err = 0;
1850
1851         if (!dev->caps.bf_reg_size)
1852                 return -ENXIO;
1853
1854         bf_start = pci_resource_start(dev->persist->pdev, 2) +
1855                         (dev->caps.num_uars << PAGE_SHIFT);
1856         bf_len = pci_resource_len(dev->persist->pdev, 2) -
1857                         (dev->caps.num_uars << PAGE_SHIFT);
1858         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1859         if (!priv->bf_mapping)
1860                 err = -ENOMEM;
1861
1862         return err;
1863 }
1864
1865 static void unmap_bf_area(struct mlx4_dev *dev)
1866 {
1867         if (mlx4_priv(dev)->bf_mapping)
1868                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1869 }
1870
1871 u64 mlx4_read_clock(struct mlx4_dev *dev)
1872 {
1873         u32 clockhi, clocklo, clockhi1;
1874         u64 cycles;
1875         int i;
1876         struct mlx4_priv *priv = mlx4_priv(dev);
1877
1878         for (i = 0; i < 10; i++) {
1879                 clockhi = swab32(readl(priv->clock_mapping));
1880                 clocklo = swab32(readl(priv->clock_mapping + 4));
1881                 clockhi1 = swab32(readl(priv->clock_mapping));
1882                 if (clockhi == clockhi1)
1883                         break;
1884         }
1885
1886         cycles = (u64) clockhi << 32 | (u64) clocklo;
1887
1888         return cycles;
1889 }
1890 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1891
1892
1893 static int map_internal_clock(struct mlx4_dev *dev)
1894 {
1895         struct mlx4_priv *priv = mlx4_priv(dev);
1896
1897         priv->clock_mapping =
1898                 ioremap(pci_resource_start(dev->persist->pdev,
1899                                            priv->fw.clock_bar) +
1900                         priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1901
1902         if (!priv->clock_mapping)
1903                 return -ENOMEM;
1904
1905         return 0;
1906 }
1907
1908 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1909                                    struct mlx4_clock_params *params)
1910 {
1911         struct mlx4_priv *priv = mlx4_priv(dev);
1912
1913         if (mlx4_is_slave(dev))
1914                 return -EOPNOTSUPP;
1915
1916         if (!params)
1917                 return -EINVAL;
1918
1919         params->bar = priv->fw.clock_bar;
1920         params->offset = priv->fw.clock_offset;
1921         params->size = MLX4_CLOCK_SIZE;
1922
1923         return 0;
1924 }
1925 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1926
1927 static void unmap_internal_clock(struct mlx4_dev *dev)
1928 {
1929         struct mlx4_priv *priv = mlx4_priv(dev);
1930
1931         if (priv->clock_mapping)
1932                 iounmap(priv->clock_mapping);
1933 }
1934
1935 static void mlx4_close_hca(struct mlx4_dev *dev)
1936 {
1937         unmap_internal_clock(dev);
1938         unmap_bf_area(dev);
1939         if (mlx4_is_slave(dev))
1940                 mlx4_slave_exit(dev);
1941         else {
1942                 mlx4_CLOSE_HCA(dev, 0);
1943                 mlx4_free_icms(dev);
1944         }
1945 }
1946
1947 static void mlx4_close_fw(struct mlx4_dev *dev)
1948 {
1949         if (!mlx4_is_slave(dev)) {
1950                 mlx4_UNMAP_FA(dev);
1951                 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1952         }
1953 }
1954
1955 static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1956 {
1957 #define COMM_CHAN_OFFLINE_OFFSET 0x09
1958
1959         u32 comm_flags;
1960         u32 offline_bit;
1961         unsigned long end;
1962         struct mlx4_priv *priv = mlx4_priv(dev);
1963
1964         end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1965         while (time_before(jiffies, end)) {
1966                 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1967                                           MLX4_COMM_CHAN_FLAGS));
1968                 offline_bit = (comm_flags &
1969                                (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1970                 if (!offline_bit)
1971                         return 0;
1972
1973                 /* If device removal has been requested,
1974                  * do not continue retrying.
1975                  */
1976                 if (dev->persist->interface_state &
1977                     MLX4_INTERFACE_STATE_NOWAIT)
1978                         break;
1979
1980                 /* There are cases as part of AER/Reset flow that PF needs
1981                  * around 100 msec to load. We therefore sleep for 100 msec
1982                  * to allow other tasks to make use of that CPU during this
1983                  * time interval.
1984                  */
1985                 msleep(100);
1986         }
1987         mlx4_err(dev, "Communication channel is offline.\n");
1988         return -EIO;
1989 }
1990
1991 static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1992 {
1993 #define COMM_CHAN_RST_OFFSET 0x1e
1994
1995         struct mlx4_priv *priv = mlx4_priv(dev);
1996         u32 comm_rst;
1997         u32 comm_caps;
1998
1999         comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
2000                                  MLX4_COMM_CHAN_CAPS));
2001         comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
2002
2003         if (comm_rst)
2004                 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2005 }
2006
2007 static int mlx4_init_slave(struct mlx4_dev *dev)
2008 {
2009         struct mlx4_priv *priv = mlx4_priv(dev);
2010         u64 dma = (u64) priv->mfunc.vhcr_dma;
2011         int ret_from_reset = 0;
2012         u32 slave_read;
2013         u32 cmd_channel_ver;
2014
2015         if (atomic_read(&pf_loading)) {
2016                 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
2017                 return -EPROBE_DEFER;
2018         }
2019
2020         mutex_lock(&priv->cmd.slave_cmd_mutex);
2021         priv->cmd.max_cmds = 1;
2022         if (mlx4_comm_check_offline(dev)) {
2023                 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
2024                 goto err_offline;
2025         }
2026
2027         mlx4_reset_vf_support(dev);
2028         mlx4_warn(dev, "Sending reset\n");
2029         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
2030                                        MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
2031         /* if we are in the middle of flr the slave will try
2032          * NUM_OF_RESET_RETRIES times before leaving.*/
2033         if (ret_from_reset) {
2034                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
2035                         mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
2036                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2037                         return -EPROBE_DEFER;
2038                 } else
2039                         goto err;
2040         }
2041
2042         /* check the driver version - the slave I/F revision
2043          * must match the master's */
2044         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
2045         cmd_channel_ver = mlx4_comm_get_version();
2046
2047         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
2048                 MLX4_COMM_GET_IF_REV(slave_read)) {
2049                 mlx4_err(dev, "slave driver version is not supported by the master\n");
2050                 goto err;
2051         }
2052
2053         mlx4_warn(dev, "Sending vhcr0\n");
2054         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
2055                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2056                 goto err;
2057         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
2058                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2059                 goto err;
2060         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
2061                              MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2062                 goto err;
2063         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2064                           MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
2065                 goto err;
2066
2067         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2068         return 0;
2069
2070 err:
2071         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
2072 err_offline:
2073         mutex_unlock(&priv->cmd.slave_cmd_mutex);
2074         return -EIO;
2075 }
2076
2077 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2078 {
2079         int i;
2080
2081         for (i = 1; i <= dev->caps.num_ports; i++) {
2082                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2083                         dev->caps.gid_table_len[i] =
2084                                 mlx4_get_slave_num_gids(dev, 0, i);
2085                 else
2086                         dev->caps.gid_table_len[i] = 1;
2087                 dev->caps.pkey_table_len[i] =
2088                         dev->phys_caps.pkey_phys_table_len[i] - 1;
2089         }
2090 }
2091
2092 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2093 {
2094         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2095
2096         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2097               i++) {
2098                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2099                         break;
2100         }
2101
2102         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2103 }
2104
2105 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2106 {
2107         switch (dmfs_high_steer_mode) {
2108         case MLX4_STEERING_DMFS_A0_DEFAULT:
2109                 return "default performance";
2110
2111         case MLX4_STEERING_DMFS_A0_DYNAMIC:
2112                 return "dynamic hybrid mode";
2113
2114         case MLX4_STEERING_DMFS_A0_STATIC:
2115                 return "performance optimized for limited rule configuration (static)";
2116
2117         case MLX4_STEERING_DMFS_A0_DISABLE:
2118                 return "disabled performance optimized steering";
2119
2120         case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2121                 return "performance optimized steering not supported";
2122
2123         default:
2124                 return "Unrecognized mode";
2125         }
2126 }
2127
2128 #define MLX4_DMFS_A0_STEERING                   (1UL << 2)
2129
2130 static void choose_steering_mode(struct mlx4_dev *dev,
2131                                  struct mlx4_dev_cap *dev_cap)
2132 {
2133         if (mlx4_log_num_mgm_entry_size <= 0) {
2134                 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2135                         if (dev->caps.dmfs_high_steer_mode ==
2136                             MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2137                                 mlx4_err(dev, "DMFS high rate mode not supported\n");
2138                         else
2139                                 dev->caps.dmfs_high_steer_mode =
2140                                         MLX4_STEERING_DMFS_A0_STATIC;
2141                 }
2142         }
2143
2144         if (mlx4_log_num_mgm_entry_size <= 0 &&
2145             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2146             (!mlx4_is_mfunc(dev) ||
2147              (dev_cap->fs_max_num_qp_per_entry >=
2148              (dev->persist->num_vfs + 1))) &&
2149             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2150                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2151                 dev->oper_log_mgm_entry_size =
2152                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2153                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2154                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2155                 dev->caps.fs_log_max_ucast_qp_range_size =
2156                         dev_cap->fs_log_max_ucast_qp_range_size;
2157         } else {
2158                 if (dev->caps.dmfs_high_steer_mode !=
2159                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2160                         dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2161                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2162                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2163                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2164                 else {
2165                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2166
2167                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2168                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2169                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2170                 }
2171                 dev->oper_log_mgm_entry_size =
2172                         mlx4_log_num_mgm_entry_size > 0 ?
2173                         mlx4_log_num_mgm_entry_size :
2174                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2175                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2176         }
2177         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2178                  mlx4_steering_mode_str(dev->caps.steering_mode),
2179                  dev->oper_log_mgm_entry_size,
2180                  mlx4_log_num_mgm_entry_size);
2181 }
2182
2183 static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2184                                        struct mlx4_dev_cap *dev_cap)
2185 {
2186         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2187             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2188                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2189         else
2190                 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2191
2192         mlx4_dbg(dev, "Tunneling offload mode is: %s\n",  (dev->caps.tunnel_offload_mode
2193                  == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2194 }
2195
2196 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2197 {
2198         int i;
2199         struct mlx4_port_cap port_cap;
2200
2201         if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2202                 return -EINVAL;
2203
2204         for (i = 1; i <= dev->caps.num_ports; i++) {
2205                 if (mlx4_dev_port(dev, i, &port_cap)) {
2206                         mlx4_err(dev,
2207                                  "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2208                 } else if ((dev->caps.dmfs_high_steer_mode !=
2209                             MLX4_STEERING_DMFS_A0_DEFAULT) &&
2210                            (port_cap.dmfs_optimized_state ==
2211                             !!(dev->caps.dmfs_high_steer_mode ==
2212                             MLX4_STEERING_DMFS_A0_DISABLE))) {
2213                         mlx4_err(dev,
2214                                  "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2215                                  dmfs_high_rate_steering_mode_str(
2216                                         dev->caps.dmfs_high_steer_mode),
2217                                  (port_cap.dmfs_optimized_state ?
2218                                         "enabled" : "disabled"));
2219                 }
2220         }
2221
2222         return 0;
2223 }
2224
2225 static int mlx4_init_fw(struct mlx4_dev *dev)
2226 {
2227         struct mlx4_mod_stat_cfg   mlx4_cfg;
2228         int err = 0;
2229
2230         if (!mlx4_is_slave(dev)) {
2231                 err = mlx4_QUERY_FW(dev);
2232                 if (err) {
2233                         if (err == -EACCES)
2234                                 mlx4_info(dev, "non-primary physical function, skipping\n");
2235                         else
2236                                 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2237                         return err;
2238                 }
2239
2240                 err = mlx4_load_fw(dev);
2241                 if (err) {
2242                         mlx4_err(dev, "Failed to start FW, aborting\n");
2243                         return err;
2244                 }
2245
2246                 mlx4_cfg.log_pg_sz_m = 1;
2247                 mlx4_cfg.log_pg_sz = 0;
2248                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2249                 if (err)
2250                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2251         }
2252
2253         return err;
2254 }
2255
2256 static int mlx4_init_hca(struct mlx4_dev *dev)
2257 {
2258         struct mlx4_priv          *priv = mlx4_priv(dev);
2259         struct mlx4_adapter        adapter;
2260         struct mlx4_dev_cap        dev_cap;
2261         struct mlx4_profile        profile;
2262         struct mlx4_init_hca_param init_hca;
2263         u64 icm_size;
2264         struct mlx4_config_dev_params params;
2265         int err;
2266
2267         if (!mlx4_is_slave(dev)) {
2268                 err = mlx4_dev_cap(dev, &dev_cap);
2269                 if (err) {
2270                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2271                         return err;
2272                 }
2273
2274                 choose_steering_mode(dev, &dev_cap);
2275                 choose_tunnel_offload_mode(dev, &dev_cap);
2276
2277                 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2278                     mlx4_is_master(dev))
2279                         dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2280
2281                 err = mlx4_get_phys_port_id(dev);
2282                 if (err)
2283                         mlx4_err(dev, "Fail to get physical port id\n");
2284
2285                 if (mlx4_is_master(dev))
2286                         mlx4_parav_master_pf_caps(dev);
2287
2288                 if (mlx4_low_memory_profile()) {
2289                         mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2290                         profile = low_mem_profile;
2291                 } else {
2292                         profile = default_profile;
2293                 }
2294                 if (dev->caps.steering_mode ==
2295                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2296                         profile.num_mcg = MLX4_FS_NUM_MCG;
2297
2298                 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2299                                              &init_hca);
2300                 if ((long long) icm_size < 0) {
2301                         err = icm_size;
2302                         return err;
2303                 }
2304
2305                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2306
2307                 if (enable_4k_uar || !dev->persist->num_vfs) {
2308                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2309                                                     PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2310                         init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2311                 } else {
2312                         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2313                         init_hca.uar_page_sz = PAGE_SHIFT - 12;
2314                 }
2315
2316                 init_hca.mw_enabled = 0;
2317                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2318                     dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2319                         init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2320
2321                 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2322                 if (err)
2323                         return err;
2324
2325                 err = mlx4_INIT_HCA(dev, &init_hca);
2326                 if (err) {
2327                         mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2328                         goto err_free_icm;
2329                 }
2330
2331                 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2332                         err = mlx4_query_func(dev, &dev_cap);
2333                         if (err < 0) {
2334                                 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2335                                 goto err_close;
2336                         } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2337                                 dev->caps.num_eqs = dev_cap.max_eqs;
2338                                 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2339                                 dev->caps.reserved_uars = dev_cap.reserved_uars;
2340                         }
2341                 }
2342
2343                 /*
2344                  * If TS is supported by FW
2345                  * read HCA frequency by QUERY_HCA command
2346                  */
2347                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2348                         memset(&init_hca, 0, sizeof(init_hca));
2349                         err = mlx4_QUERY_HCA(dev, &init_hca);
2350                         if (err) {
2351                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2352                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2353                         } else {
2354                                 dev->caps.hca_core_clock =
2355                                         init_hca.hca_core_clock;
2356                         }
2357
2358                         /* In case we got HCA frequency 0 - disable timestamping
2359                          * to avoid dividing by zero
2360                          */
2361                         if (!dev->caps.hca_core_clock) {
2362                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2363                                 mlx4_err(dev,
2364                                          "HCA frequency is 0 - timestamping is not supported\n");
2365                         } else if (map_internal_clock(dev)) {
2366                                 /*
2367                                  * Map internal clock,
2368                                  * in case of failure disable timestamping
2369                                  */
2370                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2371                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2372                         }
2373                 }
2374
2375                 if (dev->caps.dmfs_high_steer_mode !=
2376                     MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2377                         if (mlx4_validate_optimized_steering(dev))
2378                                 mlx4_warn(dev, "Optimized steering validation failed\n");
2379
2380                         if (dev->caps.dmfs_high_steer_mode ==
2381                             MLX4_STEERING_DMFS_A0_DISABLE) {
2382                                 dev->caps.dmfs_high_rate_qpn_base =
2383                                         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2384                                 dev->caps.dmfs_high_rate_qpn_range =
2385                                         MLX4_A0_STEERING_TABLE_SIZE;
2386                         }
2387
2388                         mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2389                                   dmfs_high_rate_steering_mode_str(
2390                                         dev->caps.dmfs_high_steer_mode));
2391                 }
2392         } else {
2393                 err = mlx4_init_slave(dev);
2394                 if (err) {
2395                         if (err != -EPROBE_DEFER)
2396                                 mlx4_err(dev, "Failed to initialize slave\n");
2397                         return err;
2398                 }
2399
2400                 err = mlx4_slave_cap(dev);
2401                 if (err) {
2402                         mlx4_err(dev, "Failed to obtain slave caps\n");
2403                         goto err_close;
2404                 }
2405         }
2406
2407         if (map_bf_area(dev))
2408                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2409
2410         /*Only the master set the ports, all the rest got it from it.*/
2411         if (!mlx4_is_slave(dev))
2412                 mlx4_set_port_mask(dev);
2413
2414         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2415         if (err) {
2416                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2417                 goto unmap_bf;
2418         }
2419
2420         /* Query CONFIG_DEV parameters */
2421         err = mlx4_config_dev_retrieval(dev, &params);
2422         if (err && err != -EOPNOTSUPP) {
2423                 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2424         } else if (!err) {
2425                 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2426                 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2427         }
2428         priv->eq_table.inta_pin = adapter.inta_pin;
2429         memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
2430
2431         return 0;
2432
2433 unmap_bf:
2434         unmap_internal_clock(dev);
2435         unmap_bf_area(dev);
2436
2437         if (mlx4_is_slave(dev))
2438                 mlx4_slave_destroy_special_qp_cap(dev);
2439
2440 err_close:
2441         if (mlx4_is_slave(dev))
2442                 mlx4_slave_exit(dev);
2443         else
2444                 mlx4_CLOSE_HCA(dev, 0);
2445
2446 err_free_icm:
2447         if (!mlx4_is_slave(dev))
2448                 mlx4_free_icms(dev);
2449
2450         return err;
2451 }
2452
2453 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2454 {
2455         struct mlx4_priv *priv = mlx4_priv(dev);
2456         int nent_pow2;
2457
2458         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2459                 return -ENOENT;
2460
2461         if (!dev->caps.max_counters)
2462                 return -ENOSPC;
2463
2464         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2465         /* reserve last counter index for sink counter */
2466         return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2467                                 nent_pow2 - 1, 0,
2468                                 nent_pow2 - dev->caps.max_counters + 1);
2469 }
2470
2471 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2472 {
2473         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2474                 return;
2475
2476         if (!dev->caps.max_counters)
2477                 return;
2478
2479         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2480 }
2481
2482 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2483 {
2484         struct mlx4_priv *priv = mlx4_priv(dev);
2485         int port;
2486
2487         for (port = 0; port < dev->caps.num_ports; port++)
2488                 if (priv->def_counter[port] != -1)
2489                         mlx4_counter_free(dev,  priv->def_counter[port]);
2490 }
2491
2492 static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2493 {
2494         struct mlx4_priv *priv = mlx4_priv(dev);
2495         int port, err = 0;
2496         u32 idx;
2497
2498         for (port = 0; port < dev->caps.num_ports; port++)
2499                 priv->def_counter[port] = -1;
2500
2501         for (port = 0; port < dev->caps.num_ports; port++) {
2502                 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
2503
2504                 if (!err || err == -ENOSPC) {
2505                         priv->def_counter[port] = idx;
2506                         err = 0;
2507                 } else if (err == -ENOENT) {
2508                         err = 0;
2509                         continue;
2510                 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2511                         priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2512                         mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2513                                   MLX4_SINK_COUNTER_INDEX(dev));
2514                         err = 0;
2515                 } else {
2516                         mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2517                                  __func__, port + 1, err);
2518                         mlx4_cleanup_default_counters(dev);
2519                         return err;
2520                 }
2521
2522                 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2523                          __func__, priv->def_counter[port], port + 1);
2524         }
2525
2526         return err;
2527 }
2528
2529 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2530 {
2531         struct mlx4_priv *priv = mlx4_priv(dev);
2532
2533         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2534                 return -ENOENT;
2535
2536         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2537         if (*idx == -1) {
2538                 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2539                 return -ENOSPC;
2540         }
2541
2542         return 0;
2543 }
2544
2545 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
2546 {
2547         u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
2548         u64 out_param;
2549         int err;
2550
2551         if (mlx4_is_mfunc(dev)) {
2552                 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
2553                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2554                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2555                 if (!err)
2556                         *idx = get_param_l(&out_param);
2557                 if (WARN_ON(err == -ENOSPC))
2558                         err = -EINVAL;
2559                 return err;
2560         }
2561         return __mlx4_counter_alloc(dev, idx);
2562 }
2563 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2564
2565 static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2566                                 u8 counter_index)
2567 {
2568         struct mlx4_cmd_mailbox *if_stat_mailbox;
2569         int err;
2570         u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2571
2572         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2573         if (IS_ERR(if_stat_mailbox))
2574                 return PTR_ERR(if_stat_mailbox);
2575
2576         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2577                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2578                            MLX4_CMD_NATIVE);
2579
2580         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2581         return err;
2582 }
2583
2584 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2585 {
2586         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2587                 return;
2588
2589         if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2590                 return;
2591
2592         __mlx4_clear_if_stat(dev, idx);
2593
2594         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2595         return;
2596 }
2597
2598 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2599 {
2600         u64 in_param = 0;
2601
2602         if (mlx4_is_mfunc(dev)) {
2603                 set_param_l(&in_param, idx);
2604                 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2605                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2606                          MLX4_CMD_WRAPPED);
2607                 return;
2608         }
2609         __mlx4_counter_free(dev, idx);
2610 }
2611 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2612
2613 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2614 {
2615         struct mlx4_priv *priv = mlx4_priv(dev);
2616
2617         return priv->def_counter[port - 1];
2618 }
2619 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2620
2621 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2622 {
2623         struct mlx4_priv *priv = mlx4_priv(dev);
2624
2625         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2626 }
2627 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2628
2629 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2630 {
2631         struct mlx4_priv *priv = mlx4_priv(dev);
2632
2633         return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2634 }
2635 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2636
2637 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2638 {
2639         struct mlx4_priv *priv = mlx4_priv(dev);
2640         __be64 guid;
2641
2642         /* hw GUID */
2643         if (entry == 0)
2644                 return;
2645
2646         get_random_bytes((char *)&guid, sizeof(guid));
2647         guid &= ~(cpu_to_be64(1ULL << 56));
2648         guid |= cpu_to_be64(1ULL << 57);
2649         priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2650 }
2651
2652 static int mlx4_setup_hca(struct mlx4_dev *dev)
2653 {
2654         struct mlx4_priv *priv = mlx4_priv(dev);
2655         int err;
2656         int port;
2657         __be32 ib_port_default_caps;
2658
2659         err = mlx4_init_uar_table(dev);
2660         if (err) {
2661                 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2662                 return err;
2663         }
2664
2665         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2666         if (err) {
2667                 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2668                 goto err_uar_table_free;
2669         }
2670
2671         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2672         if (!priv->kar) {
2673                 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2674                 err = -ENOMEM;
2675                 goto err_uar_free;
2676         }
2677
2678         err = mlx4_init_pd_table(dev);
2679         if (err) {
2680                 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2681                 goto err_kar_unmap;
2682         }
2683
2684         err = mlx4_init_xrcd_table(dev);
2685         if (err) {
2686                 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2687                 goto err_pd_table_free;
2688         }
2689
2690         err = mlx4_init_mr_table(dev);
2691         if (err) {
2692                 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2693                 goto err_xrcd_table_free;
2694         }
2695
2696         if (!mlx4_is_slave(dev)) {
2697                 err = mlx4_init_mcg_table(dev);
2698                 if (err) {
2699                         mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2700                         goto err_mr_table_free;
2701                 }
2702                 err = mlx4_config_mad_demux(dev);
2703                 if (err) {
2704                         mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2705                         goto err_mcg_table_free;
2706                 }
2707         }
2708
2709         err = mlx4_init_eq_table(dev);
2710         if (err) {
2711                 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2712                 goto err_mcg_table_free;
2713         }
2714
2715         err = mlx4_cmd_use_events(dev);
2716         if (err) {
2717                 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2718                 goto err_eq_table_free;
2719         }
2720
2721         err = mlx4_NOP(dev);
2722         if (err) {
2723                 if (dev->flags & MLX4_FLAG_MSI_X) {
2724                         mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2725                                   priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2726                         mlx4_warn(dev, "Trying again without MSI-X\n");
2727                 } else {
2728                         mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2729                                  priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2730                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2731                 }
2732
2733                 goto err_cmd_poll;
2734         }
2735
2736         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2737
2738         err = mlx4_init_cq_table(dev);
2739         if (err) {
2740                 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2741                 goto err_cmd_poll;
2742         }
2743
2744         err = mlx4_init_srq_table(dev);
2745         if (err) {
2746                 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2747                 goto err_cq_table_free;
2748         }
2749
2750         err = mlx4_init_qp_table(dev);
2751         if (err) {
2752                 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2753                 goto err_srq_table_free;
2754         }
2755
2756         if (!mlx4_is_slave(dev)) {
2757                 err = mlx4_init_counters_table(dev);
2758                 if (err && err != -ENOENT) {
2759                         mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2760                         goto err_qp_table_free;
2761                 }
2762         }
2763
2764         err = mlx4_allocate_default_counters(dev);
2765         if (err) {
2766                 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2767                 goto err_counters_table_free;
2768         }
2769
2770         if (!mlx4_is_slave(dev)) {
2771                 for (port = 1; port <= dev->caps.num_ports; port++) {
2772                         ib_port_default_caps = 0;
2773                         err = mlx4_get_port_ib_caps(dev, port,
2774                                                     &ib_port_default_caps);
2775                         if (err)
2776                                 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2777                                           port, err);
2778                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2779
2780                         /* initialize per-slave default ib port capabilities */
2781                         if (mlx4_is_master(dev)) {
2782                                 int i;
2783                                 for (i = 0; i < dev->num_slaves; i++) {
2784                                         if (i == mlx4_master_func_num(dev))
2785                                                 continue;
2786                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2787                                                 ib_port_default_caps;
2788                                 }
2789                         }
2790
2791                         if (mlx4_is_mfunc(dev))
2792                                 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2793                         else
2794                                 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2795
2796                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2797                                             dev->caps.pkey_table_len[port] : -1);
2798                         if (err) {
2799                                 mlx4_err(dev, "Failed to set port %d, aborting\n",
2800                                          port);
2801                                 goto err_default_countes_free;
2802                         }
2803                 }
2804         }
2805
2806         return 0;
2807
2808 err_default_countes_free:
2809         mlx4_cleanup_default_counters(dev);
2810
2811 err_counters_table_free:
2812         if (!mlx4_is_slave(dev))
2813                 mlx4_cleanup_counters_table(dev);
2814
2815 err_qp_table_free:
2816         mlx4_cleanup_qp_table(dev);
2817
2818 err_srq_table_free:
2819         mlx4_cleanup_srq_table(dev);
2820
2821 err_cq_table_free:
2822         mlx4_cleanup_cq_table(dev);
2823
2824 err_cmd_poll:
2825         mlx4_cmd_use_polling(dev);
2826
2827 err_eq_table_free:
2828         mlx4_cleanup_eq_table(dev);
2829
2830 err_mcg_table_free:
2831         if (!mlx4_is_slave(dev))
2832                 mlx4_cleanup_mcg_table(dev);
2833
2834 err_mr_table_free:
2835         mlx4_cleanup_mr_table(dev);
2836
2837 err_xrcd_table_free:
2838         mlx4_cleanup_xrcd_table(dev);
2839
2840 err_pd_table_free:
2841         mlx4_cleanup_pd_table(dev);
2842
2843 err_kar_unmap:
2844         iounmap(priv->kar);
2845
2846 err_uar_free:
2847         mlx4_uar_free(dev, &priv->driver_uar);
2848
2849 err_uar_table_free:
2850         mlx4_cleanup_uar_table(dev);
2851         return err;
2852 }
2853
2854 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2855 {
2856         int requested_cpu = 0;
2857         struct mlx4_priv *priv = mlx4_priv(dev);
2858         struct mlx4_eq *eq;
2859         int off = 0;
2860         int i;
2861
2862         if (eqn > dev->caps.num_comp_vectors)
2863                 return -EINVAL;
2864
2865         for (i = 1; i < port; i++)
2866                 off += mlx4_get_eqs_per_port(dev, i);
2867
2868         requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2869
2870         /* Meaning EQs are shared, and this call comes from the second port */
2871         if (requested_cpu < 0)
2872                 return 0;
2873
2874         eq = &priv->eq_table.eq[eqn];
2875
2876         if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2877                 return -ENOMEM;
2878
2879         cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2880
2881         return 0;
2882 }
2883
2884 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2885 {
2886         struct mlx4_priv *priv = mlx4_priv(dev);
2887         struct msix_entry *entries;
2888         int i;
2889         int port = 0;
2890
2891         if (msi_x) {
2892                 int nreq = min3(dev->caps.num_ports *
2893                                 (int)num_online_cpus() + 1,
2894                                 dev->caps.num_eqs - dev->caps.reserved_eqs,
2895                                 MAX_MSIX);
2896
2897                 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
2898                 if (!entries)
2899                         goto no_msi;
2900
2901                 for (i = 0; i < nreq; ++i)
2902                         entries[i].entry = i;
2903
2904                 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2905                                              nreq);
2906
2907                 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2908                         kfree(entries);
2909                         goto no_msi;
2910                 }
2911                 /* 1 is reserved for events (asyncrounous EQ) */
2912                 dev->caps.num_comp_vectors = nreq - 1;
2913
2914                 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2915                 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2916                             dev->caps.num_ports);
2917
2918                 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2919                         if (i == MLX4_EQ_ASYNC)
2920                                 continue;
2921
2922                         priv->eq_table.eq[i].irq =
2923                                 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2924
2925                         if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2926                                 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2927                                             dev->caps.num_ports);
2928                                 /* We don't set affinity hint when there
2929                                  * aren't enough EQs
2930                                  */
2931                         } else {
2932                                 set_bit(port,
2933                                         priv->eq_table.eq[i].actv_ports.ports);
2934                                 if (mlx4_init_affinity_hint(dev, port + 1, i))
2935                                         mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2936                                                   i);
2937                         }
2938                         /* We divide the Eqs evenly between the two ports.
2939                          * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2940                          * refers to the number of Eqs per port
2941                          * (i.e eqs_per_port). Theoretically, we would like to
2942                          * write something like (i + 1) % eqs_per_port == 0.
2943                          * However, since there's an asynchronous Eq, we have
2944                          * to skip over it by comparing this condition to
2945                          * !!((i + 1) > MLX4_EQ_ASYNC).
2946                          */
2947                         if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2948                             ((i + 1) %
2949                              (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2950                             !!((i + 1) > MLX4_EQ_ASYNC))
2951                                 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2952                                  * everything is shared anyway.
2953                                  */
2954                                 port++;
2955                 }
2956
2957                 dev->flags |= MLX4_FLAG_MSI_X;
2958
2959                 kfree(entries);
2960                 return;
2961         }
2962
2963 no_msi:
2964         dev->caps.num_comp_vectors = 1;
2965
2966         BUG_ON(MLX4_EQ_ASYNC >= 2);
2967         for (i = 0; i < 2; ++i) {
2968                 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2969                 if (i != MLX4_EQ_ASYNC) {
2970                         bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2971                                     dev->caps.num_ports);
2972                 }
2973         }
2974 }
2975
2976 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2977 {
2978         struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2979         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2980         int err;
2981
2982         err = devlink_port_register(devlink, &info->devlink_port, port);
2983         if (err)
2984                 return err;
2985
2986         info->dev = dev;
2987         info->port = port;
2988         if (!mlx4_is_slave(dev)) {
2989                 mlx4_init_mac_table(dev, &info->mac_table);
2990                 mlx4_init_vlan_table(dev, &info->vlan_table);
2991                 mlx4_init_roce_gid_table(dev, &info->gid_table);
2992                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2993         }
2994
2995         sprintf(info->dev_name, "mlx4_port%d", port);
2996         info->port_attr.attr.name = info->dev_name;
2997         if (mlx4_is_mfunc(dev))
2998                 info->port_attr.attr.mode = S_IRUGO;
2999         else {
3000                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
3001                 info->port_attr.store     = set_port_type;
3002         }
3003         info->port_attr.show      = show_port_type;
3004         sysfs_attr_init(&info->port_attr.attr);
3005
3006         err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
3007         if (err) {
3008                 mlx4_err(dev, "Failed to create file for port %d\n", port);
3009                 devlink_port_unregister(&info->devlink_port);
3010                 info->port = -1;
3011                 return err;
3012         }
3013
3014         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
3015         info->port_mtu_attr.attr.name = info->dev_mtu_name;
3016         if (mlx4_is_mfunc(dev))
3017                 info->port_mtu_attr.attr.mode = S_IRUGO;
3018         else {
3019                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
3020                 info->port_mtu_attr.store     = set_port_ib_mtu;
3021         }
3022         info->port_mtu_attr.show      = show_port_ib_mtu;
3023         sysfs_attr_init(&info->port_mtu_attr.attr);
3024
3025         err = device_create_file(&dev->persist->pdev->dev,
3026                                  &info->port_mtu_attr);
3027         if (err) {
3028                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
3029                 device_remove_file(&info->dev->persist->pdev->dev,
3030                                    &info->port_attr);
3031                 devlink_port_unregister(&info->devlink_port);
3032                 info->port = -1;
3033                 return err;
3034         }
3035
3036         return 0;
3037 }
3038
3039 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3040 {
3041         if (info->port < 0)
3042                 return;
3043
3044         device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
3045         device_remove_file(&info->dev->persist->pdev->dev,
3046                            &info->port_mtu_attr);
3047         devlink_port_unregister(&info->devlink_port);
3048
3049 #ifdef CONFIG_RFS_ACCEL
3050         free_irq_cpu_rmap(info->rmap);
3051         info->rmap = NULL;
3052 #endif
3053 }
3054
3055 static int mlx4_init_steering(struct mlx4_dev *dev)
3056 {
3057         struct mlx4_priv *priv = mlx4_priv(dev);
3058         int num_entries = dev->caps.num_ports;
3059         int i, j;
3060
3061         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3062         if (!priv->steer)
3063                 return -ENOMEM;
3064
3065         for (i = 0; i < num_entries; i++)
3066                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3067                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3068                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3069                 }
3070         return 0;
3071 }
3072
3073 static void mlx4_clear_steering(struct mlx4_dev *dev)
3074 {
3075         struct mlx4_priv *priv = mlx4_priv(dev);
3076         struct mlx4_steer_index *entry, *tmp_entry;
3077         struct mlx4_promisc_qp *pqp, *tmp_pqp;
3078         int num_entries = dev->caps.num_ports;
3079         int i, j;
3080
3081         for (i = 0; i < num_entries; i++) {
3082                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3083                         list_for_each_entry_safe(pqp, tmp_pqp,
3084                                                  &priv->steer[i].promisc_qps[j],
3085                                                  list) {
3086                                 list_del(&pqp->list);
3087                                 kfree(pqp);
3088                         }
3089                         list_for_each_entry_safe(entry, tmp_entry,
3090                                                  &priv->steer[i].steer_entries[j],
3091                                                  list) {
3092                                 list_del(&entry->list);
3093                                 list_for_each_entry_safe(pqp, tmp_pqp,
3094                                                          &entry->duplicates,
3095                                                          list) {
3096                                         list_del(&pqp->list);
3097                                         kfree(pqp);
3098                                 }
3099                                 kfree(entry);
3100                         }
3101                 }
3102         }
3103         kfree(priv->steer);
3104 }
3105
3106 static int extended_func_num(struct pci_dev *pdev)
3107 {
3108         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3109 }
3110
3111 #define MLX4_OWNER_BASE 0x8069c
3112 #define MLX4_OWNER_SIZE 4
3113
3114 static int mlx4_get_ownership(struct mlx4_dev *dev)
3115 {
3116         void __iomem *owner;
3117         u32 ret;
3118
3119         if (pci_channel_offline(dev->persist->pdev))
3120                 return -EIO;
3121
3122         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3123                         MLX4_OWNER_BASE,
3124                         MLX4_OWNER_SIZE);
3125         if (!owner) {
3126                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3127                 return -ENOMEM;
3128         }
3129
3130         ret = readl(owner);
3131         iounmap(owner);
3132         return (int) !!ret;
3133 }
3134
3135 static void mlx4_free_ownership(struct mlx4_dev *dev)
3136 {
3137         void __iomem *owner;
3138
3139         if (pci_channel_offline(dev->persist->pdev))
3140                 return;
3141
3142         owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3143                         MLX4_OWNER_BASE,
3144                         MLX4_OWNER_SIZE);
3145         if (!owner) {
3146                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3147                 return;
3148         }
3149         writel(0, owner);
3150         msleep(1000);
3151         iounmap(owner);
3152 }
3153
3154 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3155                                   !!((flags) & MLX4_FLAG_MASTER))
3156
3157 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3158                              u8 total_vfs, int existing_vfs, int reset_flow)
3159 {
3160         u64 dev_flags = dev->flags;
3161         int err = 0;
3162         int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3163                                         MLX4_MAX_NUM_VF);
3164
3165         if (reset_flow) {
3166                 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3167                                        GFP_KERNEL);
3168                 if (!dev->dev_vfs)
3169                         goto free_mem;
3170                 return dev_flags;
3171         }
3172
3173         atomic_inc(&pf_loading);
3174         if (dev->flags &  MLX4_FLAG_SRIOV) {
3175                 if (existing_vfs != total_vfs) {
3176                         mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3177                                  existing_vfs, total_vfs);
3178                         total_vfs = existing_vfs;
3179                 }
3180         }
3181
3182         dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3183         if (NULL == dev->dev_vfs) {
3184                 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3185                 goto disable_sriov;
3186         }
3187
3188         if (!(dev->flags &  MLX4_FLAG_SRIOV)) {
3189                 if (total_vfs > fw_enabled_sriov_vfs) {
3190                         mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3191                                  total_vfs, fw_enabled_sriov_vfs);
3192                         err = -ENOMEM;
3193                         goto disable_sriov;
3194                 }
3195                 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3196                 err = pci_enable_sriov(pdev, total_vfs);
3197         }
3198         if (err) {
3199                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3200                          err);
3201                 goto disable_sriov;
3202         } else {
3203                 mlx4_warn(dev, "Running in master mode\n");
3204                 dev_flags |= MLX4_FLAG_SRIOV |
3205                         MLX4_FLAG_MASTER;
3206                 dev_flags &= ~MLX4_FLAG_SLAVE;
3207                 dev->persist->num_vfs = total_vfs;
3208         }
3209         return dev_flags;
3210
3211 disable_sriov:
3212         atomic_dec(&pf_loading);
3213 free_mem:
3214         dev->persist->num_vfs = 0;
3215         kfree(dev->dev_vfs);
3216         dev->dev_vfs = NULL;
3217         return dev_flags & ~MLX4_FLAG_MASTER;
3218 }
3219
3220 enum {
3221         MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3222 };
3223
3224 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3225                               int *nvfs)
3226 {
3227         int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3228         /* Checking for 64 VFs as a limitation of CX2 */
3229         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3230             requested_vfs >= 64) {
3231                 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3232                          requested_vfs);
3233                 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3234         }
3235         return 0;
3236 }
3237
3238 static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3239 {
3240         struct pci_dev *pdev = dev->persist->pdev;
3241         int err = 0;
3242
3243         mutex_lock(&dev->persist->pci_status_mutex);
3244         if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3245                 err = pci_enable_device(pdev);
3246                 if (!err)
3247                         dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3248         }
3249         mutex_unlock(&dev->persist->pci_status_mutex);
3250
3251         return err;
3252 }
3253
3254 static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3255 {
3256         struct pci_dev *pdev = dev->persist->pdev;
3257
3258         mutex_lock(&dev->persist->pci_status_mutex);
3259         if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3260                 pci_disable_device(pdev);
3261                 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3262         }
3263         mutex_unlock(&dev->persist->pci_status_mutex);
3264 }
3265
3266 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3267                          int total_vfs, int *nvfs, struct mlx4_priv *priv,
3268                          int reset_flow)
3269 {
3270         struct mlx4_dev *dev;
3271         unsigned sum = 0;
3272         int err;
3273         int port;
3274         int i;
3275         struct mlx4_dev_cap *dev_cap = NULL;
3276         int existing_vfs = 0;
3277
3278         dev = &priv->dev;
3279
3280         INIT_LIST_HEAD(&priv->ctx_list);
3281         spin_lock_init(&priv->ctx_lock);
3282
3283         mutex_init(&priv->port_mutex);
3284         mutex_init(&priv->bond_mutex);
3285
3286         INIT_LIST_HEAD(&priv->pgdir_list);
3287         mutex_init(&priv->pgdir_mutex);
3288         spin_lock_init(&priv->cmd.context_lock);
3289
3290         INIT_LIST_HEAD(&priv->bf_list);
3291         mutex_init(&priv->bf_mutex);
3292
3293         dev->rev_id = pdev->revision;
3294         dev->numa_node = dev_to_node(&pdev->dev);
3295
3296         /* Detect if this device is a virtual function */
3297         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3298                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3299                 dev->flags |= MLX4_FLAG_SLAVE;
3300         } else {
3301                 /* We reset the device and enable SRIOV only for physical
3302                  * devices.  Try to claim ownership on the device;
3303                  * if already taken, skip -- do not allow multiple PFs */
3304                 err = mlx4_get_ownership(dev);
3305                 if (err) {
3306                         if (err < 0)
3307                                 return err;
3308                         else {
3309                                 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3310                                 return -EINVAL;
3311                         }
3312                 }
3313
3314                 atomic_set(&priv->opreq_count, 0);
3315                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3316
3317                 /*
3318                  * Now reset the HCA before we touch the PCI capabilities or
3319                  * attempt a firmware command, since a boot ROM may have left
3320                  * the HCA in an undefined state.
3321                  */
3322                 err = mlx4_reset(dev);
3323                 if (err) {
3324                         mlx4_err(dev, "Failed to reset HCA, aborting\n");
3325                         goto err_sriov;
3326                 }
3327
3328                 if (total_vfs) {
3329                         dev->flags = MLX4_FLAG_MASTER;
3330                         existing_vfs = pci_num_vf(pdev);
3331                         if (existing_vfs)
3332                                 dev->flags |= MLX4_FLAG_SRIOV;
3333                         dev->persist->num_vfs = total_vfs;
3334                 }
3335         }
3336
3337         /* on load remove any previous indication of internal error,
3338          * device is up.
3339          */
3340         dev->persist->state = MLX4_DEVICE_STATE_UP;
3341
3342 slave_start:
3343         err = mlx4_cmd_init(dev);
3344         if (err) {
3345                 mlx4_err(dev, "Failed to init command interface, aborting\n");
3346                 goto err_sriov;
3347         }
3348
3349         /* In slave functions, the communication channel must be initialized
3350          * before posting commands. Also, init num_slaves before calling
3351          * mlx4_init_hca */
3352         if (mlx4_is_mfunc(dev)) {
3353                 if (mlx4_is_master(dev)) {
3354                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3355
3356                 } else {
3357                         dev->num_slaves = 0;
3358                         err = mlx4_multi_func_init(dev);
3359                         if (err) {
3360                                 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3361                                 goto err_cmd;
3362                         }
3363                 }
3364         }
3365
3366         err = mlx4_init_fw(dev);
3367         if (err) {
3368                 mlx4_err(dev, "Failed to init fw, aborting.\n");
3369                 goto err_mfunc;
3370         }
3371
3372         if (mlx4_is_master(dev)) {
3373                 /* when we hit the goto slave_start below, dev_cap already initialized */
3374                 if (!dev_cap) {
3375                         dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3376
3377                         if (!dev_cap) {
3378                                 err = -ENOMEM;
3379                                 goto err_fw;
3380                         }
3381
3382                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3383                         if (err) {
3384                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3385                                 goto err_fw;
3386                         }
3387
3388                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3389                                 goto err_fw;
3390
3391                         if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3392                                 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3393                                                                   total_vfs,
3394                                                                   existing_vfs,
3395                                                                   reset_flow);
3396
3397                                 mlx4_close_fw(dev);
3398                                 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3399                                 dev->flags = dev_flags;
3400                                 if (!SRIOV_VALID_STATE(dev->flags)) {
3401                                         mlx4_err(dev, "Invalid SRIOV state\n");
3402                                         goto err_sriov;
3403                                 }
3404                                 err = mlx4_reset(dev);
3405                                 if (err) {
3406                                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3407                                         goto err_sriov;
3408                                 }
3409                                 goto slave_start;
3410                         }
3411                 } else {
3412                         /* Legacy mode FW requires SRIOV to be enabled before
3413                          * doing QUERY_DEV_CAP, since max_eq's value is different if
3414                          * SRIOV is enabled.
3415                          */
3416                         memset(dev_cap, 0, sizeof(*dev_cap));
3417                         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3418                         if (err) {
3419                                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3420                                 goto err_fw;
3421                         }
3422
3423                         if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3424                                 goto err_fw;
3425                 }
3426         }
3427
3428         err = mlx4_init_hca(dev);
3429         if (err) {
3430                 if (err == -EACCES) {
3431                         /* Not primary Physical function
3432                          * Running in slave mode */
3433                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3434                         /* We're not a PF */
3435                         if (dev->flags & MLX4_FLAG_SRIOV) {
3436                                 if (!existing_vfs)
3437                                         pci_disable_sriov(pdev);
3438                                 if (mlx4_is_master(dev) && !reset_flow)
3439                                         atomic_dec(&pf_loading);
3440                                 dev->flags &= ~MLX4_FLAG_SRIOV;
3441                         }
3442                         if (!mlx4_is_slave(dev))
3443                                 mlx4_free_ownership(dev);
3444                         dev->flags |= MLX4_FLAG_SLAVE;
3445                         dev->flags &= ~MLX4_FLAG_MASTER;
3446                         goto slave_start;
3447                 } else
3448                         goto err_fw;
3449         }
3450
3451         if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3452                 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3453                                                   existing_vfs, reset_flow);
3454
3455                 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3456                         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3457                         dev->flags = dev_flags;
3458                         err = mlx4_cmd_init(dev);
3459                         if (err) {
3460                                 /* Only VHCR is cleaned up, so could still
3461                                  * send FW commands
3462                                  */
3463                                 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3464                                 goto err_close;
3465                         }
3466                 } else {
3467                         dev->flags = dev_flags;
3468                 }
3469
3470                 if (!SRIOV_VALID_STATE(dev->flags)) {
3471                         mlx4_err(dev, "Invalid SRIOV state\n");
3472                         err = -EINVAL;
3473                         goto err_close;
3474                 }
3475         }
3476
3477         /* check if the device is functioning at its maximum possible speed.
3478          * No return code for this call, just warn the user in case of PCI
3479          * express device capabilities are under-satisfied by the bus.
3480          */
3481         if (!mlx4_is_slave(dev))
3482                 mlx4_check_pcie_caps(dev);
3483
3484         /* In master functions, the communication channel must be initialized
3485          * after obtaining its address from fw */
3486         if (mlx4_is_master(dev)) {
3487                 if (dev->caps.num_ports < 2 &&
3488                     num_vfs_argc > 1) {
3489                         err = -EINVAL;
3490                         mlx4_err(dev,
3491                                  "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3492                                  dev->caps.num_ports);
3493                         goto err_close;
3494                 }
3495                 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3496
3497                 for (i = 0;
3498                      i < sizeof(dev->persist->nvfs)/
3499                      sizeof(dev->persist->nvfs[0]); i++) {
3500                         unsigned j;
3501
3502                         for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3503                                 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3504                                 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3505                                         dev->caps.num_ports;
3506                         }
3507                 }
3508
3509                 /* In master functions, the communication channel
3510                  * must be initialized after obtaining its address from fw
3511                  */
3512                 err = mlx4_multi_func_init(dev);
3513                 if (err) {
3514                         mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3515                         goto err_close;
3516                 }
3517         }
3518
3519         err = mlx4_alloc_eq_table(dev);
3520         if (err)
3521                 goto err_master_mfunc;
3522
3523         bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3524         mutex_init(&priv->msix_ctl.pool_lock);
3525
3526         mlx4_enable_msi_x(dev);
3527         if ((mlx4_is_mfunc(dev)) &&
3528             !(dev->flags & MLX4_FLAG_MSI_X)) {
3529                 err = -EOPNOTSUPP;
3530                 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3531                 goto err_free_eq;
3532         }
3533
3534         if (!mlx4_is_slave(dev)) {
3535                 err = mlx4_init_steering(dev);
3536                 if (err)
3537                         goto err_disable_msix;
3538         }
3539
3540         mlx4_init_quotas(dev);
3541
3542         err = mlx4_setup_hca(dev);
3543         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3544             !mlx4_is_mfunc(dev)) {
3545                 dev->flags &= ~MLX4_FLAG_MSI_X;
3546                 dev->caps.num_comp_vectors = 1;
3547                 pci_disable_msix(pdev);
3548                 err = mlx4_setup_hca(dev);
3549         }
3550
3551         if (err)
3552                 goto err_steer;
3553
3554         /* When PF resources are ready arm its comm channel to enable
3555          * getting commands
3556          */
3557         if (mlx4_is_master(dev)) {
3558                 err = mlx4_ARM_COMM_CHANNEL(dev);
3559                 if (err) {
3560                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3561                                  err);
3562                         goto err_steer;
3563                 }
3564         }
3565
3566         for (port = 1; port <= dev->caps.num_ports; port++) {
3567                 err = mlx4_init_port_info(dev, port);
3568                 if (err)
3569                         goto err_port;
3570         }
3571
3572         priv->v2p.port1 = 1;
3573         priv->v2p.port2 = 2;
3574
3575         err = mlx4_register_device(dev);
3576         if (err)
3577                 goto err_port;
3578
3579         mlx4_request_modules(dev);
3580
3581         mlx4_sense_init(dev);
3582         mlx4_start_sense(dev);
3583
3584         priv->removed = 0;
3585
3586         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3587                 atomic_dec(&pf_loading);
3588
3589         kfree(dev_cap);
3590         return 0;
3591
3592 err_port:
3593         for (--port; port >= 1; --port)
3594                 mlx4_cleanup_port_info(&priv->port[port]);
3595
3596         mlx4_cleanup_default_counters(dev);
3597         if (!mlx4_is_slave(dev))
3598                 mlx4_cleanup_counters_table(dev);
3599         mlx4_cleanup_qp_table(dev);
3600         mlx4_cleanup_srq_table(dev);
3601         mlx4_cleanup_cq_table(dev);
3602         mlx4_cmd_use_polling(dev);
3603         mlx4_cleanup_eq_table(dev);
3604         mlx4_cleanup_mcg_table(dev);
3605         mlx4_cleanup_mr_table(dev);
3606         mlx4_cleanup_xrcd_table(dev);
3607         mlx4_cleanup_pd_table(dev);
3608         mlx4_cleanup_uar_table(dev);
3609
3610 err_steer:
3611         if (!mlx4_is_slave(dev))
3612                 mlx4_clear_steering(dev);
3613
3614 err_disable_msix:
3615         if (dev->flags & MLX4_FLAG_MSI_X)
3616                 pci_disable_msix(pdev);
3617
3618 err_free_eq:
3619         mlx4_free_eq_table(dev);
3620
3621 err_master_mfunc:
3622         if (mlx4_is_master(dev)) {
3623                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3624                 mlx4_multi_func_cleanup(dev);
3625         }
3626
3627         if (mlx4_is_slave(dev))
3628                 mlx4_slave_destroy_special_qp_cap(dev);
3629
3630 err_close:
3631         mlx4_close_hca(dev);
3632
3633 err_fw:
3634         mlx4_close_fw(dev);
3635
3636 err_mfunc:
3637         if (mlx4_is_slave(dev))
3638                 mlx4_multi_func_cleanup(dev);
3639
3640 err_cmd:
3641         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3642
3643 err_sriov:
3644         if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3645                 pci_disable_sriov(pdev);
3646                 dev->flags &= ~MLX4_FLAG_SRIOV;
3647         }
3648
3649         if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3650                 atomic_dec(&pf_loading);
3651
3652         kfree(priv->dev.dev_vfs);
3653
3654         if (!mlx4_is_slave(dev))
3655                 mlx4_free_ownership(dev);
3656
3657         kfree(dev_cap);
3658         return err;
3659 }
3660
3661 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3662                            struct mlx4_priv *priv)
3663 {
3664         int err;
3665         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3666         int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3667         const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3668                 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3669         unsigned total_vfs = 0;
3670         unsigned int i;
3671
3672         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3673
3674         err = mlx4_pci_enable_device(&priv->dev);
3675         if (err) {
3676                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3677                 return err;
3678         }
3679
3680         /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3681          * per port, we must limit the number of VFs to 63 (since their are
3682          * 128 MACs)
3683          */
3684         for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc;
3685              total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3686                 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3687                 if (nvfs[i] < 0) {
3688                         dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3689                         err = -EINVAL;
3690                         goto err_disable_pdev;
3691                 }
3692         }
3693         for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc;
3694              i++) {
3695                 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3696                 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3697                         dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3698                         err = -EINVAL;
3699                         goto err_disable_pdev;
3700                 }
3701         }
3702         if (total_vfs > MLX4_MAX_NUM_VF) {
3703                 dev_err(&pdev->dev,
3704                         "Requested more VF's (%d) than allowed by hw (%d)\n",
3705                         total_vfs, MLX4_MAX_NUM_VF);
3706                 err = -EINVAL;
3707                 goto err_disable_pdev;
3708         }
3709
3710         for (i = 0; i < MLX4_MAX_PORTS; i++) {
3711                 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3712                         dev_err(&pdev->dev,
3713                                 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3714                                 nvfs[i] + nvfs[2], i + 1,
3715                                 MLX4_MAX_NUM_VF_P_PORT);
3716                         err = -EINVAL;
3717                         goto err_disable_pdev;
3718                 }
3719         }
3720
3721         /* Check for BARs. */
3722         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3723             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3724                 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3725                         pci_dev_data, pci_resource_flags(pdev, 0));
3726                 err = -ENODEV;
3727                 goto err_disable_pdev;
3728         }
3729         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3730                 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3731                 err = -ENODEV;
3732                 goto err_disable_pdev;
3733         }
3734
3735         err = pci_request_regions(pdev, DRV_NAME);
3736         if (err) {
3737                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3738                 goto err_disable_pdev;
3739         }
3740
3741         pci_set_master(pdev);
3742
3743         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3744         if (err) {
3745                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3746                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3747                 if (err) {
3748                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3749                         goto err_release_regions;
3750                 }
3751         }
3752         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3753         if (err) {
3754                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3755                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3756                 if (err) {
3757                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3758                         goto err_release_regions;
3759                 }
3760         }
3761
3762         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3763         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3764         /* Detect if this device is a virtual function */
3765         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3766                 /* When acting as pf, we normally skip vfs unless explicitly
3767                  * requested to probe them.
3768                  */
3769                 if (total_vfs) {
3770                         unsigned vfs_offset = 0;
3771
3772                         for (i = 0; i < ARRAY_SIZE(nvfs) &&
3773                              vfs_offset + nvfs[i] < extended_func_num(pdev);
3774                              vfs_offset += nvfs[i], i++)
3775                                 ;
3776                         if (i == ARRAY_SIZE(nvfs)) {
3777                                 err = -ENODEV;
3778                                 goto err_release_regions;
3779                         }
3780                         if ((extended_func_num(pdev) - vfs_offset)
3781                             > prb_vf[i]) {
3782                                 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3783                                          extended_func_num(pdev));
3784                                 err = -ENODEV;
3785                                 goto err_release_regions;
3786                         }
3787                 }
3788         }
3789
3790         err = mlx4_catas_init(&priv->dev);
3791         if (err)
3792                 goto err_release_regions;
3793
3794         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3795         if (err)
3796                 goto err_catas;
3797
3798         return 0;
3799
3800 err_catas:
3801         mlx4_catas_end(&priv->dev);
3802
3803 err_release_regions:
3804         pci_release_regions(pdev);
3805
3806 err_disable_pdev:
3807         mlx4_pci_disable_device(&priv->dev);
3808         return err;
3809 }
3810
3811 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3812                                       enum devlink_port_type port_type)
3813 {
3814         struct mlx4_port_info *info = container_of(devlink_port,
3815                                                    struct mlx4_port_info,
3816                                                    devlink_port);
3817         enum mlx4_port_type mlx4_port_type;
3818
3819         switch (port_type) {
3820         case DEVLINK_PORT_TYPE_AUTO:
3821                 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3822                 break;
3823         case DEVLINK_PORT_TYPE_ETH:
3824                 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3825                 break;
3826         case DEVLINK_PORT_TYPE_IB:
3827                 mlx4_port_type = MLX4_PORT_TYPE_IB;
3828                 break;
3829         default:
3830                 return -EOPNOTSUPP;
3831         }
3832
3833         return __set_port_type(info, mlx4_port_type);
3834 }
3835
3836 static const struct devlink_ops mlx4_devlink_ops = {
3837         .port_type_set  = mlx4_devlink_port_type_set,
3838 };
3839
3840 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3841 {
3842         struct devlink *devlink;
3843         struct mlx4_priv *priv;
3844         struct mlx4_dev *dev;
3845         int ret;
3846
3847         printk_once(KERN_INFO "%s", mlx4_version);
3848
3849         devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
3850         if (!devlink)
3851                 return -ENOMEM;
3852         priv = devlink_priv(devlink);
3853
3854         dev       = &priv->dev;
3855         dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3856         if (!dev->persist) {
3857                 ret = -ENOMEM;
3858                 goto err_devlink_free;
3859         }
3860         dev->persist->pdev = pdev;
3861         dev->persist->dev = dev;
3862         pci_set_drvdata(pdev, dev->persist);
3863         priv->pci_dev_data = id->driver_data;
3864         mutex_init(&dev->persist->device_state_mutex);
3865         mutex_init(&dev->persist->interface_state_mutex);
3866         mutex_init(&dev->persist->pci_status_mutex);
3867
3868         ret = devlink_register(devlink, &pdev->dev);
3869         if (ret)
3870                 goto err_persist_free;
3871
3872         ret =  __mlx4_init_one(pdev, id->driver_data, priv);
3873         if (ret)
3874                 goto err_devlink_unregister;
3875
3876         pci_save_state(pdev);
3877         return 0;
3878
3879 err_devlink_unregister:
3880         devlink_unregister(devlink);
3881 err_persist_free:
3882         kfree(dev->persist);
3883 err_devlink_free:
3884         devlink_free(devlink);
3885         return ret;
3886 }
3887
3888 static void mlx4_clean_dev(struct mlx4_dev *dev)
3889 {
3890         struct mlx4_dev_persistent *persist = dev->persist;
3891         struct mlx4_priv *priv = mlx4_priv(dev);
3892         unsigned long   flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3893
3894         memset(priv, 0, sizeof(*priv));
3895         priv->dev.persist = persist;
3896         priv->dev.flags = flags;
3897 }
3898
3899 static void mlx4_unload_one(struct pci_dev *pdev)
3900 {
3901         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3902         struct mlx4_dev  *dev  = persist->dev;
3903         struct mlx4_priv *priv = mlx4_priv(dev);
3904         int               pci_dev_data;
3905         int p, i;
3906
3907         if (priv->removed)
3908                 return;
3909
3910         /* saving current ports type for further use */
3911         for (i = 0; i < dev->caps.num_ports; i++) {
3912                 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3913                 dev->persist->curr_port_poss_type[i] = dev->caps.
3914                                                        possible_type[i + 1];
3915         }
3916
3917         pci_dev_data = priv->pci_dev_data;
3918
3919         mlx4_stop_sense(dev);
3920         mlx4_unregister_device(dev);
3921
3922         for (p = 1; p <= dev->caps.num_ports; p++) {
3923                 mlx4_cleanup_port_info(&priv->port[p]);
3924                 mlx4_CLOSE_PORT(dev, p);
3925         }
3926
3927         if (mlx4_is_master(dev))
3928                 mlx4_free_resource_tracker(dev,
3929                                            RES_TR_FREE_SLAVES_ONLY);
3930
3931         mlx4_cleanup_default_counters(dev);
3932         if (!mlx4_is_slave(dev))
3933                 mlx4_cleanup_counters_table(dev);
3934         mlx4_cleanup_qp_table(dev);
3935         mlx4_cleanup_srq_table(dev);
3936         mlx4_cleanup_cq_table(dev);
3937         mlx4_cmd_use_polling(dev);
3938         mlx4_cleanup_eq_table(dev);
3939         mlx4_cleanup_mcg_table(dev);
3940         mlx4_cleanup_mr_table(dev);
3941         mlx4_cleanup_xrcd_table(dev);
3942         mlx4_cleanup_pd_table(dev);
3943
3944         if (mlx4_is_master(dev))
3945                 mlx4_free_resource_tracker(dev,
3946                                            RES_TR_FREE_STRUCTS_ONLY);
3947
3948         iounmap(priv->kar);
3949         mlx4_uar_free(dev, &priv->driver_uar);
3950         mlx4_cleanup_uar_table(dev);
3951         if (!mlx4_is_slave(dev))
3952                 mlx4_clear_steering(dev);
3953         mlx4_free_eq_table(dev);
3954         if (mlx4_is_master(dev))
3955                 mlx4_multi_func_cleanup(dev);
3956         mlx4_close_hca(dev);
3957         mlx4_close_fw(dev);
3958         if (mlx4_is_slave(dev))
3959                 mlx4_multi_func_cleanup(dev);
3960         mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3961
3962         if (dev->flags & MLX4_FLAG_MSI_X)
3963                 pci_disable_msix(pdev);
3964
3965         if (!mlx4_is_slave(dev))
3966                 mlx4_free_ownership(dev);
3967
3968         mlx4_slave_destroy_special_qp_cap(dev);
3969         kfree(dev->dev_vfs);
3970
3971         mlx4_clean_dev(dev);
3972         priv->pci_dev_data = pci_dev_data;
3973         priv->removed = 1;
3974 }
3975
3976 static void mlx4_remove_one(struct pci_dev *pdev)
3977 {
3978         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3979         struct mlx4_dev  *dev  = persist->dev;
3980         struct mlx4_priv *priv = mlx4_priv(dev);
3981         struct devlink *devlink = priv_to_devlink(priv);
3982         int active_vfs = 0;
3983
3984         if (mlx4_is_slave(dev))
3985                 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3986
3987         mutex_lock(&persist->interface_state_mutex);
3988         persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3989         mutex_unlock(&persist->interface_state_mutex);
3990
3991         /* Disabling SR-IOV is not allowed while there are active vf's */
3992         if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3993                 active_vfs = mlx4_how_many_lives_vf(dev);
3994                 if (active_vfs) {
3995                         pr_warn("Removing PF when there are active VF's !!\n");
3996                         pr_warn("Will not disable SR-IOV.\n");
3997                 }
3998         }
3999
4000         /* device marked to be under deletion running now without the lock
4001          * letting other tasks to be terminated
4002          */
4003         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4004                 mlx4_unload_one(pdev);
4005         else
4006                 mlx4_info(dev, "%s: interface is down\n", __func__);
4007         mlx4_catas_end(dev);
4008         if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
4009                 mlx4_warn(dev, "Disabling SR-IOV\n");
4010                 pci_disable_sriov(pdev);
4011         }
4012
4013         pci_release_regions(pdev);
4014         mlx4_pci_disable_device(dev);
4015         devlink_unregister(devlink);
4016         kfree(dev->persist);
4017         devlink_free(devlink);
4018 }
4019
4020 static int restore_current_port_types(struct mlx4_dev *dev,
4021                                       enum mlx4_port_type *types,
4022                                       enum mlx4_port_type *poss_types)
4023 {
4024         struct mlx4_priv *priv = mlx4_priv(dev);
4025         int err, i;
4026
4027         mlx4_stop_sense(dev);
4028
4029         mutex_lock(&priv->port_mutex);
4030         for (i = 0; i < dev->caps.num_ports; i++)
4031                 dev->caps.possible_type[i + 1] = poss_types[i];
4032         err = mlx4_change_port_types(dev, types);
4033         mlx4_start_sense(dev);
4034         mutex_unlock(&priv->port_mutex);
4035
4036         return err;
4037 }
4038
4039 int mlx4_restart_one(struct pci_dev *pdev)
4040 {
4041         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4042         struct mlx4_dev  *dev  = persist->dev;
4043         struct mlx4_priv *priv = mlx4_priv(dev);
4044         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4045         int pci_dev_data, err, total_vfs;
4046
4047         pci_dev_data = priv->pci_dev_data;
4048         total_vfs = dev->persist->num_vfs;
4049         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4050
4051         mlx4_unload_one(pdev);
4052         err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
4053         if (err) {
4054                 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4055                          __func__, pci_name(pdev), err);
4056                 return err;
4057         }
4058
4059         err = restore_current_port_types(dev, dev->persist->curr_port_type,
4060                                          dev->persist->curr_port_poss_type);
4061         if (err)
4062                 mlx4_err(dev, "could not restore original port types (%d)\n",
4063                          err);
4064
4065         return err;
4066 }
4067
4068 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
4069 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
4070 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
4071
4072 static const struct pci_device_id mlx4_pci_table[] = {
4073         /* MT25408 "Hermon" */
4074         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR),      /* SDR */
4075         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR),      /* DDR */
4076         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR),      /* QDR */
4077         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4078         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4079         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN),       /* EN 10GigE */
4080         MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2),  /* EN 10GigE Gen2 */
4081         /* MT25458 ConnectX EN 10GBASE-T */
4082         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4083         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2),      /* Gen2 */
4084         /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4085         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4086         /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4087         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4088         /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4089         MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4090         /* MT25400 Family [ConnectX-2] */
4091         MLX_VF(0x1002),                                 /* Virtual Function */
4092         /* MT27500 Family [ConnectX-3] */
4093         MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4094         MLX_VF(0x1004),                                 /* Virtual Function */
4095         MLX_GN(0x1005),                                 /* MT27510 Family */
4096         MLX_GN(0x1006),                                 /* MT27511 Family */
4097         MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO),   /* MT27520 Family */
4098         MLX_GN(0x1008),                                 /* MT27521 Family */
4099         MLX_GN(0x1009),                                 /* MT27530 Family */
4100         MLX_GN(0x100a),                                 /* MT27531 Family */
4101         MLX_GN(0x100b),                                 /* MT27540 Family */
4102         MLX_GN(0x100c),                                 /* MT27541 Family */
4103         MLX_GN(0x100d),                                 /* MT27550 Family */
4104         MLX_GN(0x100e),                                 /* MT27551 Family */
4105         MLX_GN(0x100f),                                 /* MT27560 Family */
4106         MLX_GN(0x1010),                                 /* MT27561 Family */
4107
4108         /*
4109          * See the mellanox_check_broken_intx_masking() quirk when
4110          * adding devices
4111          */
4112
4113         { 0, }
4114 };
4115
4116 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4117
4118 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4119                                               pci_channel_state_t state)
4120 {
4121         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4122
4123         mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4124         mlx4_enter_error_state(persist);
4125
4126         mutex_lock(&persist->interface_state_mutex);
4127         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4128                 mlx4_unload_one(pdev);
4129
4130         mutex_unlock(&persist->interface_state_mutex);
4131         if (state == pci_channel_io_perm_failure)
4132                 return PCI_ERS_RESULT_DISCONNECT;
4133
4134         mlx4_pci_disable_device(persist->dev);
4135         return PCI_ERS_RESULT_NEED_RESET;
4136 }
4137
4138 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4139 {
4140         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4141         struct mlx4_dev  *dev  = persist->dev;
4142         int err;
4143
4144         mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4145         err = mlx4_pci_enable_device(dev);
4146         if (err) {
4147                 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
4148                 return PCI_ERS_RESULT_DISCONNECT;
4149         }
4150
4151         pci_set_master(pdev);
4152         pci_restore_state(pdev);
4153         pci_save_state(pdev);
4154         return PCI_ERS_RESULT_RECOVERED;
4155 }
4156
4157 static void mlx4_pci_resume(struct pci_dev *pdev)
4158 {
4159         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4160         struct mlx4_dev  *dev  = persist->dev;
4161         struct mlx4_priv *priv = mlx4_priv(dev);
4162         int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4163         int total_vfs;
4164         int err;
4165
4166         mlx4_err(dev, "%s was called\n", __func__);
4167         total_vfs = dev->persist->num_vfs;
4168         memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4169
4170         mutex_lock(&persist->interface_state_mutex);
4171         if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4172                 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
4173                                     priv, 1);
4174                 if (err) {
4175                         mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4176                                  __func__,  err);
4177                         goto end;
4178                 }
4179
4180                 err = restore_current_port_types(dev, dev->persist->
4181                                                  curr_port_type, dev->persist->
4182                                                  curr_port_poss_type);
4183                 if (err)
4184                         mlx4_err(dev, "could not restore original port types (%d)\n", err);
4185         }
4186 end:
4187         mutex_unlock(&persist->interface_state_mutex);
4188
4189 }
4190
4191 static void mlx4_shutdown(struct pci_dev *pdev)
4192 {
4193         struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4194         struct mlx4_dev *dev = persist->dev;
4195
4196         mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4197         mutex_lock(&persist->interface_state_mutex);
4198         if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4199                 mlx4_unload_one(pdev);
4200         mutex_unlock(&persist->interface_state_mutex);
4201         mlx4_pci_disable_device(dev);
4202 }
4203
4204 static const struct pci_error_handlers mlx4_err_handler = {
4205         .error_detected = mlx4_pci_err_detected,
4206         .slot_reset     = mlx4_pci_slot_reset,
4207         .resume         = mlx4_pci_resume,
4208 };
4209
4210 static struct pci_driver mlx4_driver = {
4211         .name           = DRV_NAME,
4212         .id_table       = mlx4_pci_table,
4213         .probe          = mlx4_init_one,
4214         .shutdown       = mlx4_shutdown,
4215         .remove         = mlx4_remove_one,
4216         .err_handler    = &mlx4_err_handler,
4217 };
4218
4219 static int __init mlx4_verify_params(void)
4220 {
4221         if ((log_num_mac < 0) || (log_num_mac > 7)) {
4222                 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
4223                 return -1;
4224         }
4225
4226         if (log_num_vlan != 0)
4227                 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4228                         MLX4_LOG_NUM_VLANS);
4229
4230         if (use_prio != 0)
4231                 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
4232
4233         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
4234                 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4235                         log_mtts_per_seg);
4236                 return -1;
4237         }
4238
4239         /* Check if module param for ports type has legal combination */
4240         if (port_type_array[0] == false && port_type_array[1] == true) {
4241                 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
4242                 port_type_array[0] = true;
4243         }
4244
4245         if (mlx4_log_num_mgm_entry_size < -7 ||
4246             (mlx4_log_num_mgm_entry_size > 0 &&
4247              (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4248               mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4249                 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
4250                         mlx4_log_num_mgm_entry_size,
4251                         MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4252                         MLX4_MAX_MGM_LOG_ENTRY_SIZE);
4253                 return -1;
4254         }
4255
4256         return 0;
4257 }
4258
4259 static int __init mlx4_init(void)
4260 {
4261         int ret;
4262
4263         if (mlx4_verify_params())
4264                 return -EINVAL;
4265
4266
4267         mlx4_wq = create_singlethread_workqueue("mlx4");
4268         if (!mlx4_wq)
4269                 return -ENOMEM;
4270
4271         ret = pci_register_driver(&mlx4_driver);
4272         if (ret < 0)
4273                 destroy_workqueue(mlx4_wq);
4274         return ret < 0 ? ret : 0;
4275 }
4276
4277 static void __exit mlx4_cleanup(void)
4278 {
4279         pci_unregister_driver(&mlx4_driver);
4280         destroy_workqueue(mlx4_wq);
4281 }
4282
4283 module_init(mlx4_init);
4284 module_exit(mlx4_cleanup);