2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/interrupt.h>
35 #include <linux/slab.h>
36 #include <linux/export.h>
38 #include <linux/dma-mapping.h>
40 #include <linux/mlx4/cmd.h>
41 #include <linux/cpu_rmap.h>
47 MLX4_IRQNAME_SIZE = 32
51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
56 #define MLX4_EQ_STATUS_OK ( 0 << 28)
57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
58 #define MLX4_EQ_OWNER_SW ( 0 << 24)
59 #define MLX4_EQ_OWNER_HW ( 1 << 24)
60 #define MLX4_EQ_FLAG_EC ( 1 << 18)
61 #define MLX4_EQ_FLAG_OI ( 1 << 17)
62 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
63 #define MLX4_EQ_STATE_FIRED (10 << 8)
64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
80 (1ull << MLX4_EVENT_TYPE_CMD) | \
81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT);
97 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
102 /* We still want ordering, just not swabbing, so add a barrier */
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
109 /* (entry & (eq->nent - 1)) gives us a cyclic array */
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with
112 * strides of 64B,128B and 256B.
113 * When 64B EQE is used, the first (in the lower addresses)
114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
115 * contain the legacy EQE information.
116 * In all other cases, the first 32B contains the legacy EQE info.
118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
129 struct mlx4_eqe *eqe =
130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
131 return (!!(eqe->owner & 0x80) ^
132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
136 void mlx4_gen_slave_eqe(struct work_struct *work)
138 struct mlx4_mfunc_master_ctx *master =
139 container_of(work, struct mlx4_mfunc_master_ctx,
141 struct mlx4_mfunc *mfunc =
142 container_of(master, struct mlx4_mfunc, master);
143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
144 struct mlx4_dev *dev = &priv->dev;
145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
146 struct mlx4_eqe *eqe;
148 int i, phys_port, slave_port;
150 for (eqe = next_slave_event_eqe(slave_eq); eqe;
151 eqe = next_slave_event_eqe(slave_eq)) {
152 slave = eqe->slave_id;
154 /* All active slaves need to receive the event */
155 if (slave == ALL_SLAVES) {
156 for (i = 0; i <= dev->persist->num_vfs; i++) {
158 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT &&
159 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) {
160 phys_port = eqe->event.port_mgmt_change.port;
161 slave_port = mlx4_phys_to_slave_port(dev, i, phys_port);
162 if (slave_port < 0) /* VF doesn't have this port */
164 eqe->event.port_mgmt_change.port = slave_port;
166 if (mlx4_GEN_EQE(dev, i, eqe))
167 mlx4_warn(dev, "Failed to generate event for slave %d\n",
170 eqe->event.port_mgmt_change.port = phys_port;
173 if (mlx4_GEN_EQE(dev, slave, eqe))
174 mlx4_warn(dev, "Failed to generate event for slave %d\n",
182 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
184 struct mlx4_priv *priv = mlx4_priv(dev);
185 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
186 struct mlx4_eqe *s_eqe;
189 spin_lock_irqsave(&slave_eq->event_lock, flags);
190 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
191 if ((!!(s_eqe->owner & 0x80)) ^
192 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
193 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
195 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
199 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1);
200 s_eqe->slave_id = slave;
201 /* ensure all information is written before setting the ownersip bit */
203 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
206 queue_work(priv->mfunc.master.comm_wq,
207 &priv->mfunc.master.slave_event_work);
208 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
211 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
212 struct mlx4_eqe *eqe)
214 struct mlx4_priv *priv = mlx4_priv(dev);
216 if (slave < 0 || slave > dev->persist->num_vfs ||
217 slave == dev->caps.function ||
218 !priv->mfunc.master.slave_state[slave].active)
221 slave_event(dev, slave, eqe);
224 #if defined(CONFIG_SMP)
225 static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec)
228 struct mlx4_dev *dev = &priv->dev;
229 struct mlx4_eq *eq = &priv->eq_table.eq[vec];
231 if (!cpumask_available(eq->affinity_mask) ||
232 cpumask_empty(eq->affinity_mask))
235 hint_err = irq_set_affinity_hint(eq->irq, eq->affinity_mask);
237 mlx4_warn(dev, "irq_set_affinity_hint failed, err %d\n", hint_err);
241 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
245 struct mlx4_priv *priv = mlx4_priv(dev);
246 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
248 if (!s_slave->active)
251 memset(&eqe, 0, sizeof eqe);
253 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
254 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
255 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
257 return mlx4_GEN_EQE(dev, slave, &eqe);
259 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
261 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
265 /*don't send if we don't have the that slave */
266 if (dev->persist->num_vfs < slave)
268 memset(&eqe, 0, sizeof eqe);
270 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
271 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
272 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
274 return mlx4_GEN_EQE(dev, slave, &eqe);
276 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
278 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
279 u8 port_subtype_change)
282 u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port);
284 /*don't send if we don't have the that slave */
285 if (dev->persist->num_vfs < slave)
287 memset(&eqe, 0, sizeof eqe);
289 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
290 eqe.subtype = port_subtype_change;
291 eqe.event.port_change.port = cpu_to_be32(slave_port << 28);
293 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
294 port_subtype_change, slave, port);
295 return mlx4_GEN_EQE(dev, slave, &eqe);
297 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
299 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
301 struct mlx4_priv *priv = mlx4_priv(dev);
302 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
303 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
305 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
306 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
307 pr_err("%s: Error: asking for slave:%d, port:%d\n",
308 __func__, slave, port);
309 return SLAVE_PORT_DOWN;
311 return s_state[slave].port_state[port];
313 EXPORT_SYMBOL(mlx4_get_slave_port_state);
315 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
316 enum slave_port_state state)
318 struct mlx4_priv *priv = mlx4_priv(dev);
319 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
320 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
322 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
323 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
324 pr_err("%s: Error: asking for slave:%d, port:%d\n",
325 __func__, slave, port);
328 s_state[slave].port_state[port] = state;
333 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
336 enum slave_port_gen_event gen_event;
337 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
340 for (i = 0; i < dev->persist->num_vfs + 1; i++)
341 if (test_bit(i, slaves_pport.slaves))
342 set_and_calc_slave_port_state(dev, i, port,
345 /**************************************************************************
346 The function get as input the new event to that port,
347 and according to the prev state change the slave's port state.
349 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
350 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
351 MLX4_PORT_STATE_IB_EVENT_GID_VALID
352 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
353 ***************************************************************************/
354 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
356 enum slave_port_gen_event *gen_event)
358 struct mlx4_priv *priv = mlx4_priv(dev);
359 struct mlx4_slave_state *ctx = NULL;
362 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
363 enum slave_port_state cur_state =
364 mlx4_get_slave_port_state(dev, slave, port);
366 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
368 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
369 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
370 pr_err("%s: Error: asking for slave:%d, port:%d\n",
371 __func__, slave, port);
375 ctx = &priv->mfunc.master.slave_state[slave];
376 spin_lock_irqsave(&ctx->lock, flags);
379 case SLAVE_PORT_DOWN:
380 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
381 mlx4_set_slave_port_state(dev, slave, port,
384 case SLAVE_PENDING_UP:
385 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
386 mlx4_set_slave_port_state(dev, slave, port,
388 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
389 mlx4_set_slave_port_state(dev, slave, port,
391 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
395 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
396 mlx4_set_slave_port_state(dev, slave, port,
398 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
399 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
401 mlx4_set_slave_port_state(dev, slave, port,
403 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
407 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
408 __func__, slave, port);
411 ret = mlx4_get_slave_port_state(dev, slave, port);
414 spin_unlock_irqrestore(&ctx->lock, flags);
418 EXPORT_SYMBOL(set_and_calc_slave_port_state);
420 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
424 memset(&eqe, 0, sizeof eqe);
426 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
427 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
428 eqe.event.port_mgmt_change.port = port;
429 eqe.event.port_mgmt_change.params.port_info.changed_attr =
430 cpu_to_be32((u32) attr);
432 slave_event(dev, ALL_SLAVES, &eqe);
435 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
437 void mlx4_master_handle_slave_flr(struct work_struct *work)
439 struct mlx4_mfunc_master_ctx *master =
440 container_of(work, struct mlx4_mfunc_master_ctx,
441 slave_flr_event_work);
442 struct mlx4_mfunc *mfunc =
443 container_of(master, struct mlx4_mfunc, master);
444 struct mlx4_priv *priv =
445 container_of(mfunc, struct mlx4_priv, mfunc);
446 struct mlx4_dev *dev = &priv->dev;
447 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
452 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
454 for (i = 0 ; i < dev->num_slaves; i++) {
456 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
457 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
459 /* In case of 'Reset flow' FLR can be generated for
460 * a slave before mlx4_load_one is done.
461 * make sure interface is up before trying to delete
462 * slave resources which weren't allocated yet.
464 if (dev->persist->interface_state &
465 MLX4_INTERFACE_STATE_UP)
466 mlx4_delete_all_resources_for_slave(dev, i);
467 /*return the slave to running mode*/
468 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
469 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
470 slave_state[i].is_slave_going_down = 0;
471 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
473 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
474 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
476 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
482 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
484 struct mlx4_priv *priv = mlx4_priv(dev);
485 struct mlx4_eqe *eqe;
493 u8 update_slave_state;
495 enum slave_port_gen_event gen_event;
497 struct mlx4_vport_state *s_info;
498 int eqe_size = dev->caps.eqe_size;
500 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
502 * Make sure we read EQ entry contents after we've
503 * checked the ownership bit.
508 case MLX4_EVENT_TYPE_COMP:
509 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
510 mlx4_cq_completion(dev, cqn);
513 case MLX4_EVENT_TYPE_PATH_MIG:
514 case MLX4_EVENT_TYPE_COMM_EST:
515 case MLX4_EVENT_TYPE_SQ_DRAINED:
516 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
517 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
518 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
519 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
520 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
521 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
522 if (mlx4_is_master(dev)) {
523 /* forward only to slave owning the QP */
524 ret = mlx4_get_slave_from_resource_id(dev,
526 be32_to_cpu(eqe->event.qp.qpn)
528 if (ret && ret != -ENOENT) {
529 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
530 eqe->type, eqe->subtype,
531 eq->eqn, eq->cons_index, ret);
535 if (!ret && slave != dev->caps.function) {
536 mlx4_slave_event(dev, slave, eqe);
541 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
542 0xffffff, eqe->type);
545 case MLX4_EVENT_TYPE_SRQ_LIMIT:
546 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n",
547 __func__, be32_to_cpu(eqe->event.srq.srqn),
549 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
550 if (mlx4_is_master(dev)) {
551 /* forward only to slave owning the SRQ */
552 ret = mlx4_get_slave_from_resource_id(dev,
554 be32_to_cpu(eqe->event.srq.srqn)
557 if (ret && ret != -ENOENT) {
558 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
559 eqe->type, eqe->subtype,
560 eq->eqn, eq->cons_index, ret);
564 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
565 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
567 be32_to_cpu(eqe->event.srq.srqn),
568 eqe->type, eqe->subtype);
570 if (!ret && slave != dev->caps.function) {
572 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
573 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
575 eqe->subtype, slave);
576 mlx4_slave_event(dev, slave, eqe);
580 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
581 0xffffff, eqe->type);
584 case MLX4_EVENT_TYPE_CMD:
586 be16_to_cpu(eqe->event.cmd.token),
587 eqe->event.cmd.status,
588 be64_to_cpu(eqe->event.cmd.out_param));
591 case MLX4_EVENT_TYPE_PORT_CHANGE: {
592 struct mlx4_slaves_pport slaves_port;
593 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
594 slaves_port = mlx4_phys_to_slaves_pport(dev, port);
595 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
596 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
598 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
599 if (!mlx4_is_master(dev))
601 for (i = 0; i < dev->persist->num_vfs + 1;
603 if (!test_bit(i, slaves_port.slaves))
605 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
606 if (i == mlx4_master_func_num(dev))
608 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
610 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
611 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
612 eqe->event.port_change.port =
614 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
615 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
616 mlx4_slave_event(dev, i, eqe);
618 } else { /* IB port */
619 set_and_calc_slave_port_state(dev, i, port,
620 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
622 /*we can be in pending state, then do not send port_down event*/
623 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
624 if (i == mlx4_master_func_num(dev))
626 eqe->event.port_change.port =
628 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
629 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
630 mlx4_slave_event(dev, i, eqe);
635 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
637 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
639 if (!mlx4_is_master(dev))
641 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
643 i < dev->persist->num_vfs + 1;
645 if (!test_bit(i, slaves_port.slaves))
647 if (i == mlx4_master_func_num(dev))
649 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
650 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
651 eqe->event.port_change.port =
653 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
654 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
655 mlx4_slave_event(dev, i, eqe);
659 /* port-up event will be sent to a slave when the
660 * slave's alias-guid is set. This is done in alias_GUID.c
662 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
667 case MLX4_EVENT_TYPE_CQ_ERROR:
668 mlx4_warn(dev, "CQ %s on CQN %06x\n",
669 eqe->event.cq_err.syndrome == 1 ?
670 "overrun" : "access violation",
671 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
672 if (mlx4_is_master(dev)) {
673 ret = mlx4_get_slave_from_resource_id(dev,
675 be32_to_cpu(eqe->event.cq_err.cqn)
677 if (ret && ret != -ENOENT) {
678 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
679 eqe->type, eqe->subtype,
680 eq->eqn, eq->cons_index, ret);
684 if (!ret && slave != dev->caps.function) {
685 mlx4_slave_event(dev, slave, eqe);
690 be32_to_cpu(eqe->event.cq_err.cqn)
695 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
696 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
699 case MLX4_EVENT_TYPE_OP_REQUIRED:
700 atomic_inc(&priv->opreq_count);
701 /* FW commands can't be executed from interrupt context
702 * working in deferred task
704 queue_work(mlx4_wq, &priv->opreq_task);
707 case MLX4_EVENT_TYPE_COMM_CHANNEL:
708 if (!mlx4_is_master(dev)) {
709 mlx4_warn(dev, "Received comm channel event for non master device\n");
712 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
713 eqe->event.comm_channel_arm.bit_vec,
714 sizeof eqe->event.comm_channel_arm.bit_vec);
715 queue_work(priv->mfunc.master.comm_wq,
716 &priv->mfunc.master.comm_work);
719 case MLX4_EVENT_TYPE_FLR_EVENT:
720 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
721 if (!mlx4_is_master(dev)) {
722 mlx4_warn(dev, "Non-master function received FLR event\n");
726 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
728 if (flr_slave >= dev->num_slaves) {
730 "Got FLR for unknown function: %d\n",
732 update_slave_state = 0;
734 update_slave_state = 1;
736 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
737 if (update_slave_state) {
738 priv->mfunc.master.slave_state[flr_slave].active = false;
739 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
740 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
742 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
743 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN,
745 queue_work(priv->mfunc.master.comm_wq,
746 &priv->mfunc.master.slave_flr_event_work);
749 case MLX4_EVENT_TYPE_FATAL_WARNING:
750 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
751 if (mlx4_is_master(dev))
752 for (i = 0; i < dev->num_slaves; i++) {
753 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
755 if (i == dev->caps.function)
757 mlx4_slave_event(dev, i, eqe);
759 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
760 be16_to_cpu(eqe->event.warming.warning_threshold),
761 be16_to_cpu(eqe->event.warming.current_temperature));
763 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
764 eqe->type, eqe->subtype, eq->eqn,
765 eq->cons_index, eqe->owner, eq->nent,
767 !!(eqe->owner & 0x80) ^
768 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
772 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
773 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
774 (unsigned long) eqe);
777 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT:
778 switch (eqe->subtype) {
779 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE:
780 mlx4_warn(dev, "Bad cable detected on port %u\n",
781 eqe->event.bad_cable.port);
783 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE:
784 mlx4_warn(dev, "Unsupported cable detected\n");
788 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n",
789 eqe->type, eqe->subtype, eq->eqn,
790 eq->cons_index, eqe->owner, eq->nent,
791 !!(eqe->owner & 0x80) ^
792 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
797 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
798 case MLX4_EVENT_TYPE_ECC_DETECT:
800 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
801 eqe->type, eqe->subtype, eq->eqn,
802 eq->cons_index, eqe->owner, eq->nent,
804 !!(eqe->owner & 0x80) ^
805 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
814 * The HCA will think the queue has overflowed if we
815 * don't tell it we've been processing events. We
816 * create our EQs with MLX4_NUM_SPARE_EQE extra
817 * entries, so we must update our consumer index at
820 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
828 /* cqn is 24bit wide but is initialized such that its higher bits
829 * are ones too. Thus, if we got any event, cqn's high bits should be off
830 * and we need to schedule the tasklet.
832 if (!(cqn & ~0xffffff))
833 tasklet_schedule(&eq->tasklet_ctx.task);
838 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
840 struct mlx4_dev *dev = dev_ptr;
841 struct mlx4_priv *priv = mlx4_priv(dev);
845 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
847 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
848 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
850 return IRQ_RETVAL(work);
853 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
855 struct mlx4_eq *eq = eq_ptr;
856 struct mlx4_dev *dev = eq->dev;
858 mlx4_eq_int(dev, eq);
860 /* MSI-X vectors always belong to us */
864 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
865 struct mlx4_vhcr *vhcr,
866 struct mlx4_cmd_mailbox *inbox,
867 struct mlx4_cmd_mailbox *outbox,
868 struct mlx4_cmd_info *cmd)
870 struct mlx4_priv *priv = mlx4_priv(dev);
871 struct mlx4_slave_event_eq_info *event_eq =
872 priv->mfunc.master.slave_state[slave].event_eq;
873 u32 in_modifier = vhcr->in_modifier;
874 u32 eqn = in_modifier & 0x3FF;
875 u64 in_param = vhcr->in_param;
879 if (slave == dev->caps.function)
880 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
881 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
884 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
885 if (in_param & (1LL << i))
886 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
891 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
894 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
895 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
899 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
902 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
903 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
907 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num)
909 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
910 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
913 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
916 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
917 * we need to map, take the difference of highest index and
918 * the lowest index we'll use and add 1.
920 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
921 dev->caps.reserved_eqs / 4 + 1;
924 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
926 struct mlx4_priv *priv = mlx4_priv(dev);
929 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
931 if (!priv->eq_table.uar_map[index]) {
932 priv->eq_table.uar_map[index] =
933 ioremap(pci_resource_start(dev->persist->pdev, 2) +
934 ((eq->eqn / 4) << PAGE_SHIFT),
936 if (!priv->eq_table.uar_map[index]) {
937 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
943 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
946 static void mlx4_unmap_uar(struct mlx4_dev *dev)
948 struct mlx4_priv *priv = mlx4_priv(dev);
951 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
952 if (priv->eq_table.uar_map[i]) {
953 iounmap(priv->eq_table.uar_map[i]);
954 priv->eq_table.uar_map[i] = NULL;
958 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
959 u8 intr, struct mlx4_eq *eq)
961 struct mlx4_priv *priv = mlx4_priv(dev);
962 struct mlx4_cmd_mailbox *mailbox;
963 struct mlx4_eq_context *eq_context;
965 u64 *dma_list = NULL;
972 eq->nent = roundup_pow_of_two(max(nent, 2));
973 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
974 * strides of 64B,128B and 256B.
976 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
978 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
983 for (i = 0; i < npages; ++i)
984 eq->page_list[i].buf = NULL;
986 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
990 mailbox = mlx4_alloc_cmd_mailbox(dev);
993 eq_context = mailbox->buf;
995 for (i = 0; i < npages; ++i) {
996 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
1000 if (!eq->page_list[i].buf)
1001 goto err_out_free_pages;
1004 eq->page_list[i].map = t;
1006 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
1009 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
1011 goto err_out_free_pages;
1013 eq->doorbell = mlx4_get_eq_uar(dev, eq);
1014 if (!eq->doorbell) {
1016 goto err_out_free_eq;
1019 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
1021 goto err_out_free_eq;
1023 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
1025 goto err_out_free_mtt;
1027 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
1028 MLX4_EQ_STATE_ARMED);
1029 eq_context->log_eq_size = ilog2(eq->nent);
1030 eq_context->intr = intr;
1031 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
1033 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
1034 eq_context->mtt_base_addr_h = mtt_addr >> 32;
1035 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
1037 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
1039 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
1040 goto err_out_free_mtt;
1044 mlx4_free_cmd_mailbox(dev, mailbox);
1048 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
1049 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
1050 spin_lock_init(&eq->tasklet_ctx.lock);
1051 tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb,
1052 (unsigned long)&eq->tasklet_ctx);
1057 mlx4_mtt_cleanup(dev, &eq->mtt);
1060 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1063 for (i = 0; i < npages; ++i)
1064 if (eq->page_list[i].buf)
1065 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1066 eq->page_list[i].buf,
1067 eq->page_list[i].map);
1069 mlx4_free_cmd_mailbox(dev, mailbox);
1072 kfree(eq->page_list);
1079 static void mlx4_free_eq(struct mlx4_dev *dev,
1082 struct mlx4_priv *priv = mlx4_priv(dev);
1085 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1086 * strides of 64B,128B and 256B
1088 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE;
1090 err = mlx4_HW2SW_EQ(dev, eq->eqn);
1092 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1094 synchronize_irq(eq->irq);
1095 tasklet_disable(&eq->tasklet_ctx.task);
1097 mlx4_mtt_cleanup(dev, &eq->mtt);
1098 for (i = 0; i < npages; ++i)
1099 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1100 eq->page_list[i].buf,
1101 eq->page_list[i].map);
1103 kfree(eq->page_list);
1104 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1107 static void mlx4_free_irqs(struct mlx4_dev *dev)
1109 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1112 if (eq_table->have_irq)
1113 free_irq(dev->persist->pdev->irq, dev);
1115 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1116 if (eq_table->eq[i].have_irq) {
1117 free_cpumask_var(eq_table->eq[i].affinity_mask);
1118 #if defined(CONFIG_SMP)
1119 irq_set_affinity_hint(eq_table->eq[i].irq, NULL);
1121 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1122 eq_table->eq[i].have_irq = 0;
1125 kfree(eq_table->irq_names);
1128 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1130 struct mlx4_priv *priv = mlx4_priv(dev);
1132 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev,
1133 priv->fw.clr_int_bar) +
1134 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1135 if (!priv->clr_base) {
1136 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
1143 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1145 struct mlx4_priv *priv = mlx4_priv(dev);
1147 iounmap(priv->clr_base);
1150 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1152 struct mlx4_priv *priv = mlx4_priv(dev);
1154 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1155 sizeof *priv->eq_table.eq, GFP_KERNEL);
1156 if (!priv->eq_table.eq)
1162 void mlx4_free_eq_table(struct mlx4_dev *dev)
1164 kfree(mlx4_priv(dev)->eq_table.eq);
1167 int mlx4_init_eq_table(struct mlx4_dev *dev)
1169 struct mlx4_priv *priv = mlx4_priv(dev);
1173 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1174 sizeof *priv->eq_table.uar_map,
1176 if (!priv->eq_table.uar_map) {
1181 err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1182 roundup_pow_of_two(dev->caps.num_eqs),
1183 dev->caps.num_eqs - 1,
1184 dev->caps.reserved_eqs,
1185 roundup_pow_of_two(dev->caps.num_eqs) -
1190 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1191 priv->eq_table.uar_map[i] = NULL;
1193 if (!mlx4_is_slave(dev)) {
1194 err = mlx4_map_clr_int(dev);
1196 goto err_out_bitmap;
1198 priv->eq_table.clr_mask =
1199 swab32(1 << (priv->eq_table.inta_pin & 31));
1200 priv->eq_table.clr_int = priv->clr_base +
1201 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1204 priv->eq_table.irq_names =
1205 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1),
1207 if (!priv->eq_table.irq_names) {
1209 goto err_out_clr_int;
1212 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1213 if (i == MLX4_EQ_ASYNC) {
1214 err = mlx4_create_eq(dev,
1215 MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1216 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
1218 struct mlx4_eq *eq = &priv->eq_table.eq[i];
1219 #ifdef CONFIG_RFS_ACCEL
1220 int port = find_first_bit(eq->actv_ports.ports,
1221 dev->caps.num_ports) + 1;
1223 if (port <= dev->caps.num_ports) {
1224 struct mlx4_port_info *info =
1225 &mlx4_priv(dev)->port[port];
1228 info->rmap = alloc_irq_cpu_rmap(
1229 mlx4_get_eqs_per_port(dev, port));
1231 mlx4_warn(dev, "Failed to allocate cpu rmap\n");
1237 err = irq_cpu_rmap_add(
1238 info->rmap, eq->irq);
1240 mlx4_warn(dev, "Failed adding irq rmap\n");
1243 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1244 dev->caps.reserved_cqs +
1246 (dev->flags & MLX4_FLAG_MSI_X) ?
1247 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0,
1254 if (dev->flags & MLX4_FLAG_MSI_X) {
1255 const char *eq_name;
1257 snprintf(priv->eq_table.irq_names +
1258 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE,
1260 "mlx4-async@pci:%s",
1261 pci_name(dev->persist->pdev));
1262 eq_name = priv->eq_table.irq_names +
1263 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE;
1265 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq,
1266 mlx4_msi_x_interrupt, 0, eq_name,
1267 priv->eq_table.eq + MLX4_EQ_ASYNC);
1271 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1;
1273 snprintf(priv->eq_table.irq_names,
1276 pci_name(dev->persist->pdev));
1277 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt,
1278 IRQF_SHARED, priv->eq_table.irq_names, dev);
1282 priv->eq_table.have_irq = 1;
1285 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1286 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1288 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1289 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
1292 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1);
1298 mlx4_free_eq(dev, &priv->eq_table.eq[i--]);
1299 #ifdef CONFIG_RFS_ACCEL
1300 for (i = 1; i <= dev->caps.num_ports; i++) {
1301 if (mlx4_priv(dev)->port[i].rmap) {
1302 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1303 mlx4_priv(dev)->port[i].rmap = NULL;
1307 mlx4_free_irqs(dev);
1310 if (!mlx4_is_slave(dev))
1311 mlx4_unmap_clr_int(dev);
1314 mlx4_unmap_uar(dev);
1315 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1318 kfree(priv->eq_table.uar_map);
1323 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1325 struct mlx4_priv *priv = mlx4_priv(dev);
1328 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1329 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1331 #ifdef CONFIG_RFS_ACCEL
1332 for (i = 1; i <= dev->caps.num_ports; i++) {
1333 if (mlx4_priv(dev)->port[i].rmap) {
1334 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1335 mlx4_priv(dev)->port[i].rmap = NULL;
1339 mlx4_free_irqs(dev);
1341 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1342 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1344 if (!mlx4_is_slave(dev))
1345 mlx4_unmap_clr_int(dev);
1347 mlx4_unmap_uar(dev);
1348 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1350 kfree(priv->eq_table.uar_map);
1353 /* A test that verifies that we can accept interrupts on all
1354 * the irq vectors of the device.
1355 * Interrupts are checked using the NOP command.
1357 int mlx4_test_interrupts(struct mlx4_dev *dev)
1359 struct mlx4_priv *priv = mlx4_priv(dev);
1363 err = mlx4_NOP(dev);
1364 /* When not in MSI_X, there is only one irq to check */
1365 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1368 /* A loop over all completion vectors, for each vector we will check
1369 * whether it works by mapping command completions to that vector
1370 * and performing a NOP command
1372 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1373 /* Make sure request_irq was called */
1374 if (!priv->eq_table.eq[i].have_irq)
1377 /* Temporary use polling for command completions */
1378 mlx4_cmd_use_polling(dev);
1380 /* Map the new eq to handle all asynchronous events */
1381 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1382 priv->eq_table.eq[i].eqn);
1384 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1385 mlx4_cmd_use_events(dev);
1389 /* Go back to using events */
1390 mlx4_cmd_use_events(dev);
1391 err = mlx4_NOP(dev);
1394 /* Return to default */
1395 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1396 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
1399 EXPORT_SYMBOL(mlx4_test_interrupts);
1401 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector)
1403 struct mlx4_priv *priv = mlx4_priv(dev);
1405 vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1406 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) ||
1407 (vector == MLX4_EQ_ASYNC))
1410 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports);
1412 EXPORT_SYMBOL(mlx4_is_eq_vector_valid);
1414 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port)
1416 struct mlx4_priv *priv = mlx4_priv(dev);
1418 unsigned int sum = 0;
1420 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++)
1421 sum += !!test_bit(port - 1,
1422 priv->eq_table.eq[i].actv_ports.ports);
1426 EXPORT_SYMBOL(mlx4_get_eqs_per_port);
1428 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector)
1430 struct mlx4_priv *priv = mlx4_priv(dev);
1432 vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1433 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1))
1436 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports,
1437 dev->caps.num_ports) > 1);
1439 EXPORT_SYMBOL(mlx4_is_eq_shared);
1441 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port)
1443 return mlx4_priv(dev)->port[port].rmap;
1445 EXPORT_SYMBOL(mlx4_get_cpu_rmap);
1447 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector)
1449 struct mlx4_priv *priv = mlx4_priv(dev);
1451 u32 min_ref_count_val = (u32)-1;
1452 int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector);
1453 int *prequested_vector = NULL;
1456 mutex_lock(&priv->msix_ctl.pool_lock);
1457 if (requested_vector < (dev->caps.num_comp_vectors + 1) &&
1458 (requested_vector >= 0) &&
1459 (requested_vector != MLX4_EQ_ASYNC)) {
1460 if (test_bit(port - 1,
1461 priv->eq_table.eq[requested_vector].actv_ports.ports)) {
1462 prequested_vector = &requested_vector;
1466 for (i = 1; i < port;
1467 requested_vector += mlx4_get_eqs_per_port(dev, i++))
1470 eq = &priv->eq_table.eq[requested_vector];
1471 if (requested_vector < dev->caps.num_comp_vectors + 1 &&
1472 test_bit(port - 1, eq->actv_ports.ports)) {
1473 prequested_vector = &requested_vector;
1478 if (!prequested_vector) {
1479 requested_vector = -1;
1480 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1;
1482 struct mlx4_eq *eq = &priv->eq_table.eq[i];
1484 if (min_ref_count_val > eq->ref_count &&
1485 test_bit(port - 1, eq->actv_ports.ports)) {
1486 min_ref_count_val = eq->ref_count;
1487 requested_vector = i;
1491 if (requested_vector < 0) {
1496 prequested_vector = &requested_vector;
1499 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) &&
1500 dev->flags & MLX4_FLAG_MSI_X) {
1501 set_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1502 snprintf(priv->eq_table.irq_names +
1503 *prequested_vector * MLX4_IRQNAME_SIZE,
1504 MLX4_IRQNAME_SIZE, "mlx4-%d@%s",
1505 *prequested_vector, dev_name(&dev->persist->pdev->dev));
1507 err = request_irq(priv->eq_table.eq[*prequested_vector].irq,
1508 mlx4_msi_x_interrupt, 0,
1509 &priv->eq_table.irq_names[*prequested_vector << 5],
1510 priv->eq_table.eq + *prequested_vector);
1513 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1514 *prequested_vector = -1;
1516 #if defined(CONFIG_SMP)
1517 mlx4_set_eq_affinity_hint(priv, *prequested_vector);
1519 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1);
1520 priv->eq_table.eq[*prequested_vector].have_irq = 1;
1524 if (!err && *prequested_vector >= 0)
1525 priv->eq_table.eq[*prequested_vector].ref_count++;
1528 mutex_unlock(&priv->msix_ctl.pool_lock);
1530 if (!err && *prequested_vector >= 0)
1531 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector);
1537 EXPORT_SYMBOL(mlx4_assign_eq);
1539 int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec)
1541 struct mlx4_priv *priv = mlx4_priv(dev);
1543 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq;
1545 EXPORT_SYMBOL(mlx4_eq_get_irq);
1547 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1549 struct mlx4_priv *priv = mlx4_priv(dev);
1550 int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec);
1552 mutex_lock(&priv->msix_ctl.pool_lock);
1553 priv->eq_table.eq[eq_vec].ref_count--;
1555 /* once we allocated EQ, we don't release it because it might be binded
1558 mutex_unlock(&priv->msix_ctl.pool_lock);
1560 EXPORT_SYMBOL(mlx4_release_eq);