drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/tcp.h>
  43 #include <linux/ip.h>
  44 #include <linux/ipv6.h>
  45 #include <linux/moduleparam.h>
  46
  47 #include "mlx4_en.h"
  48
  49 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  50                            struct mlx4_en_tx_ring **pring, u32 size,
  51                            u16 stride, int node, int queue_index)
  52 {
  53         struct mlx4_en_dev *mdev = priv->mdev;
  54         struct mlx4_en_tx_ring *ring;
  55         int tmp;
  56         int err;
  57
  58         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  59         if (!ring) {
  60                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  61                 if (!ring) {
  62                         en_err(priv, "Failed allocating TX ring\n");
  63                         return -ENOMEM;
  64                 }
  65         }
  66
  67         ring->size = size;
  68         ring->size_mask = size - 1;
  69         ring->sp_stride = stride;
  70         ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS;
  71
  72         tmp = size * sizeof(struct mlx4_en_tx_info);
  73         ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node);
  74         if (!ring->tx_info) {
  75                 err = -ENOMEM;
  76                 goto err_ring;
  77         }
  78
  79         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  80                  ring->tx_info, tmp);
  81
  82         ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
  83         if (!ring->bounce_buf) {
  84                 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  85                 if (!ring->bounce_buf) {
  86                         err = -ENOMEM;
  87                         goto err_info;
  88                 }
  89         }
  90         ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE);
  91
  92         /* Allocate HW buffers on provided NUMA node */
  93         set_dev_node(&mdev->dev->persist->pdev->dev, node);
  94         err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
  95         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
  96         if (err) {
  97                 en_err(priv, "Failed allocating hwq resources\n");
  98                 goto err_bounce;
  99         }
 100
 101         ring->buf = ring->sp_wqres.buf.direct.buf;
 102
 103         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 104                ring, ring->buf, ring->size, ring->buf_size,
 105                (unsigned long long) ring->sp_wqres.buf.direct.map);
 106
 107         err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
 108                                     MLX4_RESERVE_ETH_BF_QP,
 109                                     MLX4_RES_USAGE_DRIVER);
 110         if (err) {
 111                 en_err(priv, "failed reserving qp for TX ring\n");
 112                 goto err_hwq_res;
 113         }
 114
 115         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp);
 116         if (err) {
 117                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 118                 goto err_reserve;
 119         }
 120         ring->sp_qp.event = mlx4_en_sqp_event;
 121
 122         err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 123         if (err) {
 124                 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 125                 ring->bf.uar = &mdev->priv_uar;
 126                 ring->bf.uar->map = mdev->uar_map;
 127                 ring->bf_enabled = false;
 128                 ring->bf_alloced = false;
 129                 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 130         } else {
 131                 ring->bf_alloced = true;
 132                 ring->bf_enabled = !!(priv->pflags &
 133                                       MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 134         }
 135
 136         ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 137         ring->queue_index = queue_index;
 138
 139         if (queue_index < priv->num_tx_rings_p_up)
 140                 cpumask_set_cpu(cpumask_local_spread(queue_index,
 141                                                      priv->mdev->dev->numa_node),
 142                                 &ring->sp_affinity_mask);
 143
 144         *pring = ring;
 145         return 0;
 146
 147 err_reserve:
 148         mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
 149 err_hwq_res:
 150         mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 151 err_bounce:
 152         kfree(ring->bounce_buf);
 153         ring->bounce_buf = NULL;
 154 err_info:
 155         kvfree(ring->tx_info);
 156         ring->tx_info = NULL;
 157 err_ring:
 158         kfree(ring);
 159         *pring = NULL;
 160         return err;
 161 }
 162
 163 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 164                              struct mlx4_en_tx_ring **pring)
 165 {
 166         struct mlx4_en_dev *mdev = priv->mdev;
 167         struct mlx4_en_tx_ring *ring = *pring;
 168         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 169
 170         if (ring->bf_alloced)
 171                 mlx4_bf_free(mdev->dev, &ring->bf);
 172         mlx4_qp_remove(mdev->dev, &ring->sp_qp);
 173         mlx4_qp_free(mdev->dev, &ring->sp_qp);
 174         mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
 175         mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size);
 176         kfree(ring->bounce_buf);
 177         ring->bounce_buf = NULL;
 178         kvfree(ring->tx_info);
 179         ring->tx_info = NULL;
 180         kfree(ring);
 181         *pring = NULL;
 182 }
 183
 184 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 185                              struct mlx4_en_tx_ring *ring,
 186                              int cq, int user_prio)
 187 {
 188         struct mlx4_en_dev *mdev = priv->mdev;
 189         int err;
 190
 191         ring->sp_cqn = cq;
 192         ring->prod = 0;
 193         ring->cons = 0xffffffff;
 194         ring->last_nr_txbb = 1;
 195         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 196         memset(ring->buf, 0, ring->buf_size);
 197         ring->free_tx_desc = mlx4_en_free_tx_desc;
 198
 199         ring->sp_qp_state = MLX4_QP_STATE_RST;
 200         ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8);
 201         ring->mr_key = cpu_to_be32(mdev->mr.key);
 202
 203         mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn,
 204                                 ring->sp_cqn, user_prio, &ring->sp_context);
 205         if (ring->bf_alloced)
 206                 ring->sp_context.usr_page =
 207                         cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev,
 208                                                          ring->bf.uar->index));
 209
 210         err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context,
 211                                &ring->sp_qp, &ring->sp_qp_state);
 212         if (!cpumask_empty(&ring->sp_affinity_mask))
 213                 netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask,
 214                                     ring->queue_index);
 215
 216         return err;
 217 }
 218
 219 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 220                                 struct mlx4_en_tx_ring *ring)
 221 {
 222         struct mlx4_en_dev *mdev = priv->mdev;
 223
 224         mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state,
 225                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp);
 226 }
 227
 228 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring)
 229 {
 230         return ring->prod - ring->cons > ring->full_size;
 231 }
 232
 233 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 234                               struct mlx4_en_tx_ring *ring, int index,
 235                               u8 owner)
 236 {
 237         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 238         struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 239         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 240         void *end = ring->buf + ring->buf_size;
 241         __be32 *ptr = (__be32 *)tx_desc;
 242         int i;
 243
 244         /* Optimize the common case when there are no wraparounds */
 245         if (likely((void *)tx_desc +
 246                    (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
 247                 /* Stamp the freed descriptor */
 248                 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
 249                      i += STAMP_STRIDE) {
 250                         *ptr = stamp;
 251                         ptr += STAMP_DWORDS;
 252                 }
 253         } else {
 254                 /* Stamp the freed descriptor */
 255                 for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE;
 256                      i += STAMP_STRIDE) {
 257                         *ptr = stamp;
 258                         ptr += STAMP_DWORDS;
 259                         if ((void *)ptr >= end) {
 260                                 ptr = ring->buf;
 261                                 stamp ^= cpu_to_be32(0x80000000);
 262                         }
 263                 }
 264         }
 265 }
 266
 267
 268 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 269                          struct mlx4_en_tx_ring *ring,
 270                          int index, u64 timestamp,
 271                          int napi_mode)
 272 {
 273         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 274         struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 275         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 276         void *end = ring->buf + ring->buf_size;
 277         struct sk_buff *skb = tx_info->skb;
 278         int nr_maps = tx_info->nr_maps;
 279         int i;
 280
 281         /* We do not touch skb here, so prefetch skb->users location
 282          * to speedup consume_skb()
 283          */
 284         prefetchw(&skb->users);
 285
 286         if (unlikely(timestamp)) {
 287                 struct skb_shared_hwtstamps hwts;
 288
 289                 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 290                 skb_tstamp_tx(skb, &hwts);
 291         }
 292
 293         if (!tx_info->inl) {
 294                 if (tx_info->linear)
 295                         dma_unmap_single(priv->ddev,
 296                                          tx_info->map0_dma,
 297                                          tx_info->map0_byte_count,
 298                                          PCI_DMA_TODEVICE);
 299                 else
 300                         dma_unmap_page(priv->ddev,
 301                                        tx_info->map0_dma,
 302                                        tx_info->map0_byte_count,
 303                                        PCI_DMA_TODEVICE);
 304                 /* Optimize the common case when there are no wraparounds */
 305                 if (likely((void *)tx_desc +
 306                            (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) {
 307                         for (i = 1; i < nr_maps; i++) {
 308                                 data++;
 309                                 dma_unmap_page(priv->ddev,
 310                                         (dma_addr_t)be64_to_cpu(data->addr),
 311                                         be32_to_cpu(data->byte_count),
 312                                         PCI_DMA_TODEVICE);
 313                         }
 314                 } else {
 315                         if ((void *)data >= end)
 316                                 data = ring->buf + ((void *)data - end);
 317
 318                         for (i = 1; i < nr_maps; i++) {
 319                                 data++;
 320                                 /* Check for wraparound before unmapping */
 321                                 if ((void *) data >= end)
 322                                         data = ring->buf;
 323                                 dma_unmap_page(priv->ddev,
 324                                         (dma_addr_t)be64_to_cpu(data->addr),
 325                                         be32_to_cpu(data->byte_count),
 326                                         PCI_DMA_TODEVICE);
 327                         }
 328                 }
 329         }
 330         napi_consume_skb(skb, napi_mode);
 331
 332         return tx_info->nr_txbb;
 333 }
 334
 335 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
 336                             struct mlx4_en_tx_ring *ring,
 337                             int index, u64 timestamp,
 338                             int napi_mode)
 339 {
 340         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 341         struct mlx4_en_rx_alloc frame = {
 342                 .page = tx_info->page,
 343                 .dma = tx_info->map0_dma,
 344         };
 345
 346         if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) {
 347                 dma_unmap_page(priv->ddev, tx_info->map0_dma,
 348                                PAGE_SIZE, priv->dma_dir);
 349                 put_page(tx_info->page);
 350         }
 351
 352         return tx_info->nr_txbb;
 353 }
 354
 355 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 356 {
 357         struct mlx4_en_priv *priv = netdev_priv(dev);
 358         int cnt = 0;
 359
 360         /* Skip last polled descriptor */
 361         ring->cons += ring->last_nr_txbb;
 362         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 363                  ring->cons, ring->prod);
 364
 365         if ((u32) (ring->prod - ring->cons) > ring->size) {
 366                 if (netif_msg_tx_err(priv))
 367                         en_warn(priv, "Tx consumer passed producer!\n");
 368                 return 0;
 369         }
 370
 371         while (ring->cons != ring->prod) {
 372                 ring->last_nr_txbb = ring->free_tx_desc(priv, ring,
 373                                                 ring->cons & ring->size_mask,
 374                                                 0, 0 /* Non-NAPI caller */);
 375                 ring->cons += ring->last_nr_txbb;
 376                 cnt++;
 377         }
 378
 379         if (ring->tx_queue)
 380                 netdev_tx_reset_queue(ring->tx_queue);
 381
 382         if (cnt)
 383                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 384
 385         return cnt;
 386 }
 387
 388 static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe,
 389                                    u16 cqe_index, struct mlx4_en_tx_ring *ring)
 390 {
 391         struct mlx4_en_dev *mdev = priv->mdev;
 392         struct mlx4_en_tx_info *tx_info;
 393         struct mlx4_en_tx_desc *tx_desc;
 394         u16 wqe_index;
 395         int desc_size;
 396
 397         en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n",
 398                ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome);
 399         print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe),
 400                        false);
 401
 402         wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask;
 403         tx_info = &ring->tx_info[wqe_index];
 404         desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE;
 405         en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn,
 406                wqe_index, desc_size);
 407         tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE);
 408         print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false);
 409
 410         if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state))
 411                 return;
 412
 413         en_err(priv, "Scheduling port restart\n");
 414         queue_work(mdev->workqueue, &priv->restart_task);
 415 }
 416
 417 bool mlx4_en_process_tx_cq(struct net_device *dev,
 418                            struct mlx4_en_cq *cq, int napi_budget)
 419 {
 420         struct mlx4_en_priv *priv = netdev_priv(dev);
 421         struct mlx4_cq *mcq = &cq->mcq;
 422         struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring];
 423         struct mlx4_cqe *cqe;
 424         u16 index, ring_index, stamp_index;
 425         u32 txbbs_skipped = 0;
 426         u32 txbbs_stamp = 0;
 427         u32 cons_index = mcq->cons_index;
 428         int size = cq->size;
 429         u32 size_mask = ring->size_mask;
 430         struct mlx4_cqe *buf = cq->buf;
 431         u32 packets = 0;
 432         u32 bytes = 0;
 433         int factor = priv->cqe_factor;
 434         int done = 0;
 435         int budget = priv->tx_work_limit;
 436         u32 last_nr_txbb;
 437         u32 ring_cons;
 438
 439         if (unlikely(!priv->port_up))
 440                 return true;
 441
 442         netdev_txq_bql_complete_prefetchw(ring->tx_queue);
 443
 444         index = cons_index & size_mask;
 445         cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 446         last_nr_txbb = READ_ONCE(ring->last_nr_txbb);
 447         ring_cons = READ_ONCE(ring->cons);
 448         ring_index = ring_cons & size_mask;
 449         stamp_index = ring_index;
 450
 451         /* Process all completed CQEs */
 452         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 453                         cons_index & size) && (done < budget)) {
 454                 u16 new_index;
 455
 456                 /*
 457                  * make sure we read the CQE after we read the
 458                  * ownership bit
 459                  */
 460                 dma_rmb();
 461
 462                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 463                              MLX4_CQE_OPCODE_ERROR))
 464                         if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state))
 465                                 mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index,
 466                                                        ring);
 467
 468                 /* Skip over last polled CQE */
 469                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 470
 471                 do {
 472                         u64 timestamp = 0;
 473
 474                         txbbs_skipped += last_nr_txbb;
 475                         ring_index = (ring_index + last_nr_txbb) & size_mask;
 476
 477                         if (unlikely(ring->tx_info[ring_index].ts_requested))
 478                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 479
 480                         /* free next descriptor */
 481                         last_nr_txbb = ring->free_tx_desc(
 482                                         priv, ring, ring_index,
 483                                         timestamp, napi_budget);
 484
 485                         mlx4_en_stamp_wqe(priv, ring, stamp_index,
 486                                           !!((ring_cons + txbbs_stamp) &
 487                                                 ring->size));
 488                         stamp_index = ring_index;
 489                         txbbs_stamp = txbbs_skipped;
 490                         packets++;
 491                         bytes += ring->tx_info[ring_index].nr_bytes;
 492                 } while ((++done < budget) && (ring_index != new_index));
 493
 494                 ++cons_index;
 495                 index = cons_index & size_mask;
 496                 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 497         }
 498
 499         /*
 500          * To prevent CQ overflow we first update CQ consumer and only then
 501          * the ring consumer.
 502          */
 503         mcq->cons_index = cons_index;
 504         mlx4_cq_set_ci(mcq);
 505         wmb();
 506
 507         /* we want to dirty this cache line once */
 508         WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb);
 509         WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped);
 510
 511         if (cq->type == TX_XDP)
 512                 return done < budget;
 513
 514         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 515
 516         /* Wakeup Tx queue if this stopped, and ring is not full.
 517          */
 518         if (netif_tx_queue_stopped(ring->tx_queue) &&
 519             !mlx4_en_is_tx_ring_full(ring)) {
 520                 netif_tx_wake_queue(ring->tx_queue);
 521                 ring->wake_queue++;
 522         }
 523
 524         return done < budget;
 525 }
 526
 527 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 528 {
 529         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 530         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 531
 532         if (likely(priv->port_up))
 533                 napi_schedule_irqoff(&cq->napi);
 534         else
 535                 mlx4_en_arm_cq(priv, cq);
 536 }
 537
 538 /* TX CQ polling - called by NAPI */
 539 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 540 {
 541         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 542         struct net_device *dev = cq->dev;
 543         struct mlx4_en_priv *priv = netdev_priv(dev);
 544         bool clean_complete;
 545
 546         clean_complete = mlx4_en_process_tx_cq(dev, cq, budget);
 547         if (!clean_complete)
 548                 return budget;
 549
 550         napi_complete(napi);
 551         mlx4_en_arm_cq(priv, cq);
 552
 553         return 0;
 554 }
 555
 556 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 557                                                       struct mlx4_en_tx_ring *ring,
 558                                                       u32 index,
 559                                                       unsigned int desc_size)
 560 {
 561         u32 copy = (ring->size - index) << LOG_TXBB_SIZE;
 562         int i;
 563
 564         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 565                 if ((i & (TXBB_SIZE - 1)) == 0)
 566                         wmb();
 567
 568                 *((u32 *) (ring->buf + i)) =
 569                         *((u32 *) (ring->bounce_buf + copy + i));
 570         }
 571
 572         for (i = copy - 4; i >= 4 ; i -= 4) {
 573                 if ((i & (TXBB_SIZE - 1)) == 0)
 574                         wmb();
 575
 576                 *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) =
 577                         *((u32 *) (ring->bounce_buf + i));
 578         }
 579
 580         /* Return real descriptor location */
 581         return ring->buf + (index << LOG_TXBB_SIZE);
 582 }
 583
 584 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
 585  *
 586  * It seems strange we do not simply use skb_copy_bits().
 587  * This would allow to inline all skbs iff skb->len <= inline_thold
 588  *
 589  * Note that caller already checked skb was not a gso packet
 590  */
 591 static bool is_inline(int inline_thold, const struct sk_buff *skb,
 592                       const struct skb_shared_info *shinfo,
 593                       void **pfrag)
 594 {
 595         void *ptr;
 596
 597         if (skb->len > inline_thold || !inline_thold)
 598                 return false;
 599
 600         if (shinfo->nr_frags == 1) {
 601                 ptr = skb_frag_address_safe(&shinfo->frags[0]);
 602                 if (unlikely(!ptr))
 603                         return false;
 604                 *pfrag = ptr;
 605                 return true;
 606         }
 607         if (shinfo->nr_frags)
 608                 return false;
 609         return true;
 610 }
 611
 612 static int inline_size(const struct sk_buff *skb)
 613 {
 614         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 615             <= MLX4_INLINE_ALIGN)
 616                 return ALIGN(skb->len + CTRL_SIZE +
 617                              sizeof(struct mlx4_wqe_inline_seg), 16);
 618         else
 619                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 620                              sizeof(struct mlx4_wqe_inline_seg), 16);
 621 }
 622
 623 static int get_real_size(const struct sk_buff *skb,
 624                          const struct skb_shared_info *shinfo,
 625                          struct net_device *dev,
 626                          int *lso_header_size,
 627                          bool *inline_ok,
 628                          void **pfrag)
 629 {
 630         struct mlx4_en_priv *priv = netdev_priv(dev);
 631         int real_size;
 632
 633         if (shinfo->gso_size) {
 634                 *inline_ok = false;
 635                 if (skb->encapsulation)
 636                         *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
 637                 else
 638                         *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 639                 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 640                         ALIGN(*lso_header_size + 4, DS_SIZE);
 641                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 642                         /* We add a segment for the skb linear buffer only if
 643                          * it contains data */
 644                         if (*lso_header_size < skb_headlen(skb))
 645                                 real_size += DS_SIZE;
 646                         else {
 647                                 if (netif_msg_tx_err(priv))
 648                                         en_warn(priv, "Non-linear headers\n");
 649                                 return 0;
 650                         }
 651                 }
 652         } else {
 653                 *lso_header_size = 0;
 654                 *inline_ok = is_inline(priv->prof->inline_thold, skb,
 655                                        shinfo, pfrag);
 656
 657                 if (*inline_ok)
 658                         real_size = inline_size(skb);
 659                 else
 660                         real_size = CTRL_SIZE +
 661                                     (shinfo->nr_frags + 1) * DS_SIZE;
 662         }
 663
 664         return real_size;
 665 }
 666
 667 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 668                              const struct sk_buff *skb,
 669                              const struct skb_shared_info *shinfo,
 670                              void *fragptr)
 671 {
 672         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 673         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl);
 674         unsigned int hlen = skb_headlen(skb);
 675
 676         if (skb->len <= spc) {
 677                 if (likely(skb->len >= MIN_PKT_LEN)) {
 678                         inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 679                 } else {
 680                         inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 681                         memset(((void *)(inl + 1)) + skb->len, 0,
 682                                MIN_PKT_LEN - skb->len);
 683                 }
 684                 skb_copy_from_linear_data(skb, inl + 1, hlen);
 685                 if (shinfo->nr_frags)
 686                         memcpy(((void *)(inl + 1)) + hlen, fragptr,
 687                                skb_frag_size(&shinfo->frags[0]));
 688
 689         } else {
 690                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 691                 if (hlen <= spc) {
 692                         skb_copy_from_linear_data(skb, inl + 1, hlen);
 693                         if (hlen < spc) {
 694                                 memcpy(((void *)(inl + 1)) + hlen,
 695                                        fragptr, spc - hlen);
 696                                 fragptr +=  spc - hlen;
 697                         }
 698                         inl = (void *) (inl + 1) + spc;
 699                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 700                 } else {
 701                         skb_copy_from_linear_data(skb, inl + 1, spc);
 702                         inl = (void *) (inl + 1) + spc;
 703                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 704                                                          hlen - spc);
 705                         if (shinfo->nr_frags)
 706                                 memcpy(((void *)(inl + 1)) + hlen - spc,
 707                                        fragptr,
 708                                        skb_frag_size(&shinfo->frags[0]));
 709                 }
 710
 711                 dma_wmb();
 712                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 713         }
 714 }
 715
 716 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 717                          struct net_device *sb_dev,
 718                          select_queue_fallback_t fallback)
 719 {
 720         struct mlx4_en_priv *priv = netdev_priv(dev);
 721         u16 rings_p_up = priv->num_tx_rings_p_up;
 722
 723         if (netdev_get_num_tc(dev))
 724                 return fallback(dev, skb, NULL);
 725
 726         return fallback(dev, skb, NULL) % rings_p_up;
 727 }
 728
 729 static void mlx4_bf_copy(void __iomem *dst, const void *src,
 730                          unsigned int bytecnt)
 731 {
 732         __iowrite64_copy(dst, src, bytecnt / 8);
 733 }
 734
 735 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring)
 736 {
 737         wmb();
 738         /* Since there is no iowrite*_native() that writes the
 739          * value as is, without byteswapping - using the one
 740          * the doesn't do byteswapping in the relevant arch
 741          * endianness.
 742          */
 743 #if defined(__LITTLE_ENDIAN)
 744         iowrite32(
 745 #else
 746         iowrite32be(
 747 #endif
 748                   (__force u32)ring->doorbell_qpn,
 749                   ring->bf.uar->map + MLX4_SEND_DOORBELL);
 750 }
 751
 752 static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring,
 753                                   struct mlx4_en_tx_desc *tx_desc,
 754                                   union mlx4_wqe_qpn_vlan qpn_vlan,
 755                                   int desc_size, int bf_index,
 756                                   __be32 op_own, bool bf_ok,
 757                                   bool send_doorbell)
 758 {
 759         tx_desc->ctrl.qpn_vlan = qpn_vlan;
 760
 761         if (bf_ok) {
 762                 op_own |= htonl((bf_index & 0xffff) << 8);
 763                 /* Ensure new descriptor hits memory
 764                  * before setting ownership of this descriptor to HW
 765                  */
 766                 dma_wmb();
 767                 tx_desc->ctrl.owner_opcode = op_own;
 768
 769                 wmb();
 770
 771                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 772                              desc_size);
 773
 774                 wmb();
 775
 776                 ring->bf.offset ^= ring->bf.buf_size;
 777         } else {
 778                 /* Ensure new descriptor hits memory
 779                  * before setting ownership of this descriptor to HW
 780                  */
 781                 dma_wmb();
 782                 tx_desc->ctrl.owner_opcode = op_own;
 783                 if (send_doorbell)
 784                         mlx4_en_xmit_doorbell(ring);
 785                 else
 786                         ring->xmit_more++;
 787         }
 788 }
 789
 790 static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv,
 791                                   struct skb_shared_info *shinfo,
 792                                   struct mlx4_wqe_data_seg *data,
 793                                   struct sk_buff *skb,
 794                                   int lso_header_size,
 795                                   __be32 mr_key,
 796                                   struct mlx4_en_tx_info *tx_info)
 797 {
 798         struct device *ddev = priv->ddev;
 799         dma_addr_t dma = 0;
 800         u32 byte_count = 0;
 801         int i_frag;
 802
 803         /* Map fragments if any */
 804         for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 805                 const struct skb_frag_struct *frag;
 806
 807                 frag = &shinfo->frags[i_frag];
 808                 byte_count = skb_frag_size(frag);
 809                 dma = skb_frag_dma_map(ddev, frag,
 810                                        0, byte_count,
 811                                        DMA_TO_DEVICE);
 812                 if (dma_mapping_error(ddev, dma))
 813                         goto tx_drop_unmap;
 814
 815                 data->addr = cpu_to_be64(dma);
 816                 data->lkey = mr_key;
 817                 dma_wmb();
 818                 data->byte_count = cpu_to_be32(byte_count);
 819                 --data;
 820         }
 821
 822         /* Map linear part if needed */
 823         if (tx_info->linear) {
 824                 byte_count = skb_headlen(skb) - lso_header_size;
 825
 826                 dma = dma_map_single(ddev, skb->data +
 827                                      lso_header_size, byte_count,
 828                                      PCI_DMA_TODEVICE);
 829                 if (dma_mapping_error(ddev, dma))
 830                         goto tx_drop_unmap;
 831
 832                 data->addr = cpu_to_be64(dma);
 833                 data->lkey = mr_key;
 834                 dma_wmb();
 835                 data->byte_count = cpu_to_be32(byte_count);
 836         }
 837         /* tx completion can avoid cache line miss for common cases */
 838         tx_info->map0_dma = dma;
 839         tx_info->map0_byte_count = byte_count;
 840
 841         return true;
 842
 843 tx_drop_unmap:
 844         en_err(priv, "DMA mapping error\n");
 845
 846         while (++i_frag < shinfo->nr_frags) {
 847                 ++data;
 848                 dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr),
 849                                be32_to_cpu(data->byte_count),
 850                                PCI_DMA_TODEVICE);
 851         }
 852
 853         return false;
 854 }
 855
 856 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 857 {
 858         struct skb_shared_info *shinfo = skb_shinfo(skb);
 859         struct mlx4_en_priv *priv = netdev_priv(dev);
 860         union mlx4_wqe_qpn_vlan qpn_vlan = {};
 861         struct mlx4_en_tx_ring *ring;
 862         struct mlx4_en_tx_desc *tx_desc;
 863         struct mlx4_wqe_data_seg *data;
 864         struct mlx4_en_tx_info *tx_info;
 865         u32 __maybe_unused ring_cons;
 866         int tx_ind;
 867         int nr_txbb;
 868         int desc_size;
 869         int real_size;
 870         u32 index, bf_index;
 871         __be32 op_own;
 872         int lso_header_size;
 873         void *fragptr = NULL;
 874         bool bounce = false;
 875         bool send_doorbell;
 876         bool stop_queue;
 877         bool inline_ok;
 878         u8 data_offset;
 879         bool bf_ok;
 880
 881         tx_ind = skb_get_queue_mapping(skb);
 882         ring = priv->tx_ring[TX][tx_ind];
 883
 884         if (unlikely(!priv->port_up))
 885                 goto tx_drop;
 886
 887         /* fetch ring->cons far ahead before needing it to avoid stall */
 888         ring_cons = READ_ONCE(ring->cons);
 889
 890         real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
 891                                   &inline_ok, &fragptr);
 892         if (unlikely(!real_size))
 893                 goto tx_drop_count;
 894
 895         /* Align descriptor to TXBB size */
 896         desc_size = ALIGN(real_size, TXBB_SIZE);
 897         nr_txbb = desc_size >> LOG_TXBB_SIZE;
 898         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 899                 if (netif_msg_tx_err(priv))
 900                         en_warn(priv, "Oversized header or SG list\n");
 901                 goto tx_drop_count;
 902         }
 903
 904         bf_ok = ring->bf_enabled;
 905         if (skb_vlan_tag_present(skb)) {
 906                 u16 vlan_proto;
 907
 908                 qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb));
 909                 vlan_proto = be16_to_cpu(skb->vlan_proto);
 910                 if (vlan_proto == ETH_P_8021AD)
 911                         qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN;
 912                 else if (vlan_proto == ETH_P_8021Q)
 913                         qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
 914                 else
 915                         qpn_vlan.ins_vlan = 0;
 916                 bf_ok = false;
 917         }
 918
 919         netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
 920
 921         /* Track current inflight packets for performance analysis */
 922         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 923                          (u32)(ring->prod - ring_cons - 1));
 924
 925         /* Packet is good - grab an index and transmit it */
 926         index = ring->prod & ring->size_mask;
 927         bf_index = ring->prod;
 928
 929         /* See if we have enough space for whole descriptor TXBB for setting
 930          * SW ownership on next descriptor; if not, use a bounce buffer. */
 931         if (likely(index + nr_txbb <= ring->size))
 932                 tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
 933         else {
 934                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 935                 bounce = true;
 936                 bf_ok = false;
 937         }
 938
 939         /* Save skb in tx_info ring */
 940         tx_info = &ring->tx_info[index];
 941         tx_info->skb = skb;
 942         tx_info->nr_txbb = nr_txbb;
 943
 944         if (!lso_header_size) {
 945                 data = &tx_desc->data;
 946                 data_offset = offsetof(struct mlx4_en_tx_desc, data);
 947         } else {
 948                 int lso_align = ALIGN(lso_header_size + 4, DS_SIZE);
 949
 950                 data = (void *)&tx_desc->lso + lso_align;
 951                 data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align;
 952         }
 953
 954         /* valid only for none inline segments */
 955         tx_info->data_offset = data_offset;
 956
 957         tx_info->inl = inline_ok;
 958
 959         tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok;
 960
 961         tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 962         data += tx_info->nr_maps - 1;
 963
 964         if (!tx_info->inl)
 965                 if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb,
 966                                            lso_header_size, ring->mr_key,
 967                                            tx_info))
 968                         goto tx_drop_count;
 969
 970         /*
 971          * For timestamping add flag to skb_shinfo and
 972          * set flag for further reference
 973          */
 974         tx_info->ts_requested = 0;
 975         if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 976                      shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 977                 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 978                 tx_info->ts_requested = 1;
 979         }
 980
 981         /* Prepare ctrl segement apart opcode+ownership, which depends on
 982          * whether LSO is used */
 983         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 984         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 985                 if (!skb->encapsulation)
 986                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 987                                                                  MLX4_WQE_CTRL_TCP_UDP_CSUM);
 988                 else
 989                         tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
 990                 ring->tx_csum++;
 991         }
 992
 993         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
 994                 struct ethhdr *ethh;
 995
 996                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 997                  * so that VFs and PF can communicate with each other
 998                  */
 999                 ethh = (struct ethhdr *)skb->data;
1000                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
1001                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
1002         }
1003
1004         /* Handle LSO (TSO) packets */
1005         if (lso_header_size) {
1006                 int i;
1007
1008                 /* Mark opcode as LSO */
1009                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
1010                         ((ring->prod & ring->size) ?
1011                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1012
1013                 /* Fill in the LSO prefix */
1014                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
1015                         shinfo->gso_size << 16 | lso_header_size);
1016
1017                 /* Copy headers;
1018                  * note that we already verified that it is linear */
1019                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
1020
1021                 ring->tso_packets++;
1022
1023                 i = shinfo->gso_segs;
1024                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
1025                 ring->packets += i;
1026         } else {
1027                 /* Normal (Non LSO) packet */
1028                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1029                         ((ring->prod & ring->size) ?
1030                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1031                 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
1032                 ring->packets++;
1033         }
1034         ring->bytes += tx_info->nr_bytes;
1035         netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
1036         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
1037
1038         if (tx_info->inl)
1039                 build_inline_wqe(tx_desc, skb, shinfo, fragptr);
1040
1041         if (skb->encapsulation) {
1042                 union {
1043                         struct iphdr *v4;
1044                         struct ipv6hdr *v6;
1045                         unsigned char *hdr;
1046                 } ip;
1047                 u8 proto;
1048
1049                 ip.hdr = skb_inner_network_header(skb);
1050                 proto = (ip.v4->version == 4) ? ip.v4->protocol :
1051                                                 ip.v6->nexthdr;
1052
1053                 if (proto == IPPROTO_TCP || proto == IPPROTO_UDP)
1054                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
1055                 else
1056                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
1057         }
1058
1059         ring->prod += nr_txbb;
1060
1061         /* If we used a bounce buffer then copy descriptor back into place */
1062         if (unlikely(bounce))
1063                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
1064
1065         skb_tx_timestamp(skb);
1066
1067         /* Check available TXBBs And 2K spare for prefetch */
1068         stop_queue = mlx4_en_is_tx_ring_full(ring);
1069         if (unlikely(stop_queue)) {
1070                 netif_tx_stop_queue(ring->tx_queue);
1071                 ring->queue_stopped++;
1072         }
1073         send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
1074
1075         real_size = (real_size / 16) & 0x3f;
1076
1077         bf_ok &= desc_size <= MAX_BF && send_doorbell;
1078
1079         if (bf_ok)
1080                 qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size);
1081         else
1082                 qpn_vlan.fence_size = real_size;
1083
1084         mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index,
1085                               op_own, bf_ok, send_doorbell);
1086
1087         if (unlikely(stop_queue)) {
1088                 /* If queue was emptied after the if (stop_queue) , and before
1089                  * the netif_tx_stop_queue() - need to wake the queue,
1090                  * or else it will remain stopped forever.
1091                  * Need a memory barrier to make sure ring->cons was not
1092                  * updated before queue was stopped.
1093                  */
1094                 smp_rmb();
1095
1096                 ring_cons = READ_ONCE(ring->cons);
1097                 if (unlikely(!mlx4_en_is_tx_ring_full(ring))) {
1098                         netif_tx_wake_queue(ring->tx_queue);
1099                         ring->wake_queue++;
1100                 }
1101         }
1102         return NETDEV_TX_OK;
1103
1104 tx_drop_count:
1105         ring->tx_dropped++;
1106 tx_drop:
1107         dev_kfree_skb_any(skb);
1108         return NETDEV_TX_OK;
1109 }
1110
1111 #define MLX4_EN_XDP_TX_NRTXBB  1
1112 #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \
1113                                  / 16) & 0x3f)
1114
1115 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
1116                                     struct mlx4_en_tx_ring *ring)
1117 {
1118         int i;
1119
1120         for (i = 0; i < ring->size; i++) {
1121                 struct mlx4_en_tx_info *tx_info = &ring->tx_info[i];
1122                 struct mlx4_en_tx_desc *tx_desc = ring->buf +
1123                         (i << LOG_TXBB_SIZE);
1124
1125                 tx_info->map0_byte_count = PAGE_SIZE;
1126                 tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB;
1127                 tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data);
1128                 tx_info->ts_requested = 0;
1129                 tx_info->nr_maps = 1;
1130                 tx_info->linear = 1;
1131                 tx_info->inl = 0;
1132
1133                 tx_desc->data.lkey = ring->mr_key;
1134                 tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ;
1135                 tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
1136         }
1137 }
1138
1139 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
1140                                struct mlx4_en_rx_alloc *frame,
1141                                struct mlx4_en_priv *priv, unsigned int length,
1142                                int tx_ind, bool *doorbell_pending)
1143 {
1144         struct mlx4_en_tx_desc *tx_desc;
1145         struct mlx4_en_tx_info *tx_info;
1146         struct mlx4_wqe_data_seg *data;
1147         struct mlx4_en_tx_ring *ring;
1148         dma_addr_t dma;
1149         __be32 op_own;
1150         int index;
1151
1152         if (unlikely(!priv->port_up))
1153                 goto tx_drop;
1154
1155         ring = priv->tx_ring[TX_XDP][tx_ind];
1156
1157         if (unlikely(mlx4_en_is_tx_ring_full(ring)))
1158                 goto tx_drop_count;
1159
1160         index = ring->prod & ring->size_mask;
1161         tx_info = &ring->tx_info[index];
1162
1163         /* Track current inflight packets for performance analysis */
1164         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
1165                          (u32)(ring->prod - READ_ONCE(ring->cons) - 1));
1166
1167         tx_desc = ring->buf + (index << LOG_TXBB_SIZE);
1168         data = &tx_desc->data;
1169
1170         dma = frame->dma;
1171
1172         tx_info->page = frame->page;
1173         frame->page = NULL;
1174         tx_info->map0_dma = dma;
1175         tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN);
1176
1177         dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset,
1178                                          length, PCI_DMA_TODEVICE);
1179
1180         data->addr = cpu_to_be64(dma + frame->page_offset);
1181         dma_wmb();
1182         data->byte_count = cpu_to_be32(length);
1183
1184         /* tx completion can avoid cache line miss for common cases */
1185
1186         op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
1187                 ((ring->prod & ring->size) ?
1188                  cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
1189
1190         rx_ring->xdp_tx++;
1191         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length);
1192
1193         ring->prod += MLX4_EN_XDP_TX_NRTXBB;
1194
1195         /* Ensure new descriptor hits memory
1196          * before setting ownership of this descriptor to HW
1197          */
1198         dma_wmb();
1199         tx_desc->ctrl.owner_opcode = op_own;
1200         ring->xmit_more++;
1201
1202         *doorbell_pending = true;
1203
1204         return NETDEV_TX_OK;
1205
1206 tx_drop_count:
1207         rx_ring->xdp_tx_full++;
1208         *doorbell_pending = true;
1209 tx_drop:
1210         return NETDEV_TX_BUSY;
1211 }