2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/rculist.h>
40 #include <linux/if_ether.h>
41 #include <linux/if_vlan.h>
42 #include <linux/vmalloc.h>
43 #include <linux/irq.h>
45 #if IS_ENABLED(CONFIG_IPV6)
46 #include <net/ip6_checksum.h>
51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
52 struct mlx4_en_rx_alloc *page_alloc,
53 const struct mlx4_en_frag_info *frag_info,
60 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
64 gfp |= __GFP_COMP | __GFP_NOWARN;
65 page = alloc_pages(gfp, order);
69 ((PAGE_SIZE << order) < frag_info->frag_size))
72 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
74 if (dma_mapping_error(priv->ddev, dma)) {
78 page_alloc->page_size = PAGE_SIZE << order;
79 page_alloc->page = page;
80 page_alloc->dma = dma;
81 page_alloc->page_offset = 0;
82 /* Not doing get_page() for each frag is a big win
83 * on asymetric workloads. Note we can not use atomic_set().
85 atomic_add(page_alloc->page_size / frag_info->frag_stride - 1,
90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
91 struct mlx4_en_rx_desc *rx_desc,
92 struct mlx4_en_rx_alloc *frags,
93 struct mlx4_en_rx_alloc *ring_alloc,
96 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
97 const struct mlx4_en_frag_info *frag_info;
102 for (i = 0; i < priv->num_frags; i++) {
103 frag_info = &priv->frag_info[i];
104 page_alloc[i] = ring_alloc[i];
105 page_alloc[i].page_offset += frag_info->frag_stride;
107 if (page_alloc[i].page_offset + frag_info->frag_stride <=
108 ring_alloc[i].page_size)
111 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
115 for (i = 0; i < priv->num_frags; i++) {
116 frags[i] = ring_alloc[i];
117 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
118 ring_alloc[i] = page_alloc[i];
119 rx_desc->data[i].addr = cpu_to_be64(dma);
126 if (page_alloc[i].page != ring_alloc[i].page) {
127 dma_unmap_page(priv->ddev, page_alloc[i].dma,
128 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
129 page = page_alloc[i].page;
130 atomic_set(&page->_count, 1);
137 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
138 struct mlx4_en_rx_alloc *frags,
141 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
142 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
145 if (next_frag_end > frags[i].page_size)
146 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
150 put_page(frags[i].page);
153 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
154 struct mlx4_en_rx_ring *ring)
157 struct mlx4_en_rx_alloc *page_alloc;
159 for (i = 0; i < priv->num_frags; i++) {
160 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
162 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
163 frag_info, GFP_KERNEL | __GFP_COLD))
166 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n",
167 i, ring->page_alloc[i].page_size,
168 atomic_read(&ring->page_alloc[i].page->_count));
176 page_alloc = &ring->page_alloc[i];
177 dma_unmap_page(priv->ddev, page_alloc->dma,
178 page_alloc->page_size, PCI_DMA_FROMDEVICE);
179 page = page_alloc->page;
180 atomic_set(&page->_count, 1);
182 page_alloc->page = NULL;
187 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
188 struct mlx4_en_rx_ring *ring)
190 struct mlx4_en_rx_alloc *page_alloc;
193 for (i = 0; i < priv->num_frags; i++) {
194 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
196 page_alloc = &ring->page_alloc[i];
197 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
198 i, page_count(page_alloc->page));
200 dma_unmap_page(priv->ddev, page_alloc->dma,
201 page_alloc->page_size, PCI_DMA_FROMDEVICE);
202 while (page_alloc->page_offset + frag_info->frag_stride <
203 page_alloc->page_size) {
204 put_page(page_alloc->page);
205 page_alloc->page_offset += frag_info->frag_stride;
207 page_alloc->page = NULL;
211 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
212 struct mlx4_en_rx_ring *ring, int index)
214 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
218 /* Set size and memtype fields */
219 for (i = 0; i < priv->num_frags; i++) {
220 rx_desc->data[i].byte_count =
221 cpu_to_be32(priv->frag_info[i].frag_size);
222 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
225 /* If the number of used fragments does not fill up the ring stride,
226 * remaining (unused) fragments must be padded with null address/size
227 * and a special memory key */
228 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
229 for (i = priv->num_frags; i < possible_frags; i++) {
230 rx_desc->data[i].byte_count = 0;
231 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
232 rx_desc->data[i].addr = 0;
236 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
237 struct mlx4_en_rx_ring *ring, int index,
240 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
241 struct mlx4_en_rx_alloc *frags = ring->rx_info +
242 (index << priv->log_rx_info);
244 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
247 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
249 return ring->prod == ring->cons;
252 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
254 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
257 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
258 struct mlx4_en_rx_ring *ring,
261 struct mlx4_en_rx_alloc *frags;
264 frags = ring->rx_info + (index << priv->log_rx_info);
265 for (nr = 0; nr < priv->num_frags; nr++) {
266 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
267 mlx4_en_free_frag(priv, frags, nr);
271 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
273 struct mlx4_en_rx_ring *ring;
278 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
279 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
280 ring = priv->rx_ring[ring_ind];
282 if (mlx4_en_prepare_rx_desc(priv, ring,
284 GFP_KERNEL | __GFP_COLD)) {
285 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
286 en_err(priv, "Failed to allocate enough rx buffers\n");
289 new_size = rounddown_pow_of_two(ring->actual_size);
290 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
291 ring->actual_size, new_size);
302 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
303 ring = priv->rx_ring[ring_ind];
304 while (ring->actual_size > new_size) {
307 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
314 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
315 struct mlx4_en_rx_ring *ring)
319 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
320 ring->cons, ring->prod);
322 /* Unmap and free Rx buffers */
323 while (!mlx4_en_is_ring_empty(ring)) {
324 index = ring->cons & ring->size_mask;
325 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
326 mlx4_en_free_rx_desc(priv, ring, index);
331 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
336 struct mlx4_dev *dev = mdev->dev;
338 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
339 num_of_eqs = max_t(int, MIN_RX_RINGS,
341 mlx4_get_eqs_per_port(mdev->dev, i),
344 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
345 min_t(int, num_of_eqs,
346 netif_get_num_default_rss_queues());
347 mdev->profile.prof[i].rx_ring_num =
348 rounddown_pow_of_two(num_rx_rings);
352 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
353 struct mlx4_en_rx_ring **pring,
354 u32 size, u16 stride, int node)
356 struct mlx4_en_dev *mdev = priv->mdev;
357 struct mlx4_en_rx_ring *ring;
361 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
363 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
365 en_err(priv, "Failed to allocate RX ring structure\n");
373 ring->size_mask = size - 1;
374 ring->stride = stride;
375 ring->log_stride = ffs(ring->stride) - 1;
376 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
378 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
379 sizeof(struct mlx4_en_rx_alloc));
380 ring->rx_info = vmalloc_node(tmp, node);
381 if (!ring->rx_info) {
382 ring->rx_info = vmalloc(tmp);
383 if (!ring->rx_info) {
389 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
392 /* Allocate HW buffers on provided NUMA node */
393 set_dev_node(&mdev->dev->persist->pdev->dev, node);
394 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
395 ring->buf_size, 2 * PAGE_SIZE);
396 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
400 err = mlx4_en_map_buffer(&ring->wqres.buf);
402 en_err(priv, "Failed to map RX buffer\n");
405 ring->buf = ring->wqres.buf.direct.buf;
407 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
413 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
415 vfree(ring->rx_info);
416 ring->rx_info = NULL;
424 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
426 struct mlx4_en_rx_ring *ring;
430 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
431 DS_SIZE * priv->num_frags);
433 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
434 ring = priv->rx_ring[ring_ind];
438 ring->actual_size = 0;
439 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
441 ring->stride = stride;
442 if (ring->stride <= TXBB_SIZE) {
443 /* Stamp first unused send wqe */
444 __be32 *ptr = (__be32 *)ring->buf;
445 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
447 /* Move pointer to start of rx section */
448 ring->buf += TXBB_SIZE;
451 ring->log_stride = ffs(ring->stride) - 1;
452 ring->buf_size = ring->size * ring->stride;
454 memset(ring->buf, 0, ring->buf_size);
455 mlx4_en_update_rx_prod_db(ring);
457 /* Initialize all descriptors */
458 for (i = 0; i < ring->size; i++)
459 mlx4_en_init_rx_desc(priv, ring, i);
461 /* Initialize page allocators */
462 err = mlx4_en_init_allocator(priv, ring);
464 en_err(priv, "Failed initializing ring allocator\n");
465 if (ring->stride <= TXBB_SIZE)
466 ring->buf -= TXBB_SIZE;
471 err = mlx4_en_fill_rx_buffers(priv);
475 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
476 ring = priv->rx_ring[ring_ind];
478 ring->size_mask = ring->actual_size - 1;
479 mlx4_en_update_rx_prod_db(ring);
485 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
486 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
488 ring_ind = priv->rx_ring_num - 1;
490 while (ring_ind >= 0) {
491 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
492 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
493 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
499 /* We recover from out of memory by scheduling our napi poll
500 * function (mlx4_en_process_cq), which tries to allocate
501 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
503 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
510 for (ring = 0; ring < priv->rx_ring_num; ring++) {
511 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
513 napi_reschedule(&priv->rx_cq[ring]->napi);
519 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
520 struct mlx4_en_rx_ring **pring,
521 u32 size, u16 stride)
523 struct mlx4_en_dev *mdev = priv->mdev;
524 struct mlx4_en_rx_ring *ring = *pring;
526 mlx4_en_unmap_buffer(&ring->wqres.buf);
527 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
528 vfree(ring->rx_info);
529 ring->rx_info = NULL;
532 #ifdef CONFIG_RFS_ACCEL
533 mlx4_en_cleanup_filters(priv);
537 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
538 struct mlx4_en_rx_ring *ring)
540 mlx4_en_free_rx_buf(priv, ring);
541 if (ring->stride <= TXBB_SIZE)
542 ring->buf -= TXBB_SIZE;
543 mlx4_en_destroy_allocator(priv, ring);
547 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
548 struct mlx4_en_rx_desc *rx_desc,
549 struct mlx4_en_rx_alloc *frags,
553 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
554 struct mlx4_en_frag_info *frag_info;
558 /* Collect used fragments while replacing them in the HW descriptors */
559 for (nr = 0; nr < priv->num_frags; nr++) {
560 frag_info = &priv->frag_info[nr];
561 if (length <= frag_info->frag_prefix_size)
566 dma = be64_to_cpu(rx_desc->data[nr].addr);
567 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
570 /* Save page reference in skb */
571 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
572 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
573 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
574 skb->truesize += frag_info->frag_stride;
575 frags[nr].page = NULL;
577 /* Adjust size of last fragment to match actual length */
579 skb_frag_size_set(&skb_frags_rx[nr - 1],
580 length - priv->frag_info[nr - 1].frag_prefix_size);
586 __skb_frag_unref(&skb_frags_rx[nr]);
592 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
593 struct mlx4_en_rx_desc *rx_desc,
594 struct mlx4_en_rx_alloc *frags,
602 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
604 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
607 skb_reserve(skb, NET_IP_ALIGN);
610 /* Get pointer to first fragment so we could copy the headers into the
611 * (linear part of the) skb */
612 va = page_address(frags[0].page) + frags[0].page_offset;
614 if (length <= SMALL_PACKET_SIZE) {
615 /* We are copying all relevant data to the skb - temporarily
616 * sync buffers for the copy */
617 dma = be64_to_cpu(rx_desc->data[0].addr);
618 dma_sync_single_for_cpu(priv->ddev, dma, length,
620 skb_copy_to_linear_data(skb, va, length);
623 unsigned int pull_len;
625 /* Move relevant fragments to skb */
626 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
628 if (unlikely(!used_frags)) {
632 skb_shinfo(skb)->nr_frags = used_frags;
634 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
635 /* Copy headers into the skb linear buffer */
636 memcpy(skb->data, va, pull_len);
637 skb->tail += pull_len;
639 /* Skip headers in first fragment */
640 skb_shinfo(skb)->frags[0].page_offset += pull_len;
642 /* Adjust size of first fragment */
643 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
644 skb->data_len = length - pull_len;
649 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
652 int offset = ETH_HLEN;
654 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
655 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
659 priv->loopback_ok = 1;
662 dev_kfree_skb_any(skb);
665 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
666 struct mlx4_en_rx_ring *ring)
668 int index = ring->prod & ring->size_mask;
670 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
671 if (mlx4_en_prepare_rx_desc(priv, ring, index,
672 GFP_ATOMIC | __GFP_COLD))
675 index = ring->prod & ring->size_mask;
679 /* When hardware doesn't strip the vlan, we need to calculate the checksum
680 * over it and add it to the hardware's checksum calculation
682 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
683 struct vlan_hdr *vlanh)
685 return csum_add(hw_checksum, *(__wsum *)vlanh);
688 /* Although the stack expects checksum which doesn't include the pseudo
689 * header, the HW adds it. To address that, we are subtracting the pseudo
690 * header checksum from the checksum value provided by the HW.
692 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
695 __u16 length_for_csum = 0;
696 __wsum csum_pseudo_header = 0;
698 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
699 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
700 length_for_csum, iph->protocol, 0);
701 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
704 #if IS_ENABLED(CONFIG_IPV6)
705 /* In IPv6 packets, besides subtracting the pseudo header checksum,
706 * we also compute/add the IP header checksum which
707 * is not added by the HW.
709 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
710 struct ipv6hdr *ipv6h)
712 __wsum csum_pseudo_hdr = 0;
714 if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
716 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
718 csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
719 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
720 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
721 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
723 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
724 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
729 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
731 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
732 netdev_features_t dev_features)
734 __wsum hw_checksum = 0;
737 /* CQE csum doesn't cover padding octets in short ethernet
738 * frames. And the pad field is appended prior to calculating
739 * and appending the FCS field.
741 * Detecting these padded frames requires to verify and parse
742 * IP headers, so we simply force all those small frames to skip
745 if (short_frame(skb->len))
748 hdr = (u8 *)va + sizeof(struct ethhdr);
749 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
751 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
752 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
753 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
754 hdr += sizeof(struct vlan_hdr);
757 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
758 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
759 #if IS_ENABLED(CONFIG_IPV6)
760 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
761 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
767 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
769 struct mlx4_en_priv *priv = netdev_priv(dev);
770 struct mlx4_en_dev *mdev = priv->mdev;
771 struct mlx4_cqe *cqe;
772 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
773 struct mlx4_en_rx_alloc *frags;
774 struct mlx4_en_rx_desc *rx_desc;
781 int factor = priv->cqe_factor;
791 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
792 * descriptor offset can be deduced from the CQE index instead of
793 * reading 'cqe->index' */
794 index = cq->mcq.cons_index & ring->size_mask;
795 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
797 /* Process all completed CQEs */
798 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
799 cq->mcq.cons_index & cq->size)) {
801 frags = ring->rx_info + (index << priv->log_rx_info);
802 rx_desc = ring->buf + (index << ring->log_stride);
805 * make sure we read the CQE after we read the ownership bit
809 /* Drop packet on bad receive or bad checksum */
810 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
811 MLX4_CQE_OPCODE_ERROR)) {
812 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
813 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
814 ((struct mlx4_err_cqe *)cqe)->syndrome);
817 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
818 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
822 /* Check if we need to drop the packet if SRIOV is not enabled
823 * and not performing the selftest or flb disabled
825 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
828 /* Get pointer to first fragment since we haven't
829 * skb yet and cast it to ethhdr struct
831 dma = be64_to_cpu(rx_desc->data[0].addr);
832 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
834 ethh = (struct ethhdr *)(page_address(frags[0].page) +
835 frags[0].page_offset);
837 if (is_multicast_ether_addr(ethh->h_dest)) {
838 struct mlx4_mac_entry *entry;
839 struct hlist_head *bucket;
840 unsigned int mac_hash;
842 /* Drop the packet, since HW loopback-ed it */
843 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
844 bucket = &priv->mac_hash[mac_hash];
846 hlist_for_each_entry_rcu(entry, bucket, hlist) {
847 if (ether_addr_equal_64bits(entry->mac,
858 * Packet is OK - process it.
860 length = be32_to_cpu(cqe->byte_cnt);
861 length -= ring->fcs_del;
862 ring->bytes += length;
864 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
865 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
867 if (likely(dev->features & NETIF_F_RXCSUM)) {
868 /* TODO: For IP non TCP/UDP packets when csum complete is
869 * not an option (not supported or any other reason) we can
870 * actually check cqe IPOK status bit and report
871 * CHECKSUM_UNNECESSARY rather than CHECKSUM_NONE
873 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
874 MLX4_CQE_STATUS_UDP)) {
875 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
876 cqe->checksum == cpu_to_be16(0xffff)) {
877 ip_summed = CHECKSUM_UNNECESSARY;
880 ip_summed = CHECKSUM_NONE;
884 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
885 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
886 MLX4_CQE_STATUS_IPV6))) {
887 ip_summed = CHECKSUM_COMPLETE;
888 ring->csum_complete++;
890 ip_summed = CHECKSUM_NONE;
895 ip_summed = CHECKSUM_NONE;
899 /* This packet is eligible for GRO if it is:
900 * - DIX Ethernet (type interpretation)
902 * - without IP options
903 * - not an IP fragment
904 * - no LLS polling in progress
906 if (!mlx4_en_cq_busy_polling(cq) &&
907 (dev->features & NETIF_F_GRO)) {
908 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
912 nr = mlx4_en_complete_rx_desc(priv,
913 rx_desc, frags, gro_skb,
918 if (ip_summed == CHECKSUM_COMPLETE) {
919 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
920 if (check_csum(cqe, gro_skb, va,
922 ip_summed = CHECKSUM_NONE;
924 ring->csum_complete--;
928 skb_shinfo(gro_skb)->nr_frags = nr;
929 gro_skb->len = length;
930 gro_skb->data_len = length;
931 gro_skb->ip_summed = ip_summed;
933 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
934 gro_skb->csum_level = 1;
936 if ((cqe->vlan_my_qpn &
937 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
938 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
939 u16 vid = be16_to_cpu(cqe->sl_vid);
941 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
942 } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
943 MLX4_CQE_SVLAN_PRESENT_MASK) &&
944 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
945 __vlan_hwaccel_put_tag(gro_skb,
947 be16_to_cpu(cqe->sl_vid));
950 if (dev->features & NETIF_F_RXHASH)
951 skb_set_hash(gro_skb,
952 be32_to_cpu(cqe->immed_rss_invalid),
953 (ip_summed == CHECKSUM_UNNECESSARY) ?
957 skb_record_rx_queue(gro_skb, cq->ring);
958 skb_mark_napi_id(gro_skb, &cq->napi);
960 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
961 timestamp = mlx4_en_get_cqe_ts(cqe);
962 mlx4_en_fill_hwtstamps(mdev,
963 skb_hwtstamps(gro_skb),
967 napi_gro_frags(&cq->napi);
971 /* GRO not possible, complete processing here */
972 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
974 priv->stats.rx_dropped++;
978 if (unlikely(priv->validate_loopback)) {
979 validate_loopback(priv, skb);
983 if (ip_summed == CHECKSUM_COMPLETE) {
984 if (check_csum(cqe, skb, skb->data, dev->features)) {
985 ip_summed = CHECKSUM_NONE;
986 ring->csum_complete--;
991 skb->ip_summed = ip_summed;
992 skb->protocol = eth_type_trans(skb, dev);
993 skb_record_rx_queue(skb, cq->ring);
995 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
998 if (dev->features & NETIF_F_RXHASH)
1000 be32_to_cpu(cqe->immed_rss_invalid),
1001 (ip_summed == CHECKSUM_UNNECESSARY) ?
1005 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1006 MLX4_CQE_CVLAN_PRESENT_MASK) &&
1007 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1008 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1009 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1010 MLX4_CQE_SVLAN_PRESENT_MASK) &&
1011 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1012 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1013 be16_to_cpu(cqe->sl_vid));
1015 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1016 timestamp = mlx4_en_get_cqe_ts(cqe);
1017 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1021 skb_mark_napi_id(skb, &cq->napi);
1023 if (!mlx4_en_cq_busy_polling(cq))
1024 napi_gro_receive(&cq->napi, skb);
1026 netif_receive_skb(skb);
1029 for (nr = 0; nr < priv->num_frags; nr++)
1030 mlx4_en_free_frag(priv, frags, nr);
1032 ++cq->mcq.cons_index;
1033 index = (cq->mcq.cons_index) & ring->size_mask;
1034 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1035 if (++polled == budget)
1040 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1041 mlx4_cq_set_ci(&cq->mcq);
1042 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1043 ring->cons = cq->mcq.cons_index;
1044 mlx4_en_refill_rx_buffers(priv, ring);
1045 mlx4_en_update_rx_prod_db(ring);
1050 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1052 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1053 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1055 if (likely(priv->port_up))
1056 napi_schedule_irqoff(&cq->napi);
1058 mlx4_en_arm_cq(priv, cq);
1061 /* Rx CQ polling - called by NAPI */
1062 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1064 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1065 struct net_device *dev = cq->dev;
1066 struct mlx4_en_priv *priv = netdev_priv(dev);
1069 if (!mlx4_en_cq_lock_napi(cq))
1072 done = mlx4_en_process_rx_cq(dev, cq, budget);
1074 mlx4_en_cq_unlock_napi(cq);
1076 /* If we used up all the quota - we're probably not done yet... */
1077 if (done == budget) {
1078 const struct cpumask *aff;
1079 struct irq_data *idata;
1082 INC_PERF_COUNTER(priv->pstats.napi_quota);
1084 cpu_curr = smp_processor_id();
1085 idata = irq_desc_get_irq_data(cq->irq_desc);
1086 aff = irq_data_get_affinity_mask(idata);
1088 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1091 /* Current cpu is not according to smp_irq_affinity -
1092 * probably affinity changed. need to stop this NAPI
1093 * poll, and restart it on the right CPU
1098 napi_complete_done(napi, done);
1099 mlx4_en_arm_cq(priv, cq);
1103 static const int frag_sizes[] = {
1110 void mlx4_en_calc_rx_buf(struct net_device *dev)
1112 struct mlx4_en_priv *priv = netdev_priv(dev);
1113 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1114 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1116 int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN);
1120 while (buf_size < eff_mtu) {
1121 priv->frag_info[i].frag_size =
1122 (eff_mtu > buf_size + frag_sizes[i]) ?
1123 frag_sizes[i] : eff_mtu - buf_size;
1124 priv->frag_info[i].frag_prefix_size = buf_size;
1125 priv->frag_info[i].frag_stride =
1126 ALIGN(priv->frag_info[i].frag_size,
1128 buf_size += priv->frag_info[i].frag_size;
1132 priv->num_frags = i;
1133 priv->rx_skb_size = eff_mtu;
1134 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1136 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1137 eff_mtu, priv->num_frags);
1138 for (i = 0; i < priv->num_frags; i++) {
1140 " frag:%d - size:%d prefix:%d stride:%d\n",
1142 priv->frag_info[i].frag_size,
1143 priv->frag_info[i].frag_prefix_size,
1144 priv->frag_info[i].frag_stride);
1148 /* RSS related functions */
1150 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1151 struct mlx4_en_rx_ring *ring,
1152 enum mlx4_qp_state *state,
1155 struct mlx4_en_dev *mdev = priv->mdev;
1156 struct mlx4_qp_context *context;
1159 context = kmalloc(sizeof(*context), GFP_KERNEL);
1163 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1165 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1168 qp->event = mlx4_en_sqp_event;
1170 memset(context, 0, sizeof *context);
1171 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1172 qpn, ring->cqn, -1, context);
1173 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1175 /* Cancel FCS removal if FW allows */
1176 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1177 context->param3 |= cpu_to_be32(1 << 29);
1178 if (priv->dev->features & NETIF_F_RXFCS)
1181 ring->fcs_del = ETH_FCS_LEN;
1185 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1187 mlx4_qp_remove(mdev->dev, qp);
1188 mlx4_qp_free(mdev->dev, qp);
1190 mlx4_en_update_rx_prod_db(ring);
1196 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1201 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1202 MLX4_RESERVE_A0_QP);
1204 en_err(priv, "Failed reserving drop qpn\n");
1207 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1209 en_err(priv, "Failed allocating drop qp\n");
1210 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1217 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1221 qpn = priv->drop_qp.qpn;
1222 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1223 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1224 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1227 /* Allocate rx qp's and configure them according to rss map */
1228 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1230 struct mlx4_en_dev *mdev = priv->mdev;
1231 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1232 struct mlx4_qp_context context;
1233 struct mlx4_rss_context *rss_context;
1236 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1242 en_dbg(DRV, priv, "Configuring rss steering\n");
1243 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1245 &rss_map->base_qpn, 0);
1247 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1251 for (i = 0; i < priv->rx_ring_num; i++) {
1252 qpn = rss_map->base_qpn + i;
1253 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1262 /* Configure RSS indirection qp */
1263 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1265 en_err(priv, "Failed to allocate RSS indirection QP\n");
1268 rss_map->indir_qp.event = mlx4_en_sqp_event;
1269 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1270 priv->rx_ring[0]->cqn, -1, &context);
1272 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1273 rss_rings = priv->rx_ring_num;
1275 rss_rings = priv->prof->rss_rings;
1277 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1278 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1280 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1281 (rss_map->base_qpn));
1282 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1283 if (priv->mdev->profile.udp_rss) {
1284 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1285 rss_context->base_qpn_udp = rss_context->default_qpn;
1288 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1289 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1290 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1293 rss_context->flags = rss_mask;
1294 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1295 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1296 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1297 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1298 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1299 memcpy(rss_context->rss_key, priv->rss_key,
1300 MLX4_EN_RSS_KEY_SIZE);
1302 en_err(priv, "Unknown RSS hash function requested\n");
1306 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1307 &rss_map->indir_qp, &rss_map->indir_state);
1314 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1315 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1316 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1317 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1319 for (i = 0; i < good_qps; i++) {
1320 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1321 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1322 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1323 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1325 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1329 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1331 struct mlx4_en_dev *mdev = priv->mdev;
1332 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1335 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1336 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1337 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1338 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1340 for (i = 0; i < priv->rx_ring_num; i++) {
1341 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1342 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1343 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1344 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1346 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);