2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kernel.h>
35 #include <linux/ethtool.h>
36 #include <linux/netdevice.h>
37 #include <linux/mlx4/driver.h>
38 #include <linux/mlx4/device.h>
41 #include <linux/bitmap.h>
46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
50 int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
55 for (i = 0; i < priv->tx_ring_num; i++) {
56 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
57 priv->tx_cq[i]->moder_time = priv->tx_usecs;
59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
65 if (priv->adaptive_rx_coal)
68 for (i = 0; i < priv->rx_ring_num; i++) {
69 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
70 priv->rx_cq[i]->moder_time = priv->rx_usecs;
71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
83 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
85 struct mlx4_en_priv *priv = netdev_priv(dev);
86 struct mlx4_en_dev *mdev = priv->mdev;
88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
90 sizeof(drvinfo->version));
91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
93 (u16) (mdev->dev->caps.fw_ver >> 32),
94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
95 (u16) (mdev->dev->caps.fw_ver & 0xffff));
96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
97 sizeof(drvinfo->bus_info));
100 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
105 static const char main_strings[][ETH_GSTRING_LEN] = {
106 /* main statistics */
107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
109 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
112 "tx_heartbeat_errors", "tx_window_errors",
114 /* port statistics */
117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
118 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
126 /* priority flow control statistics rx */
127 "rx_pause_prio_0", "rx_pause_duration_prio_0",
128 "rx_pause_transition_prio_0",
129 "rx_pause_prio_1", "rx_pause_duration_prio_1",
130 "rx_pause_transition_prio_1",
131 "rx_pause_prio_2", "rx_pause_duration_prio_2",
132 "rx_pause_transition_prio_2",
133 "rx_pause_prio_3", "rx_pause_duration_prio_3",
134 "rx_pause_transition_prio_3",
135 "rx_pause_prio_4", "rx_pause_duration_prio_4",
136 "rx_pause_transition_prio_4",
137 "rx_pause_prio_5", "rx_pause_duration_prio_5",
138 "rx_pause_transition_prio_5",
139 "rx_pause_prio_6", "rx_pause_duration_prio_6",
140 "rx_pause_transition_prio_6",
141 "rx_pause_prio_7", "rx_pause_duration_prio_7",
142 "rx_pause_transition_prio_7",
144 /* flow control statistics rx */
145 "rx_pause", "rx_pause_duration", "rx_pause_transition",
147 /* priority flow control statistics tx */
148 "tx_pause_prio_0", "tx_pause_duration_prio_0",
149 "tx_pause_transition_prio_0",
150 "tx_pause_prio_1", "tx_pause_duration_prio_1",
151 "tx_pause_transition_prio_1",
152 "tx_pause_prio_2", "tx_pause_duration_prio_2",
153 "tx_pause_transition_prio_2",
154 "tx_pause_prio_3", "tx_pause_duration_prio_3",
155 "tx_pause_transition_prio_3",
156 "tx_pause_prio_4", "tx_pause_duration_prio_4",
157 "tx_pause_transition_prio_4",
158 "tx_pause_prio_5", "tx_pause_duration_prio_5",
159 "tx_pause_transition_prio_5",
160 "tx_pause_prio_6", "tx_pause_duration_prio_6",
161 "tx_pause_transition_prio_6",
162 "tx_pause_prio_7", "tx_pause_duration_prio_7",
163 "tx_pause_transition_prio_7",
165 /* flow control statistics tx */
166 "tx_pause", "tx_pause_duration", "tx_pause_transition",
168 /* packet statistics */
169 "rx_multicast_packets",
170 "rx_broadcast_packets",
172 "rx_in_range_length_error",
173 "rx_out_range_length_error",
174 "tx_multicast_packets",
175 "tx_broadcast_packets",
176 "rx_prio_0_packets", "rx_prio_0_bytes",
177 "rx_prio_1_packets", "rx_prio_1_bytes",
178 "rx_prio_2_packets", "rx_prio_2_bytes",
179 "rx_prio_3_packets", "rx_prio_3_bytes",
180 "rx_prio_4_packets", "rx_prio_4_bytes",
181 "rx_prio_5_packets", "rx_prio_5_bytes",
182 "rx_prio_6_packets", "rx_prio_6_bytes",
183 "rx_prio_7_packets", "rx_prio_7_bytes",
184 "rx_novlan_packets", "rx_novlan_bytes",
185 "tx_prio_0_packets", "tx_prio_0_bytes",
186 "tx_prio_1_packets", "tx_prio_1_bytes",
187 "tx_prio_2_packets", "tx_prio_2_bytes",
188 "tx_prio_3_packets", "tx_prio_3_bytes",
189 "tx_prio_4_packets", "tx_prio_4_bytes",
190 "tx_prio_5_packets", "tx_prio_5_bytes",
191 "tx_prio_6_packets", "tx_prio_6_bytes",
192 "tx_prio_7_packets", "tx_prio_7_bytes",
193 "tx_novlan_packets", "tx_novlan_bytes",
197 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
205 static u32 mlx4_en_get_msglevel(struct net_device *dev)
207 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
210 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
212 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
215 static void mlx4_en_get_wol(struct net_device *netdev,
216 struct ethtool_wolinfo *wol)
218 struct mlx4_en_priv *priv = netdev_priv(netdev);
223 if ((priv->port < 1) || (priv->port > 2)) {
224 en_err(priv, "Failed to get WoL information\n");
228 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
229 MLX4_DEV_CAP_FLAG_WOL_PORT2;
231 if (!(priv->mdev->dev->caps.flags & mask)) {
237 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
239 en_err(priv, "Failed to get WoL information\n");
243 if (config & MLX4_EN_WOL_MAGIC)
244 wol->supported = WAKE_MAGIC;
248 if (config & MLX4_EN_WOL_ENABLED)
249 wol->wolopts = WAKE_MAGIC;
254 static int mlx4_en_set_wol(struct net_device *netdev,
255 struct ethtool_wolinfo *wol)
257 struct mlx4_en_priv *priv = netdev_priv(netdev);
262 if ((priv->port < 1) || (priv->port > 2))
265 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
266 MLX4_DEV_CAP_FLAG_WOL_PORT2;
268 if (!(priv->mdev->dev->caps.flags & mask))
271 if (wol->supported & ~WAKE_MAGIC)
274 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
276 en_err(priv, "Failed to get WoL info, unable to modify\n");
280 if (wol->wolopts & WAKE_MAGIC) {
281 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
284 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
285 config |= MLX4_EN_WOL_DO_MODIFY;
288 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
290 en_err(priv, "Failed to set WoL information\n");
295 struct bitmap_iterator {
296 unsigned long *stats_bitmap;
298 unsigned int iterator;
299 bool advance_array; /* if set, force no increments */
302 static inline void bitmap_iterator_init(struct bitmap_iterator *h,
303 unsigned long *stats_bitmap,
307 h->advance_array = !bitmap_empty(stats_bitmap, count);
308 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
310 h->stats_bitmap = stats_bitmap;
313 static inline int bitmap_iterator_test(struct bitmap_iterator *h)
315 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
318 static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
320 return h->iterator++;
323 static inline unsigned int
324 bitmap_iterator_count(struct bitmap_iterator *h)
329 static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
331 struct mlx4_en_priv *priv = netdev_priv(dev);
332 struct bitmap_iterator it;
334 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
338 return bitmap_iterator_count(&it) +
339 (priv->tx_ring_num * 2) +
340 #ifdef CONFIG_NET_RX_BUSY_POLL
341 (priv->rx_ring_num * 5);
343 (priv->rx_ring_num * 2);
346 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
347 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
348 case ETH_SS_PRIV_FLAGS:
349 return ARRAY_SIZE(mlx4_en_priv_flags);
355 static void mlx4_en_get_ethtool_stats(struct net_device *dev,
356 struct ethtool_stats *stats, uint64_t *data)
358 struct mlx4_en_priv *priv = netdev_priv(dev);
361 struct bitmap_iterator it;
363 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
365 spin_lock_bh(&priv->stats_lock);
367 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
368 if (bitmap_iterator_test(&it))
369 data[index++] = ((unsigned long *)&priv->stats)[i];
371 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
372 if (bitmap_iterator_test(&it))
373 data[index++] = ((unsigned long *)&priv->port_stats)[i];
375 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
376 if (bitmap_iterator_test(&it))
378 ((unsigned long *)&priv->pf_stats)[i];
380 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
381 i++, bitmap_iterator_inc(&it))
382 if (bitmap_iterator_test(&it))
384 ((u64 *)&priv->rx_priority_flowstats)[i];
386 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
387 if (bitmap_iterator_test(&it))
388 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
390 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
391 i++, bitmap_iterator_inc(&it))
392 if (bitmap_iterator_test(&it))
394 ((u64 *)&priv->tx_priority_flowstats)[i];
396 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
397 if (bitmap_iterator_test(&it))
398 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
400 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
401 if (bitmap_iterator_test(&it))
402 data[index++] = ((unsigned long *)&priv->pkstats)[i];
404 for (i = 0; i < priv->tx_ring_num; i++) {
405 data[index++] = priv->tx_ring[i]->packets;
406 data[index++] = priv->tx_ring[i]->bytes;
408 for (i = 0; i < priv->rx_ring_num; i++) {
409 data[index++] = priv->rx_ring[i]->packets;
410 data[index++] = priv->rx_ring[i]->bytes;
411 #ifdef CONFIG_NET_RX_BUSY_POLL
412 data[index++] = priv->rx_ring[i]->yields;
413 data[index++] = priv->rx_ring[i]->misses;
414 data[index++] = priv->rx_ring[i]->cleaned;
417 spin_unlock_bh(&priv->stats_lock);
421 static void mlx4_en_self_test(struct net_device *dev,
422 struct ethtool_test *etest, u64 *buf)
424 mlx4_en_ex_selftest(dev, &etest->flags, buf);
427 static void mlx4_en_get_strings(struct net_device *dev,
428 uint32_t stringset, uint8_t *data)
430 struct mlx4_en_priv *priv = netdev_priv(dev);
433 struct bitmap_iterator it;
435 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
439 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
440 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
441 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
442 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
443 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
447 /* Add main counters */
448 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
449 bitmap_iterator_inc(&it))
450 if (bitmap_iterator_test(&it))
451 strcpy(data + (index++) * ETH_GSTRING_LEN,
452 main_strings[strings]);
454 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
455 bitmap_iterator_inc(&it))
456 if (bitmap_iterator_test(&it))
457 strcpy(data + (index++) * ETH_GSTRING_LEN,
458 main_strings[strings]);
460 for (i = 0; i < NUM_PF_STATS; i++, strings++,
461 bitmap_iterator_inc(&it))
462 if (bitmap_iterator_test(&it))
463 strcpy(data + (index++) * ETH_GSTRING_LEN,
464 main_strings[strings]);
466 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
467 bitmap_iterator_inc(&it))
468 if (bitmap_iterator_test(&it))
469 strcpy(data + (index++) * ETH_GSTRING_LEN,
470 main_strings[strings]);
472 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
473 bitmap_iterator_inc(&it))
474 if (bitmap_iterator_test(&it))
475 strcpy(data + (index++) * ETH_GSTRING_LEN,
476 main_strings[strings]);
478 for (i = 0; i < priv->tx_ring_num; i++) {
479 sprintf(data + (index++) * ETH_GSTRING_LEN,
481 sprintf(data + (index++) * ETH_GSTRING_LEN,
484 for (i = 0; i < priv->rx_ring_num; i++) {
485 sprintf(data + (index++) * ETH_GSTRING_LEN,
487 sprintf(data + (index++) * ETH_GSTRING_LEN,
489 #ifdef CONFIG_NET_RX_BUSY_POLL
490 sprintf(data + (index++) * ETH_GSTRING_LEN,
491 "rx%d_napi_yield", i);
492 sprintf(data + (index++) * ETH_GSTRING_LEN,
494 sprintf(data + (index++) * ETH_GSTRING_LEN,
499 case ETH_SS_PRIV_FLAGS:
500 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
501 strcpy(data + i * ETH_GSTRING_LEN,
502 mlx4_en_priv_flags[i]);
508 static u32 mlx4_en_autoneg_get(struct net_device *dev)
510 struct mlx4_en_priv *priv = netdev_priv(dev);
511 struct mlx4_en_dev *mdev = priv->mdev;
512 u32 autoneg = AUTONEG_DISABLE;
514 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
515 (priv->port_state.flags & MLX4_EN_PORT_ANE))
516 autoneg = AUTONEG_ENABLE;
521 static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg)
523 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
525 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
526 | MLX4_PROT_MASK(MLX4_1000BASE_T)
527 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
531 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
532 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
533 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
534 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
535 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
536 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
537 return SUPPORTED_FIBRE;
540 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
541 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
542 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
543 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
544 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
545 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
546 return SUPPORTED_Backplane;
551 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
553 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
555 if (!eth_proto) /* link down */
556 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
558 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
559 | MLX4_PROT_MASK(MLX4_1000BASE_T)
560 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
564 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
565 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
566 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
567 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
571 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
572 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
573 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
577 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
578 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
579 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
580 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
581 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
582 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
588 #define MLX4_LINK_MODES_SZ \
589 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
591 enum ethtool_report {
597 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
598 static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = {
599 [MLX4_100BASE_TX] = {
600 SUPPORTED_100baseT_Full,
601 ADVERTISED_100baseT_Full,
605 [MLX4_1000BASE_T] = {
606 SUPPORTED_1000baseT_Full,
607 ADVERTISED_1000baseT_Full,
610 [MLX4_1000BASE_CX_SGMII] = {
611 SUPPORTED_1000baseKX_Full,
612 ADVERTISED_1000baseKX_Full,
615 [MLX4_1000BASE_KX] = {
616 SUPPORTED_1000baseKX_Full,
617 ADVERTISED_1000baseKX_Full,
622 SUPPORTED_10000baseT_Full,
623 ADVERTISED_10000baseT_Full,
626 [MLX4_10GBASE_CX4] = {
627 SUPPORTED_10000baseKX4_Full,
628 ADVERTISED_10000baseKX4_Full,
631 [MLX4_10GBASE_KX4] = {
632 SUPPORTED_10000baseKX4_Full,
633 ADVERTISED_10000baseKX4_Full,
636 [MLX4_10GBASE_KR] = {
637 SUPPORTED_10000baseKR_Full,
638 ADVERTISED_10000baseKR_Full,
641 [MLX4_10GBASE_CR] = {
642 SUPPORTED_10000baseKR_Full,
643 ADVERTISED_10000baseKR_Full,
646 [MLX4_10GBASE_SR] = {
647 SUPPORTED_10000baseKR_Full,
648 ADVERTISED_10000baseKR_Full,
652 [MLX4_20GBASE_KR2] = {
653 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full,
654 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full,
658 [MLX4_40GBASE_CR4] = {
659 SUPPORTED_40000baseCR4_Full,
660 ADVERTISED_40000baseCR4_Full,
663 [MLX4_40GBASE_KR4] = {
664 SUPPORTED_40000baseKR4_Full,
665 ADVERTISED_40000baseKR4_Full,
668 [MLX4_40GBASE_SR4] = {
669 SUPPORTED_40000baseSR4_Full,
670 ADVERTISED_40000baseSR4_Full,
674 [MLX4_56GBASE_KR4] = {
675 SUPPORTED_56000baseKR4_Full,
676 ADVERTISED_56000baseKR4_Full,
679 [MLX4_56GBASE_CR4] = {
680 SUPPORTED_56000baseCR4_Full,
681 ADVERTISED_56000baseCR4_Full,
684 [MLX4_56GBASE_SR4] = {
685 SUPPORTED_56000baseSR4_Full,
686 ADVERTISED_56000baseSR4_Full,
691 static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report)
696 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
697 if (eth_proto & MLX4_PROT_MASK(i))
698 link_modes |= ptys2ethtool_map[i][report];
703 static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report)
708 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
709 if (ptys2ethtool_map[i][report] & link_modes)
710 ptys_modes |= 1 << i;
715 /* Convert actual speed (SPEED_XXX) to ptys link modes */
716 static u32 speed2ptys_link_modes(u32 speed)
721 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
722 if (ptys2ethtool_map[i][SPEED] == speed)
723 ptys_modes |= 1 << i;
728 static int ethtool_get_ptys_settings(struct net_device *dev,
729 struct ethtool_cmd *cmd)
731 struct mlx4_en_priv *priv = netdev_priv(dev);
732 struct mlx4_ptys_reg ptys_reg;
736 memset(&ptys_reg, 0, sizeof(ptys_reg));
737 ptys_reg.local_port = priv->port;
738 ptys_reg.proto_mask = MLX4_PTYS_EN;
739 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
740 MLX4_ACCESS_REG_QUERY, &ptys_reg);
742 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
746 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
747 ptys_reg.proto_mask);
748 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
749 be32_to_cpu(ptys_reg.eth_proto_cap));
750 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
751 be32_to_cpu(ptys_reg.eth_proto_admin));
752 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
753 be32_to_cpu(ptys_reg.eth_proto_oper));
754 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
755 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
758 cmd->advertising = 0;
760 cmd->supported |= ptys_get_supported_port(&ptys_reg);
762 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
763 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED);
765 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
766 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED);
768 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
769 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0;
771 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ?
772 ADVERTISED_Asym_Pause : 0;
774 cmd->port = ptys_get_active_port(&ptys_reg);
775 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ?
776 XCVR_EXTERNAL : XCVR_INTERNAL;
778 if (mlx4_en_autoneg_get(dev)) {
779 cmd->supported |= SUPPORTED_Autoneg;
780 cmd->advertising |= ADVERTISED_Autoneg;
783 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
784 AUTONEG_ENABLE : AUTONEG_DISABLE;
786 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
787 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED);
789 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
790 ADVERTISED_Autoneg : 0;
792 cmd->phy_address = 0;
793 cmd->mdio_support = 0;
796 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
797 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
802 static void ethtool_get_default_settings(struct net_device *dev,
803 struct ethtool_cmd *cmd)
805 struct mlx4_en_priv *priv = netdev_priv(dev);
808 cmd->autoneg = AUTONEG_DISABLE;
809 cmd->supported = SUPPORTED_10000baseT_Full;
810 cmd->advertising = ADVERTISED_10000baseT_Full;
811 trans_type = priv->port_state.transceiver;
813 if (trans_type > 0 && trans_type <= 0xC) {
814 cmd->port = PORT_FIBRE;
815 cmd->transceiver = XCVR_EXTERNAL;
816 cmd->supported |= SUPPORTED_FIBRE;
817 cmd->advertising |= ADVERTISED_FIBRE;
818 } else if (trans_type == 0x80 || trans_type == 0) {
820 cmd->transceiver = XCVR_INTERNAL;
821 cmd->supported |= SUPPORTED_TP;
822 cmd->advertising |= ADVERTISED_TP;
825 cmd->transceiver = -1;
829 static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
831 struct mlx4_en_priv *priv = netdev_priv(dev);
834 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
837 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
838 priv->port_state.flags & MLX4_EN_PORT_ANC,
839 priv->port_state.flags & MLX4_EN_PORT_ANE);
841 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
842 ret = ethtool_get_ptys_settings(dev, cmd);
843 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
844 ethtool_get_default_settings(dev, cmd);
846 if (netif_carrier_ok(dev)) {
847 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
848 cmd->duplex = DUPLEX_FULL;
850 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
851 cmd->duplex = DUPLEX_UNKNOWN;
856 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
857 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
860 __be32 proto_admin = 0;
862 if (!speed) { /* Speed = 0 ==> Reset Link modes */
863 proto_admin = proto_cap;
864 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
865 be32_to_cpu(proto_cap));
867 u32 ptys_link_modes = speed2ptys_link_modes(speed);
869 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
870 en_info(priv, "Setting Speed to %d\n", speed);
875 static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
877 struct mlx4_en_priv *priv = netdev_priv(dev);
878 struct mlx4_ptys_reg ptys_reg;
882 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED);
883 int speed = ethtool_cmd_speed(cmd);
885 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n",
886 speed, cmd->advertising, cmd->autoneg, cmd->duplex);
888 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
889 (cmd->duplex == DUPLEX_HALF))
892 memset(&ptys_reg, 0, sizeof(ptys_reg));
893 ptys_reg.local_port = priv->port;
894 ptys_reg.proto_mask = MLX4_PTYS_EN;
895 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
896 MLX4_ACCESS_REG_QUERY, &ptys_reg);
898 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
903 proto_admin = cmd->autoneg == AUTONEG_ENABLE ?
904 cpu_to_be32(ptys_adv) :
905 speed_set_ptys_admin(priv, speed,
906 ptys_reg.eth_proto_cap);
908 proto_admin &= ptys_reg.eth_proto_cap;
910 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
911 return -EINVAL; /* nothing to change due to bad input */
914 if (proto_admin == ptys_reg.eth_proto_admin)
915 return 0; /* Nothing to change */
917 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
918 be32_to_cpu(proto_admin));
920 ptys_reg.eth_proto_admin = proto_admin;
921 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
924 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
925 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
929 mutex_lock(&priv->mdev->state_lock);
931 en_warn(priv, "Port link mode changed, restarting port...\n");
932 mlx4_en_stop_port(dev, 1);
933 if (mlx4_en_start_port(dev))
934 en_err(priv, "Failed restarting port %d\n", priv->port);
936 mutex_unlock(&priv->mdev->state_lock);
940 static int mlx4_en_get_coalesce(struct net_device *dev,
941 struct ethtool_coalesce *coal)
943 struct mlx4_en_priv *priv = netdev_priv(dev);
945 coal->tx_coalesce_usecs = priv->tx_usecs;
946 coal->tx_max_coalesced_frames = priv->tx_frames;
947 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
949 coal->rx_coalesce_usecs = priv->rx_usecs;
950 coal->rx_max_coalesced_frames = priv->rx_frames;
952 coal->pkt_rate_low = priv->pkt_rate_low;
953 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
954 coal->pkt_rate_high = priv->pkt_rate_high;
955 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
956 coal->rate_sample_interval = priv->sample_interval;
957 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
962 static int mlx4_en_set_coalesce(struct net_device *dev,
963 struct ethtool_coalesce *coal)
965 struct mlx4_en_priv *priv = netdev_priv(dev);
967 if (!coal->tx_max_coalesced_frames_irq)
970 if (coal->tx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
971 coal->rx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
972 coal->rx_coalesce_usecs_low > MLX4_EN_MAX_COAL_TIME ||
973 coal->rx_coalesce_usecs_high > MLX4_EN_MAX_COAL_TIME) {
974 netdev_info(dev, "%s: maximum coalesce time supported is %d usecs\n",
975 __func__, MLX4_EN_MAX_COAL_TIME);
979 if (coal->tx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS ||
980 coal->rx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS) {
981 netdev_info(dev, "%s: maximum coalesced frames supported is %d\n",
982 __func__, MLX4_EN_MAX_COAL_PKTS);
986 priv->rx_frames = (coal->rx_max_coalesced_frames ==
988 MLX4_EN_RX_COAL_TARGET :
989 coal->rx_max_coalesced_frames;
990 priv->rx_usecs = (coal->rx_coalesce_usecs ==
992 MLX4_EN_RX_COAL_TIME :
993 coal->rx_coalesce_usecs;
995 /* Setting TX coalescing parameters */
996 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
997 coal->tx_max_coalesced_frames != priv->tx_frames) {
998 priv->tx_usecs = coal->tx_coalesce_usecs;
999 priv->tx_frames = coal->tx_max_coalesced_frames;
1002 /* Set adaptive coalescing params */
1003 priv->pkt_rate_low = coal->pkt_rate_low;
1004 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
1005 priv->pkt_rate_high = coal->pkt_rate_high;
1006 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
1007 priv->sample_interval = coal->rate_sample_interval;
1008 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
1009 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
1011 return mlx4_en_moderation_update(priv);
1014 static int mlx4_en_set_pauseparam(struct net_device *dev,
1015 struct ethtool_pauseparam *pause)
1017 struct mlx4_en_priv *priv = netdev_priv(dev);
1018 struct mlx4_en_dev *mdev = priv->mdev;
1024 priv->prof->tx_pause = pause->tx_pause != 0;
1025 priv->prof->rx_pause = pause->rx_pause != 0;
1026 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1027 priv->rx_skb_size + ETH_FCS_LEN,
1028 priv->prof->tx_pause,
1030 priv->prof->rx_pause,
1031 priv->prof->rx_ppp);
1033 en_err(priv, "Failed setting pause params\n");
1035 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1037 priv->prof->rx_pause,
1039 priv->prof->tx_pause);
1044 static void mlx4_en_get_pauseparam(struct net_device *dev,
1045 struct ethtool_pauseparam *pause)
1047 struct mlx4_en_priv *priv = netdev_priv(dev);
1049 pause->tx_pause = priv->prof->tx_pause;
1050 pause->rx_pause = priv->prof->rx_pause;
1053 static int mlx4_en_set_ringparam(struct net_device *dev,
1054 struct ethtool_ringparam *param)
1056 struct mlx4_en_priv *priv = netdev_priv(dev);
1057 struct mlx4_en_dev *mdev = priv->mdev;
1058 u32 rx_size, tx_size;
1062 if (param->rx_jumbo_pending || param->rx_mini_pending)
1065 rx_size = roundup_pow_of_two(param->rx_pending);
1066 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
1067 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
1068 tx_size = roundup_pow_of_two(param->tx_pending);
1069 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
1070 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
1072 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1073 priv->rx_ring[0]->size) &&
1074 tx_size == priv->tx_ring[0]->size)
1077 mutex_lock(&mdev->state_lock);
1078 if (priv->port_up) {
1080 mlx4_en_stop_port(dev, 1);
1083 mlx4_en_free_resources(priv);
1085 priv->prof->tx_ring_size = tx_size;
1086 priv->prof->rx_ring_size = rx_size;
1088 err = mlx4_en_alloc_resources(priv);
1090 en_err(priv, "Failed reallocating port resources\n");
1094 err = mlx4_en_start_port(dev);
1096 en_err(priv, "Failed starting port\n");
1099 err = mlx4_en_moderation_update(priv);
1102 mutex_unlock(&mdev->state_lock);
1106 static void mlx4_en_get_ringparam(struct net_device *dev,
1107 struct ethtool_ringparam *param)
1109 struct mlx4_en_priv *priv = netdev_priv(dev);
1111 memset(param, 0, sizeof(*param));
1112 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1113 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1114 param->rx_pending = priv->port_up ?
1115 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1116 param->tx_pending = priv->tx_ring[0]->size;
1119 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1121 struct mlx4_en_priv *priv = netdev_priv(dev);
1123 return priv->rx_ring_num;
1126 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1128 return MLX4_EN_RSS_KEY_SIZE;
1131 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1133 struct mlx4_en_priv *priv = netdev_priv(dev);
1135 /* check if requested function is supported by the device */
1136 if (hfunc == ETH_RSS_HASH_TOP) {
1137 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1139 if (!(dev->features & NETIF_F_RXHASH))
1140 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1142 } else if (hfunc == ETH_RSS_HASH_XOR) {
1143 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1145 if (dev->features & NETIF_F_RXHASH)
1146 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1153 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1156 struct mlx4_en_priv *priv = netdev_priv(dev);
1157 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1159 size_t n = priv->rx_ring_num;
1162 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
1163 rss_rings = 1 << ilog2(rss_rings);
1168 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
1172 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1174 *hfunc = priv->rss_hash_fn;
1178 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1179 const u8 *key, const u8 hfunc)
1181 struct mlx4_en_priv *priv = netdev_priv(dev);
1182 struct mlx4_en_dev *mdev = priv->mdev;
1188 /* Calculate RSS table size and make sure flows are spread evenly
1191 for (i = 0; i < priv->rx_ring_num; i++) {
1194 if (i > 0 && !ring_index[i] && !rss_rings)
1197 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
1202 rss_rings = priv->rx_ring_num;
1204 /* RSS table size must be an order of 2 */
1205 if (!is_power_of_2(rss_rings))
1208 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1209 err = mlx4_en_check_rxfh_func(dev, hfunc);
1214 mutex_lock(&mdev->state_lock);
1215 if (priv->port_up) {
1217 mlx4_en_stop_port(dev, 1);
1221 priv->prof->rss_rings = rss_rings;
1223 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1224 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1225 priv->rss_hash_fn = hfunc;
1228 err = mlx4_en_start_port(dev);
1230 en_err(priv, "Failed starting port\n");
1233 mutex_unlock(&mdev->state_lock);
1237 #define all_zeros_or_all_ones(field) \
1238 ((field) == 0 || (field) == (__force typeof(field))-1)
1240 static int mlx4_en_validate_flow(struct net_device *dev,
1241 struct ethtool_rxnfc *cmd)
1243 struct ethtool_usrip4_spec *l3_mask;
1244 struct ethtool_tcpip4_spec *l4_mask;
1245 struct ethhdr *eth_mask;
1247 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1250 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1251 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1252 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1256 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1259 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1261 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1262 /* don't allow mask which isn't all 0 or 1 */
1263 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1264 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1265 !all_zeros_or_all_ones(l4_mask->psrc) ||
1266 !all_zeros_or_all_ones(l4_mask->pdst))
1270 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1271 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1272 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1273 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1274 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1275 !all_zeros_or_all_ones(l3_mask->ip4dst))
1279 eth_mask = &cmd->fs.m_u.ether_spec;
1280 /* source mac mask must not be set */
1281 if (!is_zero_ether_addr(eth_mask->h_source))
1284 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1285 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1288 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1295 if ((cmd->fs.flow_type & FLOW_EXT)) {
1296 if (cmd->fs.m_ext.vlan_etype ||
1297 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1299 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1300 cpu_to_be16(VLAN_VID_MASK)))
1303 if (cmd->fs.m_ext.vlan_tci) {
1304 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1313 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1314 struct list_head *rule_list_h,
1315 struct mlx4_spec_list *spec_l2,
1319 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1321 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1322 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1323 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1325 if ((cmd->fs.flow_type & FLOW_EXT) &&
1326 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1327 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1328 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1331 list_add_tail(&spec_l2->list, rule_list_h);
1336 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1337 struct ethtool_rxnfc *cmd,
1338 struct list_head *rule_list_h,
1339 struct mlx4_spec_list *spec_l2,
1343 unsigned char mac[ETH_ALEN];
1345 if (!ipv4_is_multicast(ipv4_dst)) {
1346 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1347 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1349 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1351 ip_eth_mc_map(ipv4_dst, mac);
1354 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1360 static int add_ip_rule(struct mlx4_en_priv *priv,
1361 struct ethtool_rxnfc *cmd,
1362 struct list_head *list_h)
1365 struct mlx4_spec_list *spec_l2 = NULL;
1366 struct mlx4_spec_list *spec_l3 = NULL;
1367 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1369 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1370 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1371 if (!spec_l2 || !spec_l3) {
1376 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1378 usr_ip4_spec.ip4dst);
1381 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1382 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1383 if (l3_mask->ip4src)
1384 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1385 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1386 if (l3_mask->ip4dst)
1387 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1388 list_add_tail(&spec_l3->list, list_h);
1398 static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1399 struct ethtool_rxnfc *cmd,
1400 struct list_head *list_h, int proto)
1403 struct mlx4_spec_list *spec_l2 = NULL;
1404 struct mlx4_spec_list *spec_l3 = NULL;
1405 struct mlx4_spec_list *spec_l4 = NULL;
1406 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1408 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1409 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1410 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1411 if (!spec_l2 || !spec_l3 || !spec_l4) {
1416 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1418 if (proto == TCP_V4_FLOW) {
1419 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1422 tcp_ip4_spec.ip4dst);
1425 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1426 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1427 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1428 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1429 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1431 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1434 udp_ip4_spec.ip4dst);
1437 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1438 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1439 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1440 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1441 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1444 if (l4_mask->ip4src)
1445 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1446 if (l4_mask->ip4dst)
1447 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1450 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1452 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1454 list_add_tail(&spec_l3->list, list_h);
1455 list_add_tail(&spec_l4->list, list_h);
1466 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1467 struct ethtool_rxnfc *cmd,
1468 struct list_head *rule_list_h)
1471 struct ethhdr *eth_spec;
1472 struct mlx4_spec_list *spec_l2;
1473 struct mlx4_en_priv *priv = netdev_priv(dev);
1475 err = mlx4_en_validate_flow(dev, cmd);
1479 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1481 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1485 eth_spec = &cmd->fs.h_u.ether_spec;
1486 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1487 ð_spec->h_dest[0]);
1488 spec_l2->eth.ether_type = eth_spec->h_proto;
1489 if (eth_spec->h_proto)
1490 spec_l2->eth.ether_type_enable = 1;
1493 err = add_ip_rule(priv, cmd, rule_list_h);
1496 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1499 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1506 static int mlx4_en_flow_replace(struct net_device *dev,
1507 struct ethtool_rxnfc *cmd)
1510 struct mlx4_en_priv *priv = netdev_priv(dev);
1511 struct ethtool_flow_id *loc_rule;
1512 struct mlx4_spec_list *spec, *tmp_spec;
1516 struct mlx4_net_trans_rule rule = {
1517 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1519 .allow_loopback = 1,
1520 .promisc_mode = MLX4_FS_REGULAR,
1523 rule.port = priv->port;
1524 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1525 INIT_LIST_HEAD(&rule.list);
1527 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1528 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1529 qpn = priv->drop_qp.qpn;
1530 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1531 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1533 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1534 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1535 cmd->fs.ring_cookie);
1538 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1540 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1541 cmd->fs.ring_cookie);
1546 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1550 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1552 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1554 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1555 cmd->fs.location, loc_rule->id);
1559 memset(&loc_rule->flow_spec, 0,
1560 sizeof(struct ethtool_rx_flow_spec));
1561 list_del(&loc_rule->list);
1563 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1565 en_err(priv, "Fail to attach network rule at location %d\n",
1569 loc_rule->id = reg_id;
1570 memcpy(&loc_rule->flow_spec, &cmd->fs,
1571 sizeof(struct ethtool_rx_flow_spec));
1572 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1575 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1576 list_del(&spec->list);
1582 static int mlx4_en_flow_detach(struct net_device *dev,
1583 struct ethtool_rxnfc *cmd)
1586 struct ethtool_flow_id *rule;
1587 struct mlx4_en_priv *priv = netdev_priv(dev);
1589 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1592 rule = &priv->ethtool_rules[cmd->fs.location];
1598 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1600 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1601 cmd->fs.location, rule->id);
1605 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1606 list_del(&rule->list);
1612 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1616 struct ethtool_flow_id *rule;
1617 struct mlx4_en_priv *priv = netdev_priv(dev);
1619 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1622 rule = &priv->ethtool_rules[loc];
1624 memcpy(&cmd->fs, &rule->flow_spec,
1625 sizeof(struct ethtool_rx_flow_spec));
1632 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1636 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1637 if (priv->ethtool_rules[i].id)
1644 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1647 struct mlx4_en_priv *priv = netdev_priv(dev);
1648 struct mlx4_en_dev *mdev = priv->mdev;
1650 int i = 0, priority = 0;
1652 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1653 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1654 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1655 (mdev->dev->caps.steering_mode !=
1656 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1660 case ETHTOOL_GRXRINGS:
1661 cmd->data = priv->rx_ring_num;
1663 case ETHTOOL_GRXCLSRLCNT:
1664 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1666 case ETHTOOL_GRXCLSRULE:
1667 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1669 case ETHTOOL_GRXCLSRLALL:
1670 cmd->data = MAX_NUM_OF_FS_RULES;
1671 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1672 err = mlx4_en_get_flow(dev, cmd, i);
1674 rule_locs[priority++] = i;
1687 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1690 struct mlx4_en_priv *priv = netdev_priv(dev);
1691 struct mlx4_en_dev *mdev = priv->mdev;
1693 if (mdev->dev->caps.steering_mode !=
1694 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1698 case ETHTOOL_SRXCLSRLINS:
1699 err = mlx4_en_flow_replace(dev, cmd);
1701 case ETHTOOL_SRXCLSRLDEL:
1702 err = mlx4_en_flow_detach(dev, cmd);
1705 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1712 static void mlx4_en_get_channels(struct net_device *dev,
1713 struct ethtool_channels *channel)
1715 struct mlx4_en_priv *priv = netdev_priv(dev);
1717 memset(channel, 0, sizeof(*channel));
1719 channel->max_rx = MAX_RX_RINGS;
1720 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1722 channel->rx_count = priv->rx_ring_num;
1723 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1726 static int mlx4_en_set_channels(struct net_device *dev,
1727 struct ethtool_channels *channel)
1729 struct mlx4_en_priv *priv = netdev_priv(dev);
1730 struct mlx4_en_dev *mdev = priv->mdev;
1734 if (channel->other_count || channel->combined_count ||
1735 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1736 channel->rx_count > MAX_RX_RINGS ||
1737 !channel->tx_count || !channel->rx_count)
1740 mutex_lock(&mdev->state_lock);
1741 if (priv->port_up) {
1743 mlx4_en_stop_port(dev, 1);
1746 mlx4_en_free_resources(priv);
1748 priv->num_tx_rings_p_up = channel->tx_count;
1749 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1750 priv->rx_ring_num = channel->rx_count;
1752 err = mlx4_en_alloc_resources(priv);
1754 en_err(priv, "Failed reallocating port resources\n");
1758 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
1759 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1762 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
1764 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1765 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1768 err = mlx4_en_start_port(dev);
1770 en_err(priv, "Failed starting port\n");
1773 err = mlx4_en_moderation_update(priv);
1776 mutex_unlock(&mdev->state_lock);
1780 static int mlx4_en_get_ts_info(struct net_device *dev,
1781 struct ethtool_ts_info *info)
1783 struct mlx4_en_priv *priv = netdev_priv(dev);
1784 struct mlx4_en_dev *mdev = priv->mdev;
1787 ret = ethtool_op_get_ts_info(dev, info);
1791 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1792 info->so_timestamping |=
1793 SOF_TIMESTAMPING_TX_HARDWARE |
1794 SOF_TIMESTAMPING_RX_HARDWARE |
1795 SOF_TIMESTAMPING_RAW_HARDWARE;
1798 (1 << HWTSTAMP_TX_OFF) |
1799 (1 << HWTSTAMP_TX_ON);
1802 (1 << HWTSTAMP_FILTER_NONE) |
1803 (1 << HWTSTAMP_FILTER_ALL);
1805 if (mdev->ptp_clock)
1806 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1812 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1814 struct mlx4_en_priv *priv = netdev_priv(dev);
1815 struct mlx4_en_dev *mdev = priv->mdev;
1816 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1817 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1818 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1819 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1823 if (bf_enabled_new != bf_enabled_old) {
1824 if (bf_enabled_new) {
1825 bool bf_supported = true;
1827 for (i = 0; i < priv->tx_ring_num; i++)
1828 bf_supported &= priv->tx_ring[i]->bf_alloced;
1830 if (!bf_supported) {
1831 en_err(priv, "BlueFlame is not supported\n");
1835 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1837 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1840 for (i = 0; i < priv->tx_ring_num; i++)
1841 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1843 en_info(priv, "BlueFlame %s\n",
1844 bf_enabled_new ? "Enabled" : "Disabled");
1847 if (phv_enabled_new != phv_enabled_old) {
1848 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1851 else if (phv_enabled_new)
1852 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1854 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1855 en_info(priv, "PHV bit %s\n",
1856 phv_enabled_new ? "Enabled" : "Disabled");
1861 static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1863 struct mlx4_en_priv *priv = netdev_priv(dev);
1865 return priv->pflags;
1868 static int mlx4_en_get_tunable(struct net_device *dev,
1869 const struct ethtool_tunable *tuna,
1872 const struct mlx4_en_priv *priv = netdev_priv(dev);
1876 case ETHTOOL_TX_COPYBREAK:
1877 *(u32 *)data = priv->prof->inline_thold;
1887 static int mlx4_en_set_tunable(struct net_device *dev,
1888 const struct ethtool_tunable *tuna,
1891 struct mlx4_en_priv *priv = netdev_priv(dev);
1895 case ETHTOOL_TX_COPYBREAK:
1897 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1900 priv->prof->inline_thold = val;
1910 static int mlx4_en_get_module_info(struct net_device *dev,
1911 struct ethtool_modinfo *modinfo)
1913 struct mlx4_en_priv *priv = netdev_priv(dev);
1914 struct mlx4_en_dev *mdev = priv->mdev;
1918 /* Read first 2 bytes to get Module & REV ID */
1919 ret = mlx4_get_module_info(mdev->dev, priv->port,
1920 0/*offset*/, 2/*size*/, data);
1924 switch (data[0] /* identifier */) {
1925 case MLX4_MODULE_ID_QSFP:
1926 modinfo->type = ETH_MODULE_SFF_8436;
1927 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1929 case MLX4_MODULE_ID_QSFP_PLUS:
1930 if (data[1] >= 0x3) { /* revision id */
1931 modinfo->type = ETH_MODULE_SFF_8636;
1932 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1934 modinfo->type = ETH_MODULE_SFF_8436;
1935 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1938 case MLX4_MODULE_ID_QSFP28:
1939 modinfo->type = ETH_MODULE_SFF_8636;
1940 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1942 case MLX4_MODULE_ID_SFP:
1943 modinfo->type = ETH_MODULE_SFF_8472;
1944 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1953 static int mlx4_en_get_module_eeprom(struct net_device *dev,
1954 struct ethtool_eeprom *ee,
1957 struct mlx4_en_priv *priv = netdev_priv(dev);
1958 struct mlx4_en_dev *mdev = priv->mdev;
1959 int offset = ee->offset;
1965 memset(data, 0, ee->len);
1967 while (i < ee->len) {
1969 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1970 i, offset, ee->len - i);
1972 ret = mlx4_get_module_info(mdev->dev, priv->port,
1973 offset, ee->len - i, data + i);
1975 if (!ret) /* Done reading */
1980 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
1981 i, offset, ee->len - i, ret);
1991 static int mlx4_en_set_phys_id(struct net_device *dev,
1992 enum ethtool_phys_id_state state)
1995 u16 beacon_duration;
1996 struct mlx4_en_priv *priv = netdev_priv(dev);
1997 struct mlx4_en_dev *mdev = priv->mdev;
1999 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
2003 case ETHTOOL_ID_ACTIVE:
2004 beacon_duration = PORT_BEACON_MAX_LIMIT;
2006 case ETHTOOL_ID_INACTIVE:
2007 beacon_duration = 0;
2013 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
2017 const struct ethtool_ops mlx4_en_ethtool_ops = {
2018 .get_drvinfo = mlx4_en_get_drvinfo,
2019 .get_settings = mlx4_en_get_settings,
2020 .set_settings = mlx4_en_set_settings,
2021 .get_link = ethtool_op_get_link,
2022 .get_strings = mlx4_en_get_strings,
2023 .get_sset_count = mlx4_en_get_sset_count,
2024 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2025 .self_test = mlx4_en_self_test,
2026 .set_phys_id = mlx4_en_set_phys_id,
2027 .get_wol = mlx4_en_get_wol,
2028 .set_wol = mlx4_en_set_wol,
2029 .get_msglevel = mlx4_en_get_msglevel,
2030 .set_msglevel = mlx4_en_set_msglevel,
2031 .get_coalesce = mlx4_en_get_coalesce,
2032 .set_coalesce = mlx4_en_set_coalesce,
2033 .get_pauseparam = mlx4_en_get_pauseparam,
2034 .set_pauseparam = mlx4_en_set_pauseparam,
2035 .get_ringparam = mlx4_en_get_ringparam,
2036 .set_ringparam = mlx4_en_set_ringparam,
2037 .get_rxnfc = mlx4_en_get_rxnfc,
2038 .set_rxnfc = mlx4_en_set_rxnfc,
2039 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2040 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2041 .get_rxfh = mlx4_en_get_rxfh,
2042 .set_rxfh = mlx4_en_set_rxfh,
2043 .get_channels = mlx4_en_get_channels,
2044 .set_channels = mlx4_en_set_channels,
2045 .get_ts_info = mlx4_en_get_ts_info,
2046 .set_priv_flags = mlx4_en_set_priv_flags,
2047 .get_priv_flags = mlx4_en_get_priv_flags,
2048 .get_tunable = mlx4_en_get_tunable,
2049 .set_tunable = mlx4_en_set_tunable,
2050 .get_module_info = mlx4_en_get_module_info,
2051 .get_module_eeprom = mlx4_en_get_module_eeprom