2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kernel.h>
35 #include <linux/ethtool.h>
36 #include <linux/netdevice.h>
37 #include <linux/mlx4/driver.h>
38 #include <linux/mlx4/device.h>
41 #include <linux/bitmap.h>
46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
50 int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
55 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
56 for (i = 0; i < priv->tx_ring_num[t]; i++) {
57 priv->tx_cq[t][i]->moder_cnt = priv->tx_frames;
58 priv->tx_cq[t][i]->moder_time = priv->tx_usecs;
60 err = mlx4_en_set_cq_moder(priv,
68 if (priv->adaptive_rx_coal)
71 for (i = 0; i < priv->rx_ring_num; i++) {
72 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
73 priv->rx_cq[i]->moder_time = priv->rx_usecs;
74 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
76 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
86 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
88 struct mlx4_en_priv *priv = netdev_priv(dev);
89 struct mlx4_en_dev *mdev = priv->mdev;
91 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
92 strlcpy(drvinfo->version, DRV_VERSION,
93 sizeof(drvinfo->version));
94 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
96 (u16) (mdev->dev->caps.fw_ver >> 32),
97 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
98 (u16) (mdev->dev->caps.fw_ver & 0xffff));
99 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
100 sizeof(drvinfo->bus_info));
103 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
108 static const char main_strings[][ETH_GSTRING_LEN] = {
109 /* main statistics */
110 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
111 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
112 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
113 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
114 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
115 "tx_heartbeat_errors", "tx_window_errors",
117 /* port statistics */
120 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_pages",
121 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
129 /* priority flow control statistics rx */
130 "rx_pause_prio_0", "rx_pause_duration_prio_0",
131 "rx_pause_transition_prio_0",
132 "rx_pause_prio_1", "rx_pause_duration_prio_1",
133 "rx_pause_transition_prio_1",
134 "rx_pause_prio_2", "rx_pause_duration_prio_2",
135 "rx_pause_transition_prio_2",
136 "rx_pause_prio_3", "rx_pause_duration_prio_3",
137 "rx_pause_transition_prio_3",
138 "rx_pause_prio_4", "rx_pause_duration_prio_4",
139 "rx_pause_transition_prio_4",
140 "rx_pause_prio_5", "rx_pause_duration_prio_5",
141 "rx_pause_transition_prio_5",
142 "rx_pause_prio_6", "rx_pause_duration_prio_6",
143 "rx_pause_transition_prio_6",
144 "rx_pause_prio_7", "rx_pause_duration_prio_7",
145 "rx_pause_transition_prio_7",
147 /* flow control statistics rx */
148 "rx_pause", "rx_pause_duration", "rx_pause_transition",
150 /* priority flow control statistics tx */
151 "tx_pause_prio_0", "tx_pause_duration_prio_0",
152 "tx_pause_transition_prio_0",
153 "tx_pause_prio_1", "tx_pause_duration_prio_1",
154 "tx_pause_transition_prio_1",
155 "tx_pause_prio_2", "tx_pause_duration_prio_2",
156 "tx_pause_transition_prio_2",
157 "tx_pause_prio_3", "tx_pause_duration_prio_3",
158 "tx_pause_transition_prio_3",
159 "tx_pause_prio_4", "tx_pause_duration_prio_4",
160 "tx_pause_transition_prio_4",
161 "tx_pause_prio_5", "tx_pause_duration_prio_5",
162 "tx_pause_transition_prio_5",
163 "tx_pause_prio_6", "tx_pause_duration_prio_6",
164 "tx_pause_transition_prio_6",
165 "tx_pause_prio_7", "tx_pause_duration_prio_7",
166 "tx_pause_transition_prio_7",
168 /* flow control statistics tx */
169 "tx_pause", "tx_pause_duration", "tx_pause_transition",
171 /* packet statistics */
172 "rx_multicast_packets",
173 "rx_broadcast_packets",
175 "rx_in_range_length_error",
176 "rx_out_range_length_error",
177 "tx_multicast_packets",
178 "tx_broadcast_packets",
179 "rx_prio_0_packets", "rx_prio_0_bytes",
180 "rx_prio_1_packets", "rx_prio_1_bytes",
181 "rx_prio_2_packets", "rx_prio_2_bytes",
182 "rx_prio_3_packets", "rx_prio_3_bytes",
183 "rx_prio_4_packets", "rx_prio_4_bytes",
184 "rx_prio_5_packets", "rx_prio_5_bytes",
185 "rx_prio_6_packets", "rx_prio_6_bytes",
186 "rx_prio_7_packets", "rx_prio_7_bytes",
187 "rx_novlan_packets", "rx_novlan_bytes",
188 "tx_prio_0_packets", "tx_prio_0_bytes",
189 "tx_prio_1_packets", "tx_prio_1_bytes",
190 "tx_prio_2_packets", "tx_prio_2_bytes",
191 "tx_prio_3_packets", "tx_prio_3_bytes",
192 "tx_prio_4_packets", "tx_prio_4_bytes",
193 "tx_prio_5_packets", "tx_prio_5_bytes",
194 "tx_prio_6_packets", "tx_prio_6_bytes",
195 "tx_prio_7_packets", "tx_prio_7_bytes",
196 "tx_novlan_packets", "tx_novlan_bytes",
204 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
212 static u32 mlx4_en_get_msglevel(struct net_device *dev)
214 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
217 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
219 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
222 static void mlx4_en_get_wol(struct net_device *netdev,
223 struct ethtool_wolinfo *wol)
225 struct mlx4_en_priv *priv = netdev_priv(netdev);
226 struct mlx4_caps *caps = &priv->mdev->dev->caps;
231 if ((priv->port < 1) || (priv->port > 2)) {
232 en_err(priv, "Failed to get WoL information\n");
236 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
237 MLX4_DEV_CAP_FLAG_WOL_PORT2;
239 if (!(caps->flags & mask)) {
245 if (caps->wol_port[priv->port])
246 wol->supported = WAKE_MAGIC;
250 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
252 en_err(priv, "Failed to get WoL information\n");
256 if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC))
257 wol->wolopts = WAKE_MAGIC;
262 static int mlx4_en_set_wol(struct net_device *netdev,
263 struct ethtool_wolinfo *wol)
265 struct mlx4_en_priv *priv = netdev_priv(netdev);
270 if ((priv->port < 1) || (priv->port > 2))
273 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
274 MLX4_DEV_CAP_FLAG_WOL_PORT2;
276 if (!(priv->mdev->dev->caps.flags & mask))
279 if (wol->supported & ~WAKE_MAGIC)
282 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
284 en_err(priv, "Failed to get WoL info, unable to modify\n");
288 if (wol->wolopts & WAKE_MAGIC) {
289 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
292 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
293 config |= MLX4_EN_WOL_DO_MODIFY;
296 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
298 en_err(priv, "Failed to set WoL information\n");
303 struct bitmap_iterator {
304 unsigned long *stats_bitmap;
306 unsigned int iterator;
307 bool advance_array; /* if set, force no increments */
310 static inline void bitmap_iterator_init(struct bitmap_iterator *h,
311 unsigned long *stats_bitmap,
315 h->advance_array = !bitmap_empty(stats_bitmap, count);
316 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
318 h->stats_bitmap = stats_bitmap;
321 static inline int bitmap_iterator_test(struct bitmap_iterator *h)
323 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
326 static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
328 return h->iterator++;
331 static inline unsigned int
332 bitmap_iterator_count(struct bitmap_iterator *h)
337 static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
339 struct mlx4_en_priv *priv = netdev_priv(dev);
340 struct bitmap_iterator it;
342 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
346 return bitmap_iterator_count(&it) +
347 (priv->tx_ring_num[TX] * 2) +
348 (priv->rx_ring_num * (3 + NUM_XDP_STATS));
350 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
351 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
352 case ETH_SS_PRIV_FLAGS:
353 return ARRAY_SIZE(mlx4_en_priv_flags);
359 static void mlx4_en_get_ethtool_stats(struct net_device *dev,
360 struct ethtool_stats *stats, uint64_t *data)
362 struct mlx4_en_priv *priv = netdev_priv(dev);
365 struct bitmap_iterator it;
367 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
369 spin_lock_bh(&priv->stats_lock);
371 mlx4_en_fold_software_stats(dev);
373 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
374 if (bitmap_iterator_test(&it))
375 data[index++] = ((unsigned long *)&dev->stats)[i];
377 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
378 if (bitmap_iterator_test(&it))
379 data[index++] = ((unsigned long *)&priv->port_stats)[i];
381 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
382 if (bitmap_iterator_test(&it))
384 ((unsigned long *)&priv->pf_stats)[i];
386 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
387 i++, bitmap_iterator_inc(&it))
388 if (bitmap_iterator_test(&it))
390 ((u64 *)&priv->rx_priority_flowstats)[i];
392 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
393 if (bitmap_iterator_test(&it))
394 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
396 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
397 i++, bitmap_iterator_inc(&it))
398 if (bitmap_iterator_test(&it))
400 ((u64 *)&priv->tx_priority_flowstats)[i];
402 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
403 if (bitmap_iterator_test(&it))
404 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
406 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
407 if (bitmap_iterator_test(&it))
408 data[index++] = ((unsigned long *)&priv->pkstats)[i];
410 for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it))
411 if (bitmap_iterator_test(&it))
412 data[index++] = ((unsigned long *)&priv->xdp_stats)[i];
414 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
415 data[index++] = priv->tx_ring[TX][i]->packets;
416 data[index++] = priv->tx_ring[TX][i]->bytes;
418 for (i = 0; i < priv->rx_ring_num; i++) {
419 data[index++] = priv->rx_ring[i]->packets;
420 data[index++] = priv->rx_ring[i]->bytes;
421 data[index++] = priv->rx_ring[i]->dropped;
422 data[index++] = priv->rx_ring[i]->xdp_drop;
423 data[index++] = priv->rx_ring[i]->xdp_tx;
424 data[index++] = priv->rx_ring[i]->xdp_tx_full;
426 spin_unlock_bh(&priv->stats_lock);
430 static void mlx4_en_self_test(struct net_device *dev,
431 struct ethtool_test *etest, u64 *buf)
433 mlx4_en_ex_selftest(dev, &etest->flags, buf);
436 static void mlx4_en_get_strings(struct net_device *dev,
437 uint32_t stringset, uint8_t *data)
439 struct mlx4_en_priv *priv = netdev_priv(dev);
442 struct bitmap_iterator it;
444 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
448 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
449 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
450 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
451 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
452 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
456 /* Add main counters */
457 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
458 bitmap_iterator_inc(&it))
459 if (bitmap_iterator_test(&it))
460 strcpy(data + (index++) * ETH_GSTRING_LEN,
461 main_strings[strings]);
463 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
464 bitmap_iterator_inc(&it))
465 if (bitmap_iterator_test(&it))
466 strcpy(data + (index++) * ETH_GSTRING_LEN,
467 main_strings[strings]);
469 for (i = 0; i < NUM_PF_STATS; i++, strings++,
470 bitmap_iterator_inc(&it))
471 if (bitmap_iterator_test(&it))
472 strcpy(data + (index++) * ETH_GSTRING_LEN,
473 main_strings[strings]);
475 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
476 bitmap_iterator_inc(&it))
477 if (bitmap_iterator_test(&it))
478 strcpy(data + (index++) * ETH_GSTRING_LEN,
479 main_strings[strings]);
481 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
482 bitmap_iterator_inc(&it))
483 if (bitmap_iterator_test(&it))
484 strcpy(data + (index++) * ETH_GSTRING_LEN,
485 main_strings[strings]);
487 for (i = 0; i < NUM_XDP_STATS; i++, strings++,
488 bitmap_iterator_inc(&it))
489 if (bitmap_iterator_test(&it))
490 strcpy(data + (index++) * ETH_GSTRING_LEN,
491 main_strings[strings]);
493 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
494 sprintf(data + (index++) * ETH_GSTRING_LEN,
496 sprintf(data + (index++) * ETH_GSTRING_LEN,
499 for (i = 0; i < priv->rx_ring_num; i++) {
500 sprintf(data + (index++) * ETH_GSTRING_LEN,
502 sprintf(data + (index++) * ETH_GSTRING_LEN,
504 sprintf(data + (index++) * ETH_GSTRING_LEN,
506 sprintf(data + (index++) * ETH_GSTRING_LEN,
508 sprintf(data + (index++) * ETH_GSTRING_LEN,
510 sprintf(data + (index++) * ETH_GSTRING_LEN,
511 "rx%d_xdp_tx_full", i);
514 case ETH_SS_PRIV_FLAGS:
515 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
516 strcpy(data + i * ETH_GSTRING_LEN,
517 mlx4_en_priv_flags[i]);
523 static u32 mlx4_en_autoneg_get(struct net_device *dev)
525 struct mlx4_en_priv *priv = netdev_priv(dev);
526 struct mlx4_en_dev *mdev = priv->mdev;
527 u32 autoneg = AUTONEG_DISABLE;
529 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
530 (priv->port_state.flags & MLX4_EN_PORT_ANE))
531 autoneg = AUTONEG_ENABLE;
536 static void ptys2ethtool_update_supported_port(unsigned long *mask,
537 struct mlx4_ptys_reg *ptys_reg)
539 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
541 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
542 | MLX4_PROT_MASK(MLX4_1000BASE_T)
543 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
544 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
545 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
546 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
547 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
548 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
549 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
550 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
551 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
552 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
553 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
554 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
555 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
556 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
557 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
558 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
562 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
564 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
566 if (!eth_proto) /* link down */
567 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
569 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
570 | MLX4_PROT_MASK(MLX4_1000BASE_T)
571 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
575 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
576 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
577 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
578 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
582 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
583 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
584 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
588 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
589 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
590 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
591 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
592 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
593 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
599 #define MLX4_LINK_MODES_SZ \
600 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
602 enum ethtool_report {
607 struct ptys2ethtool_config {
608 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
609 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
613 static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
614 enum ethtool_report report)
618 return cfg->supported;
620 return cfg->advertised;
625 #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
627 struct ptys2ethtool_config *cfg; \
628 const unsigned int modes[] = { __VA_ARGS__ }; \
630 cfg = &ptys2ethtool_map[reg_]; \
631 cfg->speed = speed_; \
632 bitmap_zero(cfg->supported, \
633 __ETHTOOL_LINK_MODE_MASK_NBITS); \
634 bitmap_zero(cfg->advertised, \
635 __ETHTOOL_LINK_MODE_MASK_NBITS); \
636 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
637 __set_bit(modes[i], cfg->supported); \
638 __set_bit(modes[i], cfg->advertised); \
642 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
643 static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
645 void __init mlx4_en_init_ptys2ethtool_map(void)
647 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
648 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
649 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
650 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
651 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
652 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
653 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
654 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
655 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
656 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
657 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
658 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
659 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
660 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
661 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
662 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
663 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
664 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
665 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
666 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
667 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
668 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
669 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
670 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
671 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
672 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
673 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
674 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
675 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
676 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
677 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
678 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
679 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
680 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
681 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
684 static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
686 enum ethtool_report report)
689 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
690 if (eth_proto & MLX4_PROT_MASK(i))
691 bitmap_or(link_modes, link_modes,
692 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
694 __ETHTOOL_LINK_MODE_MASK_NBITS);
698 static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
699 enum ethtool_report report)
704 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
705 if (bitmap_intersects(
706 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
709 __ETHTOOL_LINK_MODE_MASK_NBITS))
710 ptys_modes |= 1 << i;
715 /* Convert actual speed (SPEED_XXX) to ptys link modes */
716 static u32 speed2ptys_link_modes(u32 speed)
721 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
722 if (ptys2ethtool_map[i].speed == speed)
723 ptys_modes |= 1 << i;
729 ethtool_get_ptys_link_ksettings(struct net_device *dev,
730 struct ethtool_link_ksettings *link_ksettings)
732 struct mlx4_en_priv *priv = netdev_priv(dev);
733 struct mlx4_ptys_reg ptys_reg;
737 memset(&ptys_reg, 0, sizeof(ptys_reg));
738 ptys_reg.local_port = priv->port;
739 ptys_reg.proto_mask = MLX4_PTYS_EN;
740 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
741 MLX4_ACCESS_REG_QUERY, &ptys_reg);
743 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
747 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
748 ptys_reg.proto_mask);
749 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
750 be32_to_cpu(ptys_reg.eth_proto_cap));
751 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
752 be32_to_cpu(ptys_reg.eth_proto_admin));
753 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
754 be32_to_cpu(ptys_reg.eth_proto_oper));
755 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
756 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
758 /* reset supported/advertising masks */
759 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
760 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
762 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
765 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
766 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
767 eth_proto, SUPPORTED);
769 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
770 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
771 eth_proto, ADVERTISED);
773 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
775 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
778 if (priv->prof->tx_pause)
779 ethtool_link_ksettings_add_link_mode(link_ksettings,
781 if (priv->prof->tx_pause ^ priv->prof->rx_pause)
782 ethtool_link_ksettings_add_link_mode(link_ksettings,
783 advertising, Asym_Pause);
785 link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
787 if (mlx4_en_autoneg_get(dev)) {
788 ethtool_link_ksettings_add_link_mode(link_ksettings,
790 ethtool_link_ksettings_add_link_mode(link_ksettings,
791 advertising, Autoneg);
794 link_ksettings->base.autoneg
795 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
796 AUTONEG_ENABLE : AUTONEG_DISABLE;
798 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
800 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
801 ptys2ethtool_update_link_modes(
802 link_ksettings->link_modes.lp_advertising,
803 eth_proto, ADVERTISED);
804 if (priv->port_state.flags & MLX4_EN_PORT_ANC)
805 ethtool_link_ksettings_add_link_mode(link_ksettings,
806 lp_advertising, Autoneg);
808 link_ksettings->base.phy_address = 0;
809 link_ksettings->base.mdio_support = 0;
810 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
811 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
817 ethtool_get_default_link_ksettings(
818 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
820 struct mlx4_en_priv *priv = netdev_priv(dev);
823 link_ksettings->base.autoneg = AUTONEG_DISABLE;
825 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
826 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
829 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
830 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
833 trans_type = priv->port_state.transceiver;
834 if (trans_type > 0 && trans_type <= 0xC) {
835 link_ksettings->base.port = PORT_FIBRE;
836 ethtool_link_ksettings_add_link_mode(link_ksettings,
838 ethtool_link_ksettings_add_link_mode(link_ksettings,
840 } else if (trans_type == 0x80 || trans_type == 0) {
841 link_ksettings->base.port = PORT_TP;
842 ethtool_link_ksettings_add_link_mode(link_ksettings,
844 ethtool_link_ksettings_add_link_mode(link_ksettings,
847 link_ksettings->base.port = -1;
852 mlx4_en_get_link_ksettings(struct net_device *dev,
853 struct ethtool_link_ksettings *link_ksettings)
855 struct mlx4_en_priv *priv = netdev_priv(dev);
858 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
861 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
862 priv->port_state.flags & MLX4_EN_PORT_ANC,
863 priv->port_state.flags & MLX4_EN_PORT_ANE);
865 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
866 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
867 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
868 ethtool_get_default_link_ksettings(dev, link_ksettings);
870 if (netif_carrier_ok(dev)) {
871 link_ksettings->base.speed = priv->port_state.link_speed;
872 link_ksettings->base.duplex = DUPLEX_FULL;
874 link_ksettings->base.speed = SPEED_UNKNOWN;
875 link_ksettings->base.duplex = DUPLEX_UNKNOWN;
880 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
881 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
884 __be32 proto_admin = 0;
886 if (!speed) { /* Speed = 0 ==> Reset Link modes */
887 proto_admin = proto_cap;
888 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
889 be32_to_cpu(proto_cap));
891 u32 ptys_link_modes = speed2ptys_link_modes(speed);
893 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
894 en_info(priv, "Setting Speed to %d\n", speed);
900 mlx4_en_set_link_ksettings(struct net_device *dev,
901 const struct ethtool_link_ksettings *link_ksettings)
903 struct mlx4_en_priv *priv = netdev_priv(dev);
904 struct mlx4_ptys_reg ptys_reg;
909 u32 ptys_adv = ethtool2ptys_link_modes(
910 link_ksettings->link_modes.advertising, ADVERTISED);
911 const int speed = link_ksettings->base.speed;
914 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
915 speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
916 link_ksettings->link_modes.advertising,
917 link_ksettings->base.autoneg,
918 link_ksettings->base.duplex);
920 if (!(priv->mdev->dev->caps.flags2 &
921 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
922 (link_ksettings->base.duplex == DUPLEX_HALF))
925 memset(&ptys_reg, 0, sizeof(ptys_reg));
926 ptys_reg.local_port = priv->port;
927 ptys_reg.proto_mask = MLX4_PTYS_EN;
928 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
929 MLX4_ACCESS_REG_QUERY, &ptys_reg);
931 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
936 cur_autoneg = ptys_reg.flags & MLX4_PTYS_AN_DISABLE_ADMIN ?
937 AUTONEG_DISABLE : AUTONEG_ENABLE;
939 if (link_ksettings->base.autoneg == AUTONEG_DISABLE) {
940 proto_admin = speed_set_ptys_admin(priv, speed,
941 ptys_reg.eth_proto_cap);
942 if ((be32_to_cpu(proto_admin) &
943 (MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII) |
944 MLX4_PROT_MASK(MLX4_1000BASE_KX))) &&
945 (ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP))
946 ptys_reg.flags |= MLX4_PTYS_AN_DISABLE_ADMIN;
948 proto_admin = cpu_to_be32(ptys_adv);
949 ptys_reg.flags &= ~MLX4_PTYS_AN_DISABLE_ADMIN;
952 proto_admin &= ptys_reg.eth_proto_cap;
954 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
955 return -EINVAL; /* nothing to change due to bad input */
958 if ((proto_admin == ptys_reg.eth_proto_admin) &&
959 ((ptys_reg.flags & MLX4_PTYS_AN_DISABLE_CAP) &&
960 (link_ksettings->base.autoneg == cur_autoneg)))
961 return 0; /* Nothing to change */
963 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
964 be32_to_cpu(proto_admin));
966 ptys_reg.eth_proto_admin = proto_admin;
967 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
970 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
971 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
975 mutex_lock(&priv->mdev->state_lock);
977 en_warn(priv, "Port link mode changed, restarting port...\n");
978 mlx4_en_stop_port(dev, 1);
979 if (mlx4_en_start_port(dev))
980 en_err(priv, "Failed restarting port %d\n", priv->port);
982 mutex_unlock(&priv->mdev->state_lock);
986 static int mlx4_en_get_coalesce(struct net_device *dev,
987 struct ethtool_coalesce *coal)
989 struct mlx4_en_priv *priv = netdev_priv(dev);
991 coal->tx_coalesce_usecs = priv->tx_usecs;
992 coal->tx_max_coalesced_frames = priv->tx_frames;
993 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
995 coal->rx_coalesce_usecs = priv->rx_usecs;
996 coal->rx_max_coalesced_frames = priv->rx_frames;
998 coal->pkt_rate_low = priv->pkt_rate_low;
999 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
1000 coal->pkt_rate_high = priv->pkt_rate_high;
1001 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
1002 coal->rate_sample_interval = priv->sample_interval;
1003 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
1008 static int mlx4_en_set_coalesce(struct net_device *dev,
1009 struct ethtool_coalesce *coal)
1011 struct mlx4_en_priv *priv = netdev_priv(dev);
1013 if (!coal->tx_max_coalesced_frames_irq)
1016 if (coal->tx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
1017 coal->rx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
1018 coal->rx_coalesce_usecs_low > MLX4_EN_MAX_COAL_TIME ||
1019 coal->rx_coalesce_usecs_high > MLX4_EN_MAX_COAL_TIME) {
1020 netdev_info(dev, "%s: maximum coalesce time supported is %d usecs\n",
1021 __func__, MLX4_EN_MAX_COAL_TIME);
1025 if (coal->tx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS ||
1026 coal->rx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS) {
1027 netdev_info(dev, "%s: maximum coalesced frames supported is %d\n",
1028 __func__, MLX4_EN_MAX_COAL_PKTS);
1032 priv->rx_frames = (coal->rx_max_coalesced_frames ==
1033 MLX4_EN_AUTO_CONF) ?
1034 MLX4_EN_RX_COAL_TARGET :
1035 coal->rx_max_coalesced_frames;
1036 priv->rx_usecs = (coal->rx_coalesce_usecs ==
1037 MLX4_EN_AUTO_CONF) ?
1038 MLX4_EN_RX_COAL_TIME :
1039 coal->rx_coalesce_usecs;
1041 /* Setting TX coalescing parameters */
1042 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
1043 coal->tx_max_coalesced_frames != priv->tx_frames) {
1044 priv->tx_usecs = coal->tx_coalesce_usecs;
1045 priv->tx_frames = coal->tx_max_coalesced_frames;
1048 /* Set adaptive coalescing params */
1049 priv->pkt_rate_low = coal->pkt_rate_low;
1050 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
1051 priv->pkt_rate_high = coal->pkt_rate_high;
1052 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
1053 priv->sample_interval = coal->rate_sample_interval;
1054 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
1055 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
1057 return mlx4_en_moderation_update(priv);
1060 static int mlx4_en_set_pauseparam(struct net_device *dev,
1061 struct ethtool_pauseparam *pause)
1063 struct mlx4_en_priv *priv = netdev_priv(dev);
1064 struct mlx4_en_dev *mdev = priv->mdev;
1065 u8 tx_pause, tx_ppp, rx_pause, rx_ppp;
1071 tx_pause = !!(pause->tx_pause);
1072 rx_pause = !!(pause->rx_pause);
1073 rx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->rx_ppp;
1074 tx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->tx_ppp;
1076 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1077 priv->rx_skb_size + ETH_FCS_LEN,
1078 tx_pause, tx_ppp, rx_pause, rx_ppp);
1080 en_err(priv, "Failed setting pause params, err = %d\n", err);
1084 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1085 rx_ppp, rx_pause, tx_ppp, tx_pause);
1087 priv->prof->tx_pause = tx_pause;
1088 priv->prof->rx_pause = rx_pause;
1089 priv->prof->tx_ppp = tx_ppp;
1090 priv->prof->rx_ppp = rx_ppp;
1095 static void mlx4_en_get_pauseparam(struct net_device *dev,
1096 struct ethtool_pauseparam *pause)
1098 struct mlx4_en_priv *priv = netdev_priv(dev);
1100 pause->tx_pause = priv->prof->tx_pause;
1101 pause->rx_pause = priv->prof->rx_pause;
1104 static int mlx4_en_set_ringparam(struct net_device *dev,
1105 struct ethtool_ringparam *param)
1107 struct mlx4_en_priv *priv = netdev_priv(dev);
1108 struct mlx4_en_dev *mdev = priv->mdev;
1109 struct mlx4_en_port_profile new_prof;
1110 struct mlx4_en_priv *tmp;
1111 u32 rx_size, tx_size;
1115 if (param->rx_jumbo_pending || param->rx_mini_pending)
1118 rx_size = roundup_pow_of_two(param->rx_pending);
1119 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
1120 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
1121 tx_size = roundup_pow_of_two(param->tx_pending);
1122 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
1123 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
1125 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1126 priv->rx_ring[0]->size) &&
1127 tx_size == priv->tx_ring[TX][0]->size)
1130 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1134 mutex_lock(&mdev->state_lock);
1135 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1136 new_prof.tx_ring_size = tx_size;
1137 new_prof.rx_ring_size = rx_size;
1138 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1142 if (priv->port_up) {
1144 mlx4_en_stop_port(dev, 1);
1147 mlx4_en_safe_replace_resources(priv, tmp);
1150 err = mlx4_en_start_port(dev);
1152 en_err(priv, "Failed starting port\n");
1155 err = mlx4_en_moderation_update(priv);
1158 mutex_unlock(&mdev->state_lock);
1162 static void mlx4_en_get_ringparam(struct net_device *dev,
1163 struct ethtool_ringparam *param)
1165 struct mlx4_en_priv *priv = netdev_priv(dev);
1167 memset(param, 0, sizeof(*param));
1168 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1169 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1170 param->rx_pending = priv->port_up ?
1171 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1172 param->tx_pending = priv->tx_ring[TX][0]->size;
1175 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1177 struct mlx4_en_priv *priv = netdev_priv(dev);
1179 return rounddown_pow_of_two(priv->rx_ring_num);
1182 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1184 return MLX4_EN_RSS_KEY_SIZE;
1187 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1189 struct mlx4_en_priv *priv = netdev_priv(dev);
1191 /* check if requested function is supported by the device */
1192 if (hfunc == ETH_RSS_HASH_TOP) {
1193 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1195 if (!(dev->features & NETIF_F_RXHASH))
1196 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1198 } else if (hfunc == ETH_RSS_HASH_XOR) {
1199 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1201 if (dev->features & NETIF_F_RXHASH)
1202 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1209 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1212 struct mlx4_en_priv *priv = netdev_priv(dev);
1213 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1217 rss_rings = priv->prof->rss_rings ?: n;
1218 rss_rings = rounddown_pow_of_two(rss_rings);
1220 for (i = 0; i < n; i++) {
1223 ring_index[i] = i % rss_rings;
1226 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1228 *hfunc = priv->rss_hash_fn;
1232 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1233 const u8 *key, const u8 hfunc)
1235 struct mlx4_en_priv *priv = netdev_priv(dev);
1236 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1237 struct mlx4_en_dev *mdev = priv->mdev;
1243 /* Calculate RSS table size and make sure flows are spread evenly
1246 for (i = 0; i < n; i++) {
1249 if (i > 0 && !ring_index[i] && !rss_rings)
1252 if (ring_index[i] != (i % (rss_rings ?: n)))
1259 /* RSS table size must be an order of 2 */
1260 if (!is_power_of_2(rss_rings))
1263 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1264 err = mlx4_en_check_rxfh_func(dev, hfunc);
1269 mutex_lock(&mdev->state_lock);
1270 if (priv->port_up) {
1272 mlx4_en_stop_port(dev, 1);
1276 priv->prof->rss_rings = rss_rings;
1278 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1279 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1280 priv->rss_hash_fn = hfunc;
1283 err = mlx4_en_start_port(dev);
1285 en_err(priv, "Failed starting port\n");
1288 mutex_unlock(&mdev->state_lock);
1292 #define all_zeros_or_all_ones(field) \
1293 ((field) == 0 || (field) == (__force typeof(field))-1)
1295 static int mlx4_en_validate_flow(struct net_device *dev,
1296 struct ethtool_rxnfc *cmd)
1298 struct ethtool_usrip4_spec *l3_mask;
1299 struct ethtool_tcpip4_spec *l4_mask;
1300 struct ethhdr *eth_mask;
1302 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1305 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1306 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1307 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1311 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1314 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1316 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1317 /* don't allow mask which isn't all 0 or 1 */
1318 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1319 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1320 !all_zeros_or_all_ones(l4_mask->psrc) ||
1321 !all_zeros_or_all_ones(l4_mask->pdst))
1325 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1326 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1327 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1328 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1329 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1330 !all_zeros_or_all_ones(l3_mask->ip4dst))
1334 eth_mask = &cmd->fs.m_u.ether_spec;
1335 /* source mac mask must not be set */
1336 if (!is_zero_ether_addr(eth_mask->h_source))
1339 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1340 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1343 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1350 if ((cmd->fs.flow_type & FLOW_EXT)) {
1351 if (cmd->fs.m_ext.vlan_etype ||
1352 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1354 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1355 cpu_to_be16(VLAN_VID_MASK)))
1358 if (cmd->fs.m_ext.vlan_tci) {
1359 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1368 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1369 struct list_head *rule_list_h,
1370 struct mlx4_spec_list *spec_l2,
1374 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1376 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1377 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1378 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1380 if ((cmd->fs.flow_type & FLOW_EXT) &&
1381 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1382 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1383 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1386 list_add_tail(&spec_l2->list, rule_list_h);
1391 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1392 struct ethtool_rxnfc *cmd,
1393 struct list_head *rule_list_h,
1394 struct mlx4_spec_list *spec_l2,
1398 unsigned char mac[ETH_ALEN];
1400 if (!ipv4_is_multicast(ipv4_dst)) {
1401 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1402 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1404 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1406 ip_eth_mc_map(ipv4_dst, mac);
1409 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1415 static int add_ip_rule(struct mlx4_en_priv *priv,
1416 struct ethtool_rxnfc *cmd,
1417 struct list_head *list_h)
1420 struct mlx4_spec_list *spec_l2 = NULL;
1421 struct mlx4_spec_list *spec_l3 = NULL;
1422 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1424 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1425 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1426 if (!spec_l2 || !spec_l3) {
1431 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1433 usr_ip4_spec.ip4dst);
1436 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1437 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1438 if (l3_mask->ip4src)
1439 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1440 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1441 if (l3_mask->ip4dst)
1442 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1443 list_add_tail(&spec_l3->list, list_h);
1453 static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1454 struct ethtool_rxnfc *cmd,
1455 struct list_head *list_h, int proto)
1458 struct mlx4_spec_list *spec_l2 = NULL;
1459 struct mlx4_spec_list *spec_l3 = NULL;
1460 struct mlx4_spec_list *spec_l4 = NULL;
1461 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1463 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1464 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1465 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1466 if (!spec_l2 || !spec_l3 || !spec_l4) {
1471 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1473 if (proto == TCP_V4_FLOW) {
1474 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1477 tcp_ip4_spec.ip4dst);
1480 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1481 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1482 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1483 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1484 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1486 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1489 udp_ip4_spec.ip4dst);
1492 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1493 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1494 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1495 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1496 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1499 if (l4_mask->ip4src)
1500 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1501 if (l4_mask->ip4dst)
1502 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1505 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1507 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1509 list_add_tail(&spec_l3->list, list_h);
1510 list_add_tail(&spec_l4->list, list_h);
1521 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1522 struct ethtool_rxnfc *cmd,
1523 struct list_head *rule_list_h)
1526 struct ethhdr *eth_spec;
1527 struct mlx4_spec_list *spec_l2;
1528 struct mlx4_en_priv *priv = netdev_priv(dev);
1530 err = mlx4_en_validate_flow(dev, cmd);
1534 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1536 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1540 eth_spec = &cmd->fs.h_u.ether_spec;
1541 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1542 ð_spec->h_dest[0]);
1543 spec_l2->eth.ether_type = eth_spec->h_proto;
1544 if (eth_spec->h_proto)
1545 spec_l2->eth.ether_type_enable = 1;
1548 err = add_ip_rule(priv, cmd, rule_list_h);
1551 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1554 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1561 static int mlx4_en_flow_replace(struct net_device *dev,
1562 struct ethtool_rxnfc *cmd)
1565 struct mlx4_en_priv *priv = netdev_priv(dev);
1566 struct ethtool_flow_id *loc_rule;
1567 struct mlx4_spec_list *spec, *tmp_spec;
1571 struct mlx4_net_trans_rule rule = {
1572 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1574 .allow_loopback = 1,
1575 .promisc_mode = MLX4_FS_REGULAR,
1578 rule.port = priv->port;
1579 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1580 INIT_LIST_HEAD(&rule.list);
1582 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1583 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1584 qpn = priv->drop_qp.qpn;
1585 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1586 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1588 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1589 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1590 cmd->fs.ring_cookie);
1593 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1595 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1596 cmd->fs.ring_cookie);
1601 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1605 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1607 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1609 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1610 cmd->fs.location, loc_rule->id);
1614 memset(&loc_rule->flow_spec, 0,
1615 sizeof(struct ethtool_rx_flow_spec));
1616 list_del(&loc_rule->list);
1618 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1620 en_err(priv, "Fail to attach network rule at location %d\n",
1624 loc_rule->id = reg_id;
1625 memcpy(&loc_rule->flow_spec, &cmd->fs,
1626 sizeof(struct ethtool_rx_flow_spec));
1627 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1630 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1631 list_del(&spec->list);
1637 static int mlx4_en_flow_detach(struct net_device *dev,
1638 struct ethtool_rxnfc *cmd)
1641 struct ethtool_flow_id *rule;
1642 struct mlx4_en_priv *priv = netdev_priv(dev);
1644 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1647 rule = &priv->ethtool_rules[cmd->fs.location];
1653 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1655 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1656 cmd->fs.location, rule->id);
1660 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1661 list_del(&rule->list);
1667 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1671 struct ethtool_flow_id *rule;
1672 struct mlx4_en_priv *priv = netdev_priv(dev);
1674 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1677 rule = &priv->ethtool_rules[loc];
1679 memcpy(&cmd->fs, &rule->flow_spec,
1680 sizeof(struct ethtool_rx_flow_spec));
1687 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1691 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1692 if (priv->ethtool_rules[i].id)
1699 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1702 struct mlx4_en_priv *priv = netdev_priv(dev);
1703 struct mlx4_en_dev *mdev = priv->mdev;
1705 int i = 0, priority = 0;
1707 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1708 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1709 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1710 (mdev->dev->caps.steering_mode !=
1711 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1715 case ETHTOOL_GRXRINGS:
1716 cmd->data = priv->rx_ring_num;
1718 case ETHTOOL_GRXCLSRLCNT:
1719 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1721 case ETHTOOL_GRXCLSRULE:
1722 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1724 case ETHTOOL_GRXCLSRLALL:
1725 cmd->data = MAX_NUM_OF_FS_RULES;
1726 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1727 err = mlx4_en_get_flow(dev, cmd, i);
1729 rule_locs[priority++] = i;
1742 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1745 struct mlx4_en_priv *priv = netdev_priv(dev);
1746 struct mlx4_en_dev *mdev = priv->mdev;
1748 if (mdev->dev->caps.steering_mode !=
1749 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1753 case ETHTOOL_SRXCLSRLINS:
1754 err = mlx4_en_flow_replace(dev, cmd);
1756 case ETHTOOL_SRXCLSRLDEL:
1757 err = mlx4_en_flow_detach(dev, cmd);
1760 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1767 static void mlx4_en_get_channels(struct net_device *dev,
1768 struct ethtool_channels *channel)
1770 struct mlx4_en_priv *priv = netdev_priv(dev);
1772 channel->max_rx = MAX_RX_RINGS;
1773 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1775 channel->rx_count = priv->rx_ring_num;
1776 channel->tx_count = priv->tx_ring_num[TX] /
1780 static int mlx4_en_set_channels(struct net_device *dev,
1781 struct ethtool_channels *channel)
1783 struct mlx4_en_priv *priv = netdev_priv(dev);
1784 struct mlx4_en_dev *mdev = priv->mdev;
1785 struct mlx4_en_port_profile new_prof;
1786 struct mlx4_en_priv *tmp;
1792 if (!channel->tx_count || !channel->rx_count)
1795 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1799 mutex_lock(&mdev->state_lock);
1800 xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0;
1801 if (channel->tx_count * priv->prof->num_up + xdp_count >
1805 "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
1806 channel->tx_count * priv->prof->num_up + xdp_count,
1811 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1812 new_prof.num_tx_rings_p_up = channel->tx_count;
1813 new_prof.tx_ring_num[TX] = channel->tx_count * priv->prof->num_up;
1814 new_prof.tx_ring_num[TX_XDP] = xdp_count;
1815 new_prof.rx_ring_num = channel->rx_count;
1817 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1821 if (priv->port_up) {
1823 mlx4_en_stop_port(dev, 1);
1826 mlx4_en_safe_replace_resources(priv, tmp);
1828 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1830 up = (priv->prof->num_up == MLX4_EN_NUM_UP_LOW) ?
1831 0 : priv->prof->num_up;
1832 mlx4_en_setup_tc(dev, up);
1834 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]);
1835 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1838 err = mlx4_en_start_port(dev);
1840 en_err(priv, "Failed starting port\n");
1843 err = mlx4_en_moderation_update(priv);
1845 mutex_unlock(&mdev->state_lock);
1850 static int mlx4_en_get_ts_info(struct net_device *dev,
1851 struct ethtool_ts_info *info)
1853 struct mlx4_en_priv *priv = netdev_priv(dev);
1854 struct mlx4_en_dev *mdev = priv->mdev;
1857 ret = ethtool_op_get_ts_info(dev, info);
1861 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1862 info->so_timestamping |=
1863 SOF_TIMESTAMPING_TX_HARDWARE |
1864 SOF_TIMESTAMPING_RX_HARDWARE |
1865 SOF_TIMESTAMPING_RAW_HARDWARE;
1868 (1 << HWTSTAMP_TX_OFF) |
1869 (1 << HWTSTAMP_TX_ON);
1872 (1 << HWTSTAMP_FILTER_NONE) |
1873 (1 << HWTSTAMP_FILTER_ALL);
1875 if (mdev->ptp_clock)
1876 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1882 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1884 struct mlx4_en_priv *priv = netdev_priv(dev);
1885 struct mlx4_en_dev *mdev = priv->mdev;
1886 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1887 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1888 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1889 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1893 if (bf_enabled_new != bf_enabled_old) {
1896 if (bf_enabled_new) {
1897 bool bf_supported = true;
1899 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1900 for (i = 0; i < priv->tx_ring_num[t]; i++)
1902 priv->tx_ring[t][i]->bf_alloced;
1904 if (!bf_supported) {
1905 en_err(priv, "BlueFlame is not supported\n");
1909 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1911 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1914 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1915 for (i = 0; i < priv->tx_ring_num[t]; i++)
1916 priv->tx_ring[t][i]->bf_enabled =
1919 en_info(priv, "BlueFlame %s\n",
1920 bf_enabled_new ? "Enabled" : "Disabled");
1923 if (phv_enabled_new != phv_enabled_old) {
1924 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1927 else if (phv_enabled_new)
1928 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1930 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1931 en_info(priv, "PHV bit %s\n",
1932 phv_enabled_new ? "Enabled" : "Disabled");
1937 static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1939 struct mlx4_en_priv *priv = netdev_priv(dev);
1941 return priv->pflags;
1944 static int mlx4_en_get_tunable(struct net_device *dev,
1945 const struct ethtool_tunable *tuna,
1948 const struct mlx4_en_priv *priv = netdev_priv(dev);
1952 case ETHTOOL_TX_COPYBREAK:
1953 *(u32 *)data = priv->prof->inline_thold;
1963 static int mlx4_en_set_tunable(struct net_device *dev,
1964 const struct ethtool_tunable *tuna,
1967 struct mlx4_en_priv *priv = netdev_priv(dev);
1971 case ETHTOOL_TX_COPYBREAK:
1973 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1976 priv->prof->inline_thold = val;
1986 static int mlx4_en_get_module_info(struct net_device *dev,
1987 struct ethtool_modinfo *modinfo)
1989 struct mlx4_en_priv *priv = netdev_priv(dev);
1990 struct mlx4_en_dev *mdev = priv->mdev;
1994 /* Read first 2 bytes to get Module & REV ID */
1995 ret = mlx4_get_module_info(mdev->dev, priv->port,
1996 0/*offset*/, 2/*size*/, data);
2000 switch (data[0] /* identifier */) {
2001 case MLX4_MODULE_ID_QSFP:
2002 modinfo->type = ETH_MODULE_SFF_8436;
2003 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2005 case MLX4_MODULE_ID_QSFP_PLUS:
2006 if (data[1] >= 0x3) { /* revision id */
2007 modinfo->type = ETH_MODULE_SFF_8636;
2008 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2010 modinfo->type = ETH_MODULE_SFF_8436;
2011 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2014 case MLX4_MODULE_ID_QSFP28:
2015 modinfo->type = ETH_MODULE_SFF_8636;
2016 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2018 case MLX4_MODULE_ID_SFP:
2019 modinfo->type = ETH_MODULE_SFF_8472;
2020 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2029 static int mlx4_en_get_module_eeprom(struct net_device *dev,
2030 struct ethtool_eeprom *ee,
2033 struct mlx4_en_priv *priv = netdev_priv(dev);
2034 struct mlx4_en_dev *mdev = priv->mdev;
2035 int offset = ee->offset;
2041 memset(data, 0, ee->len);
2043 while (i < ee->len) {
2045 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
2046 i, offset, ee->len - i);
2048 ret = mlx4_get_module_info(mdev->dev, priv->port,
2049 offset, ee->len - i, data + i);
2051 if (!ret) /* Done reading */
2056 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
2057 i, offset, ee->len - i, ret);
2067 static int mlx4_en_set_phys_id(struct net_device *dev,
2068 enum ethtool_phys_id_state state)
2071 u16 beacon_duration;
2072 struct mlx4_en_priv *priv = netdev_priv(dev);
2073 struct mlx4_en_dev *mdev = priv->mdev;
2075 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
2079 case ETHTOOL_ID_ACTIVE:
2080 beacon_duration = PORT_BEACON_MAX_LIMIT;
2082 case ETHTOOL_ID_INACTIVE:
2083 beacon_duration = 0;
2089 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
2093 const struct ethtool_ops mlx4_en_ethtool_ops = {
2094 .get_drvinfo = mlx4_en_get_drvinfo,
2095 .get_link_ksettings = mlx4_en_get_link_ksettings,
2096 .set_link_ksettings = mlx4_en_set_link_ksettings,
2097 .get_link = ethtool_op_get_link,
2098 .get_strings = mlx4_en_get_strings,
2099 .get_sset_count = mlx4_en_get_sset_count,
2100 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2101 .self_test = mlx4_en_self_test,
2102 .set_phys_id = mlx4_en_set_phys_id,
2103 .get_wol = mlx4_en_get_wol,
2104 .set_wol = mlx4_en_set_wol,
2105 .get_msglevel = mlx4_en_get_msglevel,
2106 .set_msglevel = mlx4_en_set_msglevel,
2107 .get_coalesce = mlx4_en_get_coalesce,
2108 .set_coalesce = mlx4_en_set_coalesce,
2109 .get_pauseparam = mlx4_en_get_pauseparam,
2110 .set_pauseparam = mlx4_en_set_pauseparam,
2111 .get_ringparam = mlx4_en_get_ringparam,
2112 .set_ringparam = mlx4_en_set_ringparam,
2113 .get_rxnfc = mlx4_en_get_rxnfc,
2114 .set_rxnfc = mlx4_en_set_rxnfc,
2115 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2116 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2117 .get_rxfh = mlx4_en_get_rxfh,
2118 .set_rxfh = mlx4_en_set_rxfh,
2119 .get_channels = mlx4_en_get_channels,
2120 .set_channels = mlx4_en_set_channels,
2121 .get_ts_info = mlx4_en_get_ts_info,
2122 .set_priv_flags = mlx4_en_set_priv_flags,
2123 .get_priv_flags = mlx4_en_get_priv_flags,
2124 .get_tunable = mlx4_en_get_tunable,
2125 .set_tunable = mlx4_en_set_tunable,
2126 .get_module_info = mlx4_en_get_module_info,
2127 .get_module_eeprom = mlx4_en_get_module_eeprom