2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kernel.h>
35 #include <linux/ethtool.h>
36 #include <linux/netdevice.h>
37 #include <linux/mlx4/driver.h>
38 #include <linux/mlx4/device.h>
41 #include <linux/bitmap.h>
46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
50 int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
55 for (i = 0; i < priv->tx_ring_num; i++) {
56 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
57 priv->tx_cq[i]->moder_time = priv->tx_usecs;
59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
65 if (priv->adaptive_rx_coal)
68 for (i = 0; i < priv->rx_ring_num; i++) {
69 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
70 priv->rx_cq[i]->moder_time = priv->rx_usecs;
71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
83 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
85 struct mlx4_en_priv *priv = netdev_priv(dev);
86 struct mlx4_en_dev *mdev = priv->mdev;
88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
90 sizeof(drvinfo->version));
91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
93 (u16) (mdev->dev->caps.fw_ver >> 32),
94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
95 (u16) (mdev->dev->caps.fw_ver & 0xffff));
96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
97 sizeof(drvinfo->bus_info));
100 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
105 static const char main_strings[][ETH_GSTRING_LEN] = {
106 /* main statistics */
107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
109 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
112 "tx_heartbeat_errors", "tx_window_errors",
114 /* port statistics */
117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
118 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
126 /* priority flow control statistics rx */
127 "rx_pause_prio_0", "rx_pause_duration_prio_0",
128 "rx_pause_transition_prio_0",
129 "rx_pause_prio_1", "rx_pause_duration_prio_1",
130 "rx_pause_transition_prio_1",
131 "rx_pause_prio_2", "rx_pause_duration_prio_2",
132 "rx_pause_transition_prio_2",
133 "rx_pause_prio_3", "rx_pause_duration_prio_3",
134 "rx_pause_transition_prio_3",
135 "rx_pause_prio_4", "rx_pause_duration_prio_4",
136 "rx_pause_transition_prio_4",
137 "rx_pause_prio_5", "rx_pause_duration_prio_5",
138 "rx_pause_transition_prio_5",
139 "rx_pause_prio_6", "rx_pause_duration_prio_6",
140 "rx_pause_transition_prio_6",
141 "rx_pause_prio_7", "rx_pause_duration_prio_7",
142 "rx_pause_transition_prio_7",
144 /* flow control statistics rx */
145 "rx_pause", "rx_pause_duration", "rx_pause_transition",
147 /* priority flow control statistics tx */
148 "tx_pause_prio_0", "tx_pause_duration_prio_0",
149 "tx_pause_transition_prio_0",
150 "tx_pause_prio_1", "tx_pause_duration_prio_1",
151 "tx_pause_transition_prio_1",
152 "tx_pause_prio_2", "tx_pause_duration_prio_2",
153 "tx_pause_transition_prio_2",
154 "tx_pause_prio_3", "tx_pause_duration_prio_3",
155 "tx_pause_transition_prio_3",
156 "tx_pause_prio_4", "tx_pause_duration_prio_4",
157 "tx_pause_transition_prio_4",
158 "tx_pause_prio_5", "tx_pause_duration_prio_5",
159 "tx_pause_transition_prio_5",
160 "tx_pause_prio_6", "tx_pause_duration_prio_6",
161 "tx_pause_transition_prio_6",
162 "tx_pause_prio_7", "tx_pause_duration_prio_7",
163 "tx_pause_transition_prio_7",
165 /* flow control statistics tx */
166 "tx_pause", "tx_pause_duration", "tx_pause_transition",
168 /* packet statistics */
169 "rx_multicast_packets",
170 "rx_broadcast_packets",
172 "rx_in_range_length_error",
173 "rx_out_range_length_error",
174 "tx_multicast_packets",
175 "tx_broadcast_packets",
176 "rx_prio_0_packets", "rx_prio_0_bytes",
177 "rx_prio_1_packets", "rx_prio_1_bytes",
178 "rx_prio_2_packets", "rx_prio_2_bytes",
179 "rx_prio_3_packets", "rx_prio_3_bytes",
180 "rx_prio_4_packets", "rx_prio_4_bytes",
181 "rx_prio_5_packets", "rx_prio_5_bytes",
182 "rx_prio_6_packets", "rx_prio_6_bytes",
183 "rx_prio_7_packets", "rx_prio_7_bytes",
184 "rx_novlan_packets", "rx_novlan_bytes",
185 "tx_prio_0_packets", "tx_prio_0_bytes",
186 "tx_prio_1_packets", "tx_prio_1_bytes",
187 "tx_prio_2_packets", "tx_prio_2_bytes",
188 "tx_prio_3_packets", "tx_prio_3_bytes",
189 "tx_prio_4_packets", "tx_prio_4_bytes",
190 "tx_prio_5_packets", "tx_prio_5_bytes",
191 "tx_prio_6_packets", "tx_prio_6_bytes",
192 "tx_prio_7_packets", "tx_prio_7_bytes",
193 "tx_novlan_packets", "tx_novlan_bytes",
197 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
205 static u32 mlx4_en_get_msglevel(struct net_device *dev)
207 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
210 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
212 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
215 static void mlx4_en_get_wol(struct net_device *netdev,
216 struct ethtool_wolinfo *wol)
218 struct mlx4_en_priv *priv = netdev_priv(netdev);
223 if ((priv->port < 1) || (priv->port > 2)) {
224 en_err(priv, "Failed to get WoL information\n");
228 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
229 MLX4_DEV_CAP_FLAG_WOL_PORT2;
231 if (!(priv->mdev->dev->caps.flags & mask)) {
237 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
239 en_err(priv, "Failed to get WoL information\n");
243 if (config & MLX4_EN_WOL_MAGIC)
244 wol->supported = WAKE_MAGIC;
248 if (config & MLX4_EN_WOL_ENABLED)
249 wol->wolopts = WAKE_MAGIC;
254 static int mlx4_en_set_wol(struct net_device *netdev,
255 struct ethtool_wolinfo *wol)
257 struct mlx4_en_priv *priv = netdev_priv(netdev);
262 if ((priv->port < 1) || (priv->port > 2))
265 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
266 MLX4_DEV_CAP_FLAG_WOL_PORT2;
268 if (!(priv->mdev->dev->caps.flags & mask))
271 if (wol->supported & ~WAKE_MAGIC)
274 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
276 en_err(priv, "Failed to get WoL info, unable to modify\n");
280 if (wol->wolopts & WAKE_MAGIC) {
281 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
284 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
285 config |= MLX4_EN_WOL_DO_MODIFY;
288 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
290 en_err(priv, "Failed to set WoL information\n");
295 struct bitmap_iterator {
296 unsigned long *stats_bitmap;
298 unsigned int iterator;
299 bool advance_array; /* if set, force no increments */
302 static inline void bitmap_iterator_init(struct bitmap_iterator *h,
303 unsigned long *stats_bitmap,
307 h->advance_array = !bitmap_empty(stats_bitmap, count);
308 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
310 h->stats_bitmap = stats_bitmap;
313 static inline int bitmap_iterator_test(struct bitmap_iterator *h)
315 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
318 static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
320 return h->iterator++;
323 static inline unsigned int
324 bitmap_iterator_count(struct bitmap_iterator *h)
329 static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
331 struct mlx4_en_priv *priv = netdev_priv(dev);
332 struct bitmap_iterator it;
334 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
338 return bitmap_iterator_count(&it) +
339 (priv->tx_ring_num * 2) +
340 (priv->rx_ring_num * 3);
342 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
343 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
344 case ETH_SS_PRIV_FLAGS:
345 return ARRAY_SIZE(mlx4_en_priv_flags);
351 static void mlx4_en_get_ethtool_stats(struct net_device *dev,
352 struct ethtool_stats *stats, uint64_t *data)
354 struct mlx4_en_priv *priv = netdev_priv(dev);
357 struct bitmap_iterator it;
359 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
361 spin_lock_bh(&priv->stats_lock);
363 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
364 if (bitmap_iterator_test(&it))
365 data[index++] = ((unsigned long *)&dev->stats)[i];
367 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
368 if (bitmap_iterator_test(&it))
369 data[index++] = ((unsigned long *)&priv->port_stats)[i];
371 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
372 if (bitmap_iterator_test(&it))
374 ((unsigned long *)&priv->pf_stats)[i];
376 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
377 i++, bitmap_iterator_inc(&it))
378 if (bitmap_iterator_test(&it))
380 ((u64 *)&priv->rx_priority_flowstats)[i];
382 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
383 if (bitmap_iterator_test(&it))
384 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
386 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
387 i++, bitmap_iterator_inc(&it))
388 if (bitmap_iterator_test(&it))
390 ((u64 *)&priv->tx_priority_flowstats)[i];
392 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
393 if (bitmap_iterator_test(&it))
394 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
396 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
397 if (bitmap_iterator_test(&it))
398 data[index++] = ((unsigned long *)&priv->pkstats)[i];
400 for (i = 0; i < priv->tx_ring_num; i++) {
401 data[index++] = priv->tx_ring[i]->packets;
402 data[index++] = priv->tx_ring[i]->bytes;
404 for (i = 0; i < priv->rx_ring_num; i++) {
405 data[index++] = priv->rx_ring[i]->packets;
406 data[index++] = priv->rx_ring[i]->bytes;
407 data[index++] = priv->rx_ring[i]->dropped;
409 spin_unlock_bh(&priv->stats_lock);
413 static void mlx4_en_self_test(struct net_device *dev,
414 struct ethtool_test *etest, u64 *buf)
416 mlx4_en_ex_selftest(dev, &etest->flags, buf);
419 static void mlx4_en_get_strings(struct net_device *dev,
420 uint32_t stringset, uint8_t *data)
422 struct mlx4_en_priv *priv = netdev_priv(dev);
425 struct bitmap_iterator it;
427 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
431 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
432 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
433 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
434 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
435 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
439 /* Add main counters */
440 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
441 bitmap_iterator_inc(&it))
442 if (bitmap_iterator_test(&it))
443 strcpy(data + (index++) * ETH_GSTRING_LEN,
444 main_strings[strings]);
446 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
447 bitmap_iterator_inc(&it))
448 if (bitmap_iterator_test(&it))
449 strcpy(data + (index++) * ETH_GSTRING_LEN,
450 main_strings[strings]);
452 for (i = 0; i < NUM_PF_STATS; i++, strings++,
453 bitmap_iterator_inc(&it))
454 if (bitmap_iterator_test(&it))
455 strcpy(data + (index++) * ETH_GSTRING_LEN,
456 main_strings[strings]);
458 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
459 bitmap_iterator_inc(&it))
460 if (bitmap_iterator_test(&it))
461 strcpy(data + (index++) * ETH_GSTRING_LEN,
462 main_strings[strings]);
464 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
465 bitmap_iterator_inc(&it))
466 if (bitmap_iterator_test(&it))
467 strcpy(data + (index++) * ETH_GSTRING_LEN,
468 main_strings[strings]);
470 for (i = 0; i < priv->tx_ring_num; i++) {
471 sprintf(data + (index++) * ETH_GSTRING_LEN,
473 sprintf(data + (index++) * ETH_GSTRING_LEN,
476 for (i = 0; i < priv->rx_ring_num; i++) {
477 sprintf(data + (index++) * ETH_GSTRING_LEN,
479 sprintf(data + (index++) * ETH_GSTRING_LEN,
481 sprintf(data + (index++) * ETH_GSTRING_LEN,
485 case ETH_SS_PRIV_FLAGS:
486 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
487 strcpy(data + i * ETH_GSTRING_LEN,
488 mlx4_en_priv_flags[i]);
494 static u32 mlx4_en_autoneg_get(struct net_device *dev)
496 struct mlx4_en_priv *priv = netdev_priv(dev);
497 struct mlx4_en_dev *mdev = priv->mdev;
498 u32 autoneg = AUTONEG_DISABLE;
500 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
501 (priv->port_state.flags & MLX4_EN_PORT_ANE))
502 autoneg = AUTONEG_ENABLE;
507 static void ptys2ethtool_update_supported_port(unsigned long *mask,
508 struct mlx4_ptys_reg *ptys_reg)
510 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
512 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
513 | MLX4_PROT_MASK(MLX4_1000BASE_T)
514 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
515 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
516 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
517 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
518 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
519 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
520 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
521 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
522 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
523 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
524 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
525 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
526 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
527 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
528 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
529 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
533 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
535 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
537 if (!eth_proto) /* link down */
538 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
540 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
541 | MLX4_PROT_MASK(MLX4_1000BASE_T)
542 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
546 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
547 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
548 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
549 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
553 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
554 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
555 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
559 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
560 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
561 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
562 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
563 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
564 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
570 #define MLX4_LINK_MODES_SZ \
571 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
573 enum ethtool_report {
578 struct ptys2ethtool_config {
579 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
580 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
584 static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
585 enum ethtool_report report)
589 return cfg->supported;
591 return cfg->advertised;
596 #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
598 struct ptys2ethtool_config *cfg; \
599 const unsigned int modes[] = { __VA_ARGS__ }; \
601 cfg = &ptys2ethtool_map[reg_]; \
602 cfg->speed = speed_; \
603 bitmap_zero(cfg->supported, \
604 __ETHTOOL_LINK_MODE_MASK_NBITS); \
605 bitmap_zero(cfg->advertised, \
606 __ETHTOOL_LINK_MODE_MASK_NBITS); \
607 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
608 __set_bit(modes[i], cfg->supported); \
609 __set_bit(modes[i], cfg->advertised); \
613 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
614 static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
616 void __init mlx4_en_init_ptys2ethtool_map(void)
618 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
619 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
620 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
621 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
622 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
623 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
624 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
625 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
626 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
627 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
628 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
629 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
630 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
631 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
632 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
633 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
634 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
635 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT);
636 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
637 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT);
638 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
639 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
640 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
641 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
642 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
643 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
644 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
645 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
646 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
647 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
648 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
649 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
650 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
651 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
652 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
655 static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
657 enum ethtool_report report)
660 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
661 if (eth_proto & MLX4_PROT_MASK(i))
662 bitmap_or(link_modes, link_modes,
663 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
665 __ETHTOOL_LINK_MODE_MASK_NBITS);
669 static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
670 enum ethtool_report report)
675 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
676 if (bitmap_intersects(
677 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
680 __ETHTOOL_LINK_MODE_MASK_NBITS))
681 ptys_modes |= 1 << i;
686 /* Convert actual speed (SPEED_XXX) to ptys link modes */
687 static u32 speed2ptys_link_modes(u32 speed)
692 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
693 if (ptys2ethtool_map[i].speed == speed)
694 ptys_modes |= 1 << i;
700 ethtool_get_ptys_link_ksettings(struct net_device *dev,
701 struct ethtool_link_ksettings *link_ksettings)
703 struct mlx4_en_priv *priv = netdev_priv(dev);
704 struct mlx4_ptys_reg ptys_reg;
708 memset(&ptys_reg, 0, sizeof(ptys_reg));
709 ptys_reg.local_port = priv->port;
710 ptys_reg.proto_mask = MLX4_PTYS_EN;
711 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
712 MLX4_ACCESS_REG_QUERY, &ptys_reg);
714 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
718 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
719 ptys_reg.proto_mask);
720 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
721 be32_to_cpu(ptys_reg.eth_proto_cap));
722 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
723 be32_to_cpu(ptys_reg.eth_proto_admin));
724 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
725 be32_to_cpu(ptys_reg.eth_proto_oper));
726 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
727 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
729 /* reset supported/advertising masks */
730 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
731 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
733 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
736 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
737 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
738 eth_proto, SUPPORTED);
740 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
741 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
742 eth_proto, ADVERTISED);
744 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
746 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
749 if (priv->prof->tx_pause)
750 ethtool_link_ksettings_add_link_mode(link_ksettings,
752 if (priv->prof->tx_pause ^ priv->prof->rx_pause)
753 ethtool_link_ksettings_add_link_mode(link_ksettings,
754 advertising, Asym_Pause);
756 link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
758 if (mlx4_en_autoneg_get(dev)) {
759 ethtool_link_ksettings_add_link_mode(link_ksettings,
761 ethtool_link_ksettings_add_link_mode(link_ksettings,
762 advertising, Autoneg);
765 link_ksettings->base.autoneg
766 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
767 AUTONEG_ENABLE : AUTONEG_DISABLE;
769 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
771 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
772 ptys2ethtool_update_link_modes(
773 link_ksettings->link_modes.lp_advertising,
774 eth_proto, ADVERTISED);
775 if (priv->port_state.flags & MLX4_EN_PORT_ANC)
776 ethtool_link_ksettings_add_link_mode(link_ksettings,
777 lp_advertising, Autoneg);
779 link_ksettings->base.phy_address = 0;
780 link_ksettings->base.mdio_support = 0;
781 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
782 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
788 ethtool_get_default_link_ksettings(
789 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
791 struct mlx4_en_priv *priv = netdev_priv(dev);
794 link_ksettings->base.autoneg = AUTONEG_DISABLE;
796 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
797 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
800 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
801 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
804 trans_type = priv->port_state.transceiver;
805 if (trans_type > 0 && trans_type <= 0xC) {
806 link_ksettings->base.port = PORT_FIBRE;
807 ethtool_link_ksettings_add_link_mode(link_ksettings,
809 ethtool_link_ksettings_add_link_mode(link_ksettings,
811 } else if (trans_type == 0x80 || trans_type == 0) {
812 link_ksettings->base.port = PORT_TP;
813 ethtool_link_ksettings_add_link_mode(link_ksettings,
815 ethtool_link_ksettings_add_link_mode(link_ksettings,
818 link_ksettings->base.port = -1;
823 mlx4_en_get_link_ksettings(struct net_device *dev,
824 struct ethtool_link_ksettings *link_ksettings)
826 struct mlx4_en_priv *priv = netdev_priv(dev);
829 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
832 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
833 priv->port_state.flags & MLX4_EN_PORT_ANC,
834 priv->port_state.flags & MLX4_EN_PORT_ANE);
836 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
837 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
838 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
839 ethtool_get_default_link_ksettings(dev, link_ksettings);
841 if (netif_carrier_ok(dev)) {
842 link_ksettings->base.speed = priv->port_state.link_speed;
843 link_ksettings->base.duplex = DUPLEX_FULL;
845 link_ksettings->base.speed = SPEED_UNKNOWN;
846 link_ksettings->base.duplex = DUPLEX_UNKNOWN;
851 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
852 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
855 __be32 proto_admin = 0;
857 if (!speed) { /* Speed = 0 ==> Reset Link modes */
858 proto_admin = proto_cap;
859 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
860 be32_to_cpu(proto_cap));
862 u32 ptys_link_modes = speed2ptys_link_modes(speed);
864 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
865 en_info(priv, "Setting Speed to %d\n", speed);
871 mlx4_en_set_link_ksettings(struct net_device *dev,
872 const struct ethtool_link_ksettings *link_ksettings)
874 struct mlx4_en_priv *priv = netdev_priv(dev);
875 struct mlx4_ptys_reg ptys_reg;
879 u32 ptys_adv = ethtool2ptys_link_modes(
880 link_ksettings->link_modes.advertising, ADVERTISED);
881 const int speed = link_ksettings->base.speed;
884 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
885 speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
886 link_ksettings->link_modes.advertising,
887 link_ksettings->base.autoneg,
888 link_ksettings->base.duplex);
890 if (!(priv->mdev->dev->caps.flags2 &
891 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
892 (link_ksettings->base.duplex == DUPLEX_HALF))
895 memset(&ptys_reg, 0, sizeof(ptys_reg));
896 ptys_reg.local_port = priv->port;
897 ptys_reg.proto_mask = MLX4_PTYS_EN;
898 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
899 MLX4_ACCESS_REG_QUERY, &ptys_reg);
901 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
906 proto_admin = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
907 cpu_to_be32(ptys_adv) :
908 speed_set_ptys_admin(priv, speed,
909 ptys_reg.eth_proto_cap);
911 proto_admin &= ptys_reg.eth_proto_cap;
913 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
914 return -EINVAL; /* nothing to change due to bad input */
917 if (proto_admin == ptys_reg.eth_proto_admin)
918 return 0; /* Nothing to change */
920 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
921 be32_to_cpu(proto_admin));
923 ptys_reg.eth_proto_admin = proto_admin;
924 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
927 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
928 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
932 mutex_lock(&priv->mdev->state_lock);
934 en_warn(priv, "Port link mode changed, restarting port...\n");
935 mlx4_en_stop_port(dev, 1);
936 if (mlx4_en_start_port(dev))
937 en_err(priv, "Failed restarting port %d\n", priv->port);
939 mutex_unlock(&priv->mdev->state_lock);
943 static int mlx4_en_get_coalesce(struct net_device *dev,
944 struct ethtool_coalesce *coal)
946 struct mlx4_en_priv *priv = netdev_priv(dev);
948 coal->tx_coalesce_usecs = priv->tx_usecs;
949 coal->tx_max_coalesced_frames = priv->tx_frames;
950 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
952 coal->rx_coalesce_usecs = priv->rx_usecs;
953 coal->rx_max_coalesced_frames = priv->rx_frames;
955 coal->pkt_rate_low = priv->pkt_rate_low;
956 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
957 coal->pkt_rate_high = priv->pkt_rate_high;
958 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
959 coal->rate_sample_interval = priv->sample_interval;
960 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
965 static int mlx4_en_set_coalesce(struct net_device *dev,
966 struct ethtool_coalesce *coal)
968 struct mlx4_en_priv *priv = netdev_priv(dev);
970 if (!coal->tx_max_coalesced_frames_irq)
973 if (coal->tx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
974 coal->rx_coalesce_usecs > MLX4_EN_MAX_COAL_TIME ||
975 coal->rx_coalesce_usecs_low > MLX4_EN_MAX_COAL_TIME ||
976 coal->rx_coalesce_usecs_high > MLX4_EN_MAX_COAL_TIME) {
977 netdev_info(dev, "%s: maximum coalesce time supported is %d usecs\n",
978 __func__, MLX4_EN_MAX_COAL_TIME);
982 if (coal->tx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS ||
983 coal->rx_max_coalesced_frames > MLX4_EN_MAX_COAL_PKTS) {
984 netdev_info(dev, "%s: maximum coalesced frames supported is %d\n",
985 __func__, MLX4_EN_MAX_COAL_PKTS);
989 priv->rx_frames = (coal->rx_max_coalesced_frames ==
991 MLX4_EN_RX_COAL_TARGET :
992 coal->rx_max_coalesced_frames;
993 priv->rx_usecs = (coal->rx_coalesce_usecs ==
995 MLX4_EN_RX_COAL_TIME :
996 coal->rx_coalesce_usecs;
998 /* Setting TX coalescing parameters */
999 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
1000 coal->tx_max_coalesced_frames != priv->tx_frames) {
1001 priv->tx_usecs = coal->tx_coalesce_usecs;
1002 priv->tx_frames = coal->tx_max_coalesced_frames;
1005 /* Set adaptive coalescing params */
1006 priv->pkt_rate_low = coal->pkt_rate_low;
1007 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
1008 priv->pkt_rate_high = coal->pkt_rate_high;
1009 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
1010 priv->sample_interval = coal->rate_sample_interval;
1011 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
1012 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
1014 return mlx4_en_moderation_update(priv);
1017 static int mlx4_en_set_pauseparam(struct net_device *dev,
1018 struct ethtool_pauseparam *pause)
1020 struct mlx4_en_priv *priv = netdev_priv(dev);
1021 struct mlx4_en_dev *mdev = priv->mdev;
1022 u8 tx_pause, tx_ppp, rx_pause, rx_ppp;
1028 tx_pause = !!(pause->tx_pause);
1029 rx_pause = !!(pause->rx_pause);
1030 rx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->rx_ppp;
1031 tx_ppp = (tx_pause || rx_pause) ? 0 : priv->prof->tx_ppp;
1033 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1034 priv->rx_skb_size + ETH_FCS_LEN,
1035 tx_pause, tx_ppp, rx_pause, rx_ppp);
1037 en_err(priv, "Failed setting pause params, err = %d\n", err);
1041 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1042 rx_ppp, rx_pause, tx_ppp, tx_pause);
1044 priv->prof->tx_pause = tx_pause;
1045 priv->prof->rx_pause = rx_pause;
1046 priv->prof->tx_ppp = tx_ppp;
1047 priv->prof->rx_ppp = rx_ppp;
1052 static void mlx4_en_get_pauseparam(struct net_device *dev,
1053 struct ethtool_pauseparam *pause)
1055 struct mlx4_en_priv *priv = netdev_priv(dev);
1057 pause->tx_pause = priv->prof->tx_pause;
1058 pause->rx_pause = priv->prof->rx_pause;
1061 static int mlx4_en_set_ringparam(struct net_device *dev,
1062 struct ethtool_ringparam *param)
1064 struct mlx4_en_priv *priv = netdev_priv(dev);
1065 struct mlx4_en_dev *mdev = priv->mdev;
1066 struct mlx4_en_port_profile new_prof;
1067 struct mlx4_en_priv *tmp;
1068 u32 rx_size, tx_size;
1072 if (param->rx_jumbo_pending || param->rx_mini_pending)
1075 rx_size = roundup_pow_of_two(param->rx_pending);
1076 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
1077 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
1078 tx_size = roundup_pow_of_two(param->tx_pending);
1079 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
1080 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
1082 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1083 priv->rx_ring[0]->size) &&
1084 tx_size == priv->tx_ring[0]->size)
1087 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1091 mutex_lock(&mdev->state_lock);
1092 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1093 new_prof.tx_ring_size = tx_size;
1094 new_prof.rx_ring_size = rx_size;
1095 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
1099 if (priv->port_up) {
1101 mlx4_en_stop_port(dev, 1);
1104 mlx4_en_safe_replace_resources(priv, tmp);
1107 err = mlx4_en_start_port(dev);
1109 en_err(priv, "Failed starting port\n");
1112 err = mlx4_en_moderation_update(priv);
1115 mutex_unlock(&mdev->state_lock);
1119 static void mlx4_en_get_ringparam(struct net_device *dev,
1120 struct ethtool_ringparam *param)
1122 struct mlx4_en_priv *priv = netdev_priv(dev);
1124 memset(param, 0, sizeof(*param));
1125 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1126 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1127 param->rx_pending = priv->port_up ?
1128 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1129 param->tx_pending = priv->tx_ring[0]->size;
1132 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1134 struct mlx4_en_priv *priv = netdev_priv(dev);
1136 return rounddown_pow_of_two(priv->rx_ring_num);
1139 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1141 return MLX4_EN_RSS_KEY_SIZE;
1144 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1146 struct mlx4_en_priv *priv = netdev_priv(dev);
1148 /* check if requested function is supported by the device */
1149 if (hfunc == ETH_RSS_HASH_TOP) {
1150 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1152 if (!(dev->features & NETIF_F_RXHASH))
1153 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1155 } else if (hfunc == ETH_RSS_HASH_XOR) {
1156 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1158 if (dev->features & NETIF_F_RXHASH)
1159 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1166 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1169 struct mlx4_en_priv *priv = netdev_priv(dev);
1170 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1174 rss_rings = priv->prof->rss_rings ?: n;
1175 rss_rings = rounddown_pow_of_two(rss_rings);
1177 for (i = 0; i < n; i++) {
1180 ring_index[i] = i % rss_rings;
1183 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1185 *hfunc = priv->rss_hash_fn;
1189 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1190 const u8 *key, const u8 hfunc)
1192 struct mlx4_en_priv *priv = netdev_priv(dev);
1193 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1194 struct mlx4_en_dev *mdev = priv->mdev;
1200 /* Calculate RSS table size and make sure flows are spread evenly
1203 for (i = 0; i < n; i++) {
1206 if (i > 0 && !ring_index[i] && !rss_rings)
1209 if (ring_index[i] != (i % (rss_rings ?: n)))
1216 /* RSS table size must be an order of 2 */
1217 if (!is_power_of_2(rss_rings))
1220 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1221 err = mlx4_en_check_rxfh_func(dev, hfunc);
1226 mutex_lock(&mdev->state_lock);
1227 if (priv->port_up) {
1229 mlx4_en_stop_port(dev, 1);
1233 priv->prof->rss_rings = rss_rings;
1235 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1236 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1237 priv->rss_hash_fn = hfunc;
1240 err = mlx4_en_start_port(dev);
1242 en_err(priv, "Failed starting port\n");
1245 mutex_unlock(&mdev->state_lock);
1249 #define all_zeros_or_all_ones(field) \
1250 ((field) == 0 || (field) == (__force typeof(field))-1)
1252 static int mlx4_en_validate_flow(struct net_device *dev,
1253 struct ethtool_rxnfc *cmd)
1255 struct ethtool_usrip4_spec *l3_mask;
1256 struct ethtool_tcpip4_spec *l4_mask;
1257 struct ethhdr *eth_mask;
1259 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1262 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1263 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1264 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1268 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1271 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1273 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1274 /* don't allow mask which isn't all 0 or 1 */
1275 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1276 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1277 !all_zeros_or_all_ones(l4_mask->psrc) ||
1278 !all_zeros_or_all_ones(l4_mask->pdst))
1282 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1283 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1284 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1285 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1286 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1287 !all_zeros_or_all_ones(l3_mask->ip4dst))
1291 eth_mask = &cmd->fs.m_u.ether_spec;
1292 /* source mac mask must not be set */
1293 if (!is_zero_ether_addr(eth_mask->h_source))
1296 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1297 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1300 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1307 if ((cmd->fs.flow_type & FLOW_EXT)) {
1308 if (cmd->fs.m_ext.vlan_etype ||
1309 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1311 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1312 cpu_to_be16(VLAN_VID_MASK)))
1315 if (cmd->fs.m_ext.vlan_tci) {
1316 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1325 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1326 struct list_head *rule_list_h,
1327 struct mlx4_spec_list *spec_l2,
1331 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1333 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1334 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1335 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1337 if ((cmd->fs.flow_type & FLOW_EXT) &&
1338 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1339 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1340 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1343 list_add_tail(&spec_l2->list, rule_list_h);
1348 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1349 struct ethtool_rxnfc *cmd,
1350 struct list_head *rule_list_h,
1351 struct mlx4_spec_list *spec_l2,
1355 unsigned char mac[ETH_ALEN];
1357 if (!ipv4_is_multicast(ipv4_dst)) {
1358 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1359 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1361 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1363 ip_eth_mc_map(ipv4_dst, mac);
1366 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1372 static int add_ip_rule(struct mlx4_en_priv *priv,
1373 struct ethtool_rxnfc *cmd,
1374 struct list_head *list_h)
1377 struct mlx4_spec_list *spec_l2 = NULL;
1378 struct mlx4_spec_list *spec_l3 = NULL;
1379 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1381 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1382 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1383 if (!spec_l2 || !spec_l3) {
1388 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1390 usr_ip4_spec.ip4dst);
1393 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1394 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1395 if (l3_mask->ip4src)
1396 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1397 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1398 if (l3_mask->ip4dst)
1399 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1400 list_add_tail(&spec_l3->list, list_h);
1410 static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1411 struct ethtool_rxnfc *cmd,
1412 struct list_head *list_h, int proto)
1415 struct mlx4_spec_list *spec_l2 = NULL;
1416 struct mlx4_spec_list *spec_l3 = NULL;
1417 struct mlx4_spec_list *spec_l4 = NULL;
1418 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1420 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1421 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1422 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1423 if (!spec_l2 || !spec_l3 || !spec_l4) {
1428 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1430 if (proto == TCP_V4_FLOW) {
1431 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1434 tcp_ip4_spec.ip4dst);
1437 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1438 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1439 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1440 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1441 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1443 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1446 udp_ip4_spec.ip4dst);
1449 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1450 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1451 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1452 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1453 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1456 if (l4_mask->ip4src)
1457 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1458 if (l4_mask->ip4dst)
1459 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1462 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1464 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1466 list_add_tail(&spec_l3->list, list_h);
1467 list_add_tail(&spec_l4->list, list_h);
1478 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1479 struct ethtool_rxnfc *cmd,
1480 struct list_head *rule_list_h)
1483 struct ethhdr *eth_spec;
1484 struct mlx4_spec_list *spec_l2;
1485 struct mlx4_en_priv *priv = netdev_priv(dev);
1487 err = mlx4_en_validate_flow(dev, cmd);
1491 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1493 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1497 eth_spec = &cmd->fs.h_u.ether_spec;
1498 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1499 ð_spec->h_dest[0]);
1500 spec_l2->eth.ether_type = eth_spec->h_proto;
1501 if (eth_spec->h_proto)
1502 spec_l2->eth.ether_type_enable = 1;
1505 err = add_ip_rule(priv, cmd, rule_list_h);
1508 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1511 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1518 static int mlx4_en_flow_replace(struct net_device *dev,
1519 struct ethtool_rxnfc *cmd)
1522 struct mlx4_en_priv *priv = netdev_priv(dev);
1523 struct ethtool_flow_id *loc_rule;
1524 struct mlx4_spec_list *spec, *tmp_spec;
1528 struct mlx4_net_trans_rule rule = {
1529 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1531 .allow_loopback = 1,
1532 .promisc_mode = MLX4_FS_REGULAR,
1535 rule.port = priv->port;
1536 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1537 INIT_LIST_HEAD(&rule.list);
1539 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1540 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1541 qpn = priv->drop_qp.qpn;
1542 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1543 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1545 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1546 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1547 cmd->fs.ring_cookie);
1550 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1552 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1553 cmd->fs.ring_cookie);
1558 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1562 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1564 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1566 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1567 cmd->fs.location, loc_rule->id);
1571 memset(&loc_rule->flow_spec, 0,
1572 sizeof(struct ethtool_rx_flow_spec));
1573 list_del(&loc_rule->list);
1575 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1577 en_err(priv, "Fail to attach network rule at location %d\n",
1581 loc_rule->id = reg_id;
1582 memcpy(&loc_rule->flow_spec, &cmd->fs,
1583 sizeof(struct ethtool_rx_flow_spec));
1584 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1587 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1588 list_del(&spec->list);
1594 static int mlx4_en_flow_detach(struct net_device *dev,
1595 struct ethtool_rxnfc *cmd)
1598 struct ethtool_flow_id *rule;
1599 struct mlx4_en_priv *priv = netdev_priv(dev);
1601 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1604 rule = &priv->ethtool_rules[cmd->fs.location];
1610 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1612 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1613 cmd->fs.location, rule->id);
1617 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1618 list_del(&rule->list);
1624 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1628 struct ethtool_flow_id *rule;
1629 struct mlx4_en_priv *priv = netdev_priv(dev);
1631 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1634 rule = &priv->ethtool_rules[loc];
1636 memcpy(&cmd->fs, &rule->flow_spec,
1637 sizeof(struct ethtool_rx_flow_spec));
1644 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1648 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1649 if (priv->ethtool_rules[i].id)
1656 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1659 struct mlx4_en_priv *priv = netdev_priv(dev);
1660 struct mlx4_en_dev *mdev = priv->mdev;
1662 int i = 0, priority = 0;
1664 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1665 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1666 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1667 (mdev->dev->caps.steering_mode !=
1668 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1672 case ETHTOOL_GRXRINGS:
1673 cmd->data = priv->rx_ring_num;
1675 case ETHTOOL_GRXCLSRLCNT:
1676 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1678 case ETHTOOL_GRXCLSRULE:
1679 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1681 case ETHTOOL_GRXCLSRLALL:
1682 cmd->data = MAX_NUM_OF_FS_RULES;
1683 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1684 err = mlx4_en_get_flow(dev, cmd, i);
1686 rule_locs[priority++] = i;
1699 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1702 struct mlx4_en_priv *priv = netdev_priv(dev);
1703 struct mlx4_en_dev *mdev = priv->mdev;
1705 if (mdev->dev->caps.steering_mode !=
1706 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1710 case ETHTOOL_SRXCLSRLINS:
1711 err = mlx4_en_flow_replace(dev, cmd);
1713 case ETHTOOL_SRXCLSRLDEL:
1714 err = mlx4_en_flow_detach(dev, cmd);
1717 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1724 static void mlx4_en_get_channels(struct net_device *dev,
1725 struct ethtool_channels *channel)
1727 struct mlx4_en_priv *priv = netdev_priv(dev);
1729 memset(channel, 0, sizeof(*channel));
1731 channel->max_rx = MAX_RX_RINGS;
1732 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1734 channel->rx_count = priv->rx_ring_num;
1735 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1738 static int mlx4_en_set_channels(struct net_device *dev,
1739 struct ethtool_channels *channel)
1741 struct mlx4_en_priv *priv = netdev_priv(dev);
1742 struct mlx4_en_dev *mdev = priv->mdev;
1743 struct mlx4_en_port_profile new_prof;
1744 struct mlx4_en_priv *tmp;
1748 if (channel->other_count || channel->combined_count ||
1749 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1750 channel->rx_count > MAX_RX_RINGS ||
1751 !channel->tx_count || !channel->rx_count)
1754 if (channel->tx_count * MLX4_EN_NUM_UP <= priv->xdp_ring_num) {
1755 en_err(priv, "Minimum %d tx channels required with XDP on\n",
1756 priv->xdp_ring_num / MLX4_EN_NUM_UP + 1);
1760 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1764 mutex_lock(&mdev->state_lock);
1765 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1766 new_prof.num_tx_rings_p_up = channel->tx_count;
1767 new_prof.tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1768 new_prof.rx_ring_num = channel->rx_count;
1770 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
1774 if (priv->port_up) {
1776 mlx4_en_stop_port(dev, 1);
1779 mlx4_en_safe_replace_resources(priv, tmp);
1781 netif_set_real_num_tx_queues(dev, priv->tx_ring_num -
1782 priv->xdp_ring_num);
1783 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1786 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
1788 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1789 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1792 err = mlx4_en_start_port(dev);
1794 en_err(priv, "Failed starting port\n");
1797 err = mlx4_en_moderation_update(priv);
1800 mutex_unlock(&mdev->state_lock);
1804 static int mlx4_en_get_ts_info(struct net_device *dev,
1805 struct ethtool_ts_info *info)
1807 struct mlx4_en_priv *priv = netdev_priv(dev);
1808 struct mlx4_en_dev *mdev = priv->mdev;
1811 ret = ethtool_op_get_ts_info(dev, info);
1815 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1816 info->so_timestamping |=
1817 SOF_TIMESTAMPING_TX_HARDWARE |
1818 SOF_TIMESTAMPING_RX_HARDWARE |
1819 SOF_TIMESTAMPING_RAW_HARDWARE;
1822 (1 << HWTSTAMP_TX_OFF) |
1823 (1 << HWTSTAMP_TX_ON);
1826 (1 << HWTSTAMP_FILTER_NONE) |
1827 (1 << HWTSTAMP_FILTER_ALL);
1829 if (mdev->ptp_clock)
1830 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1836 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1838 struct mlx4_en_priv *priv = netdev_priv(dev);
1839 struct mlx4_en_dev *mdev = priv->mdev;
1840 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1841 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1842 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1843 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1847 if (bf_enabled_new != bf_enabled_old) {
1848 if (bf_enabled_new) {
1849 bool bf_supported = true;
1851 for (i = 0; i < priv->tx_ring_num; i++)
1852 bf_supported &= priv->tx_ring[i]->bf_alloced;
1854 if (!bf_supported) {
1855 en_err(priv, "BlueFlame is not supported\n");
1859 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1861 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1864 for (i = 0; i < priv->tx_ring_num; i++)
1865 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1867 en_info(priv, "BlueFlame %s\n",
1868 bf_enabled_new ? "Enabled" : "Disabled");
1871 if (phv_enabled_new != phv_enabled_old) {
1872 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1875 else if (phv_enabled_new)
1876 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1878 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1879 en_info(priv, "PHV bit %s\n",
1880 phv_enabled_new ? "Enabled" : "Disabled");
1885 static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1887 struct mlx4_en_priv *priv = netdev_priv(dev);
1889 return priv->pflags;
1892 static int mlx4_en_get_tunable(struct net_device *dev,
1893 const struct ethtool_tunable *tuna,
1896 const struct mlx4_en_priv *priv = netdev_priv(dev);
1900 case ETHTOOL_TX_COPYBREAK:
1901 *(u32 *)data = priv->prof->inline_thold;
1911 static int mlx4_en_set_tunable(struct net_device *dev,
1912 const struct ethtool_tunable *tuna,
1915 struct mlx4_en_priv *priv = netdev_priv(dev);
1919 case ETHTOOL_TX_COPYBREAK:
1921 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1924 priv->prof->inline_thold = val;
1934 static int mlx4_en_get_module_info(struct net_device *dev,
1935 struct ethtool_modinfo *modinfo)
1937 struct mlx4_en_priv *priv = netdev_priv(dev);
1938 struct mlx4_en_dev *mdev = priv->mdev;
1942 /* Read first 2 bytes to get Module & REV ID */
1943 ret = mlx4_get_module_info(mdev->dev, priv->port,
1944 0/*offset*/, 2/*size*/, data);
1948 switch (data[0] /* identifier */) {
1949 case MLX4_MODULE_ID_QSFP:
1950 modinfo->type = ETH_MODULE_SFF_8436;
1951 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1953 case MLX4_MODULE_ID_QSFP_PLUS:
1954 if (data[1] >= 0x3) { /* revision id */
1955 modinfo->type = ETH_MODULE_SFF_8636;
1956 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1958 modinfo->type = ETH_MODULE_SFF_8436;
1959 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1962 case MLX4_MODULE_ID_QSFP28:
1963 modinfo->type = ETH_MODULE_SFF_8636;
1964 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1966 case MLX4_MODULE_ID_SFP:
1967 modinfo->type = ETH_MODULE_SFF_8472;
1968 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1977 static int mlx4_en_get_module_eeprom(struct net_device *dev,
1978 struct ethtool_eeprom *ee,
1981 struct mlx4_en_priv *priv = netdev_priv(dev);
1982 struct mlx4_en_dev *mdev = priv->mdev;
1983 int offset = ee->offset;
1989 memset(data, 0, ee->len);
1991 while (i < ee->len) {
1993 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1994 i, offset, ee->len - i);
1996 ret = mlx4_get_module_info(mdev->dev, priv->port,
1997 offset, ee->len - i, data + i);
1999 if (!ret) /* Done reading */
2004 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
2005 i, offset, ee->len - i, ret);
2015 static int mlx4_en_set_phys_id(struct net_device *dev,
2016 enum ethtool_phys_id_state state)
2019 u16 beacon_duration;
2020 struct mlx4_en_priv *priv = netdev_priv(dev);
2021 struct mlx4_en_dev *mdev = priv->mdev;
2023 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
2027 case ETHTOOL_ID_ACTIVE:
2028 beacon_duration = PORT_BEACON_MAX_LIMIT;
2030 case ETHTOOL_ID_INACTIVE:
2031 beacon_duration = 0;
2037 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
2041 const struct ethtool_ops mlx4_en_ethtool_ops = {
2042 .get_drvinfo = mlx4_en_get_drvinfo,
2043 .get_link_ksettings = mlx4_en_get_link_ksettings,
2044 .set_link_ksettings = mlx4_en_set_link_ksettings,
2045 .get_link = ethtool_op_get_link,
2046 .get_strings = mlx4_en_get_strings,
2047 .get_sset_count = mlx4_en_get_sset_count,
2048 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2049 .self_test = mlx4_en_self_test,
2050 .set_phys_id = mlx4_en_set_phys_id,
2051 .get_wol = mlx4_en_get_wol,
2052 .set_wol = mlx4_en_set_wol,
2053 .get_msglevel = mlx4_en_get_msglevel,
2054 .set_msglevel = mlx4_en_set_msglevel,
2055 .get_coalesce = mlx4_en_get_coalesce,
2056 .set_coalesce = mlx4_en_set_coalesce,
2057 .get_pauseparam = mlx4_en_get_pauseparam,
2058 .set_pauseparam = mlx4_en_set_pauseparam,
2059 .get_ringparam = mlx4_en_get_ringparam,
2060 .set_ringparam = mlx4_en_set_ringparam,
2061 .get_rxnfc = mlx4_en_get_rxnfc,
2062 .set_rxnfc = mlx4_en_set_rxnfc,
2063 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2064 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2065 .get_rxfh = mlx4_en_get_rxfh,
2066 .set_rxfh = mlx4_en_set_rxfh,
2067 .get_channels = mlx4_en_get_channels,
2068 .set_channels = mlx4_en_set_channels,
2069 .get_ts_info = mlx4_en_get_ts_info,
2070 .set_priv_flags = mlx4_en_set_priv_flags,
2071 .get_priv_flags = mlx4_en_get_priv_flags,
2072 .get_tunable = mlx4_en_get_tunable,
2073 .set_tunable = mlx4_en_set_tunable,
2074 .get_module_info = mlx4_en_get_module_info,
2075 .get_module_eeprom = mlx4_en_get_module_eeprom