2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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34 #include <linux/mlx4/cq.h>
35 #include <linux/mlx4/qp.h>
36 #include <linux/mlx4/cmd.h>
40 static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
46 int mlx4_en_create_cq(struct mlx4_en_priv *priv,
47 struct mlx4_en_cq **pcq,
48 int entries, int ring, enum cq_type mode,
51 struct mlx4_en_dev *mdev = priv->mdev;
52 struct mlx4_en_cq *cq;
55 cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node);
57 en_err(priv, "Failed to allocate CQ structure\n");
62 cq->buf_size = cq->size * mdev->dev->caps.cqe_size;
66 cq->vector = mdev->dev->caps.num_comp_vectors;
68 /* Allocate HW buffers on provided NUMA node.
69 * dev->numa_node is used in mtt range allocation flow.
71 set_dev_node(&mdev->dev->persist->pdev->dev, node);
72 err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
74 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
78 cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf;
89 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
92 struct mlx4_en_dev *mdev = priv->mdev;
95 bool assigned_eq = false;
97 cq->dev = mdev->pndev[priv->port];
98 cq->mcq.set_ci_db = cq->wqres.db.db;
99 cq->mcq.arm_db = cq->wqres.db.db + 1;
100 *cq->mcq.set_ci_db = 0;
102 memset(cq->buf, 0, cq->buf_size);
104 if (cq->type == RX) {
105 if (!mlx4_is_eq_vector_valid(mdev->dev, priv->port,
107 cq->vector = cpumask_first(priv->rx_ring[cq->ring]->affinity_mask);
109 err = mlx4_assign_eq(mdev->dev, priv->port,
112 mlx4_err(mdev, "Failed assigning an EQ to CQ vector %d\n",
119 irq = mlx4_eq_get_irq(mdev->dev, cq->vector);
120 cq->aff_mask = irq_get_effective_affinity_mask(irq);
122 /* For TX we use the same irq per
123 ring we assigned for the RX */
124 struct mlx4_en_cq *rx_cq;
126 cq_idx = cq_idx % priv->rx_ring_num;
127 rx_cq = priv->rx_cq[cq_idx];
128 cq->vector = rx_cq->vector;
132 cq->size = priv->rx_ring[cq->ring]->actual_size;
134 if ((cq->type != RX && priv->hwtstamp_config.tx_type) ||
135 (cq->type == RX && priv->hwtstamp_config.rx_filter))
138 cq->mcq.usage = MLX4_RES_USAGE_DRIVER;
139 err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt,
140 &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq,
141 cq->vector, 0, timestamp_en, &cq->wqres.buf, false);
145 cq->mcq.event = mlx4_en_cq_event;
149 cq->mcq.comp = mlx4_en_tx_irq;
150 netif_napi_add_tx(cq->dev, &cq->napi, mlx4_en_poll_tx_cq);
151 napi_enable(&cq->napi);
154 cq->mcq.comp = mlx4_en_rx_irq;
155 netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq);
156 napi_enable(&cq->napi);
159 /* nothing regarding napi, it's shared with rx ring */
160 cq->xdp_busy = false;
168 mlx4_release_eq(mdev->dev, cq->vector);
169 cq->vector = mdev->dev->caps.num_comp_vectors;
173 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq)
175 struct mlx4_en_dev *mdev = priv->mdev;
176 struct mlx4_en_cq *cq = *pcq;
178 mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
179 if (mlx4_is_eq_vector_valid(mdev->dev, priv->port, cq->vector) &&
181 mlx4_release_eq(priv->mdev->dev, cq->vector);
189 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
191 if (cq->type != TX_XDP) {
192 napi_disable(&cq->napi);
193 netif_napi_del(&cq->napi);
196 mlx4_cq_free(priv->mdev->dev, &cq->mcq);
199 /* Set rx cq moderation parameters */
200 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
202 return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
203 cq->moder_cnt, cq->moder_time);
206 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
208 mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
209 &priv->mdev->uar_lock);