2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
45 #include <linux/delay.h>
46 #include <linux/etherdevice.h>
53 #include "mlx4_stats.h"
55 #define CMD_POLL_TOKEN 0xffff
56 #define INBOX_MASK 0xffffffffffffff00ULL
58 #define CMD_CHAN_VER 1
59 #define CMD_CHAN_IF_REV 1
62 /* command completed successfully: */
64 /* Internal error (such as a bus error) occurred while processing command: */
65 CMD_STAT_INTERNAL_ERR = 0x01,
66 /* Operation/command not supported or opcode modifier not supported: */
67 CMD_STAT_BAD_OP = 0x02,
68 /* Parameter not supported or parameter out of range: */
69 CMD_STAT_BAD_PARAM = 0x03,
70 /* System not enabled or bad system state: */
71 CMD_STAT_BAD_SYS_STATE = 0x04,
72 /* Attempt to access reserved or unallocaterd resource: */
73 CMD_STAT_BAD_RESOURCE = 0x05,
74 /* Requested resource is currently executing a command, or is otherwise busy: */
75 CMD_STAT_RESOURCE_BUSY = 0x06,
76 /* Required capability exceeds device limits: */
77 CMD_STAT_EXCEED_LIM = 0x08,
78 /* Resource is not in the appropriate state or ownership: */
79 CMD_STAT_BAD_RES_STATE = 0x09,
80 /* Index out of range: */
81 CMD_STAT_BAD_INDEX = 0x0a,
82 /* FW image corrupted: */
83 CMD_STAT_BAD_NVMEM = 0x0b,
84 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
85 CMD_STAT_ICM_ERROR = 0x0c,
86 /* Attempt to modify a QP/EE which is not in the presumed state: */
87 CMD_STAT_BAD_QP_STATE = 0x10,
88 /* Bad segment parameters (Address/Size): */
89 CMD_STAT_BAD_SEG_PARAM = 0x20,
90 /* Memory Region has Memory Windows bound to: */
91 CMD_STAT_REG_BOUND = 0x21,
92 /* HCA local attached memory not present: */
93 CMD_STAT_LAM_NOT_PRE = 0x22,
94 /* Bad management packet (silently discarded): */
95 CMD_STAT_BAD_PKT = 0x30,
96 /* More outstanding CQEs in CQ than new CQ size: */
97 CMD_STAT_BAD_SIZE = 0x40,
98 /* Multi Function device support required: */
99 CMD_STAT_MULTI_FUNC_REQ = 0x50,
103 HCR_IN_PARAM_OFFSET = 0x00,
104 HCR_IN_MODIFIER_OFFSET = 0x08,
105 HCR_OUT_PARAM_OFFSET = 0x0c,
106 HCR_TOKEN_OFFSET = 0x14,
107 HCR_STATUS_OFFSET = 0x18,
109 HCR_OPMOD_SHIFT = 12,
116 GO_BIT_TIMEOUT_MSECS = 10000
119 enum mlx4_vlan_transition {
120 MLX4_VLAN_TRANSITION_VST_VST = 0,
121 MLX4_VLAN_TRANSITION_VST_VGT = 1,
122 MLX4_VLAN_TRANSITION_VGT_VST = 2,
123 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
127 struct mlx4_cmd_context {
128 struct completion done;
136 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
137 struct mlx4_vhcr_cmd *in_vhcr);
139 static int mlx4_status_to_errno(u8 status)
141 static const int trans_table[] = {
142 [CMD_STAT_INTERNAL_ERR] = -EIO,
143 [CMD_STAT_BAD_OP] = -EPERM,
144 [CMD_STAT_BAD_PARAM] = -EINVAL,
145 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
146 [CMD_STAT_BAD_RESOURCE] = -EBADF,
147 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
148 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
149 [CMD_STAT_BAD_RES_STATE] = -EBADF,
150 [CMD_STAT_BAD_INDEX] = -EBADF,
151 [CMD_STAT_BAD_NVMEM] = -EFAULT,
152 [CMD_STAT_ICM_ERROR] = -ENFILE,
153 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
154 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
155 [CMD_STAT_REG_BOUND] = -EBUSY,
156 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
157 [CMD_STAT_BAD_PKT] = -EINVAL,
158 [CMD_STAT_BAD_SIZE] = -ENOMEM,
159 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
162 if (status >= ARRAY_SIZE(trans_table) ||
163 (status != CMD_STAT_OK && trans_table[status] == 0))
166 return trans_table[status];
169 static u8 mlx4_errno_to_status(int errno)
173 return CMD_STAT_BAD_OP;
175 return CMD_STAT_BAD_PARAM;
177 return CMD_STAT_BAD_SYS_STATE;
179 return CMD_STAT_RESOURCE_BUSY;
181 return CMD_STAT_EXCEED_LIM;
183 return CMD_STAT_ICM_ERROR;
185 return CMD_STAT_INTERNAL_ERR;
189 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
193 case MLX4_CMD_UNMAP_ICM:
194 case MLX4_CMD_UNMAP_ICM_AUX:
195 case MLX4_CMD_UNMAP_FA:
196 case MLX4_CMD_2RST_QP:
197 case MLX4_CMD_HW2SW_EQ:
198 case MLX4_CMD_HW2SW_CQ:
199 case MLX4_CMD_HW2SW_SRQ:
200 case MLX4_CMD_HW2SW_MPT:
201 case MLX4_CMD_CLOSE_HCA:
202 case MLX4_QP_FLOW_STEERING_DETACH:
203 case MLX4_CMD_FREE_RES:
204 case MLX4_CMD_CLOSE_PORT:
207 case MLX4_CMD_QP_ATTACH:
208 /* On Detach case return success */
209 if (op_modifier == 0)
211 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
214 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
218 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
220 /* Any error during the closing commands below is considered fatal */
221 if (op == MLX4_CMD_CLOSE_HCA ||
222 op == MLX4_CMD_HW2SW_EQ ||
223 op == MLX4_CMD_HW2SW_CQ ||
224 op == MLX4_CMD_2RST_QP ||
225 op == MLX4_CMD_HW2SW_SRQ ||
226 op == MLX4_CMD_SYNC_TPT ||
227 op == MLX4_CMD_UNMAP_ICM ||
228 op == MLX4_CMD_UNMAP_ICM_AUX ||
229 op == MLX4_CMD_UNMAP_FA)
231 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
232 * CMD_STAT_REG_BOUND.
233 * This status indicates that memory region has memory windows bound to it
234 * which may result from invalid user space usage and is not fatal.
236 if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
241 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
244 /* Only if reset flow is really active return code is based on
245 * command, otherwise current error code is returned.
247 if (mlx4_internal_err_reset) {
248 mlx4_enter_error_state(dev->persist);
249 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
255 static int comm_pending(struct mlx4_dev *dev)
257 struct mlx4_priv *priv = mlx4_priv(dev);
258 u32 status = readl(&priv->mfunc.comm->slave_read);
260 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
263 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
265 struct mlx4_priv *priv = mlx4_priv(dev);
268 /* To avoid writing to unknown addresses after the device state was
269 * changed to internal error and the function was rest,
270 * check the INTERNAL_ERROR flag which is updated under
271 * device_state_mutex lock.
273 mutex_lock(&dev->persist->device_state_mutex);
275 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
276 mutex_unlock(&dev->persist->device_state_mutex);
280 priv->cmd.comm_toggle ^= 1;
281 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
282 __raw_writel((__force u32) cpu_to_be32(val),
283 &priv->mfunc.comm->slave_write);
284 mutex_unlock(&dev->persist->device_state_mutex);
288 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
289 unsigned long timeout)
291 struct mlx4_priv *priv = mlx4_priv(dev);
294 int ret_from_pending = 0;
296 /* First, verify that the master reports correct status */
297 if (comm_pending(dev)) {
298 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
299 priv->cmd.comm_toggle, cmd);
304 down(&priv->cmd.poll_sem);
305 if (mlx4_comm_cmd_post(dev, cmd, param)) {
306 /* Only in case the device state is INTERNAL_ERROR,
307 * mlx4_comm_cmd_post returns with an error
309 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
313 end = msecs_to_jiffies(timeout) + jiffies;
314 while (comm_pending(dev) && time_before(jiffies, end))
316 ret_from_pending = comm_pending(dev);
317 if (ret_from_pending) {
318 /* check if the slave is trying to boot in the middle of
319 * FLR process. The only non-zero result in the RESET command
320 * is MLX4_DELAY_RESET_SLAVE*/
321 if ((MLX4_COMM_CMD_RESET == cmd)) {
322 err = MLX4_DELAY_RESET_SLAVE;
325 mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
327 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
332 mlx4_enter_error_state(dev->persist);
334 up(&priv->cmd.poll_sem);
338 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
339 u16 param, u16 op, unsigned long timeout)
341 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
342 struct mlx4_cmd_context *context;
346 down(&cmd->event_sem);
348 spin_lock(&cmd->context_lock);
349 BUG_ON(cmd->free_head < 0);
350 context = &cmd->context[cmd->free_head];
351 context->token += cmd->token_mask + 1;
352 cmd->free_head = context->next;
353 spin_unlock(&cmd->context_lock);
355 reinit_completion(&context->done);
357 if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
358 /* Only in case the device state is INTERNAL_ERROR,
359 * mlx4_comm_cmd_post returns with an error
361 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
365 if (!wait_for_completion_timeout(&context->done,
366 msecs_to_jiffies(timeout))) {
367 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
372 err = context->result;
373 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
374 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
375 vhcr_cmd, context->fw_status);
376 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
380 /* wait for comm channel ready
381 * this is necessary for prevention the race
382 * when switching between event to polling mode
383 * Skipping this section in case the device is in FATAL_ERROR state,
384 * In this state, no commands are sent via the comm channel until
385 * the device has returned from reset.
387 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
388 end = msecs_to_jiffies(timeout) + jiffies;
389 while (comm_pending(dev) && time_before(jiffies, end))
395 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
396 mlx4_enter_error_state(dev->persist);
398 spin_lock(&cmd->context_lock);
399 context->next = cmd->free_head;
400 cmd->free_head = context - cmd->context;
401 spin_unlock(&cmd->context_lock);
407 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
408 u16 op, unsigned long timeout)
410 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
411 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
413 if (mlx4_priv(dev)->cmd.use_events)
414 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
415 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
418 static int cmd_pending(struct mlx4_dev *dev)
422 if (pci_channel_offline(dev->persist->pdev))
425 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
427 return (status & swab32(1 << HCR_GO_BIT)) ||
428 (mlx4_priv(dev)->cmd.toggle ==
429 !!(status & swab32(1 << HCR_T_BIT)));
432 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
433 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
436 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
437 u32 __iomem *hcr = cmd->hcr;
441 mutex_lock(&dev->persist->device_state_mutex);
442 /* To avoid writing to unknown addresses after the device state was
443 * changed to internal error and the chip was reset,
444 * check the INTERNAL_ERROR flag which is updated under
445 * device_state_mutex lock.
447 if (pci_channel_offline(dev->persist->pdev) ||
448 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
450 * Device is going through error recovery
451 * and cannot accept commands.
458 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
460 while (cmd_pending(dev)) {
461 if (pci_channel_offline(dev->persist->pdev)) {
463 * Device is going through error recovery
464 * and cannot accept commands.
469 if (time_after_eq(jiffies, end)) {
470 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
477 * We use writel (instead of something like memcpy_toio)
478 * because writes of less than 32 bits to the HCR don't work
479 * (and some architectures such as ia64 implement memcpy_toio
480 * in terms of writeb).
482 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
483 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
484 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
485 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
486 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
487 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
489 /* __raw_writel may not order writes. */
492 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
493 (cmd->toggle << HCR_T_BIT) |
494 (event ? (1 << HCR_E_BIT) : 0) |
495 (op_modifier << HCR_OPMOD_SHIFT) |
498 cmd->toggle = cmd->toggle ^ 1;
504 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
505 op, ret, in_param, in_modifier, op_modifier);
506 mutex_unlock(&dev->persist->device_state_mutex);
511 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
512 int out_is_imm, u32 in_modifier, u8 op_modifier,
513 u16 op, unsigned long timeout)
515 struct mlx4_priv *priv = mlx4_priv(dev);
516 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
519 mutex_lock(&priv->cmd.slave_cmd_mutex);
521 vhcr->in_param = cpu_to_be64(in_param);
522 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
523 vhcr->in_modifier = cpu_to_be32(in_modifier);
524 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
525 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
527 vhcr->flags = !!(priv->cmd.use_events) << 6;
529 if (mlx4_is_master(dev)) {
530 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
535 be64_to_cpu(vhcr->out_param);
537 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
539 vhcr->status = CMD_STAT_BAD_PARAM;
542 ret = mlx4_status_to_errno(vhcr->status);
545 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
546 ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
548 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
549 MLX4_COMM_TIME + timeout);
554 be64_to_cpu(vhcr->out_param);
556 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
558 vhcr->status = CMD_STAT_BAD_PARAM;
561 ret = mlx4_status_to_errno(vhcr->status);
563 if (dev->persist->state &
564 MLX4_DEVICE_STATE_INTERNAL_ERROR)
565 ret = mlx4_internal_err_ret_value(dev, op,
568 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
572 mutex_unlock(&priv->cmd.slave_cmd_mutex);
576 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
577 int out_is_imm, u32 in_modifier, u8 op_modifier,
578 u16 op, unsigned long timeout)
580 struct mlx4_priv *priv = mlx4_priv(dev);
581 void __iomem *hcr = priv->cmd.hcr;
586 down(&priv->cmd.poll_sem);
588 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
590 * Device is going through error recovery
591 * and cannot accept commands.
593 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
597 if (out_is_imm && !out_param) {
598 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
604 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
605 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
609 end = msecs_to_jiffies(timeout) + jiffies;
610 while (cmd_pending(dev) && time_before(jiffies, end)) {
611 if (pci_channel_offline(dev->persist->pdev)) {
613 * Device is going through error recovery
614 * and cannot accept commands.
620 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
621 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
628 if (cmd_pending(dev)) {
629 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
637 (u64) be32_to_cpu((__force __be32)
638 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
639 (u64) be32_to_cpu((__force __be32)
640 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
641 stat = be32_to_cpu((__force __be32)
642 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
643 err = mlx4_status_to_errno(stat);
645 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
647 if (mlx4_closing_cmd_fatal_error(op, stat))
654 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
656 up(&priv->cmd.poll_sem);
660 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
662 struct mlx4_priv *priv = mlx4_priv(dev);
663 struct mlx4_cmd_context *context =
664 &priv->cmd.context[token & priv->cmd.token_mask];
666 /* previously timed out command completing at long last */
667 if (token != context->token)
670 context->fw_status = status;
671 context->result = mlx4_status_to_errno(status);
672 context->out_param = out_param;
674 complete(&context->done);
677 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
678 int out_is_imm, u32 in_modifier, u8 op_modifier,
679 u16 op, unsigned long timeout)
681 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
682 struct mlx4_cmd_context *context;
686 down(&cmd->event_sem);
688 spin_lock(&cmd->context_lock);
689 BUG_ON(cmd->free_head < 0);
690 context = &cmd->context[cmd->free_head];
691 context->token += cmd->token_mask + 1;
692 cmd->free_head = context->next;
693 spin_unlock(&cmd->context_lock);
695 if (out_is_imm && !out_param) {
696 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
702 reinit_completion(&context->done);
704 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
705 in_modifier, op_modifier, op, context->token, 1);
709 if (op == MLX4_CMD_SENSE_PORT) {
711 wait_for_completion_interruptible_timeout(&context->done,
712 msecs_to_jiffies(timeout));
714 context->fw_status = 0;
715 context->out_param = 0;
719 ret_wait = (long)wait_for_completion_timeout(&context->done,
720 msecs_to_jiffies(timeout));
723 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
725 if (op == MLX4_CMD_NOP) {
734 err = context->result;
736 /* Since we do not want to have this error message always
737 * displayed at driver start when there are ConnectX2 HCAs
738 * on the host, we deprecate the error message for this
739 * specific command/input_mod/opcode_mod/fw-status to be debug.
741 if (op == MLX4_CMD_SET_PORT &&
742 (in_modifier == 1 || in_modifier == 2) &&
743 op_modifier == MLX4_SET_PORT_IB_OPCODE &&
744 context->fw_status == CMD_STAT_BAD_SIZE)
745 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
746 op, context->fw_status);
748 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
749 op, context->fw_status);
750 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
751 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
752 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
759 *out_param = context->out_param;
763 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
765 spin_lock(&cmd->context_lock);
766 context->next = cmd->free_head;
767 cmd->free_head = context - cmd->context;
768 spin_unlock(&cmd->context_lock);
774 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
775 int out_is_imm, u32 in_modifier, u8 op_modifier,
776 u16 op, unsigned long timeout, int native)
778 if (pci_channel_offline(dev->persist->pdev))
779 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
781 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
784 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
785 return mlx4_internal_err_ret_value(dev, op,
787 down_read(&mlx4_priv(dev)->cmd.switch_sem);
788 if (mlx4_priv(dev)->cmd.use_events)
789 ret = mlx4_cmd_wait(dev, in_param, out_param,
790 out_is_imm, in_modifier,
791 op_modifier, op, timeout);
793 ret = mlx4_cmd_poll(dev, in_param, out_param,
794 out_is_imm, in_modifier,
795 op_modifier, op, timeout);
797 up_read(&mlx4_priv(dev)->cmd.switch_sem);
800 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
801 in_modifier, op_modifier, op, timeout);
803 EXPORT_SYMBOL_GPL(__mlx4_cmd);
806 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
808 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
809 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
812 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
813 int slave, u64 slave_addr,
814 int size, int is_read)
819 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
820 (slave & ~0x7f) | (size & 0xff)) {
821 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
822 slave_addr, master_addr, slave, size);
827 in_param = (u64) slave | slave_addr;
828 out_param = (u64) dev->caps.function | master_addr;
830 in_param = (u64) dev->caps.function | master_addr;
831 out_param = (u64) slave | slave_addr;
834 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
836 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
839 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
840 struct mlx4_cmd_mailbox *inbox,
841 struct mlx4_cmd_mailbox *outbox)
843 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
844 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
851 in_mad->attr_mod = cpu_to_be32(index / 32);
853 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
854 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
859 for (i = 0; i < 32; ++i)
860 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
865 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
866 struct mlx4_cmd_mailbox *inbox,
867 struct mlx4_cmd_mailbox *outbox)
872 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
873 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
880 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
881 #define PORT_STATE_OFFSET 32
883 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
885 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
886 return IB_PORT_ACTIVE;
891 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
892 struct mlx4_vhcr *vhcr,
893 struct mlx4_cmd_mailbox *inbox,
894 struct mlx4_cmd_mailbox *outbox,
895 struct mlx4_cmd_info *cmd)
897 struct ib_smp *smp = inbox->buf;
905 struct mlx4_priv *priv = mlx4_priv(dev);
906 struct ib_smp *outsmp = outbox->buf;
907 __be16 *outtab = (__be16 *)(outsmp->data);
908 __be32 slave_cap_mask;
909 __be64 slave_node_guid;
911 slave_port = vhcr->in_modifier;
912 port = mlx4_slave_convert_port(dev, slave, slave_port);
914 /* network-view bit is for driver use only, and should not be passed to FW */
915 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
916 network_view = !!(vhcr->op_modifier & 0x8);
918 if (smp->base_version == 1 &&
919 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
920 smp->class_version == 1) {
921 /* host view is paravirtualized */
922 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
923 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
924 index = be32_to_cpu(smp->attr_mod);
925 if (port < 1 || port > dev->caps.num_ports)
927 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
928 sizeof(*table) * 32, GFP_KERNEL);
932 /* need to get the full pkey table because the paravirtualized
933 * pkeys may be scattered among several pkey blocks.
935 err = get_full_pkey_table(dev, port, table, inbox, outbox);
937 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
938 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
939 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
945 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
946 /*get the slave specific caps:*/
948 smp->attr_mod = cpu_to_be32(port);
949 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
950 port, opcode_modifier,
951 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
952 /* modify the response for slaves */
953 if (!err && slave != mlx4_master_func_num(dev)) {
954 u8 *state = outsmp->data + PORT_STATE_OFFSET;
956 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
957 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
958 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
962 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
963 __be64 guid = mlx4_get_admin_guid(dev, slave,
966 /* set the PF admin guid to the FW/HW burned
967 * GUID, if it wasn't yet set
969 if (slave == 0 && guid == 0) {
971 err = mlx4_cmd_box(dev,
977 MLX4_CMD_TIME_CLASS_C,
981 mlx4_set_admin_guid(dev,
985 memcpy(outsmp->data, &guid, 8);
988 /* clean all other gids */
989 memset(outsmp->data + 8, 0, 56);
992 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
993 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
994 port, opcode_modifier,
995 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
997 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
998 memcpy(outsmp->data + 12, &slave_node_guid, 8);
1005 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
1006 * These are the MADs used by ib verbs (such as ib_query_gids).
1008 if (slave != mlx4_master_func_num(dev) &&
1009 !mlx4_vf_smi_enabled(dev, slave, port)) {
1010 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
1011 smp->method == IB_MGMT_METHOD_GET) || network_view) {
1012 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
1013 slave, smp->mgmt_class, smp->method,
1014 network_view ? "Network" : "Host",
1015 be16_to_cpu(smp->attr_id));
1020 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1021 vhcr->in_modifier, opcode_modifier,
1022 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1025 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
1026 struct mlx4_vhcr *vhcr,
1027 struct mlx4_cmd_mailbox *inbox,
1028 struct mlx4_cmd_mailbox *outbox,
1029 struct mlx4_cmd_info *cmd)
1034 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1035 struct mlx4_vhcr *vhcr,
1036 struct mlx4_cmd_mailbox *inbox,
1037 struct mlx4_cmd_mailbox *outbox,
1038 struct mlx4_cmd_info *cmd)
1044 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1045 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1046 if (cmd->encode_slave_id) {
1047 in_param &= 0xffffffffffffff00ll;
1051 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1052 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1053 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1055 if (cmd->out_is_imm)
1056 vhcr->out_param = out_param;
1061 static struct mlx4_cmd_info cmd_info[] = {
1063 .opcode = MLX4_CMD_QUERY_FW,
1066 .out_is_imm = false,
1067 .encode_slave_id = false,
1069 .wrapper = mlx4_QUERY_FW_wrapper
1072 .opcode = MLX4_CMD_QUERY_HCA,
1075 .out_is_imm = false,
1076 .encode_slave_id = false,
1081 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1084 .out_is_imm = false,
1085 .encode_slave_id = false,
1087 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1090 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1093 .out_is_imm = false,
1094 .encode_slave_id = false,
1096 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1099 .opcode = MLX4_CMD_QUERY_ADAPTER,
1102 .out_is_imm = false,
1103 .encode_slave_id = false,
1108 .opcode = MLX4_CMD_INIT_PORT,
1110 .has_outbox = false,
1111 .out_is_imm = false,
1112 .encode_slave_id = false,
1114 .wrapper = mlx4_INIT_PORT_wrapper
1117 .opcode = MLX4_CMD_CLOSE_PORT,
1119 .has_outbox = false,
1120 .out_is_imm = false,
1121 .encode_slave_id = false,
1123 .wrapper = mlx4_CLOSE_PORT_wrapper
1126 .opcode = MLX4_CMD_QUERY_PORT,
1129 .out_is_imm = false,
1130 .encode_slave_id = false,
1132 .wrapper = mlx4_QUERY_PORT_wrapper
1135 .opcode = MLX4_CMD_SET_PORT,
1137 .has_outbox = false,
1138 .out_is_imm = false,
1139 .encode_slave_id = false,
1141 .wrapper = mlx4_SET_PORT_wrapper
1144 .opcode = MLX4_CMD_MAP_EQ,
1146 .has_outbox = false,
1147 .out_is_imm = false,
1148 .encode_slave_id = false,
1150 .wrapper = mlx4_MAP_EQ_wrapper
1153 .opcode = MLX4_CMD_SW2HW_EQ,
1155 .has_outbox = false,
1156 .out_is_imm = false,
1157 .encode_slave_id = true,
1159 .wrapper = mlx4_SW2HW_EQ_wrapper
1162 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1164 .has_outbox = false,
1165 .out_is_imm = false,
1166 .encode_slave_id = false,
1171 .opcode = MLX4_CMD_NOP,
1173 .has_outbox = false,
1174 .out_is_imm = false,
1175 .encode_slave_id = false,
1180 .opcode = MLX4_CMD_CONFIG_DEV,
1183 .out_is_imm = false,
1184 .encode_slave_id = false,
1186 .wrapper = mlx4_CONFIG_DEV_wrapper
1189 .opcode = MLX4_CMD_ALLOC_RES,
1191 .has_outbox = false,
1193 .encode_slave_id = false,
1195 .wrapper = mlx4_ALLOC_RES_wrapper
1198 .opcode = MLX4_CMD_FREE_RES,
1200 .has_outbox = false,
1201 .out_is_imm = false,
1202 .encode_slave_id = false,
1204 .wrapper = mlx4_FREE_RES_wrapper
1207 .opcode = MLX4_CMD_SW2HW_MPT,
1209 .has_outbox = false,
1210 .out_is_imm = false,
1211 .encode_slave_id = true,
1213 .wrapper = mlx4_SW2HW_MPT_wrapper
1216 .opcode = MLX4_CMD_QUERY_MPT,
1219 .out_is_imm = false,
1220 .encode_slave_id = false,
1222 .wrapper = mlx4_QUERY_MPT_wrapper
1225 .opcode = MLX4_CMD_HW2SW_MPT,
1227 .has_outbox = false,
1228 .out_is_imm = false,
1229 .encode_slave_id = false,
1231 .wrapper = mlx4_HW2SW_MPT_wrapper
1234 .opcode = MLX4_CMD_READ_MTT,
1237 .out_is_imm = false,
1238 .encode_slave_id = false,
1243 .opcode = MLX4_CMD_WRITE_MTT,
1245 .has_outbox = false,
1246 .out_is_imm = false,
1247 .encode_slave_id = false,
1249 .wrapper = mlx4_WRITE_MTT_wrapper
1252 .opcode = MLX4_CMD_SYNC_TPT,
1254 .has_outbox = false,
1255 .out_is_imm = false,
1256 .encode_slave_id = false,
1261 .opcode = MLX4_CMD_HW2SW_EQ,
1263 .has_outbox = false,
1264 .out_is_imm = false,
1265 .encode_slave_id = true,
1267 .wrapper = mlx4_HW2SW_EQ_wrapper
1270 .opcode = MLX4_CMD_QUERY_EQ,
1273 .out_is_imm = false,
1274 .encode_slave_id = true,
1276 .wrapper = mlx4_QUERY_EQ_wrapper
1279 .opcode = MLX4_CMD_SW2HW_CQ,
1281 .has_outbox = false,
1282 .out_is_imm = false,
1283 .encode_slave_id = true,
1285 .wrapper = mlx4_SW2HW_CQ_wrapper
1288 .opcode = MLX4_CMD_HW2SW_CQ,
1290 .has_outbox = false,
1291 .out_is_imm = false,
1292 .encode_slave_id = false,
1294 .wrapper = mlx4_HW2SW_CQ_wrapper
1297 .opcode = MLX4_CMD_QUERY_CQ,
1300 .out_is_imm = false,
1301 .encode_slave_id = false,
1303 .wrapper = mlx4_QUERY_CQ_wrapper
1306 .opcode = MLX4_CMD_MODIFY_CQ,
1308 .has_outbox = false,
1310 .encode_slave_id = false,
1312 .wrapper = mlx4_MODIFY_CQ_wrapper
1315 .opcode = MLX4_CMD_SW2HW_SRQ,
1317 .has_outbox = false,
1318 .out_is_imm = false,
1319 .encode_slave_id = true,
1321 .wrapper = mlx4_SW2HW_SRQ_wrapper
1324 .opcode = MLX4_CMD_HW2SW_SRQ,
1326 .has_outbox = false,
1327 .out_is_imm = false,
1328 .encode_slave_id = false,
1330 .wrapper = mlx4_HW2SW_SRQ_wrapper
1333 .opcode = MLX4_CMD_QUERY_SRQ,
1336 .out_is_imm = false,
1337 .encode_slave_id = false,
1339 .wrapper = mlx4_QUERY_SRQ_wrapper
1342 .opcode = MLX4_CMD_ARM_SRQ,
1344 .has_outbox = false,
1345 .out_is_imm = false,
1346 .encode_slave_id = false,
1348 .wrapper = mlx4_ARM_SRQ_wrapper
1351 .opcode = MLX4_CMD_RST2INIT_QP,
1353 .has_outbox = false,
1354 .out_is_imm = false,
1355 .encode_slave_id = true,
1357 .wrapper = mlx4_RST2INIT_QP_wrapper
1360 .opcode = MLX4_CMD_INIT2INIT_QP,
1362 .has_outbox = false,
1363 .out_is_imm = false,
1364 .encode_slave_id = false,
1366 .wrapper = mlx4_INIT2INIT_QP_wrapper
1369 .opcode = MLX4_CMD_INIT2RTR_QP,
1371 .has_outbox = false,
1372 .out_is_imm = false,
1373 .encode_slave_id = false,
1375 .wrapper = mlx4_INIT2RTR_QP_wrapper
1378 .opcode = MLX4_CMD_RTR2RTS_QP,
1380 .has_outbox = false,
1381 .out_is_imm = false,
1382 .encode_slave_id = false,
1384 .wrapper = mlx4_RTR2RTS_QP_wrapper
1387 .opcode = MLX4_CMD_RTS2RTS_QP,
1389 .has_outbox = false,
1390 .out_is_imm = false,
1391 .encode_slave_id = false,
1393 .wrapper = mlx4_RTS2RTS_QP_wrapper
1396 .opcode = MLX4_CMD_SQERR2RTS_QP,
1398 .has_outbox = false,
1399 .out_is_imm = false,
1400 .encode_slave_id = false,
1402 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1405 .opcode = MLX4_CMD_2ERR_QP,
1407 .has_outbox = false,
1408 .out_is_imm = false,
1409 .encode_slave_id = false,
1411 .wrapper = mlx4_GEN_QP_wrapper
1414 .opcode = MLX4_CMD_RTS2SQD_QP,
1416 .has_outbox = false,
1417 .out_is_imm = false,
1418 .encode_slave_id = false,
1420 .wrapper = mlx4_GEN_QP_wrapper
1423 .opcode = MLX4_CMD_SQD2SQD_QP,
1425 .has_outbox = false,
1426 .out_is_imm = false,
1427 .encode_slave_id = false,
1429 .wrapper = mlx4_SQD2SQD_QP_wrapper
1432 .opcode = MLX4_CMD_SQD2RTS_QP,
1434 .has_outbox = false,
1435 .out_is_imm = false,
1436 .encode_slave_id = false,
1438 .wrapper = mlx4_SQD2RTS_QP_wrapper
1441 .opcode = MLX4_CMD_2RST_QP,
1443 .has_outbox = false,
1444 .out_is_imm = false,
1445 .encode_slave_id = false,
1447 .wrapper = mlx4_2RST_QP_wrapper
1450 .opcode = MLX4_CMD_QUERY_QP,
1453 .out_is_imm = false,
1454 .encode_slave_id = false,
1456 .wrapper = mlx4_GEN_QP_wrapper
1459 .opcode = MLX4_CMD_SUSPEND_QP,
1461 .has_outbox = false,
1462 .out_is_imm = false,
1463 .encode_slave_id = false,
1465 .wrapper = mlx4_GEN_QP_wrapper
1468 .opcode = MLX4_CMD_UNSUSPEND_QP,
1470 .has_outbox = false,
1471 .out_is_imm = false,
1472 .encode_slave_id = false,
1474 .wrapper = mlx4_GEN_QP_wrapper
1477 .opcode = MLX4_CMD_UPDATE_QP,
1479 .has_outbox = false,
1480 .out_is_imm = false,
1481 .encode_slave_id = false,
1483 .wrapper = mlx4_UPDATE_QP_wrapper
1486 .opcode = MLX4_CMD_GET_OP_REQ,
1488 .has_outbox = false,
1489 .out_is_imm = false,
1490 .encode_slave_id = false,
1492 .wrapper = mlx4_CMD_EPERM_wrapper,
1495 .opcode = MLX4_CMD_ALLOCATE_VPP,
1498 .out_is_imm = false,
1499 .encode_slave_id = false,
1501 .wrapper = mlx4_CMD_EPERM_wrapper,
1504 .opcode = MLX4_CMD_SET_VPORT_QOS,
1507 .out_is_imm = false,
1508 .encode_slave_id = false,
1510 .wrapper = mlx4_CMD_EPERM_wrapper,
1513 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1515 .has_outbox = false,
1516 .out_is_imm = false,
1517 .encode_slave_id = false,
1518 .verify = NULL, /* XXX verify: only demux can do this */
1522 .opcode = MLX4_CMD_MAD_IFC,
1525 .out_is_imm = false,
1526 .encode_slave_id = false,
1528 .wrapper = mlx4_MAD_IFC_wrapper
1531 .opcode = MLX4_CMD_MAD_DEMUX,
1533 .has_outbox = false,
1534 .out_is_imm = false,
1535 .encode_slave_id = false,
1537 .wrapper = mlx4_CMD_EPERM_wrapper
1540 .opcode = MLX4_CMD_QUERY_IF_STAT,
1543 .out_is_imm = false,
1544 .encode_slave_id = false,
1546 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1549 .opcode = MLX4_CMD_ACCESS_REG,
1552 .out_is_imm = false,
1553 .encode_slave_id = false,
1555 .wrapper = mlx4_ACCESS_REG_wrapper,
1558 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1560 .has_outbox = false,
1561 .out_is_imm = false,
1562 .encode_slave_id = false,
1564 .wrapper = mlx4_CMD_EPERM_wrapper,
1566 /* Native multicast commands are not available for guests */
1568 .opcode = MLX4_CMD_QP_ATTACH,
1570 .has_outbox = false,
1571 .out_is_imm = false,
1572 .encode_slave_id = false,
1574 .wrapper = mlx4_QP_ATTACH_wrapper
1577 .opcode = MLX4_CMD_PROMISC,
1579 .has_outbox = false,
1580 .out_is_imm = false,
1581 .encode_slave_id = false,
1583 .wrapper = mlx4_PROMISC_wrapper
1585 /* Ethernet specific commands */
1587 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1589 .has_outbox = false,
1590 .out_is_imm = false,
1591 .encode_slave_id = false,
1593 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1596 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1598 .has_outbox = false,
1599 .out_is_imm = false,
1600 .encode_slave_id = false,
1602 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1605 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1608 .out_is_imm = false,
1609 .encode_slave_id = false,
1611 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1614 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1616 .has_outbox = false,
1617 .out_is_imm = false,
1618 .encode_slave_id = false,
1622 /* flow steering commands */
1624 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1626 .has_outbox = false,
1628 .encode_slave_id = false,
1630 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1633 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1635 .has_outbox = false,
1636 .out_is_imm = false,
1637 .encode_slave_id = false,
1639 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1642 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1644 .has_outbox = false,
1645 .out_is_imm = false,
1646 .encode_slave_id = false,
1648 .wrapper = mlx4_CMD_EPERM_wrapper
1651 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1653 .has_outbox = false,
1654 .out_is_imm = false,
1655 .encode_slave_id = false,
1657 .wrapper = mlx4_CMD_EPERM_wrapper
1661 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1662 struct mlx4_vhcr_cmd *in_vhcr)
1664 struct mlx4_priv *priv = mlx4_priv(dev);
1665 struct mlx4_cmd_info *cmd = NULL;
1666 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1667 struct mlx4_vhcr *vhcr;
1668 struct mlx4_cmd_mailbox *inbox = NULL;
1669 struct mlx4_cmd_mailbox *outbox = NULL;
1676 /* Create sw representation of Virtual HCR */
1677 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1681 /* DMA in the vHCR */
1683 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1684 priv->mfunc.master.slave_state[slave].vhcr_dma,
1685 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1686 MLX4_ACCESS_MEM_ALIGN), 1);
1688 if (!(dev->persist->state &
1689 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1690 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1697 /* Fill SW VHCR fields */
1698 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1699 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1700 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1701 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1702 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1703 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1704 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1706 /* Lookup command */
1707 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1708 if (vhcr->op == cmd_info[i].opcode) {
1714 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1716 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1721 if (cmd->has_inbox) {
1722 vhcr->in_param &= INBOX_MASK;
1723 inbox = mlx4_alloc_cmd_mailbox(dev);
1724 if (IS_ERR(inbox)) {
1725 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1730 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1732 MLX4_MAILBOX_SIZE, 1);
1734 if (!(dev->persist->state &
1735 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1736 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1737 __func__, cmd->opcode);
1738 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1743 /* Apply permission and bound checks if applicable */
1744 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1745 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1746 vhcr->op, slave, vhcr->in_modifier);
1747 vhcr_cmd->status = CMD_STAT_BAD_OP;
1751 /* Allocate outbox */
1752 if (cmd->has_outbox) {
1753 outbox = mlx4_alloc_cmd_mailbox(dev);
1754 if (IS_ERR(outbox)) {
1755 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1761 /* Execute the command! */
1763 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1765 if (cmd->out_is_imm)
1766 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1768 in_param = cmd->has_inbox ? (u64) inbox->dma :
1770 out_param = cmd->has_outbox ? (u64) outbox->dma :
1772 err = __mlx4_cmd(dev, in_param, &out_param,
1773 cmd->out_is_imm, vhcr->in_modifier,
1774 vhcr->op_modifier, vhcr->op,
1775 MLX4_CMD_TIME_CLASS_A,
1778 if (cmd->out_is_imm) {
1779 vhcr->out_param = out_param;
1780 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1785 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
1786 if (vhcr->op == MLX4_CMD_ALLOC_RES &&
1787 (vhcr->in_modifier & 0xff) == RES_COUNTER &&
1790 "Unable to allocate counter for slave %d (%d)\n",
1793 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1794 vhcr->op, slave, vhcr->errno, err);
1796 vhcr_cmd->status = mlx4_errno_to_status(err);
1801 /* Write outbox if command completed successfully */
1802 if (cmd->has_outbox && !vhcr_cmd->status) {
1803 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1805 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1807 /* If we failed to write back the outbox after the
1808 *command was successfully executed, we must fail this
1809 * slave, as it is now in undefined state */
1810 if (!(dev->persist->state &
1811 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1812 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1818 /* DMA back vhcr result */
1820 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1821 priv->mfunc.master.slave_state[slave].vhcr_dma,
1822 ALIGN(sizeof(struct mlx4_vhcr),
1823 MLX4_ACCESS_MEM_ALIGN),
1826 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1828 else if (vhcr->e_bit &&
1829 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1830 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1836 mlx4_free_cmd_mailbox(dev, inbox);
1837 mlx4_free_cmd_mailbox(dev, outbox);
1841 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1842 int slave, int port)
1844 struct mlx4_vport_oper_state *vp_oper;
1845 struct mlx4_vport_state *vp_admin;
1846 struct mlx4_vf_immed_vlan_work *work;
1847 struct mlx4_dev *dev = &(priv->dev);
1849 int admin_vlan_ix = NO_INDX;
1851 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1852 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1854 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1855 vp_oper->state.default_qos == vp_admin->default_qos &&
1856 vp_oper->state.vlan_proto == vp_admin->vlan_proto &&
1857 vp_oper->state.link_state == vp_admin->link_state &&
1858 vp_oper->state.qos_vport == vp_admin->qos_vport)
1861 if (!(priv->mfunc.master.slave_state[slave].active &&
1862 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1863 /* even if the UPDATE_QP command isn't supported, we still want
1864 * to set this VF link according to the admin directive
1866 vp_oper->state.link_state = vp_admin->link_state;
1870 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1872 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1873 vp_admin->default_vlan, vp_admin->default_qos,
1874 vp_admin->link_state);
1876 work = kzalloc(sizeof(*work), GFP_KERNEL);
1880 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1881 if (MLX4_VGT != vp_admin->default_vlan) {
1882 err = __mlx4_register_vlan(&priv->dev, port,
1883 vp_admin->default_vlan,
1887 mlx4_warn(&priv->dev,
1888 "No vlan resources slave %d, port %d\n",
1893 admin_vlan_ix = NO_INDX;
1895 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1896 mlx4_dbg(&priv->dev,
1897 "alloc vlan %d idx %d slave %d port %d\n",
1898 (int)(vp_admin->default_vlan),
1899 admin_vlan_ix, slave, port);
1902 /* save original vlan ix and vlan id */
1903 work->orig_vlan_id = vp_oper->state.default_vlan;
1904 work->orig_vlan_ix = vp_oper->vlan_idx;
1906 /* handle new qos */
1907 if (vp_oper->state.default_qos != vp_admin->default_qos)
1908 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1910 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1911 vp_oper->vlan_idx = admin_vlan_ix;
1913 vp_oper->state.default_vlan = vp_admin->default_vlan;
1914 vp_oper->state.default_qos = vp_admin->default_qos;
1915 vp_oper->state.vlan_proto = vp_admin->vlan_proto;
1916 vp_oper->state.link_state = vp_admin->link_state;
1917 vp_oper->state.qos_vport = vp_admin->qos_vport;
1919 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1920 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1922 /* iterate over QPs owned by this slave, using UPDATE_QP */
1924 work->slave = slave;
1925 work->qos = vp_oper->state.default_qos;
1926 work->qos_vport = vp_oper->state.qos_vport;
1927 work->vlan_id = vp_oper->state.default_vlan;
1928 work->vlan_ix = vp_oper->vlan_idx;
1929 work->vlan_proto = vp_oper->state.vlan_proto;
1931 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1932 queue_work(priv->mfunc.master.comm_wq, &work->work);
1937 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1939 struct mlx4_qos_manager *port_qos_ctl;
1940 struct mlx4_priv *priv = mlx4_priv(dev);
1942 port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1943 bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1945 /* Enable only default prio at PF init routine */
1946 set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1949 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1955 u8 vpp_param[MLX4_NUM_UP];
1956 struct mlx4_qos_manager *port_qos;
1957 struct mlx4_priv *priv = mlx4_priv(dev);
1959 err = mlx4_ALLOCATE_VPP_get(dev, port, &available_vpp, vpp_param);
1961 mlx4_info(dev, "Failed query available VPPs\n");
1965 port_qos = &priv->mfunc.master.qos_ctl[port];
1966 num_vfs = (available_vpp /
1967 bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1969 for (i = 0; i < MLX4_NUM_UP; i++) {
1970 if (test_bit(i, port_qos->priority_bm))
1971 vpp_param[i] = num_vfs;
1974 err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1976 mlx4_info(dev, "Failed allocating VPPs\n");
1980 /* Query actual allocated VPP, just to make sure */
1981 err = mlx4_ALLOCATE_VPP_get(dev, port, &available_vpp, vpp_param);
1983 mlx4_info(dev, "Failed query available VPPs\n");
1987 port_qos->num_of_qos_vfs = num_vfs;
1988 mlx4_dbg(dev, "Port %d Available VPPs %d\n", port, available_vpp);
1990 for (i = 0; i < MLX4_NUM_UP; i++)
1991 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1995 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1998 struct mlx4_vport_state *vp_admin;
1999 struct mlx4_vport_oper_state *vp_oper;
2000 struct mlx4_slave_state *slave_state =
2001 &priv->mfunc.master.slave_state[slave];
2002 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2005 for_each_set_bit(p, actv_ports.ports, priv->dev.caps.num_ports) {
2007 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2008 priv->mfunc.master.vf_admin[slave].enable_smi[port];
2009 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2010 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2011 if (vp_admin->vlan_proto != htons(ETH_P_8021AD) ||
2012 slave_state->vst_qinq_supported) {
2013 vp_oper->state.vlan_proto = vp_admin->vlan_proto;
2014 vp_oper->state.default_vlan = vp_admin->default_vlan;
2015 vp_oper->state.default_qos = vp_admin->default_qos;
2017 vp_oper->state.link_state = vp_admin->link_state;
2018 vp_oper->state.mac = vp_admin->mac;
2019 vp_oper->state.spoofchk = vp_admin->spoofchk;
2020 vp_oper->state.tx_rate = vp_admin->tx_rate;
2021 vp_oper->state.qos_vport = vp_admin->qos_vport;
2022 vp_oper->state.guid = vp_admin->guid;
2024 if (MLX4_VGT != vp_admin->default_vlan) {
2025 err = __mlx4_register_vlan(&priv->dev, port,
2026 vp_admin->default_vlan, &(vp_oper->vlan_idx));
2028 vp_oper->vlan_idx = NO_INDX;
2029 vp_oper->state.default_vlan = MLX4_VGT;
2030 vp_oper->state.vlan_proto = htons(ETH_P_8021Q);
2031 mlx4_warn(&priv->dev,
2032 "No vlan resources slave %d, port %d\n",
2036 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
2037 (int)(vp_oper->state.default_vlan),
2038 vp_oper->vlan_idx, slave, port);
2040 if (vp_admin->spoofchk) {
2041 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
2044 if (0 > vp_oper->mac_idx) {
2045 err = vp_oper->mac_idx;
2046 vp_oper->mac_idx = NO_INDX;
2047 mlx4_warn(&priv->dev,
2048 "No mac resources slave %d, port %d\n",
2052 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
2053 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2059 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2062 struct mlx4_vport_oper_state *vp_oper;
2063 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2066 for_each_set_bit(p, actv_ports.ports, priv->dev.caps.num_ports) {
2068 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2069 MLX4_VF_SMI_DISABLED;
2070 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2071 if (NO_INDX != vp_oper->vlan_idx) {
2072 __mlx4_unregister_vlan(&priv->dev,
2073 port, vp_oper->state.default_vlan);
2074 vp_oper->vlan_idx = NO_INDX;
2076 if (NO_INDX != vp_oper->mac_idx) {
2077 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2078 vp_oper->mac_idx = NO_INDX;
2084 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2085 u16 param, u8 toggle)
2087 struct mlx4_priv *priv = mlx4_priv(dev);
2088 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2090 u8 is_going_down = 0;
2092 unsigned long flags;
2094 slave_state[slave].comm_toggle ^= 1;
2095 reply = (u32) slave_state[slave].comm_toggle << 31;
2096 if (toggle != slave_state[slave].comm_toggle) {
2097 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2101 if (cmd == MLX4_COMM_CMD_RESET) {
2102 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2103 slave_state[slave].active = false;
2104 slave_state[slave].old_vlan_api = false;
2105 slave_state[slave].vst_qinq_supported = false;
2106 mlx4_master_deactivate_admin_state(priv, slave);
2107 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2108 slave_state[slave].event_eq[i].eqn = -1;
2109 slave_state[slave].event_eq[i].token = 0;
2111 /*check if we are in the middle of FLR process,
2112 if so return "retry" status to the slave*/
2113 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2114 goto inform_slave_state;
2116 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, &slave);
2118 /* write the version in the event field */
2119 reply |= mlx4_comm_get_version();
2123 /*command from slave in the middle of FLR*/
2124 if (cmd != MLX4_COMM_CMD_RESET &&
2125 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2126 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2132 case MLX4_COMM_CMD_VHCR0:
2133 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2135 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2136 priv->mfunc.master.slave_state[slave].cookie = 0;
2138 case MLX4_COMM_CMD_VHCR1:
2139 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2141 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2143 case MLX4_COMM_CMD_VHCR2:
2144 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2146 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2148 case MLX4_COMM_CMD_VHCR_EN:
2149 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2151 slave_state[slave].vhcr_dma |= param;
2152 if (mlx4_master_activate_admin_state(priv, slave))
2154 slave_state[slave].active = true;
2155 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, &slave);
2157 case MLX4_COMM_CMD_VHCR_POST:
2158 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2159 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2160 mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2161 slave, cmd, slave_state[slave].last_cmd);
2165 mutex_lock(&priv->cmd.slave_cmd_mutex);
2166 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2167 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2169 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2172 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2175 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2178 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2179 if (!slave_state[slave].is_slave_going_down)
2180 slave_state[slave].last_cmd = cmd;
2183 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2184 if (is_going_down) {
2185 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2189 __raw_writel((__force u32) cpu_to_be32(reply),
2190 &priv->mfunc.comm[slave].slave_read);
2195 /* cleanup any slave resources */
2196 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2197 mlx4_delete_all_resources_for_slave(dev, slave);
2199 if (cmd != MLX4_COMM_CMD_RESET) {
2200 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2202 /* Turn on internal error letting slave reset itself immeditaly,
2203 * otherwise it might take till timeout on command is passed
2205 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2208 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2209 if (!slave_state[slave].is_slave_going_down)
2210 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2211 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2212 /*with slave in the middle of flr, no need to clean resources again.*/
2214 memset(&slave_state[slave].event_eq, 0,
2215 sizeof(struct mlx4_slave_event_eq_info));
2216 __raw_writel((__force u32) cpu_to_be32(reply),
2217 &priv->mfunc.comm[slave].slave_read);
2221 /* master command processing */
2222 void mlx4_master_comm_channel(struct work_struct *work)
2224 struct mlx4_mfunc_master_ctx *master =
2226 struct mlx4_mfunc_master_ctx,
2228 struct mlx4_mfunc *mfunc =
2229 container_of(master, struct mlx4_mfunc, master);
2230 struct mlx4_priv *priv =
2231 container_of(mfunc, struct mlx4_priv, mfunc);
2232 struct mlx4_dev *dev = &priv->dev;
2233 u32 lbit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
2243 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++)
2244 lbit_vec[i] = be32_to_cpu(master->comm_arm_bit_vector[i]);
2245 nmbr_bits = dev->persist->num_vfs + 1;
2246 if (++master->next_slave >= nmbr_bits)
2247 master->next_slave = 0;
2248 slave = master->next_slave;
2250 slave = find_next_bit((const unsigned long *)&lbit_vec, nmbr_bits, slave);
2251 if (!first && slave >= master->next_slave)
2253 if (slave == nmbr_bits) {
2261 comm_cmd = swab32(readl(&mfunc->comm[slave].slave_write));
2262 slt = swab32(readl(&mfunc->comm[slave].slave_read)) >> 31;
2263 toggle = comm_cmd >> 31;
2264 if (toggle != slt) {
2265 if (master->slave_state[slave].comm_toggle
2267 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2269 master->slave_state[slave].comm_toggle);
2270 master->slave_state[slave].comm_toggle =
2273 mlx4_master_do_cmd(dev, slave,
2274 comm_cmd >> 16 & 0xff,
2275 comm_cmd & 0xffff, toggle);
2281 if (reported && reported != served)
2282 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2285 if (mlx4_ARM_COMM_CHANNEL(dev))
2286 mlx4_warn(dev, "Failed to arm comm channel events\n");
2289 static int sync_toggles(struct mlx4_dev *dev)
2291 struct mlx4_priv *priv = mlx4_priv(dev);
2296 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2297 if (wr_toggle == 0xffffffff)
2298 end = jiffies + msecs_to_jiffies(30000);
2300 end = jiffies + msecs_to_jiffies(5000);
2302 while (time_before(jiffies, end)) {
2303 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2304 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2305 /* PCI might be offline */
2307 /* If device removal has been requested,
2308 * do not continue retrying.
2310 if (dev->persist->interface_state &
2311 MLX4_INTERFACE_STATE_NOWAIT) {
2313 "communication channel is offline\n");
2318 wr_toggle = swab32(readl(&priv->mfunc.comm->
2323 if (rd_toggle >> 31 == wr_toggle >> 31) {
2324 priv->cmd.comm_toggle = rd_toggle >> 31;
2332 * we could reach here if for example the previous VM using this
2333 * function misbehaved and left the channel with unsynced state. We
2334 * should fix this here and give this VM a chance to use a properly
2337 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2338 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2339 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2340 priv->cmd.comm_toggle = 0;
2345 int mlx4_multi_func_init(struct mlx4_dev *dev)
2347 struct mlx4_priv *priv = mlx4_priv(dev);
2348 struct mlx4_slave_state *s_state;
2349 int i, j, err, port;
2351 if (mlx4_is_master(dev))
2353 ioremap(pci_resource_start(dev->persist->pdev,
2354 priv->fw.comm_bar) +
2355 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2358 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2359 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2360 if (!priv->mfunc.comm) {
2361 mlx4_err(dev, "Couldn't map communication vector\n");
2365 if (mlx4_is_master(dev)) {
2366 struct mlx4_vf_oper_state *vf_oper;
2367 struct mlx4_vf_admin_state *vf_admin;
2369 priv->mfunc.master.slave_state =
2370 kcalloc(dev->num_slaves,
2371 sizeof(struct mlx4_slave_state),
2373 if (!priv->mfunc.master.slave_state)
2376 priv->mfunc.master.vf_admin =
2377 kcalloc(dev->num_slaves,
2378 sizeof(struct mlx4_vf_admin_state),
2380 if (!priv->mfunc.master.vf_admin)
2381 goto err_comm_admin;
2383 priv->mfunc.master.vf_oper =
2384 kcalloc(dev->num_slaves,
2385 sizeof(struct mlx4_vf_oper_state),
2387 if (!priv->mfunc.master.vf_oper)
2390 priv->mfunc.master.next_slave = 0;
2392 for (i = 0; i < dev->num_slaves; ++i) {
2393 vf_admin = &priv->mfunc.master.vf_admin[i];
2394 vf_oper = &priv->mfunc.master.vf_oper[i];
2395 s_state = &priv->mfunc.master.slave_state[i];
2396 s_state->last_cmd = MLX4_COMM_CMD_RESET;
2397 s_state->vst_qinq_supported = false;
2398 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2399 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2400 s_state->event_eq[j].eqn = -1;
2401 __raw_writel((__force u32) 0,
2402 &priv->mfunc.comm[i].slave_write);
2403 __raw_writel((__force u32) 0,
2404 &priv->mfunc.comm[i].slave_read);
2405 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2406 struct mlx4_vport_state *admin_vport;
2407 struct mlx4_vport_state *oper_vport;
2409 s_state->vlan_filter[port] =
2410 kzalloc(sizeof(struct mlx4_vlan_fltr),
2412 if (!s_state->vlan_filter[port]) {
2414 kfree(s_state->vlan_filter[port]);
2418 admin_vport = &vf_admin->vport[port];
2419 oper_vport = &vf_oper->vport[port].state;
2420 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2421 admin_vport->default_vlan = MLX4_VGT;
2422 oper_vport->default_vlan = MLX4_VGT;
2423 admin_vport->qos_vport =
2424 MLX4_VPP_DEFAULT_VPORT;
2425 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2426 admin_vport->vlan_proto = htons(ETH_P_8021Q);
2427 oper_vport->vlan_proto = htons(ETH_P_8021Q);
2428 vf_oper->vport[port].vlan_idx = NO_INDX;
2429 vf_oper->vport[port].mac_idx = NO_INDX;
2430 mlx4_set_random_admin_guid(dev, i, port);
2432 spin_lock_init(&s_state->lock);
2435 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2436 for (port = 1; port <= dev->caps.num_ports; port++) {
2437 if (mlx4_is_eth(dev, port)) {
2438 mlx4_set_default_port_qos(dev, port);
2439 mlx4_allocate_port_vpps(dev, port);
2444 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
2445 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2446 INIT_WORK(&priv->mfunc.master.comm_work,
2447 mlx4_master_comm_channel);
2448 INIT_WORK(&priv->mfunc.master.slave_event_work,
2449 mlx4_gen_slave_eqe);
2450 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2451 mlx4_master_handle_slave_flr);
2452 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2453 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2454 priv->mfunc.master.comm_wq =
2455 create_singlethread_workqueue("mlx4_comm");
2456 if (!priv->mfunc.master.comm_wq)
2459 if (mlx4_init_resource_tracker(dev))
2463 err = sync_toggles(dev);
2465 mlx4_err(dev, "Couldn't sync toggles\n");
2472 destroy_workqueue(priv->mfunc.master.comm_wq);
2475 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2476 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2478 kfree(priv->mfunc.master.vf_oper);
2480 kfree(priv->mfunc.master.vf_admin);
2482 kfree(priv->mfunc.master.slave_state);
2484 iounmap(priv->mfunc.comm);
2485 priv->mfunc.comm = NULL;
2487 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2489 priv->mfunc.vhcr_dma);
2490 priv->mfunc.vhcr = NULL;
2494 int mlx4_cmd_init(struct mlx4_dev *dev)
2496 struct mlx4_priv *priv = mlx4_priv(dev);
2499 if (!priv->cmd.initialized) {
2500 init_rwsem(&priv->cmd.switch_sem);
2501 mutex_init(&priv->cmd.slave_cmd_mutex);
2502 sema_init(&priv->cmd.poll_sem, 1);
2503 priv->cmd.use_events = 0;
2504 priv->cmd.toggle = 1;
2505 priv->cmd.initialized = 1;
2506 flags |= MLX4_CMD_CLEANUP_STRUCT;
2509 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2510 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2511 0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2512 if (!priv->cmd.hcr) {
2513 mlx4_err(dev, "Couldn't map command register\n");
2516 flags |= MLX4_CMD_CLEANUP_HCR;
2519 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2520 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2522 &priv->mfunc.vhcr_dma,
2524 if (!priv->mfunc.vhcr)
2527 flags |= MLX4_CMD_CLEANUP_VHCR;
2530 if (!priv->cmd.pool) {
2531 priv->cmd.pool = dma_pool_create("mlx4_cmd",
2532 &dev->persist->pdev->dev,
2534 MLX4_MAILBOX_SIZE, 0);
2535 if (!priv->cmd.pool)
2538 flags |= MLX4_CMD_CLEANUP_POOL;
2544 mlx4_cmd_cleanup(dev, flags);
2548 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2550 struct mlx4_priv *priv = mlx4_priv(dev);
2554 /* If the comm channel has not yet been initialized,
2555 * skip reporting the internal error event to all
2556 * the communication channels.
2558 if (!priv->mfunc.comm)
2561 /* Report an internal error event to all
2562 * communication channels.
2564 for (slave = 0; slave < dev->num_slaves; slave++) {
2565 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2566 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2567 __raw_writel((__force u32)cpu_to_be32(slave_read),
2568 &priv->mfunc.comm[slave].slave_read);
2572 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2574 struct mlx4_priv *priv = mlx4_priv(dev);
2577 if (mlx4_is_master(dev)) {
2578 destroy_workqueue(priv->mfunc.master.comm_wq);
2579 for (i = 0; i < dev->num_slaves; i++) {
2580 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2581 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2583 kfree(priv->mfunc.master.slave_state);
2584 kfree(priv->mfunc.master.vf_admin);
2585 kfree(priv->mfunc.master.vf_oper);
2586 dev->num_slaves = 0;
2589 iounmap(priv->mfunc.comm);
2590 priv->mfunc.comm = NULL;
2593 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2595 struct mlx4_priv *priv = mlx4_priv(dev);
2597 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2598 dma_pool_destroy(priv->cmd.pool);
2599 priv->cmd.pool = NULL;
2602 if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2603 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2604 iounmap(priv->cmd.hcr);
2605 priv->cmd.hcr = NULL;
2607 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2608 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2609 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2610 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2611 priv->mfunc.vhcr = NULL;
2613 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2614 priv->cmd.initialized = 0;
2618 * Switch to using events to issue FW commands (can only be called
2619 * after event queue for command events has been initialized).
2621 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2623 struct mlx4_priv *priv = mlx4_priv(dev);
2627 priv->cmd.context = kmalloc_array(priv->cmd.max_cmds,
2628 sizeof(struct mlx4_cmd_context),
2630 if (!priv->cmd.context)
2633 if (mlx4_is_mfunc(dev))
2634 mutex_lock(&priv->cmd.slave_cmd_mutex);
2635 down_write(&priv->cmd.switch_sem);
2636 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2637 priv->cmd.context[i].token = i;
2638 priv->cmd.context[i].next = i + 1;
2639 /* To support fatal error flow, initialize all
2640 * cmd contexts to allow simulating completions
2641 * with complete() at any time.
2643 init_completion(&priv->cmd.context[i].done);
2646 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2647 priv->cmd.free_head = 0;
2649 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2651 for (priv->cmd.token_mask = 1;
2652 priv->cmd.token_mask < priv->cmd.max_cmds;
2653 priv->cmd.token_mask <<= 1)
2655 --priv->cmd.token_mask;
2657 down(&priv->cmd.poll_sem);
2658 priv->cmd.use_events = 1;
2659 up_write(&priv->cmd.switch_sem);
2660 if (mlx4_is_mfunc(dev))
2661 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2667 * Switch back to polling (used when shutting down the device)
2669 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2671 struct mlx4_priv *priv = mlx4_priv(dev);
2674 if (mlx4_is_mfunc(dev))
2675 mutex_lock(&priv->cmd.slave_cmd_mutex);
2676 down_write(&priv->cmd.switch_sem);
2677 priv->cmd.use_events = 0;
2679 for (i = 0; i < priv->cmd.max_cmds; ++i)
2680 down(&priv->cmd.event_sem);
2682 kfree(priv->cmd.context);
2683 priv->cmd.context = NULL;
2685 up(&priv->cmd.poll_sem);
2686 up_write(&priv->cmd.switch_sem);
2687 if (mlx4_is_mfunc(dev))
2688 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2691 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2693 struct mlx4_cmd_mailbox *mailbox;
2695 mailbox = kmalloc(sizeof(*mailbox), GFP_KERNEL);
2697 return ERR_PTR(-ENOMEM);
2699 mailbox->buf = dma_pool_zalloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2701 if (!mailbox->buf) {
2703 return ERR_PTR(-ENOMEM);
2708 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2710 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2711 struct mlx4_cmd_mailbox *mailbox)
2716 dma_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2719 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2721 u32 mlx4_comm_get_version(void)
2723 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2726 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2728 if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2729 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2730 vf, dev->persist->num_vfs);
2737 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2739 if (slave < 1 || slave > dev->persist->num_vfs) {
2741 "Bad slave number:%d (number of activated slaves: %lu)\n",
2742 slave, dev->num_slaves);
2748 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2750 struct mlx4_priv *priv = mlx4_priv(dev);
2751 struct mlx4_cmd_context *context;
2754 spin_lock(&priv->cmd.context_lock);
2755 if (priv->cmd.context) {
2756 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2757 context = &priv->cmd.context[i];
2758 context->fw_status = CMD_STAT_INTERNAL_ERR;
2760 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2761 complete(&context->done);
2764 spin_unlock(&priv->cmd.context_lock);
2767 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2769 struct mlx4_active_ports actv_ports;
2772 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2775 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2779 vf = mlx4_get_vf_indx(dev, slave);
2783 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2784 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2785 dev->caps.num_ports));
2789 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2791 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2794 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2795 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2797 if (port <= 0 || port > m)
2800 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2806 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2808 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2810 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2811 if (test_bit(port - 1, actv_ports.ports))
2813 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2817 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2819 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2823 struct mlx4_slaves_pport slaves_pport;
2825 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2827 if (port <= 0 || port > dev->caps.num_ports)
2828 return slaves_pport;
2830 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2831 struct mlx4_active_ports actv_ports =
2832 mlx4_get_active_ports(dev, i);
2833 if (test_bit(port - 1, actv_ports.ports))
2834 set_bit(i, slaves_pport.slaves);
2837 return slaves_pport;
2839 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2841 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2842 struct mlx4_dev *dev,
2843 const struct mlx4_active_ports *crit_ports)
2846 struct mlx4_slaves_pport slaves_pport;
2848 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2850 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2851 struct mlx4_active_ports actv_ports =
2852 mlx4_get_active_ports(dev, i);
2853 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2854 dev->caps.num_ports))
2855 set_bit(i, slaves_pport.slaves);
2858 return slaves_pport;
2860 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2862 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2864 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2865 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2867 int max_port = min_port +
2868 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2870 if (port < min_port)
2872 else if (port >= max_port)
2873 port = max_port - 1;
2878 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2883 struct mlx4_qos_manager *port_qos;
2884 struct mlx4_dev *dev = &priv->dev;
2885 struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2887 port_qos = &priv->mfunc.master.qos_ctl[port];
2888 memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2890 if (slave > port_qos->num_of_qos_vfs) {
2891 mlx4_info(dev, "No available VPP resources for this VF\n");
2895 /* Query for default QoS values from Vport 0 is needed */
2896 err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2898 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2902 for (i = 0; i < MLX4_NUM_UP; i++) {
2903 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2904 vpp_qos[i].max_avg_bw = max_tx_rate;
2905 vpp_qos[i].enable = 1;
2907 /* if user supplied tx_rate == 0, meaning no rate limit
2908 * configuration is required. so we are leaving the
2909 * value of max_avg_bw as queried from Vport 0.
2911 vpp_qos[i].enable = 0;
2915 err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2917 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2924 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2925 struct mlx4_vport_state *vf_admin)
2927 struct mlx4_qos_manager *info;
2928 struct mlx4_priv *priv = mlx4_priv(dev);
2930 if (!mlx4_is_master(dev) ||
2931 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2934 info = &priv->mfunc.master.qos_ctl[port];
2936 if (vf_admin->default_vlan != MLX4_VGT &&
2937 test_bit(vf_admin->default_qos, info->priority_bm))
2943 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2944 struct mlx4_vport_state *vf_admin,
2947 struct mlx4_vport_state dummy_admin = {0};
2949 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2953 dummy_admin.default_qos = qos;
2954 dummy_admin.default_vlan = vlan;
2956 /* VF wants to move to other VST state which is valid with current
2957 * rate limit. Either differnt default vlan in VST or other
2958 * supported QoS priority. Otherwise we don't allow this change when
2959 * the TX rate is still configured.
2961 if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2964 mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2965 (vlan == MLX4_VGT) ? "VGT" : "VST");
2967 if (vlan != MLX4_VGT)
2968 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2970 mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2975 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u8 *mac)
2977 struct mlx4_priv *priv = mlx4_priv(dev);
2978 struct mlx4_vport_state *s_info;
2981 if (!mlx4_is_master(dev))
2982 return -EPROTONOSUPPORT;
2984 if (is_multicast_ether_addr(mac))
2987 slave = mlx4_get_slave_indx(dev, vf);
2991 port = mlx4_slaves_closest_port(dev, slave, port);
2992 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2994 if (s_info->spoofchk && is_zero_ether_addr(mac)) {
2995 mlx4_info(dev, "MAC invalidation is not allowed when spoofchk is on\n");
2999 s_info->mac = ether_addr_to_u64(mac);
3000 mlx4_info(dev, "default mac on vf %d port %d to %llX will take effect only after vf restart\n",
3001 vf, port, s_info->mac);
3004 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3007 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos,
3010 struct mlx4_priv *priv = mlx4_priv(dev);
3011 struct mlx4_vport_state *vf_admin;
3012 struct mlx4_slave_state *slave_state;
3013 struct mlx4_vport_oper_state *vf_oper;
3016 if ((!mlx4_is_master(dev)) ||
3017 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
3018 return -EPROTONOSUPPORT;
3020 if ((vlan > 4095) || (qos > 7))
3023 if (proto == htons(ETH_P_8021AD) &&
3024 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP))
3025 return -EPROTONOSUPPORT;
3027 if (proto != htons(ETH_P_8021Q) &&
3028 proto != htons(ETH_P_8021AD))
3031 if ((proto == htons(ETH_P_8021AD)) &&
3032 ((vlan == 0) || (vlan == MLX4_VGT)))
3035 slave = mlx4_get_slave_indx(dev, vf);
3039 slave_state = &priv->mfunc.master.slave_state[slave];
3040 if ((proto == htons(ETH_P_8021AD)) && (slave_state->active) &&
3041 (!slave_state->vst_qinq_supported)) {
3042 mlx4_err(dev, "vf %d does not support VST QinQ mode\n", vf);
3043 return -EPROTONOSUPPORT;
3045 port = mlx4_slaves_closest_port(dev, slave, port);
3046 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3047 vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3049 if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
3052 if ((0 == vlan) && (0 == qos))
3053 vf_admin->default_vlan = MLX4_VGT;
3055 vf_admin->default_vlan = vlan;
3056 vf_admin->default_qos = qos;
3057 vf_admin->vlan_proto = proto;
3059 /* If rate was configured prior to VST, we saved the configured rate
3060 * in vf_admin->rate and now, if priority supported we enforce the QoS
3062 if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
3064 vf_admin->qos_vport = slave;
3066 /* Try to activate new vf state without restart,
3067 * this option is not supported while moving to VST QinQ mode.
3069 if ((proto == htons(ETH_P_8021AD) &&
3070 vf_oper->state.vlan_proto != proto) ||
3071 mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3073 "updating vf %d port %d config will take effect on next VF restart\n",
3077 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
3079 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
3084 struct mlx4_vport_state *vf_admin;
3085 struct mlx4_priv *priv = mlx4_priv(dev);
3087 if (!mlx4_is_master(dev) ||
3088 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
3089 return -EPROTONOSUPPORT;
3092 mlx4_info(dev, "Minimum BW share not supported\n");
3093 return -EPROTONOSUPPORT;
3096 slave = mlx4_get_slave_indx(dev, vf);
3100 port = mlx4_slaves_closest_port(dev, slave, port);
3101 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3103 err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
3105 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
3110 vf_admin->tx_rate = max_tx_rate;
3111 /* if VF is not in supported mode (VST with supported prio),
3112 * we do not change vport configuration for its QPs, but save
3113 * the rate, so it will be enforced when it moves to supported
3116 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
3118 "rate set for VF %d when not in valid state\n", vf);
3120 if (vf_admin->default_vlan != MLX4_VGT)
3121 mlx4_info(dev, "VST priority not supported by QoS\n");
3123 mlx4_info(dev, "VF in VGT mode (needed VST)\n");
3126 "rate %d take affect when VF moves to valid state\n",
3131 /* If user sets rate 0 assigning default vport for its QPs */
3132 vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3134 if (priv->mfunc.master.slave_state[slave].active &&
3135 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3136 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3140 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3142 /* mlx4_get_slave_default_vlan -
3143 * return true if VST ( default vlan)
3144 * if VST, will return vlan & qos (if not NULL)
3146 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3149 struct mlx4_vport_oper_state *vp_oper;
3150 struct mlx4_priv *priv;
3152 priv = mlx4_priv(dev);
3153 port = mlx4_slaves_closest_port(dev, slave, port);
3154 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3156 if (MLX4_VGT != vp_oper->state.default_vlan) {
3158 *vlan = vp_oper->state.default_vlan;
3160 *qos = vp_oper->state.default_qos;
3165 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3167 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3169 struct mlx4_priv *priv = mlx4_priv(dev);
3170 struct mlx4_vport_state *s_info;
3174 if ((!mlx4_is_master(dev)) ||
3175 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3176 return -EPROTONOSUPPORT;
3178 slave = mlx4_get_slave_indx(dev, vf);
3182 port = mlx4_slaves_closest_port(dev, slave, port);
3183 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3185 u64_to_ether_addr(s_info->mac, mac);
3186 if (setting && !is_valid_ether_addr(mac)) {
3187 mlx4_info(dev, "Illegal MAC with spoofchk\n");
3191 s_info->spoofchk = setting;
3195 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3197 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3199 struct mlx4_priv *priv = mlx4_priv(dev);
3200 struct mlx4_vport_state *s_info;
3203 if (!mlx4_is_master(dev))
3204 return -EPROTONOSUPPORT;
3206 slave = mlx4_get_slave_indx(dev, vf);
3210 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3213 /* need to convert it to a func */
3214 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3215 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3216 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3217 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3218 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3219 ivf->mac[5] = ((s_info->mac) & 0xff);
3221 ivf->vlan = s_info->default_vlan;
3222 ivf->qos = s_info->default_qos;
3223 ivf->vlan_proto = s_info->vlan_proto;
3225 if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3226 ivf->max_tx_rate = s_info->tx_rate;
3228 ivf->max_tx_rate = 0;
3230 ivf->min_tx_rate = 0;
3231 ivf->spoofchk = s_info->spoofchk;
3232 ivf->linkstate = s_info->link_state;
3236 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3238 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3240 struct mlx4_priv *priv = mlx4_priv(dev);
3241 struct mlx4_vport_state *s_info;
3245 slave = mlx4_get_slave_indx(dev, vf);
3249 port = mlx4_slaves_closest_port(dev, slave, port);
3250 switch (link_state) {
3251 case IFLA_VF_LINK_STATE_AUTO:
3252 /* get current link state */
3253 if (!priv->sense.do_sense_port[port])
3254 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3256 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3259 case IFLA_VF_LINK_STATE_ENABLE:
3260 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3263 case IFLA_VF_LINK_STATE_DISABLE:
3264 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3268 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3269 link_state, slave, port);
3272 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3273 s_info->link_state = link_state;
3276 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3278 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3280 "updating vf %d port %d no link state HW enforcement\n",
3284 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3286 int mlx4_get_counter_stats(struct mlx4_dev *dev, int counter_index,
3287 struct mlx4_counter *counter_stats, int reset)
3289 struct mlx4_cmd_mailbox *mailbox = NULL;
3290 struct mlx4_counter *tmp_counter;
3297 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
3300 mailbox = mlx4_alloc_cmd_mailbox(dev);
3301 if (IS_ERR(mailbox))
3302 return PTR_ERR(mailbox);
3304 memset(mailbox->buf, 0, sizeof(struct mlx4_counter));
3305 if_stat_in_mod = counter_index;
3307 if_stat_in_mod |= MLX4_QUERY_IF_STAT_RESET;
3308 err = mlx4_cmd_box(dev, 0, mailbox->dma,
3310 MLX4_CMD_QUERY_IF_STAT,
3311 MLX4_CMD_TIME_CLASS_C,
3314 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n",
3315 __func__, counter_index);
3318 tmp_counter = (struct mlx4_counter *)mailbox->buf;
3319 counter_stats->counter_mode = tmp_counter->counter_mode;
3320 if (counter_stats->counter_mode == 0) {
3321 counter_stats->rx_frames =
3322 cpu_to_be64(be64_to_cpu(counter_stats->rx_frames) +
3323 be64_to_cpu(tmp_counter->rx_frames));
3324 counter_stats->tx_frames =
3325 cpu_to_be64(be64_to_cpu(counter_stats->tx_frames) +
3326 be64_to_cpu(tmp_counter->tx_frames));
3327 counter_stats->rx_bytes =
3328 cpu_to_be64(be64_to_cpu(counter_stats->rx_bytes) +
3329 be64_to_cpu(tmp_counter->rx_bytes));
3330 counter_stats->tx_bytes =
3331 cpu_to_be64(be64_to_cpu(counter_stats->tx_bytes) +
3332 be64_to_cpu(tmp_counter->tx_bytes));
3336 mlx4_free_cmd_mailbox(dev, mailbox);
3340 EXPORT_SYMBOL_GPL(mlx4_get_counter_stats);
3342 int mlx4_get_vf_stats(struct mlx4_dev *dev, int port, int vf_idx,
3343 struct ifla_vf_stats *vf_stats)
3345 struct mlx4_counter tmp_vf_stats;
3352 if (!mlx4_is_master(dev))
3353 return -EPROTONOSUPPORT;
3355 slave = mlx4_get_slave_indx(dev, vf_idx);
3359 port = mlx4_slaves_closest_port(dev, slave, port);
3360 err = mlx4_calc_vf_counters(dev, slave, port, &tmp_vf_stats);
3361 if (!err && tmp_vf_stats.counter_mode == 0) {
3362 vf_stats->rx_packets = be64_to_cpu(tmp_vf_stats.rx_frames);
3363 vf_stats->tx_packets = be64_to_cpu(tmp_vf_stats.tx_frames);
3364 vf_stats->rx_bytes = be64_to_cpu(tmp_vf_stats.rx_bytes);
3365 vf_stats->tx_bytes = be64_to_cpu(tmp_vf_stats.tx_bytes);
3370 EXPORT_SYMBOL_GPL(mlx4_get_vf_stats);
3372 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3374 struct mlx4_priv *priv = mlx4_priv(dev);
3376 if (slave < 1 || slave >= dev->num_slaves ||
3377 port < 1 || port > MLX4_MAX_PORTS)
3380 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3381 MLX4_VF_SMI_ENABLED;
3383 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3385 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3387 struct mlx4_priv *priv = mlx4_priv(dev);
3389 if (slave == mlx4_master_func_num(dev))
3392 if (slave < 1 || slave >= dev->num_slaves ||
3393 port < 1 || port > MLX4_MAX_PORTS)
3396 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3397 MLX4_VF_SMI_ENABLED;
3399 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3401 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3404 struct mlx4_priv *priv = mlx4_priv(dev);
3405 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
3407 int min_port = find_first_bit(actv_ports.ports,
3408 priv->dev.caps.num_ports) + 1;
3409 int max_port = min_port - 1 +
3410 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
3412 if (slave == mlx4_master_func_num(dev))
3415 if (slave < 1 || slave >= dev->num_slaves ||
3416 port < 1 || port > MLX4_MAX_PORTS ||
3417 enabled < 0 || enabled > 1)
3420 if (min_port == max_port && dev->caps.num_ports > 1) {
3421 mlx4_info(dev, "SMI access disallowed for single ported VFs\n");
3422 return -EPROTONOSUPPORT;
3425 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3428 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);