1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
9 #include <linux/of_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/regmap.h>
14 #include <linux/clk.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/if_vlan.h>
17 #include <linux/reset.h>
18 #include <linux/tcp.h>
19 #include <linux/interrupt.h>
20 #include <linux/pinctrl/devinfo.h>
21 #include <linux/phylink.h>
23 #include "mtk_eth_soc.h"
25 static int mtk_msg_level = -1;
26 module_param_named(msg_level, mtk_msg_level, int, 0);
27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
29 #define MTK_ETHTOOL_STAT(x) { #x, \
30 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
32 /* strings used by ethtool */
33 static const struct mtk_ethtool_stats {
34 char str[ETH_GSTRING_LEN];
36 } mtk_ethtool_stats[] = {
37 MTK_ETHTOOL_STAT(tx_bytes),
38 MTK_ETHTOOL_STAT(tx_packets),
39 MTK_ETHTOOL_STAT(tx_skip),
40 MTK_ETHTOOL_STAT(tx_collisions),
41 MTK_ETHTOOL_STAT(rx_bytes),
42 MTK_ETHTOOL_STAT(rx_packets),
43 MTK_ETHTOOL_STAT(rx_overflow),
44 MTK_ETHTOOL_STAT(rx_fcs_errors),
45 MTK_ETHTOOL_STAT(rx_short_errors),
46 MTK_ETHTOOL_STAT(rx_long_errors),
47 MTK_ETHTOOL_STAT(rx_checksum_errors),
48 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 static const char * const mtk_clks_source_name[] = {
52 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
53 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
54 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
55 "sgmii_ck", "eth2pll",
58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
60 __raw_writel(val, eth->base + reg);
63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
65 return __raw_readl(eth->base + reg);
68 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
72 val = mtk_r32(eth, reg);
75 mtk_w32(eth, val, reg);
79 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
81 unsigned long t_start = jiffies;
84 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
86 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
91 dev_err(eth->dev, "mdio: MDIO timeout\n");
95 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
96 u32 phy_register, u32 write_data)
98 if (mtk_mdio_busy_wait(eth))
101 write_data &= 0xffff;
103 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
104 (phy_register << PHY_IAC_REG_SHIFT) |
105 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
108 if (mtk_mdio_busy_wait(eth))
114 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
118 if (mtk_mdio_busy_wait(eth))
121 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
122 (phy_reg << PHY_IAC_REG_SHIFT) |
123 (phy_addr << PHY_IAC_ADDR_SHIFT),
126 if (mtk_mdio_busy_wait(eth))
129 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
134 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
135 int phy_reg, u16 val)
137 struct mtk_eth *eth = bus->priv;
139 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
142 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
144 struct mtk_eth *eth = bus->priv;
146 return _mtk_mdio_read(eth, phy_addr, phy_reg);
149 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
150 phy_interface_t interface)
154 /* Check DDR memory type.
155 * Currently TRGMII mode with DDR2 memory is not supported.
157 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
158 if (interface == PHY_INTERFACE_MODE_TRGMII &&
159 val & SYSCFG_DRAM_TYPE_DDR2) {
161 "TRGMII mode with DDR2 memory is not supported!\n");
165 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
166 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
168 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
169 ETHSYS_TRGMII_MT7621_MASK, val);
174 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
175 phy_interface_t interface, int speed)
180 if (interface == PHY_INTERFACE_MODE_TRGMII) {
181 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
183 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
185 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
189 val = (speed == SPEED_1000) ?
190 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
191 mtk_w32(eth, val, INTF_MODE);
193 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
194 ETHSYS_TRGMII_CLK_SEL362_5,
195 ETHSYS_TRGMII_CLK_SEL362_5);
197 val = (speed == SPEED_1000) ? 250000000 : 500000000;
198 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
200 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
202 val = (speed == SPEED_1000) ?
203 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
204 mtk_w32(eth, val, TRGMII_RCK_CTRL);
206 val = (speed == SPEED_1000) ?
207 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
208 mtk_w32(eth, val, TRGMII_TCK_CTRL);
211 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
212 const struct phylink_link_state *state)
214 struct mtk_mac *mac = container_of(config, struct mtk_mac,
216 struct mtk_eth *eth = mac->hw;
217 u32 mcr_cur, mcr_new, sid, i;
218 int val, ge_mode, err = 0;
220 /* MT76x8 has no hardware settings between for the MAC */
221 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
222 mac->interface != state->interface) {
223 /* Setup soc pin functions */
224 switch (state->interface) {
225 case PHY_INTERFACE_MODE_TRGMII:
228 if (!MTK_HAS_CAPS(mac->hw->soc->caps,
232 case PHY_INTERFACE_MODE_RGMII_TXID:
233 case PHY_INTERFACE_MODE_RGMII_RXID:
234 case PHY_INTERFACE_MODE_RGMII_ID:
235 case PHY_INTERFACE_MODE_RGMII:
236 case PHY_INTERFACE_MODE_MII:
237 case PHY_INTERFACE_MODE_REVMII:
238 case PHY_INTERFACE_MODE_RMII:
239 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
240 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
245 case PHY_INTERFACE_MODE_1000BASEX:
246 case PHY_INTERFACE_MODE_2500BASEX:
247 case PHY_INTERFACE_MODE_SGMII:
248 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
249 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
254 case PHY_INTERFACE_MODE_GMII:
255 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
256 err = mtk_gmac_gephy_path_setup(eth, mac->id);
265 /* Setup clock for 1st gmac */
266 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
267 !phy_interface_mode_is_8023z(state->interface) &&
268 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
269 if (MTK_HAS_CAPS(mac->hw->soc->caps,
270 MTK_TRGMII_MT7621_CLK)) {
271 if (mt7621_gmac0_rgmii_adjust(mac->hw,
275 mtk_gmac0_rgmii_adjust(mac->hw,
279 /* mt7623_pad_clk_setup */
280 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
282 TD_DM_DRVP(8) | TD_DM_DRVN(8),
285 /* Assert/release MT7623 RXC reset */
286 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
288 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
293 switch (state->interface) {
294 case PHY_INTERFACE_MODE_MII:
295 case PHY_INTERFACE_MODE_GMII:
298 case PHY_INTERFACE_MODE_REVMII:
301 case PHY_INTERFACE_MODE_RMII:
310 /* put the gmac into the right mode */
311 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
312 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
313 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
314 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
316 mac->interface = state->interface;
320 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
321 phy_interface_mode_is_8023z(state->interface)) {
322 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
325 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
327 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
329 ~(u32)SYSCFG0_SGMII_MASK);
331 /* Decide how GMAC and SGMIISYS be mapped */
332 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
335 /* Setup SGMIISYS with the determined property */
336 if (state->interface != PHY_INTERFACE_MODE_SGMII)
337 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
339 else if (phylink_autoneg_inband(mode))
340 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
345 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
346 SYSCFG0_SGMII_MASK, val);
347 } else if (phylink_autoneg_inband(mode)) {
349 "In-band mode not supported in non SGMII mode!\n");
354 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
356 mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
357 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
359 /* Only update control register when needed! */
360 if (mcr_new != mcr_cur)
361 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
366 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
367 mac->id, phy_modes(state->interface));
371 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
372 mac->id, phy_modes(state->interface), err);
375 static void mtk_mac_pcs_get_state(struct phylink_config *config,
376 struct phylink_link_state *state)
378 struct mtk_mac *mac = container_of(config, struct mtk_mac,
380 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
382 state->link = (pmsr & MAC_MSR_LINK);
383 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
385 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
387 state->speed = SPEED_10;
389 case MAC_MSR_SPEED_100:
390 state->speed = SPEED_100;
392 case MAC_MSR_SPEED_1000:
393 state->speed = SPEED_1000;
396 state->speed = SPEED_UNKNOWN;
400 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
401 if (pmsr & MAC_MSR_RX_FC)
402 state->pause |= MLO_PAUSE_RX;
403 if (pmsr & MAC_MSR_TX_FC)
404 state->pause |= MLO_PAUSE_TX;
407 static void mtk_mac_an_restart(struct phylink_config *config)
409 struct mtk_mac *mac = container_of(config, struct mtk_mac,
412 mtk_sgmii_restart_an(mac->hw, mac->id);
415 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
416 phy_interface_t interface)
418 struct mtk_mac *mac = container_of(config, struct mtk_mac,
420 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
422 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
423 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
426 static void mtk_mac_link_up(struct phylink_config *config,
427 struct phy_device *phy,
428 unsigned int mode, phy_interface_t interface,
429 int speed, int duplex, bool tx_pause, bool rx_pause)
431 struct mtk_mac *mac = container_of(config, struct mtk_mac,
433 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
435 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
436 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
437 MAC_MCR_FORCE_RX_FC);
439 /* Configure speed */
443 mcr |= MAC_MCR_SPEED_1000;
446 mcr |= MAC_MCR_SPEED_100;
450 /* Configure duplex */
451 if (duplex == DUPLEX_FULL)
452 mcr |= MAC_MCR_FORCE_DPX;
454 /* Configure pause modes - phylink will avoid these for half duplex */
456 mcr |= MAC_MCR_FORCE_TX_FC;
458 mcr |= MAC_MCR_FORCE_RX_FC;
460 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
461 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
464 static void mtk_validate(struct phylink_config *config,
465 unsigned long *supported,
466 struct phylink_link_state *state)
468 struct mtk_mac *mac = container_of(config, struct mtk_mac,
470 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
472 if (state->interface != PHY_INTERFACE_MODE_NA &&
473 state->interface != PHY_INTERFACE_MODE_MII &&
474 state->interface != PHY_INTERFACE_MODE_GMII &&
475 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
476 phy_interface_mode_is_rgmii(state->interface)) &&
477 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
478 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) &&
479 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) &&
480 (state->interface == PHY_INTERFACE_MODE_SGMII ||
481 phy_interface_mode_is_8023z(state->interface)))) {
482 linkmode_zero(supported);
486 phylink_set_port_modes(mask);
487 phylink_set(mask, Autoneg);
489 switch (state->interface) {
490 case PHY_INTERFACE_MODE_TRGMII:
491 phylink_set(mask, 1000baseT_Full);
493 case PHY_INTERFACE_MODE_1000BASEX:
494 case PHY_INTERFACE_MODE_2500BASEX:
495 phylink_set(mask, 1000baseX_Full);
496 phylink_set(mask, 2500baseX_Full);
498 case PHY_INTERFACE_MODE_GMII:
499 case PHY_INTERFACE_MODE_RGMII:
500 case PHY_INTERFACE_MODE_RGMII_ID:
501 case PHY_INTERFACE_MODE_RGMII_RXID:
502 case PHY_INTERFACE_MODE_RGMII_TXID:
503 phylink_set(mask, 1000baseT_Half);
505 case PHY_INTERFACE_MODE_SGMII:
506 phylink_set(mask, 1000baseT_Full);
507 phylink_set(mask, 1000baseX_Full);
509 case PHY_INTERFACE_MODE_MII:
510 case PHY_INTERFACE_MODE_RMII:
511 case PHY_INTERFACE_MODE_REVMII:
512 case PHY_INTERFACE_MODE_NA:
514 phylink_set(mask, 10baseT_Half);
515 phylink_set(mask, 10baseT_Full);
516 phylink_set(mask, 100baseT_Half);
517 phylink_set(mask, 100baseT_Full);
521 if (state->interface == PHY_INTERFACE_MODE_NA) {
522 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
523 phylink_set(mask, 1000baseT_Full);
524 phylink_set(mask, 1000baseX_Full);
525 phylink_set(mask, 2500baseX_Full);
527 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {
528 phylink_set(mask, 1000baseT_Full);
529 phylink_set(mask, 1000baseT_Half);
530 phylink_set(mask, 1000baseX_Full);
532 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) {
533 phylink_set(mask, 1000baseT_Full);
534 phylink_set(mask, 1000baseT_Half);
538 phylink_set(mask, Pause);
539 phylink_set(mask, Asym_Pause);
541 linkmode_and(supported, supported, mask);
542 linkmode_and(state->advertising, state->advertising, mask);
544 /* We can only operate at 2500BaseX or 1000BaseX. If requested
545 * to advertise both, only report advertising at 2500BaseX.
547 phylink_helper_basex_speed(state);
550 static const struct phylink_mac_ops mtk_phylink_ops = {
551 .validate = mtk_validate,
552 .mac_pcs_get_state = mtk_mac_pcs_get_state,
553 .mac_an_restart = mtk_mac_an_restart,
554 .mac_config = mtk_mac_config,
555 .mac_link_down = mtk_mac_link_down,
556 .mac_link_up = mtk_mac_link_up,
559 static int mtk_mdio_init(struct mtk_eth *eth)
561 struct device_node *mii_np;
564 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
566 dev_err(eth->dev, "no %s child node found", "mdio-bus");
570 if (!of_device_is_available(mii_np)) {
575 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
581 eth->mii_bus->name = "mdio";
582 eth->mii_bus->read = mtk_mdio_read;
583 eth->mii_bus->write = mtk_mdio_write;
584 eth->mii_bus->priv = eth;
585 eth->mii_bus->parent = eth->dev;
587 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
588 ret = of_mdiobus_register(eth->mii_bus, mii_np);
595 static void mtk_mdio_cleanup(struct mtk_eth *eth)
600 mdiobus_unregister(eth->mii_bus);
603 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
608 spin_lock_irqsave(ð->tx_irq_lock, flags);
609 val = mtk_r32(eth, eth->tx_int_mask_reg);
610 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
611 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
614 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
619 spin_lock_irqsave(ð->tx_irq_lock, flags);
620 val = mtk_r32(eth, eth->tx_int_mask_reg);
621 mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
622 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
625 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
630 spin_lock_irqsave(ð->rx_irq_lock, flags);
631 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
632 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
633 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
636 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
641 spin_lock_irqsave(ð->rx_irq_lock, flags);
642 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
643 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
644 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
647 static int mtk_set_mac_address(struct net_device *dev, void *p)
649 int ret = eth_mac_addr(dev, p);
650 struct mtk_mac *mac = netdev_priv(dev);
651 struct mtk_eth *eth = mac->hw;
652 const char *macaddr = dev->dev_addr;
657 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
660 spin_lock_bh(&mac->hw->page_lock);
661 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
662 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
663 MT7628_SDM_MAC_ADRH);
664 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
665 (macaddr[4] << 8) | macaddr[5],
666 MT7628_SDM_MAC_ADRL);
668 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
669 MTK_GDMA_MAC_ADRH(mac->id));
670 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
671 (macaddr[4] << 8) | macaddr[5],
672 MTK_GDMA_MAC_ADRL(mac->id));
674 spin_unlock_bh(&mac->hw->page_lock);
679 void mtk_stats_update_mac(struct mtk_mac *mac)
681 struct mtk_hw_stats *hw_stats = mac->hw_stats;
682 struct mtk_eth *eth = mac->hw;
684 u64_stats_update_begin(&hw_stats->syncp);
686 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
687 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
688 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
689 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
690 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
691 hw_stats->rx_checksum_errors +=
692 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
694 unsigned int offs = hw_stats->reg_offset;
697 hw_stats->rx_bytes += mtk_r32(mac->hw,
698 MTK_GDM1_RX_GBCNT_L + offs);
699 stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs);
701 hw_stats->rx_bytes += (stats << 32);
702 hw_stats->rx_packets +=
703 mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs);
704 hw_stats->rx_overflow +=
705 mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs);
706 hw_stats->rx_fcs_errors +=
707 mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs);
708 hw_stats->rx_short_errors +=
709 mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs);
710 hw_stats->rx_long_errors +=
711 mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs);
712 hw_stats->rx_checksum_errors +=
713 mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs);
714 hw_stats->rx_flow_control_packets +=
715 mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs);
717 mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs);
718 hw_stats->tx_collisions +=
719 mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs);
720 hw_stats->tx_bytes +=
721 mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs);
722 stats = mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs);
724 hw_stats->tx_bytes += (stats << 32);
725 hw_stats->tx_packets +=
726 mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs);
729 u64_stats_update_end(&hw_stats->syncp);
732 static void mtk_stats_update(struct mtk_eth *eth)
736 for (i = 0; i < MTK_MAC_COUNT; i++) {
737 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
739 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
740 mtk_stats_update_mac(eth->mac[i]);
741 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
746 static void mtk_get_stats64(struct net_device *dev,
747 struct rtnl_link_stats64 *storage)
749 struct mtk_mac *mac = netdev_priv(dev);
750 struct mtk_hw_stats *hw_stats = mac->hw_stats;
753 if (netif_running(dev) && netif_device_present(dev)) {
754 if (spin_trylock_bh(&hw_stats->stats_lock)) {
755 mtk_stats_update_mac(mac);
756 spin_unlock_bh(&hw_stats->stats_lock);
761 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
762 storage->rx_packets = hw_stats->rx_packets;
763 storage->tx_packets = hw_stats->tx_packets;
764 storage->rx_bytes = hw_stats->rx_bytes;
765 storage->tx_bytes = hw_stats->tx_bytes;
766 storage->collisions = hw_stats->tx_collisions;
767 storage->rx_length_errors = hw_stats->rx_short_errors +
768 hw_stats->rx_long_errors;
769 storage->rx_over_errors = hw_stats->rx_overflow;
770 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
771 storage->rx_errors = hw_stats->rx_checksum_errors;
772 storage->tx_aborted_errors = hw_stats->tx_skip;
773 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
775 storage->tx_errors = dev->stats.tx_errors;
776 storage->rx_dropped = dev->stats.rx_dropped;
777 storage->tx_dropped = dev->stats.tx_dropped;
780 static inline int mtk_max_frag_size(int mtu)
782 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
783 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
784 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
786 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
787 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
790 static inline int mtk_max_buf_size(int frag_size)
792 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
793 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
795 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
800 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
801 struct mtk_rx_dma *dma_rxd)
803 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
804 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
805 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
806 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
809 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
811 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
814 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
820 /* the qdma core needs scratch memory to be setup */
821 static int mtk_init_fq_dma(struct mtk_eth *eth)
823 dma_addr_t phy_ring_tail;
824 int cnt = MTK_DMA_SIZE;
828 eth->scratch_ring = dma_alloc_coherent(eth->dev,
829 cnt * sizeof(struct mtk_tx_dma),
830 ð->phy_scratch_ring,
832 if (unlikely(!eth->scratch_ring))
835 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
837 if (unlikely(!eth->scratch_head))
840 dma_addr = dma_map_single(eth->dev,
841 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
843 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
846 phy_ring_tail = eth->phy_scratch_ring +
847 (sizeof(struct mtk_tx_dma) * (cnt - 1));
849 for (i = 0; i < cnt; i++) {
850 eth->scratch_ring[i].txd1 =
851 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
853 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
854 ((i + 1) * sizeof(struct mtk_tx_dma)));
855 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
858 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
859 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
860 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
861 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
866 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
868 void *ret = ring->dma;
870 return ret + (desc - ring->phys);
873 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
874 struct mtk_tx_dma *txd)
876 int idx = txd - ring->dma;
878 return &ring->buf[idx];
881 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
882 struct mtk_tx_dma *dma)
884 return ring->dma_pdma - ring->dma + dma;
887 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
889 return ((void *)dma - (void *)ring->dma) / sizeof(*dma);
892 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
894 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
895 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
896 dma_unmap_single(eth->dev,
897 dma_unmap_addr(tx_buf, dma_addr0),
898 dma_unmap_len(tx_buf, dma_len0),
900 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
901 dma_unmap_page(eth->dev,
902 dma_unmap_addr(tx_buf, dma_addr0),
903 dma_unmap_len(tx_buf, dma_len0),
907 if (dma_unmap_len(tx_buf, dma_len0)) {
908 dma_unmap_page(eth->dev,
909 dma_unmap_addr(tx_buf, dma_addr0),
910 dma_unmap_len(tx_buf, dma_len0),
914 if (dma_unmap_len(tx_buf, dma_len1)) {
915 dma_unmap_page(eth->dev,
916 dma_unmap_addr(tx_buf, dma_addr1),
917 dma_unmap_len(tx_buf, dma_len1),
924 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
925 dev_kfree_skb_any(tx_buf->skb);
929 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
930 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
931 size_t size, int idx)
933 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
934 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
935 dma_unmap_len_set(tx_buf, dma_len0, size);
938 txd->txd3 = mapped_addr;
939 txd->txd2 |= TX_DMA_PLEN1(size);
940 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
941 dma_unmap_len_set(tx_buf, dma_len1, size);
943 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
944 txd->txd1 = mapped_addr;
945 txd->txd2 = TX_DMA_PLEN0(size);
946 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
947 dma_unmap_len_set(tx_buf, dma_len0, size);
952 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
953 int tx_num, struct mtk_tx_ring *ring, bool gso)
955 struct mtk_mac *mac = netdev_priv(dev);
956 struct mtk_eth *eth = mac->hw;
957 struct mtk_tx_dma *itxd, *txd;
958 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
959 struct mtk_tx_buf *itx_buf, *tx_buf;
960 dma_addr_t mapped_addr;
961 unsigned int nr_frags;
966 itxd = ring->next_free;
967 itxd_pdma = qdma_to_pdma(ring, itxd);
968 if (itxd == ring->last_free)
971 /* set the forward port */
972 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
975 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
976 memset(itx_buf, 0, sizeof(*itx_buf));
981 /* TX Checksum offload */
982 if (skb->ip_summed == CHECKSUM_PARTIAL)
983 txd4 |= TX_DMA_CHKSUM;
985 /* VLAN header offload */
986 if (skb_vlan_tag_present(skb))
987 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
989 mapped_addr = dma_map_single(eth->dev, skb->data,
990 skb_headlen(skb), DMA_TO_DEVICE);
991 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
994 WRITE_ONCE(itxd->txd1, mapped_addr);
995 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
996 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
998 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb),
1003 txd_pdma = qdma_to_pdma(ring, txd);
1004 nr_frags = skb_shinfo(skb)->nr_frags;
1006 for (i = 0; i < nr_frags; i++) {
1007 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1008 unsigned int offset = 0;
1009 int frag_size = skb_frag_size(frag);
1012 bool last_frag = false;
1013 unsigned int frag_map_size;
1014 bool new_desc = true;
1016 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
1018 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1019 txd_pdma = qdma_to_pdma(ring, txd);
1020 if (txd == ring->last_free)
1029 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
1030 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
1033 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
1036 if (i == nr_frags - 1 &&
1037 (frag_size - frag_map_size) == 0)
1040 WRITE_ONCE(txd->txd1, mapped_addr);
1041 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
1042 TX_DMA_PLEN0(frag_map_size) |
1043 last_frag * TX_DMA_LS0));
1044 WRITE_ONCE(txd->txd4, fport);
1046 tx_buf = mtk_desc_to_tx_buf(ring, txd);
1048 memset(tx_buf, 0, sizeof(*tx_buf));
1049 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
1050 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1051 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1052 MTK_TX_FLAGS_FPORT1;
1054 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr,
1055 frag_map_size, k++);
1057 frag_size -= frag_map_size;
1058 offset += frag_map_size;
1062 /* store skb to cleanup */
1065 WRITE_ONCE(itxd->txd4, txd4);
1066 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
1067 (!nr_frags * TX_DMA_LS0)));
1068 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1070 txd_pdma->txd2 |= TX_DMA_LS0;
1072 txd_pdma->txd2 |= TX_DMA_LS1;
1075 netdev_sent_queue(dev, skb->len);
1076 skb_tx_timestamp(skb);
1078 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1079 atomic_sub(n_desc, &ring->free_count);
1081 /* make sure that all changes to the dma ring are flushed before we
1086 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1087 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1088 !netdev_xmit_more())
1089 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
1091 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd),
1093 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1100 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
1103 mtk_tx_unmap(eth, tx_buf);
1105 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1106 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1107 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1109 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1110 itxd_pdma = qdma_to_pdma(ring, itxd);
1111 } while (itxd != txd);
1116 static inline int mtk_cal_txd_req(struct sk_buff *skb)
1122 if (skb_is_gso(skb)) {
1123 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1124 frag = &skb_shinfo(skb)->frags[i];
1125 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1126 MTK_TX_DMA_BUF_LEN);
1129 nfrags += skb_shinfo(skb)->nr_frags;
1135 static int mtk_queue_stopped(struct mtk_eth *eth)
1139 for (i = 0; i < MTK_MAC_COUNT; i++) {
1140 if (!eth->netdev[i])
1142 if (netif_queue_stopped(eth->netdev[i]))
1149 static void mtk_wake_queue(struct mtk_eth *eth)
1153 for (i = 0; i < MTK_MAC_COUNT; i++) {
1154 if (!eth->netdev[i])
1156 netif_wake_queue(eth->netdev[i]);
1160 static void mtk_stop_queue(struct mtk_eth *eth)
1164 for (i = 0; i < MTK_MAC_COUNT; i++) {
1165 if (!eth->netdev[i])
1167 netif_stop_queue(eth->netdev[i]);
1171 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1173 struct mtk_mac *mac = netdev_priv(dev);
1174 struct mtk_eth *eth = mac->hw;
1175 struct mtk_tx_ring *ring = ð->tx_ring;
1176 struct net_device_stats *stats = &dev->stats;
1180 /* normally we can rely on the stack not calling this more than once,
1181 * however we have 2 queues running on the same ring so we need to lock
1184 spin_lock(ð->page_lock);
1186 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1189 tx_num = mtk_cal_txd_req(skb);
1190 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1191 mtk_stop_queue(eth);
1192 netif_err(eth, tx_queued, dev,
1193 "Tx Ring full when queue awake!\n");
1194 spin_unlock(ð->page_lock);
1195 return NETDEV_TX_BUSY;
1198 /* TSO: fill MSS info in tcp checksum field */
1199 if (skb_is_gso(skb)) {
1200 if (skb_cow_head(skb, 0)) {
1201 netif_warn(eth, tx_err, dev,
1202 "GSO expand head fail.\n");
1206 if (skb_shinfo(skb)->gso_type &
1207 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1209 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1213 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1216 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1217 mtk_stop_queue(eth);
1219 spin_unlock(ð->page_lock);
1221 return NETDEV_TX_OK;
1224 spin_unlock(ð->page_lock);
1225 stats->tx_dropped++;
1226 dev_kfree_skb_any(skb);
1227 return NETDEV_TX_OK;
1230 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1233 struct mtk_rx_ring *ring;
1237 return ð->rx_ring[0];
1239 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1240 ring = ð->rx_ring[i];
1241 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1242 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
1243 ring->calc_idx_update = true;
1251 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1253 struct mtk_rx_ring *ring;
1257 ring = ð->rx_ring[0];
1258 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1260 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1261 ring = ð->rx_ring[i];
1262 if (ring->calc_idx_update) {
1263 ring->calc_idx_update = false;
1264 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1270 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1271 struct mtk_eth *eth)
1273 struct mtk_rx_ring *ring;
1275 struct sk_buff *skb;
1276 u8 *data, *new_data;
1277 struct mtk_rx_dma *rxd, trxd;
1280 while (done < budget) {
1281 struct net_device *netdev;
1282 unsigned int pktlen;
1283 dma_addr_t dma_addr;
1286 ring = mtk_get_rx_ring(eth);
1287 if (unlikely(!ring))
1290 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1291 rxd = &ring->dma[idx];
1292 data = ring->data[idx];
1294 mtk_rx_get_desc(&trxd, rxd);
1295 if (!(trxd.rxd2 & RX_DMA_DONE))
1298 /* find out which mac the packet come from. values start at 1 */
1299 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
1302 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1307 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1311 netdev = eth->netdev[mac];
1313 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1316 /* alloc new buffer */
1317 if (ring->frag_size <= PAGE_SIZE)
1318 new_data = napi_alloc_frag(ring->frag_size);
1320 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
1321 if (unlikely(!new_data)) {
1322 netdev->stats.rx_dropped++;
1325 dma_addr = dma_map_single(eth->dev,
1326 new_data + NET_SKB_PAD +
1330 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1331 skb_free_frag(new_data);
1332 netdev->stats.rx_dropped++;
1337 skb = build_skb(data, ring->frag_size);
1338 if (unlikely(!skb)) {
1339 skb_free_frag(new_data);
1340 netdev->stats.rx_dropped++;
1343 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1345 dma_unmap_single(eth->dev, trxd.rxd1,
1346 ring->buf_size, DMA_FROM_DEVICE);
1347 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1349 skb_put(skb, pktlen);
1350 if (trxd.rxd4 & eth->rx_dma_l4_valid)
1351 skb->ip_summed = CHECKSUM_UNNECESSARY;
1353 skb_checksum_none_assert(skb);
1354 skb->protocol = eth_type_trans(skb, netdev);
1356 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1357 (trxd.rxd2 & RX_DMA_VTAG))
1358 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1359 RX_DMA_VID(trxd.rxd3));
1360 skb_record_rx_queue(skb, 0);
1361 napi_gro_receive(napi, skb);
1363 ring->data[idx] = new_data;
1364 rxd->rxd1 = (unsigned int)dma_addr;
1367 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1368 rxd->rxd2 = RX_DMA_LSO;
1370 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1372 ring->calc_idx = idx;
1379 /* make sure that all changes to the dma ring are flushed before
1383 mtk_update_rx_cpu_idx(eth);
1389 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1390 unsigned int *done, unsigned int *bytes)
1392 struct mtk_tx_ring *ring = ð->tx_ring;
1393 struct mtk_tx_dma *desc;
1394 struct sk_buff *skb;
1395 struct mtk_tx_buf *tx_buf;
1398 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1399 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1401 desc = mtk_qdma_phys_to_virt(ring, cpu);
1403 while ((cpu != dma) && budget) {
1404 u32 next_cpu = desc->txd2;
1407 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1408 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1411 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1412 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1419 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1420 bytes[mac] += skb->len;
1424 mtk_tx_unmap(eth, tx_buf);
1426 ring->last_free = desc;
1427 atomic_inc(&ring->free_count);
1432 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1437 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
1438 unsigned int *done, unsigned int *bytes)
1440 struct mtk_tx_ring *ring = ð->tx_ring;
1441 struct mtk_tx_dma *desc;
1442 struct sk_buff *skb;
1443 struct mtk_tx_buf *tx_buf;
1446 cpu = ring->cpu_idx;
1447 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
1449 while ((cpu != dma) && budget) {
1450 tx_buf = &ring->buf[cpu];
1455 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1456 bytes[0] += skb->len;
1461 mtk_tx_unmap(eth, tx_buf);
1463 desc = &ring->dma[cpu];
1464 ring->last_free = desc;
1465 atomic_inc(&ring->free_count);
1467 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
1470 ring->cpu_idx = cpu;
1475 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1477 struct mtk_tx_ring *ring = ð->tx_ring;
1478 unsigned int done[MTK_MAX_DEVS];
1479 unsigned int bytes[MTK_MAX_DEVS];
1482 memset(done, 0, sizeof(done));
1483 memset(bytes, 0, sizeof(bytes));
1485 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1486 budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
1488 budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
1490 for (i = 0; i < MTK_MAC_COUNT; i++) {
1491 if (!eth->netdev[i] || !done[i])
1493 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1497 if (mtk_queue_stopped(eth) &&
1498 (atomic_read(&ring->free_count) > ring->thresh))
1499 mtk_wake_queue(eth);
1504 static void mtk_handle_status_irq(struct mtk_eth *eth)
1506 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1508 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1509 mtk_stats_update(eth);
1510 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1515 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1517 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1521 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1522 mtk_handle_status_irq(eth);
1523 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg);
1524 tx_done = mtk_poll_tx(eth, budget);
1526 if (unlikely(netif_msg_intr(eth))) {
1527 status = mtk_r32(eth, eth->tx_int_status_reg);
1528 mask = mtk_r32(eth, eth->tx_int_mask_reg);
1530 "done tx %d, intr 0x%08x/0x%x\n",
1531 tx_done, status, mask);
1534 if (tx_done == budget)
1537 status = mtk_r32(eth, eth->tx_int_status_reg);
1538 if (status & MTK_TX_DONE_INT)
1541 napi_complete(napi);
1542 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1547 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1549 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1552 int remain_budget = budget;
1554 mtk_handle_status_irq(eth);
1557 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1558 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1560 if (unlikely(netif_msg_intr(eth))) {
1561 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1562 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1564 "done rx %d, intr 0x%08x/0x%x\n",
1565 rx_done, status, mask);
1567 if (rx_done == remain_budget)
1570 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1571 if (status & MTK_RX_DONE_INT) {
1572 remain_budget -= rx_done;
1575 napi_complete(napi);
1576 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1578 return rx_done + budget - remain_budget;
1581 static int mtk_tx_alloc(struct mtk_eth *eth)
1583 struct mtk_tx_ring *ring = ð->tx_ring;
1584 int i, sz = sizeof(*ring->dma);
1586 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1591 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1592 &ring->phys, GFP_ATOMIC);
1596 for (i = 0; i < MTK_DMA_SIZE; i++) {
1597 int next = (i + 1) % MTK_DMA_SIZE;
1598 u32 next_ptr = ring->phys + next * sz;
1600 ring->dma[i].txd2 = next_ptr;
1601 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1604 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
1605 * only as the framework. The real HW descriptors are the PDMA
1606 * descriptors in ring->dma_pdma.
1608 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1609 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1612 if (!ring->dma_pdma)
1615 for (i = 0; i < MTK_DMA_SIZE; i++) {
1616 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
1617 ring->dma_pdma[i].txd4 = 0;
1621 ring->dma_size = MTK_DMA_SIZE;
1622 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1623 ring->next_free = &ring->dma[0];
1624 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1625 ring->thresh = MAX_SKB_FRAGS;
1627 /* make sure that all changes to the dma ring are flushed before we
1632 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1633 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1634 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1636 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1639 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1641 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
1644 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
1645 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
1646 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
1647 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX);
1656 static void mtk_tx_clean(struct mtk_eth *eth)
1658 struct mtk_tx_ring *ring = ð->tx_ring;
1662 for (i = 0; i < MTK_DMA_SIZE; i++)
1663 mtk_tx_unmap(eth, &ring->buf[i]);
1669 dma_free_coherent(eth->dev,
1670 MTK_DMA_SIZE * sizeof(*ring->dma),
1676 if (ring->dma_pdma) {
1677 dma_free_coherent(eth->dev,
1678 MTK_DMA_SIZE * sizeof(*ring->dma_pdma),
1681 ring->dma_pdma = NULL;
1685 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1687 struct mtk_rx_ring *ring;
1688 int rx_data_len, rx_dma_size;
1692 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1695 ring = ð->rx_ring_qdma;
1698 ring = ð->rx_ring[ring_no];
1701 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1702 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1703 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1705 rx_data_len = ETH_DATA_LEN;
1706 rx_dma_size = MTK_DMA_SIZE;
1709 ring->frag_size = mtk_max_frag_size(rx_data_len);
1710 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1711 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1716 for (i = 0; i < rx_dma_size; i++) {
1717 if (ring->frag_size <= PAGE_SIZE)
1718 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1720 ring->data[i] = mtk_max_lro_buf_alloc(GFP_KERNEL);
1725 ring->dma = dma_alloc_coherent(eth->dev,
1726 rx_dma_size * sizeof(*ring->dma),
1727 &ring->phys, GFP_ATOMIC);
1731 for (i = 0; i < rx_dma_size; i++) {
1732 dma_addr_t dma_addr = dma_map_single(eth->dev,
1733 ring->data[i] + NET_SKB_PAD + eth->ip_align,
1736 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1738 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1740 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1741 ring->dma[i].rxd2 = RX_DMA_LSO;
1743 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1745 ring->dma_size = rx_dma_size;
1746 ring->calc_idx_update = false;
1747 ring->calc_idx = rx_dma_size - 1;
1748 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1749 /* make sure that all changes to the dma ring are flushed before we
1754 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1755 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1756 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1757 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1762 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1766 if (ring->data && ring->dma) {
1767 for (i = 0; i < ring->dma_size; i++) {
1770 if (!ring->dma[i].rxd1)
1772 dma_unmap_single(eth->dev,
1776 skb_free_frag(ring->data[i]);
1783 dma_free_coherent(eth->dev,
1784 ring->dma_size * sizeof(*ring->dma),
1791 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1794 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1795 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1797 /* set LRO rings to auto-learn modes */
1798 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1800 /* validate LRO ring */
1801 ring_ctrl_dw2 |= MTK_RING_VLD;
1803 /* set AGE timer (unit: 20us) */
1804 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1805 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1807 /* set max AGG timer (unit: 20us) */
1808 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1810 /* set max LRO AGG count */
1811 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1812 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1814 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1815 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1816 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1817 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1820 /* IPv4 checksum update enable */
1821 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1823 /* switch priority comparison to packet count mode */
1824 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1826 /* bandwidth threshold setting */
1827 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1829 /* auto-learn score delta setting */
1830 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1832 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1833 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1834 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1836 /* set HW LRO mode & the max aggregation count for rx packets */
1837 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1839 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1840 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1843 lro_ctrl_dw0 |= MTK_LRO_EN;
1845 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1846 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1851 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1856 /* relinquish lro rings, flush aggregated packets */
1857 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1859 /* wait for relinquishments done */
1860 for (i = 0; i < 10; i++) {
1861 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1862 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1869 /* invalidate lro rings */
1870 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1871 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1873 /* disable HW LRO */
1874 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1877 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1881 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1883 /* invalidate the IP setting */
1884 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1886 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1888 /* validate the IP setting */
1889 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1892 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1896 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1898 /* invalidate the IP setting */
1899 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1901 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1904 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1909 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1910 if (mac->hwlro_ip[i])
1917 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1918 struct ethtool_rxnfc *cmd)
1920 struct ethtool_rx_flow_spec *fsp =
1921 (struct ethtool_rx_flow_spec *)&cmd->fs;
1922 struct mtk_mac *mac = netdev_priv(dev);
1923 struct mtk_eth *eth = mac->hw;
1926 if ((fsp->flow_type != TCP_V4_FLOW) ||
1927 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1928 (fsp->location > 1))
1931 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1932 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1934 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1936 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1941 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1942 struct ethtool_rxnfc *cmd)
1944 struct ethtool_rx_flow_spec *fsp =
1945 (struct ethtool_rx_flow_spec *)&cmd->fs;
1946 struct mtk_mac *mac = netdev_priv(dev);
1947 struct mtk_eth *eth = mac->hw;
1950 if (fsp->location > 1)
1953 mac->hwlro_ip[fsp->location] = 0;
1954 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1956 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1958 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1963 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1965 struct mtk_mac *mac = netdev_priv(dev);
1966 struct mtk_eth *eth = mac->hw;
1969 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1970 mac->hwlro_ip[i] = 0;
1971 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1973 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1976 mac->hwlro_ip_cnt = 0;
1979 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1980 struct ethtool_rxnfc *cmd)
1982 struct mtk_mac *mac = netdev_priv(dev);
1983 struct ethtool_rx_flow_spec *fsp =
1984 (struct ethtool_rx_flow_spec *)&cmd->fs;
1986 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
1989 /* only tcp dst ipv4 is meaningful, others are meaningless */
1990 fsp->flow_type = TCP_V4_FLOW;
1991 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1992 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1994 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1995 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1996 fsp->h_u.tcp_ip4_spec.psrc = 0;
1997 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1998 fsp->h_u.tcp_ip4_spec.pdst = 0;
1999 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
2000 fsp->h_u.tcp_ip4_spec.tos = 0;
2001 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2006 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2007 struct ethtool_rxnfc *cmd,
2010 struct mtk_mac *mac = netdev_priv(dev);
2014 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2015 if (mac->hwlro_ip[i]) {
2021 cmd->rule_cnt = cnt;
2026 static netdev_features_t mtk_fix_features(struct net_device *dev,
2027 netdev_features_t features)
2029 if (!(features & NETIF_F_LRO)) {
2030 struct mtk_mac *mac = netdev_priv(dev);
2031 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2034 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2036 features |= NETIF_F_LRO;
2043 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2047 if (!((dev->features ^ features) & NETIF_F_LRO))
2050 if (!(features & NETIF_F_LRO))
2051 mtk_hwlro_netdev_disable(dev);
2056 /* wait for DMA to finish whatever it is doing before we start using it again */
2057 static int mtk_dma_busy_wait(struct mtk_eth *eth)
2059 unsigned long t_start = jiffies;
2062 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2063 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
2064 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
2067 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &
2068 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
2072 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
2076 dev_err(eth->dev, "DMA init timeout\n");
2080 static int mtk_dma_init(struct mtk_eth *eth)
2085 if (mtk_dma_busy_wait(eth))
2088 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2089 /* QDMA needs scratch memory for internal reordering of the
2092 err = mtk_init_fq_dma(eth);
2097 err = mtk_tx_alloc(eth);
2101 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2102 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2107 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2112 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2113 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2117 err = mtk_hwlro_rx_init(eth);
2122 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2123 /* Enable random early drop and set drop threshold
2126 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2127 FC_THRES_MIN, MTK_QDMA_FC_THRES);
2128 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
2134 static void mtk_dma_free(struct mtk_eth *eth)
2138 for (i = 0; i < MTK_MAC_COUNT; i++)
2140 netdev_reset_queue(eth->netdev[i]);
2141 if (eth->scratch_ring) {
2142 dma_free_coherent(eth->dev,
2143 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
2145 eth->phy_scratch_ring);
2146 eth->scratch_ring = NULL;
2147 eth->phy_scratch_ring = 0;
2150 mtk_rx_clean(eth, ð->rx_ring[0]);
2151 mtk_rx_clean(eth, ð->rx_ring_qdma);
2154 mtk_hwlro_rx_uninit(eth);
2155 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2156 mtk_rx_clean(eth, ð->rx_ring[i]);
2159 kfree(eth->scratch_head);
2162 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
2164 struct mtk_mac *mac = netdev_priv(dev);
2165 struct mtk_eth *eth = mac->hw;
2167 eth->netdev[mac->id]->stats.tx_errors++;
2168 netif_err(eth, tx_err, dev,
2169 "transmit timed out\n");
2170 schedule_work(ð->pending_work);
2173 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
2175 struct mtk_eth *eth = _eth;
2177 if (likely(napi_schedule_prep(ð->rx_napi))) {
2178 __napi_schedule(ð->rx_napi);
2179 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2185 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2187 struct mtk_eth *eth = _eth;
2189 if (likely(napi_schedule_prep(ð->tx_napi))) {
2190 __napi_schedule(ð->tx_napi);
2191 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2197 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2199 struct mtk_eth *eth = _eth;
2201 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
2202 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
2203 mtk_handle_irq_rx(irq, _eth);
2205 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) {
2206 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)
2207 mtk_handle_irq_tx(irq, _eth);
2213 #ifdef CONFIG_NET_POLL_CONTROLLER
2214 static void mtk_poll_controller(struct net_device *dev)
2216 struct mtk_mac *mac = netdev_priv(dev);
2217 struct mtk_eth *eth = mac->hw;
2219 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2220 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2221 mtk_handle_irq_rx(eth->irq[2], dev);
2222 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2223 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2227 static int mtk_start_dma(struct mtk_eth *eth)
2229 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
2232 err = mtk_dma_init(eth);
2238 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2240 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
2241 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
2242 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
2247 MTK_RX_DMA_EN | rx_2b_offset |
2248 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2251 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2252 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2259 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
2263 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2266 for (i = 0; i < MTK_MAC_COUNT; i++) {
2267 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2269 /* default setup the forward port to send frame to PDMA */
2272 /* Enable RX checksum */
2273 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2277 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2279 /* Reset and enable PSE */
2280 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2281 mtk_w32(eth, 0, MTK_RST_GL);
2284 static int mtk_open(struct net_device *dev)
2286 struct mtk_mac *mac = netdev_priv(dev);
2287 struct mtk_eth *eth = mac->hw;
2290 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2292 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2297 /* we run 2 netdevs on the same dma ring so we only bring it up once */
2298 if (!refcount_read(ð->dma_refcnt)) {
2299 int err = mtk_start_dma(eth);
2304 mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
2306 napi_enable(ð->tx_napi);
2307 napi_enable(ð->rx_napi);
2308 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2309 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2310 refcount_set(ð->dma_refcnt, 1);
2313 refcount_inc(ð->dma_refcnt);
2315 phylink_start(mac->phylink);
2316 netif_start_queue(dev);
2320 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
2325 /* stop the dma engine */
2326 spin_lock_bh(ð->page_lock);
2327 val = mtk_r32(eth, glo_cfg);
2328 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
2330 spin_unlock_bh(ð->page_lock);
2332 /* wait for dma stop */
2333 for (i = 0; i < 10; i++) {
2334 val = mtk_r32(eth, glo_cfg);
2335 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
2343 static int mtk_stop(struct net_device *dev)
2345 struct mtk_mac *mac = netdev_priv(dev);
2346 struct mtk_eth *eth = mac->hw;
2348 phylink_stop(mac->phylink);
2350 netif_tx_disable(dev);
2352 phylink_disconnect_phy(mac->phylink);
2354 /* only shutdown DMA if this is the last user */
2355 if (!refcount_dec_and_test(ð->dma_refcnt))
2358 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
2360 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2361 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2362 napi_disable(ð->tx_napi);
2363 napi_disable(ð->rx_napi);
2365 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2366 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
2367 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
2374 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
2376 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2380 usleep_range(1000, 1100);
2381 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2387 static void mtk_clk_disable(struct mtk_eth *eth)
2391 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
2392 clk_disable_unprepare(eth->clks[clk]);
2395 static int mtk_clk_enable(struct mtk_eth *eth)
2399 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
2400 ret = clk_prepare_enable(eth->clks[clk]);
2402 goto err_disable_clks;
2409 clk_disable_unprepare(eth->clks[clk]);
2414 static int mtk_hw_init(struct mtk_eth *eth)
2418 if (test_and_set_bit(MTK_HW_INIT, ð->state))
2421 pm_runtime_enable(eth->dev);
2422 pm_runtime_get_sync(eth->dev);
2424 ret = mtk_clk_enable(eth);
2426 goto err_disable_pm;
2428 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2429 ret = device_reset(eth->dev);
2431 dev_err(eth->dev, "MAC reset failed!\n");
2432 goto err_disable_pm;
2435 /* enable interrupt delay for RX */
2436 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2438 /* disable delay and normal interrupt */
2439 mtk_tx_irq_disable(eth, ~0);
2440 mtk_rx_irq_disable(eth, ~0);
2445 /* Non-MT7628 handling... */
2446 ethsys_reset(eth, RSTCTRL_FE);
2447 ethsys_reset(eth, RSTCTRL_PPE);
2450 /* Set GE2 driving and slew rate */
2451 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
2454 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
2457 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
2460 /* Set linkdown as the default for each GMAC. Its own MCR would be set
2461 * up with the more appropriate value when mtk_mac_config call is being
2464 for (i = 0; i < MTK_MAC_COUNT; i++)
2465 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
2467 /* Indicates CDM to parse the MTK special tag from CPU
2468 * which also is working out for untag packets.
2470 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
2471 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
2473 /* Enable RX VLan Offloading */
2474 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
2476 /* enable interrupt delay for RX */
2477 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2479 /* disable delay and normal interrupt */
2480 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2481 mtk_tx_irq_disable(eth, ~0);
2482 mtk_rx_irq_disable(eth, ~0);
2484 /* FE int grouping */
2485 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
2486 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
2487 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
2488 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
2489 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
2494 pm_runtime_put_sync(eth->dev);
2495 pm_runtime_disable(eth->dev);
2500 static int mtk_hw_deinit(struct mtk_eth *eth)
2502 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
2505 mtk_clk_disable(eth);
2507 pm_runtime_put_sync(eth->dev);
2508 pm_runtime_disable(eth->dev);
2513 static int __init mtk_init(struct net_device *dev)
2515 struct mtk_mac *mac = netdev_priv(dev);
2516 struct mtk_eth *eth = mac->hw;
2517 const char *mac_addr;
2519 mac_addr = of_get_mac_address(mac->of_node);
2520 if (!IS_ERR(mac_addr))
2521 ether_addr_copy(dev->dev_addr, mac_addr);
2523 /* If the mac address is invalid, use random mac address */
2524 if (!is_valid_ether_addr(dev->dev_addr)) {
2525 eth_hw_addr_random(dev);
2526 dev_err(eth->dev, "generated random MAC address %pM\n",
2533 static void mtk_uninit(struct net_device *dev)
2535 struct mtk_mac *mac = netdev_priv(dev);
2536 struct mtk_eth *eth = mac->hw;
2538 phylink_disconnect_phy(mac->phylink);
2539 mtk_tx_irq_disable(eth, ~0);
2540 mtk_rx_irq_disable(eth, ~0);
2543 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2545 struct mtk_mac *mac = netdev_priv(dev);
2551 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
2559 static void mtk_pending_work(struct work_struct *work)
2561 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2563 unsigned long restart = 0;
2567 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2569 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
2572 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2573 /* stop all devices to make sure that dma is properly shut down */
2574 for (i = 0; i < MTK_MAC_COUNT; i++) {
2575 if (!eth->netdev[i])
2577 mtk_stop(eth->netdev[i]);
2578 __set_bit(i, &restart);
2580 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2582 /* restart underlying hardware such as power, clock, pin mux
2583 * and the connected phy
2588 pinctrl_select_state(eth->dev->pins->p,
2589 eth->dev->pins->default_state);
2592 /* restart DMA and enable IRQs */
2593 for (i = 0; i < MTK_MAC_COUNT; i++) {
2594 if (!test_bit(i, &restart))
2596 err = mtk_open(eth->netdev[i]);
2598 netif_alert(eth, ifup, eth->netdev[i],
2599 "Driver up/down cycle failed, closing device.\n");
2600 dev_close(eth->netdev[i]);
2604 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2606 clear_bit_unlock(MTK_RESETTING, ð->state);
2611 static int mtk_free_dev(struct mtk_eth *eth)
2615 for (i = 0; i < MTK_MAC_COUNT; i++) {
2616 if (!eth->netdev[i])
2618 free_netdev(eth->netdev[i]);
2624 static int mtk_unreg_dev(struct mtk_eth *eth)
2628 for (i = 0; i < MTK_MAC_COUNT; i++) {
2629 if (!eth->netdev[i])
2631 unregister_netdev(eth->netdev[i]);
2637 static int mtk_cleanup(struct mtk_eth *eth)
2641 cancel_work_sync(ð->pending_work);
2646 static int mtk_get_link_ksettings(struct net_device *ndev,
2647 struct ethtool_link_ksettings *cmd)
2649 struct mtk_mac *mac = netdev_priv(ndev);
2651 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2654 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
2657 static int mtk_set_link_ksettings(struct net_device *ndev,
2658 const struct ethtool_link_ksettings *cmd)
2660 struct mtk_mac *mac = netdev_priv(ndev);
2662 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2665 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
2668 static void mtk_get_drvinfo(struct net_device *dev,
2669 struct ethtool_drvinfo *info)
2671 struct mtk_mac *mac = netdev_priv(dev);
2673 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2674 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2675 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2678 static u32 mtk_get_msglevel(struct net_device *dev)
2680 struct mtk_mac *mac = netdev_priv(dev);
2682 return mac->hw->msg_enable;
2685 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2687 struct mtk_mac *mac = netdev_priv(dev);
2689 mac->hw->msg_enable = value;
2692 static int mtk_nway_reset(struct net_device *dev)
2694 struct mtk_mac *mac = netdev_priv(dev);
2696 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2702 return phylink_ethtool_nway_reset(mac->phylink);
2705 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2709 switch (stringset) {
2711 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2712 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2713 data += ETH_GSTRING_LEN;
2719 static int mtk_get_sset_count(struct net_device *dev, int sset)
2723 return ARRAY_SIZE(mtk_ethtool_stats);
2729 static void mtk_get_ethtool_stats(struct net_device *dev,
2730 struct ethtool_stats *stats, u64 *data)
2732 struct mtk_mac *mac = netdev_priv(dev);
2733 struct mtk_hw_stats *hwstats = mac->hw_stats;
2734 u64 *data_src, *data_dst;
2738 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2741 if (netif_running(dev) && netif_device_present(dev)) {
2742 if (spin_trylock_bh(&hwstats->stats_lock)) {
2743 mtk_stats_update_mac(mac);
2744 spin_unlock_bh(&hwstats->stats_lock);
2748 data_src = (u64 *)hwstats;
2752 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2754 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2755 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2756 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2759 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2762 int ret = -EOPNOTSUPP;
2765 case ETHTOOL_GRXRINGS:
2766 if (dev->hw_features & NETIF_F_LRO) {
2767 cmd->data = MTK_MAX_RX_RING_NUM;
2771 case ETHTOOL_GRXCLSRLCNT:
2772 if (dev->hw_features & NETIF_F_LRO) {
2773 struct mtk_mac *mac = netdev_priv(dev);
2775 cmd->rule_cnt = mac->hwlro_ip_cnt;
2779 case ETHTOOL_GRXCLSRULE:
2780 if (dev->hw_features & NETIF_F_LRO)
2781 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2783 case ETHTOOL_GRXCLSRLALL:
2784 if (dev->hw_features & NETIF_F_LRO)
2785 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2795 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2797 int ret = -EOPNOTSUPP;
2800 case ETHTOOL_SRXCLSRLINS:
2801 if (dev->hw_features & NETIF_F_LRO)
2802 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2804 case ETHTOOL_SRXCLSRLDEL:
2805 if (dev->hw_features & NETIF_F_LRO)
2806 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2815 static const struct ethtool_ops mtk_ethtool_ops = {
2816 .get_link_ksettings = mtk_get_link_ksettings,
2817 .set_link_ksettings = mtk_set_link_ksettings,
2818 .get_drvinfo = mtk_get_drvinfo,
2819 .get_msglevel = mtk_get_msglevel,
2820 .set_msglevel = mtk_set_msglevel,
2821 .nway_reset = mtk_nway_reset,
2822 .get_link = ethtool_op_get_link,
2823 .get_strings = mtk_get_strings,
2824 .get_sset_count = mtk_get_sset_count,
2825 .get_ethtool_stats = mtk_get_ethtool_stats,
2826 .get_rxnfc = mtk_get_rxnfc,
2827 .set_rxnfc = mtk_set_rxnfc,
2830 static const struct net_device_ops mtk_netdev_ops = {
2831 .ndo_init = mtk_init,
2832 .ndo_uninit = mtk_uninit,
2833 .ndo_open = mtk_open,
2834 .ndo_stop = mtk_stop,
2835 .ndo_start_xmit = mtk_start_xmit,
2836 .ndo_set_mac_address = mtk_set_mac_address,
2837 .ndo_validate_addr = eth_validate_addr,
2838 .ndo_do_ioctl = mtk_do_ioctl,
2839 .ndo_tx_timeout = mtk_tx_timeout,
2840 .ndo_get_stats64 = mtk_get_stats64,
2841 .ndo_fix_features = mtk_fix_features,
2842 .ndo_set_features = mtk_set_features,
2843 #ifdef CONFIG_NET_POLL_CONTROLLER
2844 .ndo_poll_controller = mtk_poll_controller,
2848 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2850 const __be32 *_id = of_get_property(np, "reg", NULL);
2851 phy_interface_t phy_mode;
2852 struct phylink *phylink;
2853 struct mtk_mac *mac;
2857 dev_err(eth->dev, "missing mac id\n");
2861 id = be32_to_cpup(_id);
2862 if (id >= MTK_MAC_COUNT) {
2863 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2867 if (eth->netdev[id]) {
2868 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2872 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2873 if (!eth->netdev[id]) {
2874 dev_err(eth->dev, "alloc_etherdev failed\n");
2877 mac = netdev_priv(eth->netdev[id]);
2883 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2884 mac->hwlro_ip_cnt = 0;
2886 mac->hw_stats = devm_kzalloc(eth->dev,
2887 sizeof(*mac->hw_stats),
2889 if (!mac->hw_stats) {
2890 dev_err(eth->dev, "failed to allocate counter memory\n");
2894 spin_lock_init(&mac->hw_stats->stats_lock);
2895 u64_stats_init(&mac->hw_stats->syncp);
2896 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2898 /* phylink create */
2899 err = of_get_phy_mode(np, &phy_mode);
2901 dev_err(eth->dev, "incorrect phy-mode\n");
2905 /* mac config is not set */
2906 mac->interface = PHY_INTERFACE_MODE_NA;
2907 mac->mode = MLO_AN_PHY;
2908 mac->speed = SPEED_UNKNOWN;
2910 mac->phylink_config.dev = ð->netdev[id]->dev;
2911 mac->phylink_config.type = PHYLINK_NETDEV;
2913 phylink = phylink_create(&mac->phylink_config,
2914 of_fwnode_handle(mac->of_node),
2915 phy_mode, &mtk_phylink_ops);
2916 if (IS_ERR(phylink)) {
2917 err = PTR_ERR(phylink);
2921 mac->phylink = phylink;
2923 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2924 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2925 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2926 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2928 eth->netdev[id]->hw_features = eth->soc->hw_features;
2930 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2932 eth->netdev[id]->vlan_features = eth->soc->hw_features &
2933 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2934 eth->netdev[id]->features |= eth->soc->hw_features;
2935 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2937 eth->netdev[id]->irq = eth->irq[0];
2938 eth->netdev[id]->dev.of_node = np;
2940 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
2945 free_netdev(eth->netdev[id]);
2949 static int mtk_probe(struct platform_device *pdev)
2951 struct device_node *mac_np;
2952 struct mtk_eth *eth;
2955 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2959 eth->soc = of_device_get_match_data(&pdev->dev);
2961 eth->dev = &pdev->dev;
2962 eth->base = devm_platform_ioremap_resource(pdev, 0);
2963 if (IS_ERR(eth->base))
2964 return PTR_ERR(eth->base);
2966 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2967 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK;
2968 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS;
2970 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK;
2971 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS;
2974 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2975 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
2976 eth->ip_align = NET_IP_ALIGN;
2978 eth->rx_dma_l4_valid = RX_DMA_L4_VALID;
2981 spin_lock_init(ð->page_lock);
2982 spin_lock_init(ð->tx_irq_lock);
2983 spin_lock_init(ð->rx_irq_lock);
2985 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2986 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2988 if (IS_ERR(eth->ethsys)) {
2989 dev_err(&pdev->dev, "no ethsys regmap found\n");
2990 return PTR_ERR(eth->ethsys);
2994 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
2995 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2996 "mediatek,infracfg");
2997 if (IS_ERR(eth->infra)) {
2998 dev_err(&pdev->dev, "no infracfg regmap found\n");
2999 return PTR_ERR(eth->infra);
3003 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
3004 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
3009 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
3010 eth->soc->ana_rgc3);
3016 if (eth->soc->required_pctl) {
3017 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
3019 if (IS_ERR(eth->pctl)) {
3020 dev_err(&pdev->dev, "no pctl regmap found\n");
3021 return PTR_ERR(eth->pctl);
3025 for (i = 0; i < 3; i++) {
3026 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
3027 eth->irq[i] = eth->irq[0];
3029 eth->irq[i] = platform_get_irq(pdev, i);
3030 if (eth->irq[i] < 0) {
3031 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
3035 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
3036 eth->clks[i] = devm_clk_get(eth->dev,
3037 mtk_clks_source_name[i]);
3038 if (IS_ERR(eth->clks[i])) {
3039 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
3040 return -EPROBE_DEFER;
3041 if (eth->soc->required_clks & BIT(i)) {
3042 dev_err(&pdev->dev, "clock %s not found\n",
3043 mtk_clks_source_name[i]);
3046 eth->clks[i] = NULL;
3050 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
3051 INIT_WORK(ð->pending_work, mtk_pending_work);
3053 err = mtk_hw_init(eth);
3057 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
3059 for_each_child_of_node(pdev->dev.of_node, mac_np) {
3060 if (!of_device_is_compatible(mac_np,
3061 "mediatek,eth-mac"))
3064 if (!of_device_is_available(mac_np))
3067 err = mtk_add_mac(eth, mac_np);
3069 of_node_put(mac_np);
3074 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
3075 err = devm_request_irq(eth->dev, eth->irq[0],
3077 dev_name(eth->dev), eth);
3079 err = devm_request_irq(eth->dev, eth->irq[1],
3080 mtk_handle_irq_tx, 0,
3081 dev_name(eth->dev), eth);
3085 err = devm_request_irq(eth->dev, eth->irq[2],
3086 mtk_handle_irq_rx, 0,
3087 dev_name(eth->dev), eth);
3092 /* No MT7628/88 support yet */
3093 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3094 err = mtk_mdio_init(eth);
3099 for (i = 0; i < MTK_MAX_DEVS; i++) {
3100 if (!eth->netdev[i])
3103 err = register_netdev(eth->netdev[i]);
3105 dev_err(eth->dev, "error bringing up device\n");
3106 goto err_deinit_mdio;
3108 netif_info(eth, probe, eth->netdev[i],
3109 "mediatek frame engine at 0x%08lx, irq %d\n",
3110 eth->netdev[i]->base_addr, eth->irq[0]);
3113 /* we run 2 devices on the same DMA ring so we need a dummy device
3116 init_dummy_netdev(ð->dummy_dev);
3117 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
3119 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
3122 platform_set_drvdata(pdev, eth);
3127 mtk_mdio_cleanup(eth);
3136 static int mtk_remove(struct platform_device *pdev)
3138 struct mtk_eth *eth = platform_get_drvdata(pdev);
3139 struct mtk_mac *mac;
3142 /* stop all devices to make sure that dma is properly shut down */
3143 for (i = 0; i < MTK_MAC_COUNT; i++) {
3144 if (!eth->netdev[i])
3146 mtk_stop(eth->netdev[i]);
3147 mac = netdev_priv(eth->netdev[i]);
3148 phylink_disconnect_phy(mac->phylink);
3153 netif_napi_del(ð->tx_napi);
3154 netif_napi_del(ð->rx_napi);
3156 mtk_mdio_cleanup(eth);
3161 static const struct mtk_soc_data mt2701_data = {
3162 .caps = MT7623_CAPS | MTK_HWLRO,
3163 .hw_features = MTK_HW_FEATURES,
3164 .required_clks = MT7623_CLKS_BITMAP,
3165 .required_pctl = true,
3168 static const struct mtk_soc_data mt7621_data = {
3169 .caps = MT7621_CAPS,
3170 .hw_features = MTK_HW_FEATURES,
3171 .required_clks = MT7621_CLKS_BITMAP,
3172 .required_pctl = false,
3175 static const struct mtk_soc_data mt7622_data = {
3177 .caps = MT7622_CAPS | MTK_HWLRO,
3178 .hw_features = MTK_HW_FEATURES,
3179 .required_clks = MT7622_CLKS_BITMAP,
3180 .required_pctl = false,
3183 static const struct mtk_soc_data mt7623_data = {
3184 .caps = MT7623_CAPS | MTK_HWLRO,
3185 .hw_features = MTK_HW_FEATURES,
3186 .required_clks = MT7623_CLKS_BITMAP,
3187 .required_pctl = true,
3190 static const struct mtk_soc_data mt7629_data = {
3192 .caps = MT7629_CAPS | MTK_HWLRO,
3193 .hw_features = MTK_HW_FEATURES,
3194 .required_clks = MT7629_CLKS_BITMAP,
3195 .required_pctl = false,
3198 static const struct mtk_soc_data rt5350_data = {
3199 .caps = MT7628_CAPS,
3200 .hw_features = MTK_HW_FEATURES_MT7628,
3201 .required_clks = MT7628_CLKS_BITMAP,
3202 .required_pctl = false,
3205 const struct of_device_id of_mtk_match[] = {
3206 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
3207 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
3208 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
3209 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
3210 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
3211 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
3214 MODULE_DEVICE_TABLE(of, of_mtk_match);
3216 static struct platform_driver mtk_driver = {
3218 .remove = mtk_remove,
3220 .name = "mtk_soc_eth",
3221 .of_match_table = of_mtk_match,
3225 module_platform_driver(mtk_driver);
3227 MODULE_LICENSE("GPL");
3228 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3229 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");