1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
4 * Copyright (C) 2021 Marvell.
8 #include "otx2_common.h"
10 static int otx2_check_pfc_config(struct otx2_nic *pfvf)
12 u8 tx_queues = pfvf->hw.tx_queues, prio;
13 u8 pfc_en = pfvf->pfc_en;
15 for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
16 if ((pfc_en & (1 << prio)) &&
17 prio > tx_queues - 1) {
19 "Increase number of tx queues from %d to %d to support PFC.\n",
28 int otx2_pfc_txschq_config(struct otx2_nic *pfvf)
30 u8 pfc_en, pfc_bit_set;
33 pfc_en = pfvf->pfc_en;
34 for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
35 pfc_bit_set = pfc_en & (1 << prio);
37 /* Either PFC bit is not set
38 * or tx scheduler is not allocated for the priority
40 if (!pfc_bit_set || !pfvf->pfc_alloc_status[prio])
43 /* configure the scheduler for the tls*/
44 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
45 err = otx2_txschq_config(pfvf, lvl, prio, true);
48 "%s configure PFC tx schq for lvl:%d, prio:%d failed!\n",
58 static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio)
60 struct nix_txsch_alloc_req *req;
61 struct nix_txsch_alloc_rsp *rsp;
64 /* Get memory to put this msg */
65 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
69 /* Request one schq per level upto max level as configured
70 * link config level. These rest of the scheduler can be
71 * same as hw.txschq_list.
73 for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++)
76 rc = otx2_sync_mbox_msg(&pfvf->mbox);
80 rsp = (struct nix_txsch_alloc_rsp *)
81 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
85 /* Setup transmit scheduler list */
86 for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++) {
90 pfvf->pfc_schq_list[lvl][prio] = rsp->schq_list[lvl][0];
93 /* Set the Tx schedulers for rest of the levels same as
94 * hw.txschq_list as those will be common for all.
96 for (; lvl < NIX_TXSCH_LVL_CNT; lvl++)
97 pfvf->pfc_schq_list[lvl][prio] = pfvf->hw.txschq_list[lvl][0];
99 pfvf->pfc_alloc_status[prio] = true;
103 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf)
105 u8 pfc_en = pfvf->pfc_en;
109 for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
110 pfc_bit_set = pfc_en & (1 << prio);
112 if (!pfc_bit_set || pfvf->pfc_alloc_status[prio])
115 /* Add new scheduler to the priority */
116 err = otx2_pfc_txschq_alloc_one(pfvf, prio);
118 dev_err(pfvf->dev, "%s failed to allocate PFC TX schedulers\n", __func__);
126 static int otx2_pfc_txschq_stop_one(struct otx2_nic *pfvf, u8 prio)
130 /* free PFC TLx nodes */
131 for (lvl = 0; lvl <= pfvf->hw.txschq_link_cfg_lvl; lvl++)
132 otx2_txschq_free_one(pfvf, lvl,
133 pfvf->pfc_schq_list[lvl][prio]);
135 pfvf->pfc_alloc_status[prio] = false;
139 static int otx2_pfc_update_sq_smq_mapping(struct otx2_nic *pfvf, int prio)
141 struct nix_cn10k_aq_enq_req *cn10k_sq_aq;
142 struct net_device *dev = pfvf->netdev;
143 bool if_up = netif_running(dev);
144 struct nix_aq_enq_req *sq_aq;
147 if (pfvf->pfc_alloc_status[prio])
148 netif_tx_stop_all_queues(pfvf->netdev);
150 netif_tx_stop_queue(netdev_get_tx_queue(dev, prio));
153 if (test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) {
154 cn10k_sq_aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox);
159 cn10k_sq_aq->qidx = prio;
160 cn10k_sq_aq->ctype = NIX_AQ_CTYPE_SQ;
161 cn10k_sq_aq->op = NIX_AQ_INSTOP_WRITE;
163 /* Fill fields to update */
164 cn10k_sq_aq->sq.ena = 1;
165 cn10k_sq_aq->sq_mask.ena = 1;
166 cn10k_sq_aq->sq_mask.smq = GENMASK(9, 0);
167 cn10k_sq_aq->sq.smq = otx2_get_smq_idx(pfvf, prio);
169 sq_aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
175 sq_aq->ctype = NIX_AQ_CTYPE_SQ;
176 sq_aq->op = NIX_AQ_INSTOP_WRITE;
178 /* Fill fields to update */
180 sq_aq->sq_mask.ena = 1;
181 sq_aq->sq_mask.smq = GENMASK(8, 0);
182 sq_aq->sq.smq = otx2_get_smq_idx(pfvf, prio);
185 otx2_sync_mbox_msg(&pfvf->mbox);
188 if (pfvf->pfc_alloc_status[prio])
189 netif_tx_start_all_queues(pfvf->netdev);
191 netif_tx_start_queue(netdev_get_tx_queue(dev, prio));
197 int otx2_pfc_txschq_update(struct otx2_nic *pfvf)
199 bool if_up = netif_running(pfvf->netdev);
200 u8 pfc_en = pfvf->pfc_en, pfc_bit_set;
201 struct mbox *mbox = &pfvf->mbox;
204 mutex_lock(&mbox->lock);
205 for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
206 pfc_bit_set = pfc_en & (1 << prio);
208 /* tx scheduler was created but user wants to disable now */
209 if (!pfc_bit_set && pfvf->pfc_alloc_status[prio]) {
210 mutex_unlock(&mbox->lock);
212 netif_tx_stop_all_queues(pfvf->netdev);
214 otx2_smq_flush(pfvf, pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][prio]);
216 netif_tx_start_all_queues(pfvf->netdev);
218 /* delete the schq */
219 err = otx2_pfc_txschq_stop_one(pfvf, prio);
222 "%s failed to stop PFC tx schedulers for priority: %d\n",
227 mutex_lock(&mbox->lock);
228 goto update_sq_smq_map;
231 /* Either PFC bit is not set
232 * or Tx scheduler is already mapped for the priority
234 if (!pfc_bit_set || pfvf->pfc_alloc_status[prio])
237 /* Add new scheduler to the priority */
238 err = otx2_pfc_txschq_alloc_one(pfvf, prio);
240 mutex_unlock(&mbox->lock);
242 "%s failed to allocate PFC tx schedulers for priority: %d\n",
248 err = otx2_pfc_update_sq_smq_mapping(pfvf, prio);
250 mutex_unlock(&mbox->lock);
251 dev_err(pfvf->dev, "%s failed PFC Tx schq sq:%d mapping", __func__, prio);
256 err = otx2_pfc_txschq_config(pfvf);
257 mutex_unlock(&mbox->lock);
264 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf)
266 u8 pfc_en, pfc_bit_set;
269 pfc_en = pfvf->pfc_en;
270 for (prio = 0; prio < NIX_PF_PFC_PRIO_MAX; prio++) {
271 pfc_bit_set = pfc_en & (1 << prio);
272 if (!pfc_bit_set || !pfvf->pfc_alloc_status[prio])
275 /* Delete the existing scheduler */
276 err = otx2_pfc_txschq_stop_one(pfvf, prio);
278 dev_err(pfvf->dev, "%s failed to stop PFC TX schedulers\n", __func__);
286 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf)
288 struct cgx_pfc_cfg *req;
289 struct cgx_pfc_rsp *rsp;
292 if (is_otx2_lbkvf(pfvf->pdev))
295 mutex_lock(&pfvf->mbox.lock);
296 req = otx2_mbox_alloc_msg_cgx_prio_flow_ctrl_cfg(&pfvf->mbox);
303 req->rx_pause = true;
304 req->tx_pause = true;
306 req->rx_pause = false;
307 req->tx_pause = false;
309 req->pfc_en = pfvf->pfc_en;
311 if (!otx2_sync_mbox_msg(&pfvf->mbox)) {
312 rsp = (struct cgx_pfc_rsp *)
313 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
314 if (req->rx_pause != rsp->rx_pause || req->tx_pause != rsp->tx_pause) {
316 "Failed to config PFC\n");
321 mutex_unlock(&pfvf->mbox.lock);
325 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx,
328 bool if_up = netif_running(pfvf->netdev);
329 struct npa_aq_enq_req *npa_aq;
330 struct nix_aq_enq_req *aq;
333 if (pfvf->queue_to_pfc_map[qidx] && pfc_enable) {
335 "PFC enable not permitted as Priority %d already mapped to Queue %d\n",
336 pfvf->queue_to_pfc_map[qidx], qidx);
341 netif_tx_stop_all_queues(pfvf->netdev);
342 netif_carrier_off(pfvf->netdev);
345 pfvf->queue_to_pfc_map[qidx] = vlan_prio;
347 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
353 aq->cq.bpid = pfvf->bpid[vlan_prio];
354 aq->cq_mask.bpid = GENMASK(8, 0);
358 aq->ctype = NIX_AQ_CTYPE_CQ;
359 aq->op = NIX_AQ_INSTOP_WRITE;
361 otx2_sync_mbox_msg(&pfvf->mbox);
363 npa_aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
368 npa_aq->aura.nix0_bpid = pfvf->bpid[vlan_prio];
369 npa_aq->aura_mask.nix0_bpid = GENMASK(8, 0);
371 /* Fill NPA AQ info */
372 npa_aq->aura_id = qidx;
373 npa_aq->ctype = NPA_AQ_CTYPE_AURA;
374 npa_aq->op = NPA_AQ_INSTOP_WRITE;
375 otx2_sync_mbox_msg(&pfvf->mbox);
379 netif_carrier_on(pfvf->netdev);
380 netif_tx_start_all_queues(pfvf->netdev);
385 "Updating BPIDs in CQ and Aura contexts of RQ%d failed with err %d\n",
389 static int otx2_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc)
391 struct otx2_nic *pfvf = netdev_priv(dev);
393 pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
394 pfc->pfc_en = pfvf->pfc_en;
399 static int otx2_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc)
401 struct otx2_nic *pfvf = netdev_priv(dev);
405 old_pfc_en = pfvf->pfc_en;
406 pfvf->pfc_en = pfc->pfc_en;
408 if (pfvf->hw.tx_queues >= NIX_PF_PFC_PRIO_MAX)
411 /* Check if the PFC configuration can be
412 * supported by the tx queue configuration
414 err = otx2_check_pfc_config(pfvf);
416 pfvf->pfc_en = old_pfc_en;
421 err = otx2_config_priority_flow_ctrl(pfvf);
423 pfvf->pfc_en = old_pfc_en;
427 /* Request Per channel Bpids */
429 otx2_nix_config_bp(pfvf, true);
431 err = otx2_pfc_txschq_update(pfvf);
434 otx2_nix_config_bp(pfvf, false);
436 otx2_pfc_txschq_stop(pfvf);
437 pfvf->pfc_en = old_pfc_en;
438 otx2_config_priority_flow_ctrl(pfvf);
439 dev_err(pfvf->dev, "%s failed to update TX schedulers\n", __func__);
446 static u8 otx2_dcbnl_getdcbx(struct net_device __always_unused *dev)
448 return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
451 static u8 otx2_dcbnl_setdcbx(struct net_device __always_unused *dev, u8 mode)
453 return (mode != (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE)) ? 1 : 0;
456 static const struct dcbnl_rtnl_ops otx2_dcbnl_ops = {
457 .ieee_getpfc = otx2_dcbnl_ieee_getpfc,
458 .ieee_setpfc = otx2_dcbnl_ieee_setpfc,
459 .getdcbx = otx2_dcbnl_getdcbx,
460 .setdcbx = otx2_dcbnl_setdcbx,
463 int otx2_dcbnl_set_ops(struct net_device *dev)
465 struct otx2_nic *pfvf = netdev_priv(dev);
467 pfvf->queue_to_pfc_map = devm_kzalloc(pfvf->dev, pfvf->hw.rx_queues,
469 if (!pfvf->queue_to_pfc_map)
471 dev->dcbnl_ops = &otx2_dcbnl_ops;