1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
4 * Copyright (C) 2020 Marvell.
12 #define IQ_SEND_STOP 1
13 #define IQ_SEND_FAILED -1
15 #define TX_BUFTYPE_NONE 0
16 #define TX_BUFTYPE_NET 1
17 #define TX_BUFTYPE_NET_SG 2
18 #define NUM_TX_BUFTYPES 3
20 /* Hardware format for Scatter/Gather list
22 * 63 48|47 32|31 16|15 0
23 * -----------------------------------------
24 * | Len 0 | Len 1 | Len 2 | Len 3 |
25 * -----------------------------------------
27 * -----------------------------------------
29 * -----------------------------------------
31 * -----------------------------------------
33 * -----------------------------------------
35 struct octep_tx_sglist_desc {
37 dma_addr_t dma_ptr[4];
40 static_assert(sizeof(struct octep_tx_sglist_desc) == 40);
42 /* Each Scatter/Gather entry sent to hardwar hold four pointers.
43 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1'
44 * is for main skb which also goes as a gather buffer to Octeon hardware.
45 * To allocate sufficient SGLIST entries for a packet with max fragments,
46 * align by adding 3 before calcuating max SGLIST entries per packet.
48 #define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4)
49 #define OCTEP_SGLIST_SIZE_PER_PKT \
50 (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc))
52 struct octep_tx_buffer {
55 struct octep_tx_sglist_desc *sglist;
56 dma_addr_t sglist_dma;
60 #define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer))
62 /* Hardware interface Tx statistics */
63 struct octep_iface_tx_stats {
64 /* Total frames sent on the interface */
67 /* Total octets sent on the interface */
70 /* Packets sent to a broadcast DMAC */
73 /* Packets sent to the multicast DMAC */
76 /* Packets dropped due to excessive collisions */
79 /* Packets dropped due to excessive deferral */
82 /* Packets sent that experienced multiple collisions before successful
87 /* Packets sent that experienced a single collision before successful
92 /* Packets sent with an octet count < 64 */
95 /* Packets sent with an octet count == 64 */
98 /* Packets sent with an octet count of 65–127 */
101 /* Packets sent with an octet count of 128–255 */
104 /* Packets sent with an octet count of 256–511 */
107 /* Packets sent with an octet count of 512–1023 */
110 /* Packets sent with an octet count of 1024-1518 */
113 /* Packets sent with an octet count of > 1518 */
116 /* Packets sent that experienced a transmit underflow and were
121 /* Control/PAUSE packets sent */
125 /* Input Queue statistics. Each input queue has four stats fields. */
126 struct octep_iq_stats {
127 /* Instructions posted to this queue. */
130 /* Instructions copied by hardware for processing. */
133 /* Instructions that could not be processed. */
136 /* Bytes sent through this queue. */
139 /* Gather entries sent through this queue. */
142 /* Number of transmit failures due to TX_BUSY */
145 /* Number of times the queue is restarted */
149 /* The instruction (input) queue.
150 * The input queue is used to post raw (instruction) mode data or packet
151 * data to Octeon device from the host. Each input queue (up to 4) for
152 * a Octeon device has one such structure to represent it.
157 struct octep_device *octep_dev;
158 struct net_device *netdev;
160 struct netdev_queue *netdev_q;
162 /* Index in input ring where driver should write the next packet */
163 u16 host_write_index;
165 /* Index in input ring where Octeon is expected to read next packet */
166 u16 octep_read_index;
168 /* This index aids in finding the window in the queue where Octeon
169 * has read the commands.
173 /* Statistics for this input queue. */
174 struct octep_iq_stats stats;
176 /* Pointer to the Virtual Base addr of the input ring. */
177 struct octep_tx_desc_hw *desc_ring;
179 /* DMA mapped base address of the input descriptor ring. */
180 dma_addr_t desc_ring_dma;
182 /* Info of Tx buffers pending completion. */
183 struct octep_tx_buffer *buff_info;
185 /* Base pointer to Scatter/Gather lists for all ring descriptors. */
186 struct octep_tx_sglist_desc *sglist;
188 /* DMA mapped addr of Scatter Gather Lists */
189 dma_addr_t sglist_dma;
191 /* Octeon doorbell register for the ring. */
192 u8 __iomem *doorbell_reg;
194 /* Octeon instruction count register for this ring. */
195 u8 __iomem *inst_cnt_reg;
197 /* interrupt level register for this ring */
198 u8 __iomem *intr_lvl_reg;
200 /* Maximum no. of instructions in this queue. */
209 /* Number of instructions pending to be posted to Octeon. */
212 /* The max. number of instructions that can be held pending by the
213 * driver before ringing doorbell.
218 /* Hardware Tx Instruction Header */
219 struct octep_instr_hdr {
229 /* Front Data size */
232 /* No. of entries in gather list */
235 /* Gather indicator 1=gather*/
242 static_assert(sizeof(struct octep_instr_hdr) == 8);
244 /* Tx offload flags */
245 #define OCTEP_TX_OFFLOAD_VLAN_INSERT BIT(0)
246 #define OCTEP_TX_OFFLOAD_IPV4_CKSUM BIT(1)
247 #define OCTEP_TX_OFFLOAD_UDP_CKSUM BIT(2)
248 #define OCTEP_TX_OFFLOAD_TCP_CKSUM BIT(3)
249 #define OCTEP_TX_OFFLOAD_SCTP_CKSUM BIT(4)
250 #define OCTEP_TX_OFFLOAD_TCP_TSO BIT(5)
251 #define OCTEP_TX_OFFLOAD_UDP_TSO BIT(6)
253 #define OCTEP_TX_OFFLOAD_CKSUM (OCTEP_TX_OFFLOAD_IPV4_CKSUM | \
254 OCTEP_TX_OFFLOAD_UDP_CKSUM | \
255 OCTEP_TX_OFFLOAD_TCP_CKSUM)
257 #define OCTEP_TX_OFFLOAD_TSO (OCTEP_TX_OFFLOAD_TCP_TSO | \
258 OCTEP_TX_OFFLOAD_UDP_TSO)
260 #define OCTEP_TX_IP_CSUM(flags) ((flags) & \
261 (OCTEP_TX_OFFLOAD_IPV4_CKSUM | \
262 OCTEP_TX_OFFLOAD_TCP_CKSUM | \
263 OCTEP_TX_OFFLOAD_UDP_CKSUM))
265 #define OCTEP_TX_TSO(flags) ((flags) & \
266 (OCTEP_TX_OFFLOAD_TCP_TSO | \
267 OCTEP_TX_OFFLOAD_UDP_TSO))
287 static_assert(sizeof(struct tx_mdata) == 16);
289 /* 64-byte Tx instruction format.
290 * Format of instruction for a 64-byte mode input queue.
292 * only first 16-bytes (dptr and ih) are mandatory; rest are optional
293 * and filled by the driver based on firmware/hardware capabilities.
294 * These optional headers together called Front Data and its size is
295 * described by ih->fsz.
297 struct octep_tx_desc_hw {
298 /* Pointer where the input data is available. */
301 /* Instruction Header. */
303 struct octep_instr_hdr ih;
310 /* Additional headers available in a 64-byte instruction. */
314 static_assert(sizeof(struct octep_tx_desc_hw) == 64);
316 #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw))
317 #endif /* _OCTEP_TX_H_ */