1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
4 * Copyright (C) 2020 Marvell.
11 /* struct octep_oq_desc_hw - Octeon Hardware OQ descriptor format.
13 * The descriptor ring is made of descriptors which have 2 64-bit values:
15 * @buffer_ptr: DMA address of the skb->data
16 * @info_ptr: DMA address of host memory, used to update pkt count by hw.
17 * This is currently unused to save pci writes.
19 struct octep_oq_desc_hw {
20 dma_addr_t buffer_ptr;
24 static_assert(sizeof(struct octep_oq_desc_hw) == 16);
26 #define OCTEP_OQ_DESC_SIZE (sizeof(struct octep_oq_desc_hw))
28 /* Rx offload flags */
29 #define OCTEP_RX_OFFLOAD_VLAN_STRIP BIT(0)
30 #define OCTEP_RX_OFFLOAD_IPV4_CKSUM BIT(1)
31 #define OCTEP_RX_OFFLOAD_UDP_CKSUM BIT(2)
32 #define OCTEP_RX_OFFLOAD_TCP_CKSUM BIT(3)
34 #define OCTEP_RX_OFFLOAD_CKSUM (OCTEP_RX_OFFLOAD_IPV4_CKSUM | \
35 OCTEP_RX_OFFLOAD_UDP_CKSUM | \
36 OCTEP_RX_OFFLOAD_TCP_CKSUM)
38 #define OCTEP_RX_IP_CSUM(flags) ((flags) & \
39 (OCTEP_RX_OFFLOAD_IPV4_CKSUM | \
40 OCTEP_RX_OFFLOAD_TCP_CKSUM | \
41 OCTEP_RX_OFFLOAD_UDP_CKSUM))
43 /* bit 0 is vlan strip */
44 #define OCTEP_RX_CSUM_IP_VERIFIED BIT(1)
45 #define OCTEP_RX_CSUM_L4_VERIFIED BIT(2)
47 #define OCTEP_RX_CSUM_VERIFIED(flags) ((flags) & \
48 (OCTEP_RX_CSUM_L4_VERIFIED | \
49 OCTEP_RX_CSUM_IP_VERIFIED))
51 /* Extended Response Header in packet data received from Hardware.
52 * Includes metadata like checksum status.
53 * this is valid only if hardware/firmware published support for this.
54 * This is at offset 0 of packet data (skb->data).
56 struct octep_oq_resp_hw_ext {
64 static_assert(sizeof(struct octep_oq_resp_hw_ext) == 8);
66 #define OCTEP_OQ_RESP_HW_EXT_SIZE (sizeof(struct octep_oq_resp_hw_ext))
68 /* Length of Rx packet DMA'ed by Octeon to Host.
69 * this is in bigendian; so need to be converted to cpu endian.
70 * Octeon writes this at the beginning of Rx buffer (skb->data).
72 struct octep_oq_resp_hw {
73 /* The Length of the packet. */
77 static_assert(sizeof(struct octep_oq_resp_hw) == 8);
79 #define OCTEP_OQ_RESP_HW_SIZE (sizeof(struct octep_oq_resp_hw))
81 /* Pointer to data buffer.
82 * Driver keeps a pointer to the data buffer that it made available to
83 * the Octeon device. Since the descriptor ring keeps physical (bus)
84 * addresses, this field is required for the driver to keep track of
85 * the virtual address pointers. The fields are operated by
86 * OS-dependent routines.
88 struct octep_rx_buffer {
91 /* length from rx hardware descriptor after converting to cpu endian */
95 #define OCTEP_OQ_RECVBUF_SIZE (sizeof(struct octep_rx_buffer))
97 /* Output Queue statistics. Each output queue has four stats fields. */
98 struct octep_oq_stats {
99 /* Number of packets received from the Device. */
102 /* Number of bytes received from the Device. */
105 /* Number of times failed to allocate buffers. */
109 #define OCTEP_OQ_STATS_SIZE (sizeof(struct octep_oq_stats))
111 /* Hardware interface Rx statistics */
112 struct octep_iface_rx_stats {
113 /* Received packets */
116 /* Octets of received packets */
119 /* Received PAUSE and Control packets */
122 /* Received PAUSE and Control octets */
125 /* Filtered DMAC0 packets */
128 /* Filtered DMAC0 octets */
131 /* Packets dropped due to RX FIFO full */
132 u64 dropped_pkts_fifo_full;
134 /* Octets dropped due to RX FIFO full */
135 u64 dropped_octets_fifo_full;
140 /* Filtered DMAC1 packets */
143 /* Filtered DMAC1 octets */
146 /* NCSI-bound packets dropped */
147 u64 ncsi_dropped_pkts;
149 /* NCSI-bound octets dropped */
150 u64 ncsi_dropped_octets;
152 /* Multicast packets received. */
155 /* Broadcast packets received. */
160 /* The Descriptor Ring Output Queue structure.
161 * This structure has all the information required to implement a
167 struct octep_device *octep_dev;
168 struct net_device *netdev;
171 struct napi_struct *napi;
173 /* The receive buffer list. This list has the virtual addresses
176 struct octep_rx_buffer *buff_info;
178 /* Pointer to the mapped packet credit register.
179 * Host writes number of info/buffer ptrs available to this register
181 u8 __iomem *pkts_credit_reg;
183 /* Pointer to the mapped packet sent register.
184 * Octeon writes the number of packets DMA'ed to host memory
187 u8 __iomem *pkts_sent_reg;
189 /* Statistics for this OQ. */
190 struct octep_oq_stats stats;
192 /* Packets pending to be processed */
196 /* Index in the ring where the driver should read the next packet */
199 /* Number of descriptors in this ring. */
203 /* The number of descriptors pending refill. */
206 /* Index in the ring where the driver will refill the
207 * descriptor's buffer
210 u32 refill_threshold;
212 /* The size of each buffer pointed by the buffer pointer. */
214 u32 max_single_buffer_size;
216 /* The 8B aligned descriptor ring starts at this address. */
217 struct octep_oq_desc_hw *desc_ring;
219 /* DMA mapped address of the OQ descriptor ring. */
220 dma_addr_t desc_ring_dma;
223 #define OCTEP_OQ_SIZE (sizeof(struct octep_oq))
224 #endif /* _OCTEP_RX_H_ */