1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
4 * Copyright (C) 2020 Marvell.
8 #ifndef _OCTEP_CONFIG_H_
9 #define _OCTEP_CONFIG_H_
11 /* Tx instruction types by length */
12 #define OCTEP_32BYTE_INSTR 32
13 #define OCTEP_64BYTE_INSTR 64
15 /* Tx Queue: maximum descriptors per ring */
16 /* This needs to be a power of 2 */
17 #define OCTEP_IQ_MAX_DESCRIPTORS 1024
18 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
19 #define OCTEP_DB_MIN 8
20 /* Packet threshold for Tx queue interrupt */
21 #define OCTEP_IQ_INTR_THRESHOLD 0x0
23 /* Minimum watermark for backpressure */
24 #define OCTEP_OQ_WMARK_MIN 256
26 /* Rx Queue: maximum descriptors per ring */
27 #define OCTEP_OQ_MAX_DESCRIPTORS 1024
29 /* Rx buffer size: Use page size buffers.
30 * Build skb from allocated page buffer once the packet is received.
31 * When a gathered packet is received, make head page as skb head and
32 * page buffers in consecutive Rx descriptors as fragments.
34 #define OCTEP_OQ_BUF_SIZE (SKB_WITH_OVERHEAD(PAGE_SIZE))
35 #define OCTEP_OQ_PKTS_PER_INTR 128
36 #define OCTEP_OQ_REFILL_THRESHOLD (OCTEP_OQ_MAX_DESCRIPTORS / 4)
38 #define OCTEP_OQ_INTR_PKT_THRESHOLD 1
39 #define OCTEP_OQ_INTR_TIME_THRESHOLD 10
41 #define OCTEP_MSIX_NAME_SIZE (IFNAMSIZ + 32)
43 /* Tx Queue wake threshold
44 * wakeup a stopped Tx queue if minimum 2 descriptors are available.
45 * Even a skb with fragments consume only one Tx queue descriptor entry.
47 #define OCTEP_WAKE_QUEUE_THRESHOLD 2
49 /* Minimum MTU supported by Octeon network interface */
50 #define OCTEP_MIN_MTU ETH_MIN_MTU
52 #define OCTEP_DEFAULT_MTU 1500
54 /* pf heartbeat interval in milliseconds */
55 #define OCTEP_DEFAULT_FW_HB_INTERVAL 1000
56 /* pf heartbeat miss count */
57 #define OCTEP_DEFAULT_FW_HB_MISS_COUNT 20
59 /* Macros to get octeon config params */
60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64)
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs)
68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size)
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
70 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
71 #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
72 #define CFG_GET_OQ_WMARK(cfg) ((cfg)->oq.wmark)
74 #define CFG_GET_PORTS_MAX_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.max_io_rings)
75 #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings)
76 #define CFG_GET_PORTS_PF_SRN(cfg) ((cfg)->pf_ring_cfg.srn)
78 #define CFG_GET_CORE_TICS_PER_US(cfg) ((cfg)->core_cfg.core_tics_per_us)
79 #define CFG_GET_COPROC_TICS_PER_US(cfg) ((cfg)->core_cfg.coproc_tics_per_us)
81 #define CFG_GET_MAX_VFS(cfg) ((cfg)->sriov_cfg.max_vfs)
82 #define CFG_GET_ACTIVE_VFS(cfg) ((cfg)->sriov_cfg.active_vfs)
83 #define CFG_GET_MAX_RPVF(cfg) ((cfg)->sriov_cfg.max_rings_per_vf)
84 #define CFG_GET_ACTIVE_RPVF(cfg) ((cfg)->sriov_cfg.active_rings_per_vf)
85 #define CFG_GET_VF_SRN(cfg) ((cfg)->sriov_cfg.vf_srn)
87 #define CFG_GET_IOQ_MSIX(cfg) ((cfg)->msix_cfg.ioq_msix)
88 #define CFG_GET_NON_IOQ_MSIX(cfg) ((cfg)->msix_cfg.non_ioq_msix)
89 #define CFG_GET_NON_IOQ_MSIX_NAMES(cfg) ((cfg)->msix_cfg.non_ioq_msix_names)
91 #define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg) ((cfg)->ctrl_mbox_cfg.barmem_addr)
93 /* Hardware Tx Queue configuration. */
94 struct octep_iq_config {
95 /* Size of the Input queue (number of commands) */
98 /* Command size - 32 or 64 bytes */
101 /* Minimum number of commands pending to be posted to Octeon before driver
102 * hits the Input queue doorbell.
106 /* Trigger the IQ interrupt when processed cmd count reaches
112 /* Hardware Rx Queue configuration. */
113 struct octep_oq_config {
114 /* Size of Output queue (number of descriptors) */
117 /* Size of buffer in this Output queue. */
120 /* The number of buffers that were consumed during packet processing
121 * by the driver on this Output queue before the driver attempts to
122 * replenish the descriptor ring with new buffers.
124 u16 refill_threshold;
126 /* Interrupt Coalescing (Packet Count). Octeon will interrupt the host
127 * only if it sent as many packets as specified by this field.
128 * The driver usually does not use packet count interrupt coalescing.
132 /* Interrupt Coalescing (Time Interval). Octeon will interrupt the host
133 * if at least one packet was sent in the time interval specified by
134 * this field. The driver uses time interval interrupt coalescing by
135 * default. The time is specified in microseconds.
139 /* Water mark for backpressure.
140 * Output queue sends backpressure signal to source when
141 * free buffer count falls below wmark.
146 /* Tx/Rx configuration */
147 struct octep_pf_ring_config {
148 /* Max number of IOQs */
151 /* Number of active IOQs */
154 /* Starting IOQ number: this changes based on which PEM is used */
158 /* Octeon Hardware SRIOV config */
159 struct octep_sriov_config {
160 /* Max number of VF devices supported */
163 /* Number of VF devices enabled */
166 /* Max number of rings assigned to VF */
169 /* Number of rings enabled per VF */
170 u8 active_rings_per_vf;
172 /* starting ring number of VF's: ring-0 of VF-0 of the PF */
176 /* Octeon MSI-x config. */
177 struct octep_msix_config {
178 /* Number of IOQ interrupts */
181 /* Number of Non IOQ interrupts */
184 /* Names of Non IOQ interrupts */
185 char **non_ioq_msix_names;
188 struct octep_ctrl_mbox_config {
189 /* Barmem address for control mbox */
190 void __iomem *barmem_addr;
193 /* Info from firmware */
194 struct octep_fw_info {
195 /* interface pkind */
198 /* front size data */
201 /* heartbeat interval in milliseconds */
204 /* heartbeat miss count */
210 /* supported rx offloads OCTEP_ETH_RX_OFFLOAD_* */
213 /* supported tx offloads OCTEP_ETH_TX_OFFLOAD_* */
217 u32 reserved_offloads;
219 /* extra offload flags */
222 /* supported features */
229 /* Data Structure to hold configuration limits and active config */
230 struct octep_config {
231 /* Input Queue attributes. */
232 struct octep_iq_config iq;
234 /* Output Queue attributes. */
235 struct octep_oq_config oq;
237 /* NIC Port Configuration */
238 struct octep_pf_ring_config pf_ring_cfg;
240 /* SRIOV configuration of the PF */
241 struct octep_sriov_config sriov_cfg;
243 /* MSI-X interrupt config */
244 struct octep_msix_config msix_cfg;
246 /* ctrl mbox config */
247 struct octep_ctrl_mbox_config ctrl_mbox_cfg;
250 struct octep_fw_info fw_info;
252 #endif /* _OCTEP_CONFIG_H_ */