2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/phy_fixed.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
35 #include "mvneta_bm.h"
41 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
42 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
43 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
44 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
45 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
46 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
47 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
48 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
49 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
50 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
51 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
52 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
53 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
54 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
55 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
56 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
57 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
59 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
60 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
61 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
62 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
63 #define MVNETA_PORT_RX_RESET 0x1cc0
64 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
65 #define MVNETA_PHY_ADDR 0x2000
66 #define MVNETA_PHY_ADDR_MASK 0x1f
67 #define MVNETA_MBUS_RETRY 0x2010
68 #define MVNETA_UNIT_INTR_CAUSE 0x2080
69 #define MVNETA_UNIT_CONTROL 0x20B0
70 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
71 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
72 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
73 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
74 #define MVNETA_BASE_ADDR_ENABLE 0x2290
75 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
76 #define MVNETA_PORT_CONFIG 0x2400
77 #define MVNETA_UNI_PROMISC_MODE BIT(0)
78 #define MVNETA_DEF_RXQ(q) ((q) << 1)
79 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
80 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
81 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
82 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
83 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
84 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
85 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
86 MVNETA_DEF_RXQ_ARP(q) | \
87 MVNETA_DEF_RXQ_TCP(q) | \
88 MVNETA_DEF_RXQ_UDP(q) | \
89 MVNETA_DEF_RXQ_BPDU(q) | \
90 MVNETA_TX_UNSET_ERR_SUM | \
91 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
92 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
93 #define MVNETA_MAC_ADDR_LOW 0x2414
94 #define MVNETA_MAC_ADDR_HIGH 0x2418
95 #define MVNETA_SDMA_CONFIG 0x241c
96 #define MVNETA_SDMA_BRST_SIZE_16 4
97 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
98 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
99 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
100 #define MVNETA_DESC_SWAP BIT(6)
101 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
102 #define MVNETA_PORT_STATUS 0x2444
103 #define MVNETA_TX_IN_PRGRS BIT(0)
104 #define MVNETA_TX_FIFO_EMPTY BIT(8)
105 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
106 #define MVNETA_SERDES_CFG 0x24A0
107 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
108 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
109 #define MVNETA_TYPE_PRIO 0x24bc
110 #define MVNETA_FORCE_UNI BIT(21)
111 #define MVNETA_TXQ_CMD_1 0x24e4
112 #define MVNETA_TXQ_CMD 0x2448
113 #define MVNETA_TXQ_DISABLE_SHIFT 8
114 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
115 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
116 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
117 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
118 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
119 #define MVNETA_ACC_MODE 0x2500
120 #define MVNETA_BM_ADDRESS 0x2504
121 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
122 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
123 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
124 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
125 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
126 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
128 /* Exception Interrupt Port/Queue Cause register
130 * Their behavior depend of the mapping done using the PCPX2Q
131 * registers. For a given CPU if the bit associated to a queue is not
132 * set, then for the register a read from this CPU will always return
133 * 0 and a write won't do anything
136 #define MVNETA_INTR_NEW_CAUSE 0x25a0
137 #define MVNETA_INTR_NEW_MASK 0x25a4
139 /* bits 0..7 = TXQ SENT, one bit per queue.
140 * bits 8..15 = RXQ OCCUP, one bit per queue.
141 * bits 16..23 = RXQ FREE, one bit per queue.
142 * bit 29 = OLD_REG_SUM, see old reg ?
143 * bit 30 = TX_ERR_SUM, one bit for 4 ports
144 * bit 31 = MISC_SUM, one bit for 4 ports
146 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
147 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
148 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
149 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
150 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
152 #define MVNETA_INTR_OLD_CAUSE 0x25a8
153 #define MVNETA_INTR_OLD_MASK 0x25ac
155 /* Data Path Port/Queue Cause Register */
156 #define MVNETA_INTR_MISC_CAUSE 0x25b0
157 #define MVNETA_INTR_MISC_MASK 0x25b4
159 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
160 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
161 #define MVNETA_CAUSE_PTP BIT(4)
163 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
164 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
165 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
166 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
167 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
168 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
169 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
170 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
174 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
176 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
177 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
178 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
180 #define MVNETA_INTR_ENABLE 0x25b8
181 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
182 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
184 #define MVNETA_RXQ_CMD 0x2680
185 #define MVNETA_RXQ_DISABLE_SHIFT 8
186 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
187 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
188 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
189 #define MVNETA_GMAC_CTRL_0 0x2c00
190 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
191 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
192 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
193 #define MVNETA_GMAC_CTRL_2 0x2c08
194 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
195 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
196 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
197 #define MVNETA_GMAC2_PORT_RESET BIT(6)
198 #define MVNETA_GMAC_STATUS 0x2c10
199 #define MVNETA_GMAC_LINK_UP BIT(0)
200 #define MVNETA_GMAC_SPEED_1000 BIT(1)
201 #define MVNETA_GMAC_SPEED_100 BIT(2)
202 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
203 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
204 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
205 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
206 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
207 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
208 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
209 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
210 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
211 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
212 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
213 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
214 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
215 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
216 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
217 #define MVNETA_MIB_COUNTERS_BASE 0x3000
218 #define MVNETA_MIB_LATE_COLLISION 0x7c
219 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
220 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
221 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
222 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
223 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
224 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
225 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
226 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
227 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
228 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
229 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
230 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
231 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
232 #define MVNETA_PORT_TX_RESET 0x3cf0
233 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
234 #define MVNETA_TX_MTU 0x3e0c
235 #define MVNETA_TX_TOKEN_SIZE 0x3e14
236 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
237 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
238 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
240 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
242 /* Descriptor ring Macros */
243 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
244 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
246 /* Various constants */
249 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
250 #define MVNETA_RX_COAL_PKTS 32
251 #define MVNETA_RX_COAL_USEC 100
253 /* The two bytes Marvell header. Either contains a special value used
254 * by Marvell switches when a specific hardware mode is enabled (not
255 * supported by this driver) or is filled automatically by zeroes on
256 * the RX side. Those two bytes being at the front of the Ethernet
257 * header, they allow to have the IP header aligned on a 4 bytes
258 * boundary automatically: the hardware skips those two bytes on its
261 #define MVNETA_MH_SIZE 2
263 #define MVNETA_VLAN_TAG_LEN 4
265 #define MVNETA_TX_CSUM_DEF_SIZE 1600
266 #define MVNETA_TX_CSUM_MAX_SIZE 9800
267 #define MVNETA_ACC_MODE_EXT1 1
268 #define MVNETA_ACC_MODE_EXT2 2
270 #define MVNETA_MAX_DECODE_WIN 6
272 /* Timeout constants */
273 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
274 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
275 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
277 #define MVNETA_TX_MTU_MAX 0x3ffff
279 /* The RSS lookup table actually has 256 entries but we do not use
282 #define MVNETA_RSS_LU_TABLE_SIZE 1
284 /* Max number of Rx descriptors */
285 #define MVNETA_MAX_RXD 128
287 /* Max number of Tx descriptors */
288 #define MVNETA_MAX_TXD 532
290 /* Max number of allowed TCP segments for software TSO */
291 #define MVNETA_MAX_TSO_SEGS 100
293 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
295 /* descriptor aligned size */
296 #define MVNETA_DESC_ALIGNED_SIZE 32
298 /* Number of bytes to be taken into account by HW when putting incoming data
299 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
300 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
302 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
304 #define MVNETA_RX_PKT_SIZE(mtu) \
305 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
306 ETH_HLEN + ETH_FCS_LEN, \
309 #define IS_TSO_HEADER(txq, addr) \
310 ((addr >= txq->tso_hdrs_phys) && \
311 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
313 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
314 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
316 struct mvneta_statistic {
317 unsigned short offset;
319 const char name[ETH_GSTRING_LEN];
325 static const struct mvneta_statistic mvneta_statistics[] = {
326 { 0x3000, T_REG_64, "good_octets_received", },
327 { 0x3010, T_REG_32, "good_frames_received", },
328 { 0x3008, T_REG_32, "bad_octets_received", },
329 { 0x3014, T_REG_32, "bad_frames_received", },
330 { 0x3018, T_REG_32, "broadcast_frames_received", },
331 { 0x301c, T_REG_32, "multicast_frames_received", },
332 { 0x3050, T_REG_32, "unrec_mac_control_received", },
333 { 0x3058, T_REG_32, "good_fc_received", },
334 { 0x305c, T_REG_32, "bad_fc_received", },
335 { 0x3060, T_REG_32, "undersize_received", },
336 { 0x3064, T_REG_32, "fragments_received", },
337 { 0x3068, T_REG_32, "oversize_received", },
338 { 0x306c, T_REG_32, "jabber_received", },
339 { 0x3070, T_REG_32, "mac_receive_error", },
340 { 0x3074, T_REG_32, "bad_crc_event", },
341 { 0x3078, T_REG_32, "collision", },
342 { 0x307c, T_REG_32, "late_collision", },
343 { 0x2484, T_REG_32, "rx_discard", },
344 { 0x2488, T_REG_32, "rx_overrun", },
345 { 0x3020, T_REG_32, "frames_64_octets", },
346 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
347 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
348 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
349 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
350 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
351 { 0x3038, T_REG_64, "good_octets_sent", },
352 { 0x3040, T_REG_32, "good_frames_sent", },
353 { 0x3044, T_REG_32, "excessive_collision", },
354 { 0x3048, T_REG_32, "multicast_frames_sent", },
355 { 0x304c, T_REG_32, "broadcast_frames_sent", },
356 { 0x3054, T_REG_32, "fc_sent", },
357 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
360 struct mvneta_pcpu_stats {
361 struct u64_stats_sync syncp;
368 struct mvneta_pcpu_port {
369 /* Pointer to the shared port */
370 struct mvneta_port *pp;
372 /* Pointer to the CPU-local NAPI struct */
373 struct napi_struct napi;
375 /* Cause of the previous interrupt */
381 struct mvneta_pcpu_port __percpu *ports;
382 struct mvneta_pcpu_stats __percpu *stats;
385 unsigned int frag_size;
387 struct mvneta_rx_queue *rxqs;
388 struct mvneta_tx_queue *txqs;
389 struct net_device *dev;
390 struct hlist_node node_online;
391 struct hlist_node node_dead;
393 /* Protect the access to the percpu interrupt registers,
394 * ensuring that the configuration remains coherent.
400 struct napi_struct napi;
410 struct mii_bus *mii_bus;
411 phy_interface_t phy_interface;
412 struct device_node *phy_node;
416 unsigned int tx_csum_limit;
417 unsigned int use_inband_status:1;
419 struct mvneta_bm *bm_priv;
420 struct mvneta_bm_pool *pool_long;
421 struct mvneta_bm_pool *pool_short;
424 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
426 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
428 /* Flags for special SoC configurations */
429 bool neta_armada3700;
430 u16 rx_offset_correction;
431 const struct mbus_dram_target_info *dram_target_info;
434 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
435 * layout of the transmit and reception DMA descriptors, and their
436 * layout is therefore defined by the hardware design
439 #define MVNETA_TX_L3_OFF_SHIFT 0
440 #define MVNETA_TX_IP_HLEN_SHIFT 8
441 #define MVNETA_TX_L4_UDP BIT(16)
442 #define MVNETA_TX_L3_IP6 BIT(17)
443 #define MVNETA_TXD_IP_CSUM BIT(18)
444 #define MVNETA_TXD_Z_PAD BIT(19)
445 #define MVNETA_TXD_L_DESC BIT(20)
446 #define MVNETA_TXD_F_DESC BIT(21)
447 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
448 MVNETA_TXD_L_DESC | \
450 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
451 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
453 #define MVNETA_RXD_ERR_CRC 0x0
454 #define MVNETA_RXD_BM_POOL_SHIFT 13
455 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
456 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
457 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
458 #define MVNETA_RXD_ERR_LEN BIT(18)
459 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
460 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
461 #define MVNETA_RXD_L3_IP4 BIT(25)
462 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
463 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
465 #if defined(__LITTLE_ENDIAN)
466 struct mvneta_tx_desc {
467 u32 command; /* Options used by HW for packet transmitting.*/
468 u16 reserverd1; /* csum_l4 (for future use) */
469 u16 data_size; /* Data size of transmitted packet in bytes */
470 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
471 u32 reserved2; /* hw_cmd - (for future use, PMT) */
472 u32 reserved3[4]; /* Reserved - (for future use) */
475 struct mvneta_rx_desc {
476 u32 status; /* Info about received packet */
477 u16 reserved1; /* pnc_info - (for future use, PnC) */
478 u16 data_size; /* Size of received packet in bytes */
480 u32 buf_phys_addr; /* Physical address of the buffer */
481 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
483 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
484 u16 reserved3; /* prefetch_cmd, for future use */
485 u16 reserved4; /* csum_l4 - (for future use, PnC) */
487 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
488 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
491 struct mvneta_tx_desc {
492 u16 data_size; /* Data size of transmitted packet in bytes */
493 u16 reserverd1; /* csum_l4 (for future use) */
494 u32 command; /* Options used by HW for packet transmitting.*/
495 u32 reserved2; /* hw_cmd - (for future use, PMT) */
496 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
497 u32 reserved3[4]; /* Reserved - (for future use) */
500 struct mvneta_rx_desc {
501 u16 data_size; /* Size of received packet in bytes */
502 u16 reserved1; /* pnc_info - (for future use, PnC) */
503 u32 status; /* Info about received packet */
505 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
506 u32 buf_phys_addr; /* Physical address of the buffer */
508 u16 reserved4; /* csum_l4 - (for future use, PnC) */
509 u16 reserved3; /* prefetch_cmd, for future use */
510 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
512 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
513 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
517 struct mvneta_tx_queue {
518 /* Number of this TX queue, in the range 0-7 */
521 /* Number of TX DMA descriptors in the descriptor ring */
524 /* Number of currently used TX DMA descriptor in the
529 int tx_stop_threshold;
530 int tx_wake_threshold;
532 /* Array of transmitted skb */
533 struct sk_buff **tx_skb;
535 /* Index of last TX DMA descriptor that was inserted */
538 /* Index of the TX DMA descriptor to be cleaned up */
543 /* Virtual address of the TX DMA descriptors array */
544 struct mvneta_tx_desc *descs;
546 /* DMA address of the TX DMA descriptors array */
547 dma_addr_t descs_phys;
549 /* Index of the last TX DMA descriptor */
552 /* Index of the next TX DMA descriptor to process */
553 int next_desc_to_proc;
555 /* DMA buffers for TSO headers */
558 /* DMA address of TSO headers */
559 dma_addr_t tso_hdrs_phys;
561 /* Affinity mask for CPUs*/
562 cpumask_t affinity_mask;
565 struct mvneta_rx_queue {
566 /* rx queue number, in the range 0-7 */
569 /* num of rx descriptors in the rx descriptor ring */
572 /* counter of times when mvneta_refill() failed */
578 /* Virtual address of the RX buffer */
579 void **buf_virt_addr;
581 /* Virtual address of the RX DMA descriptors array */
582 struct mvneta_rx_desc *descs;
584 /* DMA address of the RX DMA descriptors array */
585 dma_addr_t descs_phys;
587 /* Index of the last RX DMA descriptor */
590 /* Index of the next RX DMA descriptor to process */
591 int next_desc_to_proc;
594 static enum cpuhp_state online_hpstate;
595 /* The hardware supports eight (8) rx queues, but we are only allowing
596 * the first one to be used. Therefore, let's just allocate one queue.
598 static int rxq_number = 8;
599 static int txq_number = 8;
603 static int rx_copybreak __read_mostly = 256;
605 /* HW BM need that each port be identify by a unique ID */
606 static int global_port_id;
608 #define MVNETA_DRIVER_NAME "mvneta"
609 #define MVNETA_DRIVER_VERSION "1.0"
611 /* Utility/helper methods */
613 /* Write helper method */
614 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
616 writel(data, pp->base + offset);
619 /* Read helper method */
620 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
622 return readl(pp->base + offset);
625 /* Increment txq get counter */
626 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
628 txq->txq_get_index++;
629 if (txq->txq_get_index == txq->size)
630 txq->txq_get_index = 0;
633 /* Increment txq put counter */
634 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
636 txq->txq_put_index++;
637 if (txq->txq_put_index == txq->size)
638 txq->txq_put_index = 0;
642 /* Clear all MIB counters */
643 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
648 /* Perform dummy reads from MIB counters */
649 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
650 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
651 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
652 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
655 /* Get System Network Statistics */
657 mvneta_get_stats64(struct net_device *dev,
658 struct rtnl_link_stats64 *stats)
660 struct mvneta_port *pp = netdev_priv(dev);
664 for_each_possible_cpu(cpu) {
665 struct mvneta_pcpu_stats *cpu_stats;
671 cpu_stats = per_cpu_ptr(pp->stats, cpu);
673 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
674 rx_packets = cpu_stats->rx_packets;
675 rx_bytes = cpu_stats->rx_bytes;
676 tx_packets = cpu_stats->tx_packets;
677 tx_bytes = cpu_stats->tx_bytes;
678 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
680 stats->rx_packets += rx_packets;
681 stats->rx_bytes += rx_bytes;
682 stats->tx_packets += tx_packets;
683 stats->tx_bytes += tx_bytes;
686 stats->rx_errors = dev->stats.rx_errors;
687 stats->rx_dropped = dev->stats.rx_dropped;
689 stats->tx_dropped = dev->stats.tx_dropped;
692 /* Rx descriptors helper methods */
694 /* Checks whether the RX descriptor having this status is both the first
695 * and the last descriptor for the RX packet. Each RX packet is currently
696 * received through a single RX descriptor, so not having each RX
697 * descriptor with its first and last bits set is an error
699 static int mvneta_rxq_desc_is_first_last(u32 status)
701 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
702 MVNETA_RXD_FIRST_LAST_DESC;
705 /* Add number of descriptors ready to receive new packets */
706 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
707 struct mvneta_rx_queue *rxq,
710 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
713 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
714 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
715 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
716 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
717 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
720 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
721 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
724 /* Get number of RX descriptors occupied by received packets */
725 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
726 struct mvneta_rx_queue *rxq)
730 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
731 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
734 /* Update num of rx desc called upon return from rx path or
735 * from mvneta_rxq_drop_pkts().
737 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
738 struct mvneta_rx_queue *rxq,
739 int rx_done, int rx_filled)
743 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
745 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
746 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
750 /* Only 255 descriptors can be added at once */
751 while ((rx_done > 0) || (rx_filled > 0)) {
752 if (rx_done <= 0xff) {
759 if (rx_filled <= 0xff) {
760 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
763 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
766 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
770 /* Get pointer to next RX descriptor to be processed by SW */
771 static struct mvneta_rx_desc *
772 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
774 int rx_desc = rxq->next_desc_to_proc;
776 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
777 prefetch(rxq->descs + rxq->next_desc_to_proc);
778 return rxq->descs + rx_desc;
781 /* Change maximum receive size of the port. */
782 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
786 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
787 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
788 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
789 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
790 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
794 /* Set rx queue offset */
795 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
796 struct mvneta_rx_queue *rxq,
801 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
802 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
805 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
806 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
810 /* Tx descriptors helper methods */
812 /* Update HW with number of TX descriptors to be sent */
813 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
814 struct mvneta_tx_queue *txq,
819 pend_desc += txq->pending;
821 /* Only 255 Tx descriptors can be added at once */
823 val = min(pend_desc, 255);
824 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
826 } while (pend_desc > 0);
830 /* Get pointer to next TX descriptor to be processed (send) by HW */
831 static struct mvneta_tx_desc *
832 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
834 int tx_desc = txq->next_desc_to_proc;
836 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
837 return txq->descs + tx_desc;
840 /* Release the last allocated TX descriptor. Useful to handle DMA
841 * mapping failures in the TX path.
843 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
845 if (txq->next_desc_to_proc == 0)
846 txq->next_desc_to_proc = txq->last_desc - 1;
848 txq->next_desc_to_proc--;
851 /* Set rxq buf size */
852 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
853 struct mvneta_rx_queue *rxq,
858 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
860 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
861 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
863 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
866 /* Disable buffer management (BM) */
867 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
868 struct mvneta_rx_queue *rxq)
872 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
873 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
874 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
877 /* Enable buffer management (BM) */
878 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
879 struct mvneta_rx_queue *rxq)
883 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
884 val |= MVNETA_RXQ_HW_BUF_ALLOC;
885 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
888 /* Notify HW about port's assignment of pool for bigger packets */
889 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
890 struct mvneta_rx_queue *rxq)
894 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
895 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
896 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
898 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
901 /* Notify HW about port's assignment of pool for smaller packets */
902 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
903 struct mvneta_rx_queue *rxq)
907 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
908 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
909 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
911 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
914 /* Set port's receive buffer size for assigned BM pool */
915 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
921 if (!IS_ALIGNED(buf_size, 8)) {
922 dev_warn(pp->dev->dev.parent,
923 "illegal buf_size value %d, round to %d\n",
924 buf_size, ALIGN(buf_size, 8));
925 buf_size = ALIGN(buf_size, 8);
928 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
929 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
930 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
933 /* Configure MBUS window in order to enable access BM internal SRAM */
934 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
937 u32 win_enable, win_protect;
940 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
942 if (pp->bm_win_id < 0) {
943 /* Find first not occupied window */
944 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
945 if (win_enable & (1 << i)) {
950 if (i == MVNETA_MAX_DECODE_WIN)
956 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
957 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
960 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
962 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
963 (attr << 8) | target);
965 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
967 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
968 win_protect |= 3 << (2 * i);
969 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
971 win_enable &= ~(1 << i);
972 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
977 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
983 /* Get BM window information */
984 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
991 /* Open NETA -> BM window */
992 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
995 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1001 /* Assign and initialize pools for port. In case of fail
1002 * buffer manager will remain disabled for current port.
1004 static int mvneta_bm_port_init(struct platform_device *pdev,
1005 struct mvneta_port *pp)
1007 struct device_node *dn = pdev->dev.of_node;
1008 u32 long_pool_id, short_pool_id;
1010 if (!pp->neta_armada3700) {
1013 ret = mvneta_bm_port_mbus_init(pp);
1018 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1019 netdev_info(pp->dev, "missing long pool id\n");
1023 /* Create port's long pool depending on mtu */
1024 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1025 MVNETA_BM_LONG, pp->id,
1026 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1027 if (!pp->pool_long) {
1028 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1032 pp->pool_long->port_map |= 1 << pp->id;
1034 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1037 /* If short pool id is not defined, assume using single pool */
1038 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1039 short_pool_id = long_pool_id;
1041 /* Create port's short pool */
1042 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1043 MVNETA_BM_SHORT, pp->id,
1044 MVNETA_BM_SHORT_PKT_SIZE);
1045 if (!pp->pool_short) {
1046 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1047 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1051 if (short_pool_id != long_pool_id) {
1052 pp->pool_short->port_map |= 1 << pp->id;
1053 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1054 pp->pool_short->id);
1060 /* Update settings of a pool for bigger packets */
1061 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1063 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1064 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1067 /* Release all buffers from long pool */
1068 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1069 if (hwbm_pool->buf_num) {
1070 WARN(1, "cannot free all buffers in pool %d\n",
1075 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1076 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1077 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1078 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1080 /* Fill entire long pool */
1081 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1082 if (num != hwbm_pool->size) {
1083 WARN(1, "pool %d: %d of %d allocated\n",
1084 bm_pool->id, num, hwbm_pool->size);
1087 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1092 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1093 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1096 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1097 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1100 /* Start the Ethernet port RX and TX activity */
1101 static void mvneta_port_up(struct mvneta_port *pp)
1106 /* Enable all initialized TXs. */
1108 for (queue = 0; queue < txq_number; queue++) {
1109 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1111 q_map |= (1 << queue);
1113 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1116 /* Enable all initialized RXQs. */
1117 for (queue = 0; queue < rxq_number; queue++) {
1118 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1121 q_map |= (1 << queue);
1123 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1126 /* Stop the Ethernet port activity */
1127 static void mvneta_port_down(struct mvneta_port *pp)
1132 /* Stop Rx port activity. Check port Rx activity. */
1133 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1135 /* Issue stop command for active channels only */
1137 mvreg_write(pp, MVNETA_RXQ_CMD,
1138 val << MVNETA_RXQ_DISABLE_SHIFT);
1140 /* Wait for all Rx activity to terminate. */
1143 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1144 netdev_warn(pp->dev,
1145 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1151 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1152 } while (val & MVNETA_RXQ_ENABLE_MASK);
1154 /* Stop Tx port activity. Check port Tx activity. Issue stop
1155 * command for active channels only
1157 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1160 mvreg_write(pp, MVNETA_TXQ_CMD,
1161 (val << MVNETA_TXQ_DISABLE_SHIFT));
1163 /* Wait for all Tx activity to terminate. */
1166 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1167 netdev_warn(pp->dev,
1168 "TIMEOUT for TX stopped status=0x%08x\n",
1174 /* Check TX Command reg that all Txqs are stopped */
1175 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1177 } while (val & MVNETA_TXQ_ENABLE_MASK);
1179 /* Double check to verify that TX FIFO is empty */
1182 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1183 netdev_warn(pp->dev,
1184 "TX FIFO empty timeout status=0x%08x\n",
1190 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1191 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1192 (val & MVNETA_TX_IN_PRGRS));
1197 /* Enable the port by setting the port enable bit of the MAC control register */
1198 static void mvneta_port_enable(struct mvneta_port *pp)
1203 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1204 val |= MVNETA_GMAC0_PORT_ENABLE;
1205 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1208 /* Disable the port and wait for about 200 usec before retuning */
1209 static void mvneta_port_disable(struct mvneta_port *pp)
1213 /* Reset the Enable bit in the Serial Control Register */
1214 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1215 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1216 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1225 /* Multicast tables methods */
1227 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1228 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1236 val = 0x1 | (queue << 1);
1237 val |= (val << 24) | (val << 16) | (val << 8);
1240 for (offset = 0; offset <= 0xc; offset += 4)
1241 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1244 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1245 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1253 val = 0x1 | (queue << 1);
1254 val |= (val << 24) | (val << 16) | (val << 8);
1257 for (offset = 0; offset <= 0xfc; offset += 4)
1258 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1262 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1263 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1269 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1272 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1273 val = 0x1 | (queue << 1);
1274 val |= (val << 24) | (val << 16) | (val << 8);
1277 for (offset = 0; offset <= 0xfc; offset += 4)
1278 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1281 static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
1286 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1287 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1288 MVNETA_GMAC_FORCE_LINK_DOWN |
1289 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1290 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1291 MVNETA_GMAC_AN_SPEED_EN |
1292 MVNETA_GMAC_AN_DUPLEX_EN;
1293 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1295 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1296 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1297 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1299 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1300 val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
1301 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1303 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1304 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1305 MVNETA_GMAC_AN_SPEED_EN |
1306 MVNETA_GMAC_AN_DUPLEX_EN);
1307 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1309 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1310 val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
1311 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1313 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1314 val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
1315 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1319 static void mvneta_percpu_unmask_interrupt(void *arg)
1321 struct mvneta_port *pp = arg;
1323 /* All the queue are unmasked, but actually only the ones
1324 * mapped to this CPU will be unmasked
1326 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1327 MVNETA_RX_INTR_MASK_ALL |
1328 MVNETA_TX_INTR_MASK_ALL |
1329 MVNETA_MISCINTR_INTR_MASK);
1332 static void mvneta_percpu_mask_interrupt(void *arg)
1334 struct mvneta_port *pp = arg;
1336 /* All the queue are masked, but actually only the ones
1337 * mapped to this CPU will be masked
1339 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1340 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1341 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1344 static void mvneta_percpu_clear_intr_cause(void *arg)
1346 struct mvneta_port *pp = arg;
1348 /* All the queue are cleared, but actually only the ones
1349 * mapped to this CPU will be cleared
1351 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1352 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1353 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1356 /* This method sets defaults to the NETA port:
1357 * Clears interrupt Cause and Mask registers.
1358 * Clears all MAC tables.
1359 * Sets defaults to all registers.
1360 * Resets RX and TX descriptor rings.
1362 * This method can be called after mvneta_port_down() to return the port
1363 * settings to defaults.
1365 static void mvneta_defaults_set(struct mvneta_port *pp)
1370 int max_cpu = num_present_cpus();
1372 /* Clear all Cause registers */
1373 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1375 /* Mask all interrupts */
1376 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1377 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1379 /* Enable MBUS Retry bit16 */
1380 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1382 /* Set CPU queue access map. CPUs are assigned to the RX and
1383 * TX queues modulo their number. If there is only one TX
1384 * queue then it is assigned to the CPU associated to the
1387 for_each_present_cpu(cpu) {
1388 int rxq_map = 0, txq_map = 0;
1390 if (!pp->neta_armada3700) {
1391 for (rxq = 0; rxq < rxq_number; rxq++)
1392 if ((rxq % max_cpu) == cpu)
1393 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1395 for (txq = 0; txq < txq_number; txq++)
1396 if ((txq % max_cpu) == cpu)
1397 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1399 /* With only one TX queue we configure a special case
1400 * which will allow to get all the irq on a single
1403 if (txq_number == 1)
1404 txq_map = (cpu == pp->rxq_def) ?
1405 MVNETA_CPU_TXQ_ACCESS(0) : 0;
1408 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1409 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1412 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1415 /* Reset RX and TX DMAs */
1416 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1417 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1419 /* Disable Legacy WRR, Disable EJP, Release from reset */
1420 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1421 for (queue = 0; queue < txq_number; queue++) {
1422 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1423 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1426 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1427 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1429 /* Set Port Acceleration Mode */
1431 /* HW buffer management + legacy parser */
1432 val = MVNETA_ACC_MODE_EXT2;
1434 /* SW buffer management + legacy parser */
1435 val = MVNETA_ACC_MODE_EXT1;
1436 mvreg_write(pp, MVNETA_ACC_MODE, val);
1439 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1441 /* Update val of portCfg register accordingly with all RxQueue types */
1442 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1443 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1446 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1447 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1449 /* Build PORT_SDMA_CONFIG_REG */
1452 /* Default burst size */
1453 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1454 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1455 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1457 #if defined(__BIG_ENDIAN)
1458 val |= MVNETA_DESC_SWAP;
1461 /* Assign port SDMA configuration */
1462 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1464 /* Disable PHY polling in hardware, since we're using the
1465 * kernel phylib to do this.
1467 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1468 val &= ~MVNETA_PHY_POLLING_ENABLE;
1469 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1471 mvneta_set_autoneg(pp, pp->use_inband_status);
1472 mvneta_set_ucast_table(pp, -1);
1473 mvneta_set_special_mcast_table(pp, -1);
1474 mvneta_set_other_mcast_table(pp, -1);
1476 /* Set port interrupt enable register - default enable all */
1477 mvreg_write(pp, MVNETA_INTR_ENABLE,
1478 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1479 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1481 mvneta_mib_counters_clear(pp);
1484 /* Set max sizes for tx queues */
1485 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1491 mtu = max_tx_size * 8;
1492 if (mtu > MVNETA_TX_MTU_MAX)
1493 mtu = MVNETA_TX_MTU_MAX;
1496 val = mvreg_read(pp, MVNETA_TX_MTU);
1497 val &= ~MVNETA_TX_MTU_MAX;
1499 mvreg_write(pp, MVNETA_TX_MTU, val);
1501 /* TX token size and all TXQs token size must be larger that MTU */
1502 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1504 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1507 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1509 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1511 for (queue = 0; queue < txq_number; queue++) {
1512 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1514 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1517 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1519 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1524 /* Set unicast address */
1525 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1528 unsigned int unicast_reg;
1529 unsigned int tbl_offset;
1530 unsigned int reg_offset;
1532 /* Locate the Unicast table entry */
1533 last_nibble = (0xf & last_nibble);
1535 /* offset from unicast tbl base */
1536 tbl_offset = (last_nibble / 4) * 4;
1538 /* offset within the above reg */
1539 reg_offset = last_nibble % 4;
1541 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1544 /* Clear accepts frame bit at specified unicast DA tbl entry */
1545 unicast_reg &= ~(0xff << (8 * reg_offset));
1547 unicast_reg &= ~(0xff << (8 * reg_offset));
1548 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1551 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1554 /* Set mac address */
1555 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1562 mac_l = (addr[4] << 8) | (addr[5]);
1563 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1564 (addr[2] << 8) | (addr[3] << 0);
1566 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1567 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1570 /* Accept frames of this address */
1571 mvneta_set_ucast_addr(pp, addr[5], queue);
1574 /* Set the number of packets that will be received before RX interrupt
1575 * will be generated by HW.
1577 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1578 struct mvneta_rx_queue *rxq, u32 value)
1580 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1581 value | MVNETA_RXQ_NON_OCCUPIED(0));
1582 rxq->pkts_coal = value;
1585 /* Set the time delay in usec before RX interrupt will be generated by
1588 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1589 struct mvneta_rx_queue *rxq, u32 value)
1592 unsigned long clk_rate;
1594 clk_rate = clk_get_rate(pp->clk);
1595 val = (clk_rate / 1000000) * value;
1597 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1598 rxq->time_coal = value;
1601 /* Set threshold for TX_DONE pkts coalescing */
1602 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1603 struct mvneta_tx_queue *txq, u32 value)
1607 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1609 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1610 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1612 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1614 txq->done_pkts_coal = value;
1617 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1618 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1619 u32 phys_addr, void *virt_addr,
1620 struct mvneta_rx_queue *rxq)
1624 rx_desc->buf_phys_addr = phys_addr;
1625 i = rx_desc - rxq->descs;
1626 rxq->buf_virt_addr[i] = virt_addr;
1629 /* Decrement sent descriptors counter */
1630 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1631 struct mvneta_tx_queue *txq,
1636 /* Only 255 TX descriptors can be updated at once */
1637 while (sent_desc > 0xff) {
1638 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1639 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1640 sent_desc = sent_desc - 0xff;
1643 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1644 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1647 /* Get number of TX descriptors already sent by HW */
1648 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1649 struct mvneta_tx_queue *txq)
1654 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1655 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1656 MVNETA_TXQ_SENT_DESC_SHIFT;
1661 /* Get number of sent descriptors and decrement counter.
1662 * The number of sent descriptors is returned.
1664 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1665 struct mvneta_tx_queue *txq)
1669 /* Get number of sent descriptors */
1670 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1672 /* Decrement sent descriptors counter */
1674 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1679 /* Set TXQ descriptors fields relevant for CSUM calculation */
1680 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1681 int ip_hdr_len, int l4_proto)
1685 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1686 * G_L4_chk, L4_type; required only for checksum
1689 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1690 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1692 if (l3_proto == htons(ETH_P_IP))
1693 command |= MVNETA_TXD_IP_CSUM;
1695 command |= MVNETA_TX_L3_IP6;
1697 if (l4_proto == IPPROTO_TCP)
1698 command |= MVNETA_TX_L4_CSUM_FULL;
1699 else if (l4_proto == IPPROTO_UDP)
1700 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1702 command |= MVNETA_TX_L4_CSUM_NOT;
1708 /* Display more error info */
1709 static void mvneta_rx_error(struct mvneta_port *pp,
1710 struct mvneta_rx_desc *rx_desc)
1712 u32 status = rx_desc->status;
1714 if (!mvneta_rxq_desc_is_first_last(status)) {
1716 "bad rx status %08x (buffer oversize), size=%d\n",
1717 status, rx_desc->data_size);
1721 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1722 case MVNETA_RXD_ERR_CRC:
1723 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1724 status, rx_desc->data_size);
1726 case MVNETA_RXD_ERR_OVERRUN:
1727 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1728 status, rx_desc->data_size);
1730 case MVNETA_RXD_ERR_LEN:
1731 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1732 status, rx_desc->data_size);
1734 case MVNETA_RXD_ERR_RESOURCE:
1735 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1736 status, rx_desc->data_size);
1741 /* Handle RX checksum offload based on the descriptor's status */
1742 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1743 struct sk_buff *skb)
1745 if ((status & MVNETA_RXD_L3_IP4) &&
1746 (status & MVNETA_RXD_L4_CSUM_OK)) {
1748 skb->ip_summed = CHECKSUM_UNNECESSARY;
1752 skb->ip_summed = CHECKSUM_NONE;
1755 /* Return tx queue pointer (find last set bit) according to <cause> returned
1756 * form tx_done reg. <cause> must not be null. The return value is always a
1757 * valid queue for matching the first one found in <cause>.
1759 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1762 int queue = fls(cause) - 1;
1764 return &pp->txqs[queue];
1767 /* Free tx queue skbuffs */
1768 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1769 struct mvneta_tx_queue *txq, int num,
1770 struct netdev_queue *nq)
1772 unsigned int bytes_compl = 0, pkts_compl = 0;
1775 for (i = 0; i < num; i++) {
1776 struct mvneta_tx_desc *tx_desc = txq->descs +
1778 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1781 bytes_compl += skb->len;
1785 mvneta_txq_inc_get(txq);
1787 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1788 dma_unmap_single(pp->dev->dev.parent,
1789 tx_desc->buf_phys_addr,
1790 tx_desc->data_size, DMA_TO_DEVICE);
1793 dev_kfree_skb_any(skb);
1796 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1799 /* Handle end of transmission */
1800 static void mvneta_txq_done(struct mvneta_port *pp,
1801 struct mvneta_tx_queue *txq)
1803 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1806 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1810 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1812 txq->count -= tx_done;
1814 if (netif_tx_queue_stopped(nq)) {
1815 if (txq->count <= txq->tx_wake_threshold)
1816 netif_tx_wake_queue(nq);
1820 void *mvneta_frag_alloc(unsigned int frag_size)
1822 if (likely(frag_size <= PAGE_SIZE))
1823 return netdev_alloc_frag(frag_size);
1825 return kmalloc(frag_size, GFP_ATOMIC);
1827 EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
1829 void mvneta_frag_free(unsigned int frag_size, void *data)
1831 if (likely(frag_size <= PAGE_SIZE))
1832 skb_free_frag(data);
1836 EXPORT_SYMBOL_GPL(mvneta_frag_free);
1838 /* Refill processing for SW buffer management */
1839 static int mvneta_rx_refill(struct mvneta_port *pp,
1840 struct mvneta_rx_desc *rx_desc,
1841 struct mvneta_rx_queue *rxq)
1844 dma_addr_t phys_addr;
1847 data = mvneta_frag_alloc(pp->frag_size);
1851 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1852 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1854 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1855 mvneta_frag_free(pp->frag_size, data);
1859 phys_addr += pp->rx_offset_correction;
1860 mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
1864 /* Handle tx checksum */
1865 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1867 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1869 __be16 l3_proto = vlan_get_protocol(skb);
1872 if (l3_proto == htons(ETH_P_IP)) {
1873 struct iphdr *ip4h = ip_hdr(skb);
1875 /* Calculate IPv4 checksum and L4 checksum */
1876 ip_hdr_len = ip4h->ihl;
1877 l4_proto = ip4h->protocol;
1878 } else if (l3_proto == htons(ETH_P_IPV6)) {
1879 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1881 /* Read l4_protocol from one of IPv6 extra headers */
1882 if (skb_network_header_len(skb) > 0)
1883 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1884 l4_proto = ip6h->nexthdr;
1886 return MVNETA_TX_L4_CSUM_NOT;
1888 return mvneta_txq_desc_csum(skb_network_offset(skb),
1889 l3_proto, ip_hdr_len, l4_proto);
1892 return MVNETA_TX_L4_CSUM_NOT;
1895 /* Drop packets received by the RXQ and free buffers */
1896 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1897 struct mvneta_rx_queue *rxq)
1901 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1903 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1906 for (i = 0; i < rx_done; i++) {
1907 struct mvneta_rx_desc *rx_desc =
1908 mvneta_rxq_next_desc_get(rxq);
1909 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1910 struct mvneta_bm_pool *bm_pool;
1912 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1913 /* Return dropped buffer to the pool */
1914 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1915 rx_desc->buf_phys_addr);
1920 for (i = 0; i < rxq->size; i++) {
1921 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1922 void *data = rxq->buf_virt_addr[i];
1924 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1925 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1926 mvneta_frag_free(pp->frag_size, data);
1930 /* Main rx processing when using software buffer management */
1931 static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
1932 struct mvneta_rx_queue *rxq)
1934 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1935 struct net_device *dev = pp->dev;
1940 /* Get number of received packets */
1941 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1943 if (rx_todo > rx_done)
1948 /* Fairness NAPI loop */
1949 while (rx_done < rx_todo) {
1950 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1951 struct sk_buff *skb;
1952 unsigned char *data;
1953 dma_addr_t phys_addr;
1954 u32 rx_status, frag_size;
1955 int rx_bytes, err, index;
1958 rx_status = rx_desc->status;
1959 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1960 index = rx_desc - rxq->descs;
1961 data = rxq->buf_virt_addr[index];
1962 phys_addr = rx_desc->buf_phys_addr - pp->rx_offset_correction;
1964 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1965 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1966 mvneta_rx_error(pp, rx_desc);
1968 dev->stats.rx_errors++;
1969 /* leave the descriptor untouched */
1973 if (rx_bytes <= rx_copybreak) {
1974 /* better copy a small frame and not unmap the DMA region */
1975 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1977 goto err_drop_frame;
1979 dma_sync_single_range_for_cpu(dev->dev.parent,
1981 MVNETA_MH_SIZE + NET_SKB_PAD,
1984 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
1987 skb->protocol = eth_type_trans(skb, dev);
1988 mvneta_rx_csum(pp, rx_status, skb);
1989 napi_gro_receive(&port->napi, skb);
1992 rcvd_bytes += rx_bytes;
1994 /* leave the descriptor and buffer untouched */
1998 /* Refill processing */
1999 err = mvneta_rx_refill(pp, rx_desc, rxq);
2001 netdev_err(dev, "Linux processing - Can't refill\n");
2003 goto err_drop_frame;
2006 frag_size = pp->frag_size;
2008 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2010 /* After refill old buffer has to be unmapped regardless
2011 * the skb is successfully built or not.
2013 dma_unmap_single(dev->dev.parent, phys_addr,
2014 MVNETA_RX_BUF_SIZE(pp->pkt_size),
2018 goto err_drop_frame;
2021 rcvd_bytes += rx_bytes;
2023 /* Linux processing */
2024 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2025 skb_put(skb, rx_bytes);
2027 skb->protocol = eth_type_trans(skb, dev);
2029 mvneta_rx_csum(pp, rx_status, skb);
2031 napi_gro_receive(&port->napi, skb);
2035 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2037 u64_stats_update_begin(&stats->syncp);
2038 stats->rx_packets += rcvd_pkts;
2039 stats->rx_bytes += rcvd_bytes;
2040 u64_stats_update_end(&stats->syncp);
2043 /* Update rxq management counters */
2044 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2049 /* Main rx processing when using hardware buffer management */
2050 static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
2051 struct mvneta_rx_queue *rxq)
2053 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2054 struct net_device *dev = pp->dev;
2059 /* Get number of received packets */
2060 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2062 if (rx_todo > rx_done)
2067 /* Fairness NAPI loop */
2068 while (rx_done < rx_todo) {
2069 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2070 struct mvneta_bm_pool *bm_pool = NULL;
2071 struct sk_buff *skb;
2072 unsigned char *data;
2073 dma_addr_t phys_addr;
2074 u32 rx_status, frag_size;
2079 rx_status = rx_desc->status;
2080 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2081 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2082 phys_addr = rx_desc->buf_phys_addr;
2083 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2084 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2086 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2087 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2088 err_drop_frame_ret_pool:
2089 /* Return the buffer to the pool */
2090 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2091 rx_desc->buf_phys_addr);
2093 dev->stats.rx_errors++;
2094 mvneta_rx_error(pp, rx_desc);
2095 /* leave the descriptor untouched */
2099 if (rx_bytes <= rx_copybreak) {
2100 /* better copy a small frame and not unmap the DMA region */
2101 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2103 goto err_drop_frame_ret_pool;
2105 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2106 rx_desc->buf_phys_addr,
2107 MVNETA_MH_SIZE + NET_SKB_PAD,
2110 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2113 skb->protocol = eth_type_trans(skb, dev);
2114 mvneta_rx_csum(pp, rx_status, skb);
2115 napi_gro_receive(&port->napi, skb);
2118 rcvd_bytes += rx_bytes;
2120 /* Return the buffer to the pool */
2121 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2122 rx_desc->buf_phys_addr);
2124 /* leave the descriptor and buffer untouched */
2128 /* Refill processing */
2129 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2131 netdev_err(dev, "Linux processing - Can't refill\n");
2133 goto err_drop_frame_ret_pool;
2136 frag_size = bm_pool->hwbm_pool.frag_size;
2138 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2140 /* After refill old buffer has to be unmapped regardless
2141 * the skb is successfully built or not.
2143 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2144 bm_pool->buf_size, DMA_FROM_DEVICE);
2146 goto err_drop_frame;
2149 rcvd_bytes += rx_bytes;
2151 /* Linux processing */
2152 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2153 skb_put(skb, rx_bytes);
2155 skb->protocol = eth_type_trans(skb, dev);
2157 mvneta_rx_csum(pp, rx_status, skb);
2159 napi_gro_receive(&port->napi, skb);
2163 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2165 u64_stats_update_begin(&stats->syncp);
2166 stats->rx_packets += rcvd_pkts;
2167 stats->rx_bytes += rcvd_bytes;
2168 u64_stats_update_end(&stats->syncp);
2171 /* Update rxq management counters */
2172 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2178 mvneta_tso_put_hdr(struct sk_buff *skb,
2179 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2181 struct mvneta_tx_desc *tx_desc;
2182 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2184 txq->tx_skb[txq->txq_put_index] = NULL;
2185 tx_desc = mvneta_txq_next_desc_get(txq);
2186 tx_desc->data_size = hdr_len;
2187 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2188 tx_desc->command |= MVNETA_TXD_F_DESC;
2189 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2190 txq->txq_put_index * TSO_HEADER_SIZE;
2191 mvneta_txq_inc_put(txq);
2195 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2196 struct sk_buff *skb, char *data, int size,
2197 bool last_tcp, bool is_last)
2199 struct mvneta_tx_desc *tx_desc;
2201 tx_desc = mvneta_txq_next_desc_get(txq);
2202 tx_desc->data_size = size;
2203 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2204 size, DMA_TO_DEVICE);
2205 if (unlikely(dma_mapping_error(dev->dev.parent,
2206 tx_desc->buf_phys_addr))) {
2207 mvneta_txq_desc_put(txq);
2211 tx_desc->command = 0;
2212 txq->tx_skb[txq->txq_put_index] = NULL;
2215 /* last descriptor in the TCP packet */
2216 tx_desc->command = MVNETA_TXD_L_DESC;
2218 /* last descriptor in SKB */
2220 txq->tx_skb[txq->txq_put_index] = skb;
2222 mvneta_txq_inc_put(txq);
2226 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2227 struct mvneta_tx_queue *txq)
2229 int total_len, data_left;
2231 struct mvneta_port *pp = netdev_priv(dev);
2233 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2236 /* Count needed descriptors */
2237 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2240 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2241 pr_info("*** Is this even possible???!?!?\n");
2245 /* Initialize the TSO handler, and prepare the first payload */
2246 tso_start(skb, &tso);
2248 total_len = skb->len - hdr_len;
2249 while (total_len > 0) {
2252 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2253 total_len -= data_left;
2256 /* prepare packet headers: MAC + IP + TCP */
2257 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2258 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2260 mvneta_tso_put_hdr(skb, pp, txq);
2262 while (data_left > 0) {
2266 size = min_t(int, tso.size, data_left);
2268 if (mvneta_tso_put_data(dev, txq, skb,
2275 tso_build_data(skb, &tso, size);
2282 /* Release all used data descriptors; header descriptors must not
2285 for (i = desc_count - 1; i >= 0; i--) {
2286 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2287 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2288 dma_unmap_single(pp->dev->dev.parent,
2289 tx_desc->buf_phys_addr,
2292 mvneta_txq_desc_put(txq);
2297 /* Handle tx fragmentation processing */
2298 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2299 struct mvneta_tx_queue *txq)
2301 struct mvneta_tx_desc *tx_desc;
2302 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2304 for (i = 0; i < nr_frags; i++) {
2305 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2306 void *addr = page_address(frag->page.p) + frag->page_offset;
2308 tx_desc = mvneta_txq_next_desc_get(txq);
2309 tx_desc->data_size = frag->size;
2311 tx_desc->buf_phys_addr =
2312 dma_map_single(pp->dev->dev.parent, addr,
2313 tx_desc->data_size, DMA_TO_DEVICE);
2315 if (dma_mapping_error(pp->dev->dev.parent,
2316 tx_desc->buf_phys_addr)) {
2317 mvneta_txq_desc_put(txq);
2321 if (i == nr_frags - 1) {
2322 /* Last descriptor */
2323 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2324 txq->tx_skb[txq->txq_put_index] = skb;
2326 /* Descriptor in the middle: Not First, Not Last */
2327 tx_desc->command = 0;
2328 txq->tx_skb[txq->txq_put_index] = NULL;
2330 mvneta_txq_inc_put(txq);
2336 /* Release all descriptors that were used to map fragments of
2337 * this packet, as well as the corresponding DMA mappings
2339 for (i = i - 1; i >= 0; i--) {
2340 tx_desc = txq->descs + i;
2341 dma_unmap_single(pp->dev->dev.parent,
2342 tx_desc->buf_phys_addr,
2345 mvneta_txq_desc_put(txq);
2351 /* Main tx processing */
2352 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2354 struct mvneta_port *pp = netdev_priv(dev);
2355 u16 txq_id = skb_get_queue_mapping(skb);
2356 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2357 struct mvneta_tx_desc *tx_desc;
2362 if (!netif_running(dev))
2365 if (skb_is_gso(skb)) {
2366 frags = mvneta_tx_tso(skb, dev, txq);
2370 frags = skb_shinfo(skb)->nr_frags + 1;
2372 /* Get a descriptor for the first part of the packet */
2373 tx_desc = mvneta_txq_next_desc_get(txq);
2375 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2377 tx_desc->data_size = skb_headlen(skb);
2379 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2382 if (unlikely(dma_mapping_error(dev->dev.parent,
2383 tx_desc->buf_phys_addr))) {
2384 mvneta_txq_desc_put(txq);
2390 /* First and Last descriptor */
2391 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2392 tx_desc->command = tx_cmd;
2393 txq->tx_skb[txq->txq_put_index] = skb;
2394 mvneta_txq_inc_put(txq);
2396 /* First but not Last */
2397 tx_cmd |= MVNETA_TXD_F_DESC;
2398 txq->tx_skb[txq->txq_put_index] = NULL;
2399 mvneta_txq_inc_put(txq);
2400 tx_desc->command = tx_cmd;
2401 /* Continue with other skb fragments */
2402 if (mvneta_tx_frag_process(pp, skb, txq)) {
2403 dma_unmap_single(dev->dev.parent,
2404 tx_desc->buf_phys_addr,
2407 mvneta_txq_desc_put(txq);
2415 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2416 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2418 netdev_tx_sent_queue(nq, len);
2420 txq->count += frags;
2421 if (txq->count >= txq->tx_stop_threshold)
2422 netif_tx_stop_queue(nq);
2424 if (!skb->xmit_more || netif_xmit_stopped(nq) ||
2425 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2426 mvneta_txq_pend_desc_add(pp, txq, frags);
2428 txq->pending += frags;
2430 u64_stats_update_begin(&stats->syncp);
2431 stats->tx_packets++;
2432 stats->tx_bytes += len;
2433 u64_stats_update_end(&stats->syncp);
2435 dev->stats.tx_dropped++;
2436 dev_kfree_skb_any(skb);
2439 return NETDEV_TX_OK;
2443 /* Free tx resources, when resetting a port */
2444 static void mvneta_txq_done_force(struct mvneta_port *pp,
2445 struct mvneta_tx_queue *txq)
2448 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2449 int tx_done = txq->count;
2451 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2455 txq->txq_put_index = 0;
2456 txq->txq_get_index = 0;
2459 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2460 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2462 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2464 struct mvneta_tx_queue *txq;
2465 struct netdev_queue *nq;
2467 while (cause_tx_done) {
2468 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2470 nq = netdev_get_tx_queue(pp->dev, txq->id);
2471 __netif_tx_lock(nq, smp_processor_id());
2474 mvneta_txq_done(pp, txq);
2476 __netif_tx_unlock(nq);
2477 cause_tx_done &= ~((1 << txq->id));
2481 /* Compute crc8 of the specified address, using a unique algorithm ,
2482 * according to hw spec, different than generic crc8 algorithm
2484 static int mvneta_addr_crc(unsigned char *addr)
2489 for (i = 0; i < ETH_ALEN; i++) {
2492 crc = (crc ^ addr[i]) << 8;
2493 for (j = 7; j >= 0; j--) {
2494 if (crc & (0x100 << j))
2502 /* This method controls the net device special MAC multicast support.
2503 * The Special Multicast Table for MAC addresses supports MAC of the form
2504 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2505 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2506 * Table entries in the DA-Filter table. This method set the Special
2507 * Multicast Table appropriate entry.
2509 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2510 unsigned char last_byte,
2513 unsigned int smc_table_reg;
2514 unsigned int tbl_offset;
2515 unsigned int reg_offset;
2517 /* Register offset from SMC table base */
2518 tbl_offset = (last_byte / 4);
2519 /* Entry offset within the above reg */
2520 reg_offset = last_byte % 4;
2522 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2526 smc_table_reg &= ~(0xff << (8 * reg_offset));
2528 smc_table_reg &= ~(0xff << (8 * reg_offset));
2529 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2532 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2536 /* This method controls the network device Other MAC multicast support.
2537 * The Other Multicast Table is used for multicast of another type.
2538 * A CRC-8 is used as an index to the Other Multicast Table entries
2539 * in the DA-Filter table.
2540 * The method gets the CRC-8 value from the calling routine and
2541 * sets the Other Multicast Table appropriate entry according to the
2544 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2548 unsigned int omc_table_reg;
2549 unsigned int tbl_offset;
2550 unsigned int reg_offset;
2552 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2553 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2555 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2558 /* Clear accepts frame bit at specified Other DA table entry */
2559 omc_table_reg &= ~(0xff << (8 * reg_offset));
2561 omc_table_reg &= ~(0xff << (8 * reg_offset));
2562 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2565 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2568 /* The network device supports multicast using two tables:
2569 * 1) Special Multicast Table for MAC addresses of the form
2570 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2571 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2572 * Table entries in the DA-Filter table.
2573 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2574 * is used as an index to the Other Multicast Table entries in the
2577 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2580 unsigned char crc_result = 0;
2582 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2583 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2587 crc_result = mvneta_addr_crc(p_addr);
2589 if (pp->mcast_count[crc_result] == 0) {
2590 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2595 pp->mcast_count[crc_result]--;
2596 if (pp->mcast_count[crc_result] != 0) {
2597 netdev_info(pp->dev,
2598 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2599 pp->mcast_count[crc_result], crc_result);
2603 pp->mcast_count[crc_result]++;
2605 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2610 /* Configure Fitering mode of Ethernet port */
2611 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2614 u32 port_cfg_reg, val;
2616 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2618 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2620 /* Set / Clear UPM bit in port configuration register */
2622 /* Accept all Unicast addresses */
2623 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2624 val |= MVNETA_FORCE_UNI;
2625 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2626 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2628 /* Reject all Unicast addresses */
2629 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2630 val &= ~MVNETA_FORCE_UNI;
2633 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2634 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2637 /* register unicast and multicast addresses */
2638 static void mvneta_set_rx_mode(struct net_device *dev)
2640 struct mvneta_port *pp = netdev_priv(dev);
2641 struct netdev_hw_addr *ha;
2643 if (dev->flags & IFF_PROMISC) {
2644 /* Accept all: Multicast + Unicast */
2645 mvneta_rx_unicast_promisc_set(pp, 1);
2646 mvneta_set_ucast_table(pp, pp->rxq_def);
2647 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2648 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2650 /* Accept single Unicast */
2651 mvneta_rx_unicast_promisc_set(pp, 0);
2652 mvneta_set_ucast_table(pp, -1);
2653 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2655 if (dev->flags & IFF_ALLMULTI) {
2656 /* Accept all multicast */
2657 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2658 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2660 /* Accept only initialized multicast */
2661 mvneta_set_special_mcast_table(pp, -1);
2662 mvneta_set_other_mcast_table(pp, -1);
2664 if (!netdev_mc_empty(dev)) {
2665 netdev_for_each_mc_addr(ha, dev) {
2666 mvneta_mcast_addr_set(pp, ha->addr,
2674 /* Interrupt handling - the callback for request_irq() */
2675 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2677 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2679 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2680 napi_schedule(&pp->napi);
2685 /* Interrupt handling - the callback for request_percpu_irq() */
2686 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
2688 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2690 disable_percpu_irq(port->pp->dev->irq);
2691 napi_schedule(&port->napi);
2696 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2697 struct phy_device *phy)
2699 struct fixed_phy_status status;
2700 struct fixed_phy_status changed = {};
2701 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2703 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2704 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2705 status.speed = SPEED_1000;
2706 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2707 status.speed = SPEED_100;
2709 status.speed = SPEED_10;
2710 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2714 fixed_phy_update_state(phy, &status, &changed);
2719 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2720 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2721 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2722 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2723 * Each CPU has its own causeRxTx register
2725 static int mvneta_poll(struct napi_struct *napi, int budget)
2730 struct mvneta_port *pp = netdev_priv(napi->dev);
2731 struct net_device *ndev = pp->dev;
2732 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2734 if (!netif_running(pp->dev)) {
2735 napi_complete(napi);
2739 /* Read cause register */
2740 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2741 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2742 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2744 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2745 if (pp->use_inband_status && (cause_misc &
2746 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2747 MVNETA_CAUSE_LINK_CHANGE |
2748 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2749 mvneta_fixed_link_update(pp, ndev->phydev);
2753 /* Release Tx descriptors */
2754 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2755 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2756 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2759 /* For the case where the last mvneta_poll did not process all
2762 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
2765 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2767 rx_queue = rx_queue - 1;
2769 rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
2771 rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
2774 if (rx_done < budget) {
2776 napi_complete_done(napi, rx_done);
2778 if (pp->neta_armada3700) {
2779 unsigned long flags;
2781 local_irq_save(flags);
2782 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2783 MVNETA_RX_INTR_MASK(rxq_number) |
2784 MVNETA_TX_INTR_MASK(txq_number) |
2785 MVNETA_MISCINTR_INTR_MASK);
2786 local_irq_restore(flags);
2788 enable_percpu_irq(pp->dev->irq, 0);
2792 if (pp->neta_armada3700)
2793 pp->cause_rx_tx = cause_rx_tx;
2795 port->cause_rx_tx = cause_rx_tx;
2800 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2801 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2806 for (i = 0; i < num; i++) {
2807 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2808 if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) {
2809 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2810 __func__, rxq->id, i, num);
2815 /* Add this number of RX descriptors as non occupied (ready to
2818 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2823 /* Free all packets pending transmit from all TXQs and reset TX port */
2824 static void mvneta_tx_reset(struct mvneta_port *pp)
2828 /* free the skb's in the tx ring */
2829 for (queue = 0; queue < txq_number; queue++)
2830 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2832 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2833 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2836 static void mvneta_rx_reset(struct mvneta_port *pp)
2838 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2839 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2842 /* Rx/Tx queue initialization/cleanup methods */
2844 /* Create a specified RX queue */
2845 static int mvneta_rxq_init(struct mvneta_port *pp,
2846 struct mvneta_rx_queue *rxq)
2849 rxq->size = pp->rx_ring_size;
2851 /* Allocate memory for RX descriptors */
2852 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2853 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2854 &rxq->descs_phys, GFP_KERNEL);
2858 rxq->last_desc = rxq->size - 1;
2860 /* Set Rx descriptors queue starting address */
2861 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2862 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2865 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
2867 /* Set coalescing pkts and time */
2868 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2869 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2872 /* Fill RXQ with buffers from RX pool */
2873 mvneta_rxq_buf_size_set(pp, rxq,
2874 MVNETA_RX_BUF_SIZE(pp->pkt_size));
2875 mvneta_rxq_bm_disable(pp, rxq);
2876 mvneta_rxq_fill(pp, rxq, rxq->size);
2878 mvneta_rxq_bm_enable(pp, rxq);
2879 mvneta_rxq_long_pool_set(pp, rxq);
2880 mvneta_rxq_short_pool_set(pp, rxq);
2881 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
2887 /* Cleanup Rx queue */
2888 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2889 struct mvneta_rx_queue *rxq)
2891 mvneta_rxq_drop_pkts(pp, rxq);
2894 dma_free_coherent(pp->dev->dev.parent,
2895 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2901 rxq->next_desc_to_proc = 0;
2902 rxq->descs_phys = 0;
2905 /* Create and initialize a tx queue */
2906 static int mvneta_txq_init(struct mvneta_port *pp,
2907 struct mvneta_tx_queue *txq)
2911 txq->size = pp->tx_ring_size;
2913 /* A queue must always have room for at least one skb.
2914 * Therefore, stop the queue when the free entries reaches
2915 * the maximum number of descriptors per skb.
2917 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2918 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2921 /* Allocate memory for TX descriptors */
2922 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2923 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2924 &txq->descs_phys, GFP_KERNEL);
2928 txq->last_desc = txq->size - 1;
2930 /* Set maximum bandwidth for enabled TXQs */
2931 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2932 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2934 /* Set Tx descriptors queue starting address */
2935 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2936 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2938 txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb),
2941 dma_free_coherent(pp->dev->dev.parent,
2942 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2943 txq->descs, txq->descs_phys);
2947 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2948 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2949 txq->size * TSO_HEADER_SIZE,
2950 &txq->tso_hdrs_phys, GFP_KERNEL);
2951 if (!txq->tso_hdrs) {
2953 dma_free_coherent(pp->dev->dev.parent,
2954 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2955 txq->descs, txq->descs_phys);
2958 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2960 /* Setup XPS mapping */
2961 if (pp->neta_armada3700)
2963 else if (txq_number > 1)
2964 cpu = txq->id % num_present_cpus();
2966 cpu = pp->rxq_def % num_present_cpus();
2967 cpumask_set_cpu(cpu, &txq->affinity_mask);
2968 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2973 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2974 static void mvneta_txq_deinit(struct mvneta_port *pp,
2975 struct mvneta_tx_queue *txq)
2977 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2982 dma_free_coherent(pp->dev->dev.parent,
2983 txq->size * TSO_HEADER_SIZE,
2984 txq->tso_hdrs, txq->tso_hdrs_phys);
2986 dma_free_coherent(pp->dev->dev.parent,
2987 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2988 txq->descs, txq->descs_phys);
2990 netdev_tx_reset_queue(nq);
2994 txq->next_desc_to_proc = 0;
2995 txq->descs_phys = 0;
2997 /* Set minimum bandwidth for disabled TXQs */
2998 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2999 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3001 /* Set Tx descriptors queue starting address and size */
3002 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3003 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3006 /* Cleanup all Tx queues */
3007 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3011 for (queue = 0; queue < txq_number; queue++)
3012 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3015 /* Cleanup all Rx queues */
3016 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3020 for (queue = 0; queue < rxq_number; queue++)
3021 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3025 /* Init all Rx queues */
3026 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3030 for (queue = 0; queue < rxq_number; queue++) {
3031 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3034 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3036 mvneta_cleanup_rxqs(pp);
3044 /* Init all tx queues */
3045 static int mvneta_setup_txqs(struct mvneta_port *pp)
3049 for (queue = 0; queue < txq_number; queue++) {
3050 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3052 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3054 mvneta_cleanup_txqs(pp);
3062 static void mvneta_start_dev(struct mvneta_port *pp)
3065 struct net_device *ndev = pp->dev;
3067 mvneta_max_rx_size_set(pp, pp->pkt_size);
3068 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3070 /* start the Rx/Tx activity */
3071 mvneta_port_enable(pp);
3073 if (!pp->neta_armada3700) {
3074 /* Enable polling on the port */
3075 for_each_online_cpu(cpu) {
3076 struct mvneta_pcpu_port *port =
3077 per_cpu_ptr(pp->ports, cpu);
3079 napi_enable(&port->napi);
3082 napi_enable(&pp->napi);
3085 /* Unmask interrupts. It has to be done from each CPU */
3086 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3088 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3089 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3090 MVNETA_CAUSE_LINK_CHANGE |
3091 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3093 phy_start(ndev->phydev);
3094 netif_tx_start_all_queues(pp->dev);
3097 static void mvneta_stop_dev(struct mvneta_port *pp)
3100 struct net_device *ndev = pp->dev;
3102 phy_stop(ndev->phydev);
3104 if (!pp->neta_armada3700) {
3105 for_each_online_cpu(cpu) {
3106 struct mvneta_pcpu_port *port =
3107 per_cpu_ptr(pp->ports, cpu);
3109 napi_disable(&port->napi);
3112 napi_disable(&pp->napi);
3115 netif_carrier_off(pp->dev);
3117 mvneta_port_down(pp);
3118 netif_tx_stop_all_queues(pp->dev);
3120 /* Stop the port activity */
3121 mvneta_port_disable(pp);
3123 /* Clear all ethernet port interrupts */
3124 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3126 /* Mask all ethernet port interrupts */
3127 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3129 mvneta_tx_reset(pp);
3130 mvneta_rx_reset(pp);
3133 static void mvneta_percpu_enable(void *arg)
3135 struct mvneta_port *pp = arg;
3137 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3140 static void mvneta_percpu_disable(void *arg)
3142 struct mvneta_port *pp = arg;
3144 disable_percpu_irq(pp->dev->irq);
3147 /* Change the device mtu */
3148 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3150 struct mvneta_port *pp = netdev_priv(dev);
3153 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3154 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3155 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3156 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3161 if (!netif_running(dev)) {
3163 mvneta_bm_update_mtu(pp, mtu);
3165 netdev_update_features(dev);
3169 /* The interface is running, so we have to force a
3170 * reallocation of the queues
3172 mvneta_stop_dev(pp);
3173 on_each_cpu(mvneta_percpu_disable, pp, true);
3175 mvneta_cleanup_txqs(pp);
3176 mvneta_cleanup_rxqs(pp);
3179 mvneta_bm_update_mtu(pp, mtu);
3181 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3182 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3183 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3185 ret = mvneta_setup_rxqs(pp);
3187 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3191 ret = mvneta_setup_txqs(pp);
3193 netdev_err(dev, "unable to setup txqs after MTU change\n");
3197 on_each_cpu(mvneta_percpu_enable, pp, true);
3198 mvneta_start_dev(pp);
3200 netdev_update_features(dev);
3205 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3206 netdev_features_t features)
3208 struct mvneta_port *pp = netdev_priv(dev);
3210 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3211 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3213 "Disable IP checksum for MTU greater than %dB\n",
3220 /* Get mac address */
3221 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3223 u32 mac_addr_l, mac_addr_h;
3225 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3226 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3227 addr[0] = (mac_addr_h >> 24) & 0xFF;
3228 addr[1] = (mac_addr_h >> 16) & 0xFF;
3229 addr[2] = (mac_addr_h >> 8) & 0xFF;
3230 addr[3] = mac_addr_h & 0xFF;
3231 addr[4] = (mac_addr_l >> 8) & 0xFF;
3232 addr[5] = mac_addr_l & 0xFF;
3235 /* Handle setting mac address */
3236 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3238 struct mvneta_port *pp = netdev_priv(dev);
3239 struct sockaddr *sockaddr = addr;
3242 ret = eth_prepare_mac_addr_change(dev, addr);
3245 /* Remove previous address table entry */
3246 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3248 /* Set new addr in hw */
3249 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3251 eth_commit_mac_addr_change(dev, addr);
3255 static void mvneta_adjust_link(struct net_device *ndev)
3257 struct mvneta_port *pp = netdev_priv(ndev);
3258 struct phy_device *phydev = ndev->phydev;
3259 int status_change = 0;
3262 if ((pp->speed != phydev->speed) ||
3263 (pp->duplex != phydev->duplex)) {
3266 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3267 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3268 MVNETA_GMAC_CONFIG_GMII_SPEED |
3269 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3272 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3274 if (phydev->speed == SPEED_1000)
3275 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3276 else if (phydev->speed == SPEED_100)
3277 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3279 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3281 pp->duplex = phydev->duplex;
3282 pp->speed = phydev->speed;
3286 if (phydev->link != pp->link) {
3287 if (!phydev->link) {
3292 pp->link = phydev->link;
3296 if (status_change) {
3298 if (!pp->use_inband_status) {
3299 u32 val = mvreg_read(pp,
3300 MVNETA_GMAC_AUTONEG_CONFIG);
3301 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3302 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3303 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3308 if (!pp->use_inband_status) {
3309 u32 val = mvreg_read(pp,
3310 MVNETA_GMAC_AUTONEG_CONFIG);
3311 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3312 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3313 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3316 mvneta_port_down(pp);
3318 phy_print_status(phydev);
3322 static int mvneta_mdio_probe(struct mvneta_port *pp)
3324 struct phy_device *phy_dev;
3325 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
3327 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
3330 netdev_err(pp->dev, "could not find the PHY\n");
3334 phy_ethtool_get_wol(phy_dev, &wol);
3335 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
3337 phy_dev->supported &= PHY_GBIT_FEATURES;
3338 phy_dev->advertising = phy_dev->supported;
3347 static void mvneta_mdio_remove(struct mvneta_port *pp)
3349 struct net_device *ndev = pp->dev;
3351 phy_disconnect(ndev->phydev);
3354 /* Electing a CPU must be done in an atomic way: it should be done
3355 * after or before the removal/insertion of a CPU and this function is
3358 static void mvneta_percpu_elect(struct mvneta_port *pp)
3360 int elected_cpu = 0, max_cpu, cpu, i = 0;
3362 /* Use the cpu associated to the rxq when it is online, in all
3363 * the other cases, use the cpu 0 which can't be offline.
3365 if (pp->rxq_def < nr_cpu_ids && cpu_online(pp->rxq_def))
3366 elected_cpu = pp->rxq_def;
3368 max_cpu = num_present_cpus();
3370 for_each_online_cpu(cpu) {
3371 int rxq_map = 0, txq_map = 0;
3374 for (rxq = 0; rxq < rxq_number; rxq++)
3375 if ((rxq % max_cpu) == cpu)
3376 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3378 if (cpu == elected_cpu)
3379 /* Map the default receive queue queue to the
3382 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3384 /* We update the TX queue map only if we have one
3385 * queue. In this case we associate the TX queue to
3386 * the CPU bound to the default RX queue
3388 if (txq_number == 1)
3389 txq_map = (cpu == elected_cpu) ?
3390 MVNETA_CPU_TXQ_ACCESS(0) : 0;
3392 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3393 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3395 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3397 /* Update the interrupt mask on each CPU according the
3400 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3407 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3410 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3412 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3414 /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts
3415 * are routed to CPU 0, so we don't need all the cpu-hotplug support
3417 if (pp->neta_armada3700)
3420 spin_lock(&pp->lock);
3422 * Configuring the driver for a new CPU while the driver is
3423 * stopping is racy, so just avoid it.
3425 if (pp->is_stopped) {
3426 spin_unlock(&pp->lock);
3429 netif_tx_stop_all_queues(pp->dev);
3432 * We have to synchronise on tha napi of each CPU except the one
3433 * just being woken up
3435 for_each_online_cpu(other_cpu) {
3436 if (other_cpu != cpu) {
3437 struct mvneta_pcpu_port *other_port =
3438 per_cpu_ptr(pp->ports, other_cpu);
3440 napi_synchronize(&other_port->napi);
3444 /* Mask all ethernet port interrupts */
3445 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3446 napi_enable(&port->napi);
3449 * Enable per-CPU interrupts on the CPU that is
3452 mvneta_percpu_enable(pp);
3455 * Enable per-CPU interrupt on the one CPU we care
3458 mvneta_percpu_elect(pp);
3460 /* Unmask all ethernet port interrupts */
3461 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3462 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3463 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3464 MVNETA_CAUSE_LINK_CHANGE |
3465 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3466 netif_tx_start_all_queues(pp->dev);
3467 spin_unlock(&pp->lock);
3471 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3473 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3475 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3478 * Thanks to this lock we are sure that any pending cpu election is
3481 spin_lock(&pp->lock);
3482 /* Mask all ethernet port interrupts */
3483 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3484 spin_unlock(&pp->lock);
3486 napi_synchronize(&port->napi);
3487 napi_disable(&port->napi);
3488 /* Disable per-CPU interrupts on the CPU that is brought down. */
3489 mvneta_percpu_disable(pp);
3493 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3495 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3498 /* Check if a new CPU must be elected now this on is down */
3499 spin_lock(&pp->lock);
3500 mvneta_percpu_elect(pp);
3501 spin_unlock(&pp->lock);
3502 /* Unmask all ethernet port interrupts */
3503 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3504 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3505 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3506 MVNETA_CAUSE_LINK_CHANGE |
3507 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3508 netif_tx_start_all_queues(pp->dev);
3512 static int mvneta_open(struct net_device *dev)
3514 struct mvneta_port *pp = netdev_priv(dev);
3517 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3518 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3519 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3521 ret = mvneta_setup_rxqs(pp);
3525 ret = mvneta_setup_txqs(pp);
3527 goto err_cleanup_rxqs;
3529 /* Connect to port interrupt line */
3530 if (pp->neta_armada3700)
3531 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
3534 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
3535 dev->name, pp->ports);
3537 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3538 goto err_cleanup_txqs;
3541 if (!pp->neta_armada3700) {
3542 /* Enable per-CPU interrupt on all the CPU to handle our RX
3545 on_each_cpu(mvneta_percpu_enable, pp, true);
3547 pp->is_stopped = false;
3548 /* Register a CPU notifier to handle the case where our CPU
3549 * might be taken offline.
3551 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3556 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3559 goto err_free_online_hp;
3562 /* In default link is down */
3563 netif_carrier_off(pp->dev);
3565 ret = mvneta_mdio_probe(pp);
3567 netdev_err(dev, "cannot probe MDIO bus\n");
3568 goto err_free_dead_hp;
3571 mvneta_start_dev(pp);
3576 if (!pp->neta_armada3700)
3577 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3580 if (!pp->neta_armada3700)
3581 cpuhp_state_remove_instance_nocalls(online_hpstate,
3584 if (pp->neta_armada3700) {
3585 free_irq(pp->dev->irq, pp);
3587 on_each_cpu(mvneta_percpu_disable, pp, true);
3588 free_percpu_irq(pp->dev->irq, pp->ports);
3591 mvneta_cleanup_txqs(pp);
3593 mvneta_cleanup_rxqs(pp);
3597 /* Stop the port, free port interrupt line */
3598 static int mvneta_stop(struct net_device *dev)
3600 struct mvneta_port *pp = netdev_priv(dev);
3602 if (!pp->neta_armada3700) {
3603 /* Inform that we are stopping so we don't want to setup the
3604 * driver for new CPUs in the notifiers. The code of the
3605 * notifier for CPU online is protected by the same spinlock,
3606 * so when we get the lock, the notifer work is done.
3608 spin_lock(&pp->lock);
3609 pp->is_stopped = true;
3610 spin_unlock(&pp->lock);
3612 mvneta_stop_dev(pp);
3613 mvneta_mdio_remove(pp);
3615 cpuhp_state_remove_instance_nocalls(online_hpstate,
3617 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3619 on_each_cpu(mvneta_percpu_disable, pp, true);
3620 free_percpu_irq(dev->irq, pp->ports);
3622 mvneta_stop_dev(pp);
3623 mvneta_mdio_remove(pp);
3624 free_irq(dev->irq, pp);
3627 mvneta_cleanup_rxqs(pp);
3628 mvneta_cleanup_txqs(pp);
3633 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3638 return phy_mii_ioctl(dev->phydev, ifr, cmd);
3641 /* Ethtool methods */
3643 /* Set link ksettings (phy address, speed) for ethtools */
3645 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3646 const struct ethtool_link_ksettings *cmd)
3648 struct mvneta_port *pp = netdev_priv(ndev);
3649 struct phy_device *phydev = ndev->phydev;
3654 if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
3657 mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE);
3659 if (cmd->base.autoneg == AUTONEG_DISABLE) {
3660 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3661 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3662 MVNETA_GMAC_CONFIG_GMII_SPEED |
3663 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3666 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3668 if (phydev->speed == SPEED_1000)
3669 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3670 else if (phydev->speed == SPEED_100)
3671 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3673 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3676 pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE);
3677 netdev_info(pp->dev, "autoneg status set to %i\n",
3678 pp->use_inband_status);
3680 if (netif_running(ndev)) {
3681 mvneta_port_down(pp);
3686 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
3689 /* Set interrupt coalescing for ethtools */
3690 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3691 struct ethtool_coalesce *c)
3693 struct mvneta_port *pp = netdev_priv(dev);
3696 for (queue = 0; queue < rxq_number; queue++) {
3697 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3698 rxq->time_coal = c->rx_coalesce_usecs;
3699 rxq->pkts_coal = c->rx_max_coalesced_frames;
3700 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3701 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3704 for (queue = 0; queue < txq_number; queue++) {
3705 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3706 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3707 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3713 /* get coalescing for ethtools */
3714 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3715 struct ethtool_coalesce *c)
3717 struct mvneta_port *pp = netdev_priv(dev);
3719 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3720 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3722 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3727 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3728 struct ethtool_drvinfo *drvinfo)
3730 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3731 sizeof(drvinfo->driver));
3732 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3733 sizeof(drvinfo->version));
3734 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3735 sizeof(drvinfo->bus_info));
3739 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3740 struct ethtool_ringparam *ring)
3742 struct mvneta_port *pp = netdev_priv(netdev);
3744 ring->rx_max_pending = MVNETA_MAX_RXD;
3745 ring->tx_max_pending = MVNETA_MAX_TXD;
3746 ring->rx_pending = pp->rx_ring_size;
3747 ring->tx_pending = pp->tx_ring_size;
3750 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3751 struct ethtool_ringparam *ring)
3753 struct mvneta_port *pp = netdev_priv(dev);
3755 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3757 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3758 ring->rx_pending : MVNETA_MAX_RXD;
3760 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3761 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3762 if (pp->tx_ring_size != ring->tx_pending)
3763 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3764 pp->tx_ring_size, ring->tx_pending);
3766 if (netif_running(dev)) {
3768 if (mvneta_open(dev)) {
3770 "error on opening device after ring param change\n");
3778 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3781 if (sset == ETH_SS_STATS) {
3784 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3785 memcpy(data + i * ETH_GSTRING_LEN,
3786 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3790 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3792 const struct mvneta_statistic *s;
3793 void __iomem *base = pp->base;
3798 for (i = 0, s = mvneta_statistics;
3799 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3803 val = readl_relaxed(base + s->offset);
3804 pp->ethtool_stats[i] += val;
3807 /* Docs say to read low 32-bit then high */
3808 low = readl_relaxed(base + s->offset);
3809 high = readl_relaxed(base + s->offset + 4);
3810 val64 = (u64)high << 32 | low;
3811 pp->ethtool_stats[i] += val64;
3817 static void mvneta_ethtool_get_stats(struct net_device *dev,
3818 struct ethtool_stats *stats, u64 *data)
3820 struct mvneta_port *pp = netdev_priv(dev);
3823 mvneta_ethtool_update_stats(pp);
3825 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3826 *data++ = pp->ethtool_stats[i];
3829 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3831 if (sset == ETH_SS_STATS)
3832 return ARRAY_SIZE(mvneta_statistics);
3836 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3838 return MVNETA_RSS_LU_TABLE_SIZE;
3841 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3842 struct ethtool_rxnfc *info,
3843 u32 *rules __always_unused)
3845 switch (info->cmd) {
3846 case ETHTOOL_GRXRINGS:
3847 info->data = rxq_number;
3856 static int mvneta_config_rss(struct mvneta_port *pp)
3861 netif_tx_stop_all_queues(pp->dev);
3863 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3865 /* We have to synchronise on the napi of each CPU */
3866 for_each_online_cpu(cpu) {
3867 struct mvneta_pcpu_port *pcpu_port =
3868 per_cpu_ptr(pp->ports, cpu);
3870 napi_synchronize(&pcpu_port->napi);
3871 napi_disable(&pcpu_port->napi);
3874 pp->rxq_def = pp->indir[0];
3876 /* Update unicast mapping */
3877 mvneta_set_rx_mode(pp->dev);
3879 /* Update val of portCfg register accordingly with all RxQueue types */
3880 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3881 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3883 /* Update the elected CPU matching the new rxq_def */
3884 spin_lock(&pp->lock);
3885 mvneta_percpu_elect(pp);
3886 spin_unlock(&pp->lock);
3888 /* We have to synchronise on the napi of each CPU */
3889 for_each_online_cpu(cpu) {
3890 struct mvneta_pcpu_port *pcpu_port =
3891 per_cpu_ptr(pp->ports, cpu);
3893 napi_enable(&pcpu_port->napi);
3896 netif_tx_start_all_queues(pp->dev);
3901 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3902 const u8 *key, const u8 hfunc)
3904 struct mvneta_port *pp = netdev_priv(dev);
3906 /* Current code for Armada 3700 doesn't support RSS features yet */
3907 if (pp->neta_armada3700)
3910 /* We require at least one supported parameter to be changed
3911 * and no change in any of the unsupported parameters
3914 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3920 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
3922 return mvneta_config_rss(pp);
3925 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3928 struct mvneta_port *pp = netdev_priv(dev);
3930 /* Current code for Armada 3700 doesn't support RSS features yet */
3931 if (pp->neta_armada3700)
3935 *hfunc = ETH_RSS_HASH_TOP;
3940 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
3945 static void mvneta_ethtool_get_wol(struct net_device *dev,
3946 struct ethtool_wolinfo *wol)
3952 phy_ethtool_get_wol(dev->phydev, wol);
3955 static int mvneta_ethtool_set_wol(struct net_device *dev,
3956 struct ethtool_wolinfo *wol)
3963 ret = phy_ethtool_set_wol(dev->phydev, wol);
3965 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
3970 static const struct net_device_ops mvneta_netdev_ops = {
3971 .ndo_open = mvneta_open,
3972 .ndo_stop = mvneta_stop,
3973 .ndo_start_xmit = mvneta_tx,
3974 .ndo_set_rx_mode = mvneta_set_rx_mode,
3975 .ndo_set_mac_address = mvneta_set_mac_addr,
3976 .ndo_change_mtu = mvneta_change_mtu,
3977 .ndo_fix_features = mvneta_fix_features,
3978 .ndo_get_stats64 = mvneta_get_stats64,
3979 .ndo_do_ioctl = mvneta_ioctl,
3982 static const struct ethtool_ops mvneta_eth_tool_ops = {
3983 .nway_reset = phy_ethtool_nway_reset,
3984 .get_link = ethtool_op_get_link,
3985 .set_coalesce = mvneta_ethtool_set_coalesce,
3986 .get_coalesce = mvneta_ethtool_get_coalesce,
3987 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3988 .get_ringparam = mvneta_ethtool_get_ringparam,
3989 .set_ringparam = mvneta_ethtool_set_ringparam,
3990 .get_strings = mvneta_ethtool_get_strings,
3991 .get_ethtool_stats = mvneta_ethtool_get_stats,
3992 .get_sset_count = mvneta_ethtool_get_sset_count,
3993 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
3994 .get_rxnfc = mvneta_ethtool_get_rxnfc,
3995 .get_rxfh = mvneta_ethtool_get_rxfh,
3996 .set_rxfh = mvneta_ethtool_set_rxfh,
3997 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3998 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
3999 .get_wol = mvneta_ethtool_get_wol,
4000 .set_wol = mvneta_ethtool_set_wol,
4004 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4009 mvneta_port_disable(pp);
4011 /* Set port default values */
4012 mvneta_defaults_set(pp);
4014 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4018 /* Initialize TX descriptor rings */
4019 for (queue = 0; queue < txq_number; queue++) {
4020 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4022 txq->size = pp->tx_ring_size;
4023 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4026 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4030 /* Create Rx descriptor rings */
4031 for (queue = 0; queue < rxq_number; queue++) {
4032 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4034 rxq->size = pp->rx_ring_size;
4035 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4036 rxq->time_coal = MVNETA_RX_COAL_USEC;
4038 = devm_kmalloc_array(pp->dev->dev.parent,
4040 sizeof(*rxq->buf_virt_addr),
4042 if (!rxq->buf_virt_addr)
4049 /* platform glue : initialize decoding windows */
4050 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
4051 const struct mbus_dram_target_info *dram)
4057 for (i = 0; i < 6; i++) {
4058 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
4059 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
4062 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4069 for (i = 0; i < dram->num_cs; i++) {
4070 const struct mbus_dram_window *cs = dram->cs + i;
4072 mvreg_write(pp, MVNETA_WIN_BASE(i),
4073 (cs->base & 0xffff0000) |
4074 (cs->mbus_attr << 8) |
4075 dram->mbus_dram_target_id);
4077 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4078 (cs->size - 1) & 0xffff0000);
4080 win_enable &= ~(1 << i);
4081 win_protect |= 3 << (2 * i);
4084 /* For Armada3700 open default 4GB Mbus window, leaving
4085 * arbitration of target/attribute to a different layer
4088 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4089 win_enable &= ~BIT(0);
4093 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4094 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4097 /* Power up the port */
4098 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4102 /* MAC Cause register should be cleared */
4103 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4105 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
4107 /* Even though it might look weird, when we're configured in
4108 * SGMII or QSGMII mode, the RGMII bit needs to be set.
4111 case PHY_INTERFACE_MODE_QSGMII:
4112 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4113 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
4115 case PHY_INTERFACE_MODE_SGMII:
4116 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4117 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
4119 case PHY_INTERFACE_MODE_RGMII:
4120 case PHY_INTERFACE_MODE_RGMII_ID:
4121 case PHY_INTERFACE_MODE_RGMII_RXID:
4122 case PHY_INTERFACE_MODE_RGMII_TXID:
4123 ctrl |= MVNETA_GMAC2_PORT_RGMII;
4129 /* Cancel Port Reset */
4130 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
4131 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
4133 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
4134 MVNETA_GMAC2_PORT_RESET) != 0)
4140 /* Device initialization routine */
4141 static int mvneta_probe(struct platform_device *pdev)
4143 struct resource *res;
4144 struct device_node *dn = pdev->dev.of_node;
4145 struct device_node *phy_node;
4146 struct device_node *bm_node;
4147 struct mvneta_port *pp;
4148 struct net_device *dev;
4149 const char *dt_mac_addr;
4150 char hw_mac_addr[ETH_ALEN];
4151 const char *mac_from;
4152 const char *managed;
4158 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
4162 dev->irq = irq_of_parse_and_map(dn, 0);
4163 if (dev->irq == 0) {
4165 goto err_free_netdev;
4168 phy_node = of_parse_phandle(dn, "phy", 0);
4170 if (!of_phy_is_fixed_link(dn)) {
4171 dev_err(&pdev->dev, "no PHY specified\n");
4176 err = of_phy_register_fixed_link(dn);
4178 dev_err(&pdev->dev, "cannot register fixed PHY\n");
4182 /* In the case of a fixed PHY, the DT node associated
4183 * to the PHY is the Ethernet MAC DT node.
4185 phy_node = of_node_get(dn);
4188 phy_mode = of_get_phy_mode(dn);
4190 dev_err(&pdev->dev, "incorrect phy-mode\n");
4192 goto err_put_phy_node;
4195 dev->tx_queue_len = MVNETA_MAX_TXD;
4196 dev->watchdog_timeo = 5 * HZ;
4197 dev->netdev_ops = &mvneta_netdev_ops;
4199 dev->ethtool_ops = &mvneta_eth_tool_ops;
4201 pp = netdev_priv(dev);
4202 spin_lock_init(&pp->lock);
4203 pp->phy_node = phy_node;
4204 pp->phy_interface = phy_mode;
4206 err = of_property_read_string(dn, "managed", &managed);
4207 pp->use_inband_status = (err == 0 &&
4208 strcmp(managed, "in-band-status") == 0);
4210 pp->rxq_def = rxq_def;
4212 /* Set RX packet offset correction for platforms, whose
4213 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
4214 * platforms and 0B for 32-bit ones.
4216 pp->rx_offset_correction =
4217 max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
4219 pp->indir[0] = rxq_def;
4221 /* Get special SoC configurations */
4222 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
4223 pp->neta_armada3700 = true;
4225 pp->clk = devm_clk_get(&pdev->dev, "core");
4226 if (IS_ERR(pp->clk))
4227 pp->clk = devm_clk_get(&pdev->dev, NULL);
4228 if (IS_ERR(pp->clk)) {
4229 err = PTR_ERR(pp->clk);
4230 goto err_put_phy_node;
4233 clk_prepare_enable(pp->clk);
4235 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4236 if (!IS_ERR(pp->clk_bus))
4237 clk_prepare_enable(pp->clk_bus);
4239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4240 pp->base = devm_ioremap_resource(&pdev->dev, res);
4241 if (IS_ERR(pp->base)) {
4242 err = PTR_ERR(pp->base);
4246 /* Alloc per-cpu port structure */
4247 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4253 /* Alloc per-cpu stats */
4254 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4257 goto err_free_ports;
4260 dt_mac_addr = of_get_mac_address(dn);
4262 mac_from = "device tree";
4263 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4265 mvneta_get_mac_addr(pp, hw_mac_addr);
4266 if (is_valid_ether_addr(hw_mac_addr)) {
4267 mac_from = "hardware";
4268 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4270 mac_from = "random";
4271 eth_hw_addr_random(dev);
4275 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4276 if (tx_csum_limit < 0 ||
4277 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4278 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4279 dev_info(&pdev->dev,
4280 "Wrong TX csum limit in DT, set to %dB\n",
4281 MVNETA_TX_CSUM_DEF_SIZE);
4283 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4284 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4286 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4289 pp->tx_csum_limit = tx_csum_limit;
4291 pp->dram_target_info = mv_mbus_dram_info();
4292 /* Armada3700 requires setting default configuration of Mbus
4293 * windows, however without using filled mbus_dram_target_info
4296 if (pp->dram_target_info || pp->neta_armada3700)
4297 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4299 pp->tx_ring_size = MVNETA_MAX_TXD;
4300 pp->rx_ring_size = MVNETA_MAX_RXD;
4303 SET_NETDEV_DEV(dev, &pdev->dev);
4305 pp->id = global_port_id++;
4307 /* Obtain access to BM resources if enabled and already initialized */
4308 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4309 if (bm_node && bm_node->data) {
4310 pp->bm_priv = bm_node->data;
4311 err = mvneta_bm_port_init(pdev, pp);
4313 dev_info(&pdev->dev, "use SW buffer management\n");
4317 of_node_put(bm_node);
4319 err = mvneta_init(&pdev->dev, pp);
4323 err = mvneta_port_power_up(pp, phy_mode);
4325 dev_err(&pdev->dev, "can't power up port\n");
4329 /* Armada3700 network controller does not support per-cpu
4330 * operation, so only single NAPI should be initialized.
4332 if (pp->neta_armada3700) {
4333 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4335 for_each_present_cpu(cpu) {
4336 struct mvneta_pcpu_port *port =
4337 per_cpu_ptr(pp->ports, cpu);
4339 netif_napi_add(dev, &port->napi, mvneta_poll,
4345 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO;
4346 dev->hw_features |= dev->features;
4347 dev->vlan_features |= dev->features;
4348 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4349 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4351 /* MTU range: 68 - 9676 */
4352 dev->min_mtu = ETH_MIN_MTU;
4353 /* 9676 == 9700 - 20 and rounding to 8 */
4354 dev->max_mtu = 9676;
4356 err = register_netdev(dev);
4358 dev_err(&pdev->dev, "failed to register\n");
4362 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4365 platform_set_drvdata(pdev, pp->dev);
4367 if (pp->use_inband_status) {
4368 struct phy_device *phy = of_phy_find_device(dn);
4370 mvneta_fixed_link_update(pp, phy);
4372 put_device(&phy->mdio.dev);
4379 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4380 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4383 free_percpu(pp->stats);
4385 free_percpu(pp->ports);
4387 clk_disable_unprepare(pp->clk_bus);
4388 clk_disable_unprepare(pp->clk);
4390 of_node_put(phy_node);
4391 if (of_phy_is_fixed_link(dn))
4392 of_phy_deregister_fixed_link(dn);
4394 irq_dispose_mapping(dev->irq);
4400 /* Device removal routine */
4401 static int mvneta_remove(struct platform_device *pdev)
4403 struct net_device *dev = platform_get_drvdata(pdev);
4404 struct device_node *dn = pdev->dev.of_node;
4405 struct mvneta_port *pp = netdev_priv(dev);
4407 unregister_netdev(dev);
4408 clk_disable_unprepare(pp->clk_bus);
4409 clk_disable_unprepare(pp->clk);
4410 free_percpu(pp->ports);
4411 free_percpu(pp->stats);
4412 if (of_phy_is_fixed_link(dn))
4413 of_phy_deregister_fixed_link(dn);
4414 irq_dispose_mapping(dev->irq);
4415 of_node_put(pp->phy_node);
4419 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4420 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4427 #ifdef CONFIG_PM_SLEEP
4428 static int mvneta_suspend(struct device *device)
4430 struct net_device *dev = dev_get_drvdata(device);
4431 struct mvneta_port *pp = netdev_priv(dev);
4433 if (netif_running(dev))
4435 netif_device_detach(dev);
4436 clk_disable_unprepare(pp->clk_bus);
4437 clk_disable_unprepare(pp->clk);
4441 static int mvneta_resume(struct device *device)
4443 struct platform_device *pdev = to_platform_device(device);
4444 struct net_device *dev = dev_get_drvdata(device);
4445 struct mvneta_port *pp = netdev_priv(dev);
4448 clk_prepare_enable(pp->clk);
4449 if (!IS_ERR(pp->clk_bus))
4450 clk_prepare_enable(pp->clk_bus);
4451 if (pp->dram_target_info || pp->neta_armada3700)
4452 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4454 err = mvneta_bm_port_init(pdev, pp);
4456 dev_info(&pdev->dev, "use SW buffer management\n");
4460 mvneta_defaults_set(pp);
4461 err = mvneta_port_power_up(pp, pp->phy_interface);
4463 dev_err(device, "can't power up port\n");
4467 if (pp->use_inband_status)
4468 mvneta_fixed_link_update(pp, dev->phydev);
4470 netif_device_attach(dev);
4471 if (netif_running(dev)) {
4473 mvneta_set_rx_mode(dev);
4480 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
4482 static const struct of_device_id mvneta_match[] = {
4483 { .compatible = "marvell,armada-370-neta" },
4484 { .compatible = "marvell,armada-xp-neta" },
4485 { .compatible = "marvell,armada-3700-neta" },
4488 MODULE_DEVICE_TABLE(of, mvneta_match);
4490 static struct platform_driver mvneta_driver = {
4491 .probe = mvneta_probe,
4492 .remove = mvneta_remove,
4494 .name = MVNETA_DRIVER_NAME,
4495 .of_match_table = mvneta_match,
4496 .pm = &mvneta_pm_ops,
4500 static int __init mvneta_driver_init(void)
4504 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4506 mvneta_cpu_down_prepare);
4509 online_hpstate = ret;
4510 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4511 NULL, mvneta_cpu_dead);
4515 ret = platform_driver_register(&mvneta_driver);
4521 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4523 cpuhp_remove_multi_state(online_hpstate);
4527 module_init(mvneta_driver_init);
4529 static void __exit mvneta_driver_exit(void)
4531 platform_driver_unregister(&mvneta_driver);
4532 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4533 cpuhp_remove_multi_state(online_hpstate);
4535 module_exit(mvneta_driver_exit);
4537 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4538 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4539 MODULE_LICENSE("GPL");
4541 module_param(rxq_number, int, S_IRUGO);
4542 module_param(txq_number, int, S_IRUGO);
4544 module_param(rxq_def, int, S_IRUGO);
4545 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);