2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/if_vlan.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_address.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
35 #include <linux/cpu.h>
38 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
39 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
40 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
41 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
42 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
43 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
44 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
45 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
46 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
47 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
48 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
49 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
50 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
51 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
52 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
53 #define MVNETA_PORT_RX_RESET 0x1cc0
54 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
55 #define MVNETA_PHY_ADDR 0x2000
56 #define MVNETA_PHY_ADDR_MASK 0x1f
57 #define MVNETA_MBUS_RETRY 0x2010
58 #define MVNETA_UNIT_INTR_CAUSE 0x2080
59 #define MVNETA_UNIT_CONTROL 0x20B0
60 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
61 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
62 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
63 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
64 #define MVNETA_BASE_ADDR_ENABLE 0x2290
65 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
66 #define MVNETA_PORT_CONFIG 0x2400
67 #define MVNETA_UNI_PROMISC_MODE BIT(0)
68 #define MVNETA_DEF_RXQ(q) ((q) << 1)
69 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
70 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
71 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
72 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
73 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
74 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
75 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
76 MVNETA_DEF_RXQ_ARP(q) | \
77 MVNETA_DEF_RXQ_TCP(q) | \
78 MVNETA_DEF_RXQ_UDP(q) | \
79 MVNETA_DEF_RXQ_BPDU(q) | \
80 MVNETA_TX_UNSET_ERR_SUM | \
81 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
82 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
83 #define MVNETA_MAC_ADDR_LOW 0x2414
84 #define MVNETA_MAC_ADDR_HIGH 0x2418
85 #define MVNETA_SDMA_CONFIG 0x241c
86 #define MVNETA_SDMA_BRST_SIZE_16 4
87 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
88 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
89 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
90 #define MVNETA_DESC_SWAP BIT(6)
91 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
92 #define MVNETA_PORT_STATUS 0x2444
93 #define MVNETA_TX_IN_PRGRS BIT(0)
94 #define MVNETA_TX_FIFO_EMPTY BIT(8)
95 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
96 #define MVNETA_SERDES_CFG 0x24A0
97 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
98 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
99 #define MVNETA_TYPE_PRIO 0x24bc
100 #define MVNETA_FORCE_UNI BIT(21)
101 #define MVNETA_TXQ_CMD_1 0x24e4
102 #define MVNETA_TXQ_CMD 0x2448
103 #define MVNETA_TXQ_DISABLE_SHIFT 8
104 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
105 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
106 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
107 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
108 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
109 #define MVNETA_ACC_MODE 0x2500
110 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
111 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
112 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
113 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
115 /* Exception Interrupt Port/Queue Cause register */
117 #define MVNETA_INTR_NEW_CAUSE 0x25a0
118 #define MVNETA_INTR_NEW_MASK 0x25a4
120 /* bits 0..7 = TXQ SENT, one bit per queue.
121 * bits 8..15 = RXQ OCCUP, one bit per queue.
122 * bits 16..23 = RXQ FREE, one bit per queue.
123 * bit 29 = OLD_REG_SUM, see old reg ?
124 * bit 30 = TX_ERR_SUM, one bit for 4 ports
125 * bit 31 = MISC_SUM, one bit for 4 ports
127 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
128 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
129 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
130 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
131 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
133 #define MVNETA_INTR_OLD_CAUSE 0x25a8
134 #define MVNETA_INTR_OLD_MASK 0x25ac
136 /* Data Path Port/Queue Cause Register */
137 #define MVNETA_INTR_MISC_CAUSE 0x25b0
138 #define MVNETA_INTR_MISC_MASK 0x25b4
140 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
141 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
142 #define MVNETA_CAUSE_PTP BIT(4)
144 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
145 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
146 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
147 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
148 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
149 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
150 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
151 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
153 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
154 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
155 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
157 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
158 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
159 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
161 #define MVNETA_INTR_ENABLE 0x25b8
162 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
163 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
165 #define MVNETA_RXQ_CMD 0x2680
166 #define MVNETA_RXQ_DISABLE_SHIFT 8
167 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
168 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
169 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
170 #define MVNETA_GMAC_CTRL_0 0x2c00
171 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
172 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
173 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
174 #define MVNETA_GMAC_CTRL_2 0x2c08
175 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
176 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
177 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
178 #define MVNETA_GMAC2_PORT_RESET BIT(6)
179 #define MVNETA_GMAC_STATUS 0x2c10
180 #define MVNETA_GMAC_LINK_UP BIT(0)
181 #define MVNETA_GMAC_SPEED_1000 BIT(1)
182 #define MVNETA_GMAC_SPEED_100 BIT(2)
183 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
184 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
185 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
186 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
187 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
188 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
189 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
190 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
191 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
192 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
193 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
194 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
195 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
196 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
197 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
198 #define MVNETA_MIB_COUNTERS_BASE 0x3000
199 #define MVNETA_MIB_LATE_COLLISION 0x7c
200 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
201 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
202 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
203 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
204 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
205 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
206 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
207 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
208 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
209 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
210 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
211 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
212 #define MVNETA_PORT_TX_RESET 0x3cf0
213 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
214 #define MVNETA_TX_MTU 0x3e0c
215 #define MVNETA_TX_TOKEN_SIZE 0x3e14
216 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
217 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
218 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
220 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
222 /* Descriptor ring Macros */
223 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
224 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
226 /* Various constants */
229 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
230 #define MVNETA_RX_COAL_PKTS 32
231 #define MVNETA_RX_COAL_USEC 100
233 /* The two bytes Marvell header. Either contains a special value used
234 * by Marvell switches when a specific hardware mode is enabled (not
235 * supported by this driver) or is filled automatically by zeroes on
236 * the RX side. Those two bytes being at the front of the Ethernet
237 * header, they allow to have the IP header aligned on a 4 bytes
238 * boundary automatically: the hardware skips those two bytes on its
241 #define MVNETA_MH_SIZE 2
243 #define MVNETA_VLAN_TAG_LEN 4
245 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
246 #define MVNETA_TX_CSUM_DEF_SIZE 1600
247 #define MVNETA_TX_CSUM_MAX_SIZE 9800
248 #define MVNETA_ACC_MODE_EXT 1
250 /* Timeout constants */
251 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
252 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
253 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
255 #define MVNETA_TX_MTU_MAX 0x3ffff
257 /* TSO header size */
258 #define TSO_HEADER_SIZE 128
260 /* Max number of Rx descriptors */
261 #define MVNETA_MAX_RXD 128
263 /* Max number of Tx descriptors */
264 #define MVNETA_MAX_TXD 532
266 /* Max number of allowed TCP segments for software TSO */
267 #define MVNETA_MAX_TSO_SEGS 100
269 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
271 /* descriptor aligned size */
272 #define MVNETA_DESC_ALIGNED_SIZE 32
274 #define MVNETA_RX_PKT_SIZE(mtu) \
275 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
276 ETH_HLEN + ETH_FCS_LEN, \
277 MVNETA_CPU_D_CACHE_LINE_SIZE)
279 #define IS_TSO_HEADER(txq, addr) \
280 ((addr >= txq->tso_hdrs_phys) && \
281 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
283 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
285 struct mvneta_statistic {
286 unsigned short offset;
288 const char name[ETH_GSTRING_LEN];
294 static const struct mvneta_statistic mvneta_statistics[] = {
295 { 0x3000, T_REG_64, "good_octets_received", },
296 { 0x3010, T_REG_32, "good_frames_received", },
297 { 0x3008, T_REG_32, "bad_octets_received", },
298 { 0x3014, T_REG_32, "bad_frames_received", },
299 { 0x3018, T_REG_32, "broadcast_frames_received", },
300 { 0x301c, T_REG_32, "multicast_frames_received", },
301 { 0x3050, T_REG_32, "unrec_mac_control_received", },
302 { 0x3058, T_REG_32, "good_fc_received", },
303 { 0x305c, T_REG_32, "bad_fc_received", },
304 { 0x3060, T_REG_32, "undersize_received", },
305 { 0x3064, T_REG_32, "fragments_received", },
306 { 0x3068, T_REG_32, "oversize_received", },
307 { 0x306c, T_REG_32, "jabber_received", },
308 { 0x3070, T_REG_32, "mac_receive_error", },
309 { 0x3074, T_REG_32, "bad_crc_event", },
310 { 0x3078, T_REG_32, "collision", },
311 { 0x307c, T_REG_32, "late_collision", },
312 { 0x2484, T_REG_32, "rx_discard", },
313 { 0x2488, T_REG_32, "rx_overrun", },
314 { 0x3020, T_REG_32, "frames_64_octets", },
315 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
316 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
317 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
318 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
319 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
320 { 0x3038, T_REG_64, "good_octets_sent", },
321 { 0x3040, T_REG_32, "good_frames_sent", },
322 { 0x3044, T_REG_32, "excessive_collision", },
323 { 0x3048, T_REG_32, "multicast_frames_sent", },
324 { 0x304c, T_REG_32, "broadcast_frames_sent", },
325 { 0x3054, T_REG_32, "fc_sent", },
326 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
329 struct mvneta_pcpu_stats {
330 struct u64_stats_sync syncp;
337 struct mvneta_pcpu_port {
338 /* Pointer to the shared port */
339 struct mvneta_port *pp;
341 /* Pointer to the CPU-local NAPI struct */
342 struct napi_struct napi;
344 /* Cause of the previous interrupt */
349 struct mvneta_pcpu_port __percpu *ports;
350 struct mvneta_pcpu_stats __percpu *stats;
353 unsigned int frag_size;
355 struct mvneta_rx_queue *rxqs;
356 struct mvneta_tx_queue *txqs;
357 struct net_device *dev;
358 struct notifier_block cpu_notifier;
366 struct mii_bus *mii_bus;
367 struct phy_device *phy_dev;
368 phy_interface_t phy_interface;
369 struct device_node *phy_node;
373 unsigned int tx_csum_limit;
374 int use_inband_status:1;
376 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
379 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
380 * layout of the transmit and reception DMA descriptors, and their
381 * layout is therefore defined by the hardware design
384 #define MVNETA_TX_L3_OFF_SHIFT 0
385 #define MVNETA_TX_IP_HLEN_SHIFT 8
386 #define MVNETA_TX_L4_UDP BIT(16)
387 #define MVNETA_TX_L3_IP6 BIT(17)
388 #define MVNETA_TXD_IP_CSUM BIT(18)
389 #define MVNETA_TXD_Z_PAD BIT(19)
390 #define MVNETA_TXD_L_DESC BIT(20)
391 #define MVNETA_TXD_F_DESC BIT(21)
392 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
393 MVNETA_TXD_L_DESC | \
395 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
396 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
398 #define MVNETA_RXD_ERR_CRC 0x0
399 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
400 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
401 #define MVNETA_RXD_ERR_LEN BIT(18)
402 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
403 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
404 #define MVNETA_RXD_L3_IP4 BIT(25)
405 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
406 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
408 #if defined(__LITTLE_ENDIAN)
409 struct mvneta_tx_desc {
410 u32 command; /* Options used by HW for packet transmitting.*/
411 u16 reserverd1; /* csum_l4 (for future use) */
412 u16 data_size; /* Data size of transmitted packet in bytes */
413 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
414 u32 reserved2; /* hw_cmd - (for future use, PMT) */
415 u32 reserved3[4]; /* Reserved - (for future use) */
418 struct mvneta_rx_desc {
419 u32 status; /* Info about received packet */
420 u16 reserved1; /* pnc_info - (for future use, PnC) */
421 u16 data_size; /* Size of received packet in bytes */
423 u32 buf_phys_addr; /* Physical address of the buffer */
424 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
426 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
427 u16 reserved3; /* prefetch_cmd, for future use */
428 u16 reserved4; /* csum_l4 - (for future use, PnC) */
430 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
431 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
434 struct mvneta_tx_desc {
435 u16 data_size; /* Data size of transmitted packet in bytes */
436 u16 reserverd1; /* csum_l4 (for future use) */
437 u32 command; /* Options used by HW for packet transmitting.*/
438 u32 reserved2; /* hw_cmd - (for future use, PMT) */
439 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
440 u32 reserved3[4]; /* Reserved - (for future use) */
443 struct mvneta_rx_desc {
444 u16 data_size; /* Size of received packet in bytes */
445 u16 reserved1; /* pnc_info - (for future use, PnC) */
446 u32 status; /* Info about received packet */
448 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
449 u32 buf_phys_addr; /* Physical address of the buffer */
451 u16 reserved4; /* csum_l4 - (for future use, PnC) */
452 u16 reserved3; /* prefetch_cmd, for future use */
453 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
455 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
456 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
460 struct mvneta_tx_queue {
461 /* Number of this TX queue, in the range 0-7 */
464 /* Number of TX DMA descriptors in the descriptor ring */
467 /* Number of currently used TX DMA descriptor in the
471 int tx_stop_threshold;
472 int tx_wake_threshold;
474 /* Array of transmitted skb */
475 struct sk_buff **tx_skb;
477 /* Index of last TX DMA descriptor that was inserted */
480 /* Index of the TX DMA descriptor to be cleaned up */
485 /* Virtual address of the TX DMA descriptors array */
486 struct mvneta_tx_desc *descs;
488 /* DMA address of the TX DMA descriptors array */
489 dma_addr_t descs_phys;
491 /* Index of the last TX DMA descriptor */
494 /* Index of the next TX DMA descriptor to process */
495 int next_desc_to_proc;
497 /* DMA buffers for TSO headers */
500 /* DMA address of TSO headers */
501 dma_addr_t tso_hdrs_phys;
504 struct mvneta_rx_queue {
505 /* rx queue number, in the range 0-7 */
508 /* num of rx descriptors in the rx descriptor ring */
511 /* counter of times when mvneta_refill() failed */
517 /* Virtual address of the RX DMA descriptors array */
518 struct mvneta_rx_desc *descs;
520 /* DMA address of the RX DMA descriptors array */
521 dma_addr_t descs_phys;
523 /* Index of the last RX DMA descriptor */
526 /* Index of the next RX DMA descriptor to process */
527 int next_desc_to_proc;
530 /* The hardware supports eight (8) rx queues, but we are only allowing
531 * the first one to be used. Therefore, let's just allocate one queue.
533 static int rxq_number = 8;
534 static int txq_number = 8;
538 static int rx_copybreak __read_mostly = 256;
540 #define MVNETA_DRIVER_NAME "mvneta"
541 #define MVNETA_DRIVER_VERSION "1.0"
543 /* Utility/helper methods */
545 /* Write helper method */
546 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
548 writel(data, pp->base + offset);
551 /* Read helper method */
552 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
554 return readl(pp->base + offset);
557 /* Increment txq get counter */
558 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
560 txq->txq_get_index++;
561 if (txq->txq_get_index == txq->size)
562 txq->txq_get_index = 0;
565 /* Increment txq put counter */
566 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
568 txq->txq_put_index++;
569 if (txq->txq_put_index == txq->size)
570 txq->txq_put_index = 0;
574 /* Clear all MIB counters */
575 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
580 /* Perform dummy reads from MIB counters */
581 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
582 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
583 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
584 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
587 /* Get System Network Statistics */
588 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
589 struct rtnl_link_stats64 *stats)
591 struct mvneta_port *pp = netdev_priv(dev);
595 for_each_possible_cpu(cpu) {
596 struct mvneta_pcpu_stats *cpu_stats;
602 cpu_stats = per_cpu_ptr(pp->stats, cpu);
604 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
605 rx_packets = cpu_stats->rx_packets;
606 rx_bytes = cpu_stats->rx_bytes;
607 tx_packets = cpu_stats->tx_packets;
608 tx_bytes = cpu_stats->tx_bytes;
609 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
611 stats->rx_packets += rx_packets;
612 stats->rx_bytes += rx_bytes;
613 stats->tx_packets += tx_packets;
614 stats->tx_bytes += tx_bytes;
617 stats->rx_errors = dev->stats.rx_errors;
618 stats->rx_dropped = dev->stats.rx_dropped;
620 stats->tx_dropped = dev->stats.tx_dropped;
625 /* Rx descriptors helper methods */
627 /* Checks whether the RX descriptor having this status is both the first
628 * and the last descriptor for the RX packet. Each RX packet is currently
629 * received through a single RX descriptor, so not having each RX
630 * descriptor with its first and last bits set is an error
632 static int mvneta_rxq_desc_is_first_last(u32 status)
634 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
635 MVNETA_RXD_FIRST_LAST_DESC;
638 /* Add number of descriptors ready to receive new packets */
639 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
640 struct mvneta_rx_queue *rxq,
643 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
646 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
647 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
648 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
649 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
650 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
653 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
654 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
657 /* Get number of RX descriptors occupied by received packets */
658 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
659 struct mvneta_rx_queue *rxq)
663 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
664 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
667 /* Update num of rx desc called upon return from rx path or
668 * from mvneta_rxq_drop_pkts().
670 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
671 struct mvneta_rx_queue *rxq,
672 int rx_done, int rx_filled)
676 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
678 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
679 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
683 /* Only 255 descriptors can be added at once */
684 while ((rx_done > 0) || (rx_filled > 0)) {
685 if (rx_done <= 0xff) {
692 if (rx_filled <= 0xff) {
693 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
696 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
699 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
703 /* Get pointer to next RX descriptor to be processed by SW */
704 static struct mvneta_rx_desc *
705 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
707 int rx_desc = rxq->next_desc_to_proc;
709 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
710 prefetch(rxq->descs + rxq->next_desc_to_proc);
711 return rxq->descs + rx_desc;
714 /* Change maximum receive size of the port. */
715 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
719 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
720 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
721 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
722 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
723 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
727 /* Set rx queue offset */
728 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
729 struct mvneta_rx_queue *rxq,
734 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
735 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
738 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
739 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
743 /* Tx descriptors helper methods */
745 /* Update HW with number of TX descriptors to be sent */
746 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
747 struct mvneta_tx_queue *txq,
752 /* Only 255 descriptors can be added at once ; Assume caller
753 * process TX desriptors in quanta less than 256
756 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
759 /* Get pointer to next TX descriptor to be processed (send) by HW */
760 static struct mvneta_tx_desc *
761 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
763 int tx_desc = txq->next_desc_to_proc;
765 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
766 return txq->descs + tx_desc;
769 /* Release the last allocated TX descriptor. Useful to handle DMA
770 * mapping failures in the TX path.
772 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
774 if (txq->next_desc_to_proc == 0)
775 txq->next_desc_to_proc = txq->last_desc - 1;
777 txq->next_desc_to_proc--;
780 /* Set rxq buf size */
781 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
782 struct mvneta_rx_queue *rxq,
787 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
789 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
790 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
792 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
795 /* Disable buffer management (BM) */
796 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
797 struct mvneta_rx_queue *rxq)
801 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
802 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
803 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
806 /* Start the Ethernet port RX and TX activity */
807 static void mvneta_port_up(struct mvneta_port *pp)
812 /* Enable all initialized TXs. */
814 for (queue = 0; queue < txq_number; queue++) {
815 struct mvneta_tx_queue *txq = &pp->txqs[queue];
816 if (txq->descs != NULL)
817 q_map |= (1 << queue);
819 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
822 /* Enable all initialized RXQs. */
823 mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def));
826 /* Stop the Ethernet port activity */
827 static void mvneta_port_down(struct mvneta_port *pp)
832 /* Stop Rx port activity. Check port Rx activity. */
833 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
835 /* Issue stop command for active channels only */
837 mvreg_write(pp, MVNETA_RXQ_CMD,
838 val << MVNETA_RXQ_DISABLE_SHIFT);
840 /* Wait for all Rx activity to terminate. */
843 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
845 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
851 val = mvreg_read(pp, MVNETA_RXQ_CMD);
852 } while (val & 0xff);
854 /* Stop Tx port activity. Check port Tx activity. Issue stop
855 * command for active channels only
857 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
860 mvreg_write(pp, MVNETA_TXQ_CMD,
861 (val << MVNETA_TXQ_DISABLE_SHIFT));
863 /* Wait for all Tx activity to terminate. */
866 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
868 "TIMEOUT for TX stopped status=0x%08x\n",
874 /* Check TX Command reg that all Txqs are stopped */
875 val = mvreg_read(pp, MVNETA_TXQ_CMD);
877 } while (val & 0xff);
879 /* Double check to verify that TX FIFO is empty */
882 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
884 "TX FIFO empty timeout status=0x08%x\n",
890 val = mvreg_read(pp, MVNETA_PORT_STATUS);
891 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
892 (val & MVNETA_TX_IN_PRGRS));
897 /* Enable the port by setting the port enable bit of the MAC control register */
898 static void mvneta_port_enable(struct mvneta_port *pp)
903 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
904 val |= MVNETA_GMAC0_PORT_ENABLE;
905 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
908 /* Disable the port and wait for about 200 usec before retuning */
909 static void mvneta_port_disable(struct mvneta_port *pp)
913 /* Reset the Enable bit in the Serial Control Register */
914 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
915 val &= ~MVNETA_GMAC0_PORT_ENABLE;
916 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
925 /* Multicast tables methods */
927 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
928 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
936 val = 0x1 | (queue << 1);
937 val |= (val << 24) | (val << 16) | (val << 8);
940 for (offset = 0; offset <= 0xc; offset += 4)
941 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
944 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
945 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
953 val = 0x1 | (queue << 1);
954 val |= (val << 24) | (val << 16) | (val << 8);
957 for (offset = 0; offset <= 0xfc; offset += 4)
958 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
962 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
963 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
969 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
972 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
973 val = 0x1 | (queue << 1);
974 val |= (val << 24) | (val << 16) | (val << 8);
977 for (offset = 0; offset <= 0xfc; offset += 4)
978 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
981 /* This method sets defaults to the NETA port:
982 * Clears interrupt Cause and Mask registers.
983 * Clears all MAC tables.
984 * Sets defaults to all registers.
985 * Resets RX and TX descriptor rings.
987 * This method can be called after mvneta_port_down() to return the port
988 * settings to defaults.
990 static void mvneta_defaults_set(struct mvneta_port *pp)
996 /* Clear all Cause registers */
997 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
998 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
999 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1001 /* Mask all interrupts */
1002 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1003 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1004 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1005 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1007 /* Enable MBUS Retry bit16 */
1008 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1010 /* Set CPU queue access map - all CPUs have access to all RX
1011 * queues and to all TX queues
1013 for_each_present_cpu(cpu)
1014 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
1015 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
1016 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
1018 /* Reset RX and TX DMAs */
1019 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1020 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1022 /* Disable Legacy WRR, Disable EJP, Release from reset */
1023 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1024 for (queue = 0; queue < txq_number; queue++) {
1025 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1026 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1029 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1030 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1032 /* Set Port Acceleration Mode */
1033 val = MVNETA_ACC_MODE_EXT;
1034 mvreg_write(pp, MVNETA_ACC_MODE, val);
1036 /* Update val of portCfg register accordingly with all RxQueue types */
1037 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
1038 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1041 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1042 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1044 /* Build PORT_SDMA_CONFIG_REG */
1047 /* Default burst size */
1048 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1049 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1050 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1052 #if defined(__BIG_ENDIAN)
1053 val |= MVNETA_DESC_SWAP;
1056 /* Assign port SDMA configuration */
1057 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1059 /* Disable PHY polling in hardware, since we're using the
1060 * kernel phylib to do this.
1062 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1063 val &= ~MVNETA_PHY_POLLING_ENABLE;
1064 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1066 if (pp->use_inband_status) {
1067 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1068 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1069 MVNETA_GMAC_FORCE_LINK_DOWN |
1070 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1071 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1072 MVNETA_GMAC_AN_SPEED_EN |
1073 MVNETA_GMAC_AN_DUPLEX_EN;
1074 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1075 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1076 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1077 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1079 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1080 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1081 MVNETA_GMAC_AN_SPEED_EN |
1082 MVNETA_GMAC_AN_DUPLEX_EN);
1083 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1086 mvneta_set_ucast_table(pp, -1);
1087 mvneta_set_special_mcast_table(pp, -1);
1088 mvneta_set_other_mcast_table(pp, -1);
1090 /* Set port interrupt enable register - default enable all */
1091 mvreg_write(pp, MVNETA_INTR_ENABLE,
1092 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1093 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1095 mvneta_mib_counters_clear(pp);
1098 /* Set max sizes for tx queues */
1099 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1105 mtu = max_tx_size * 8;
1106 if (mtu > MVNETA_TX_MTU_MAX)
1107 mtu = MVNETA_TX_MTU_MAX;
1110 val = mvreg_read(pp, MVNETA_TX_MTU);
1111 val &= ~MVNETA_TX_MTU_MAX;
1113 mvreg_write(pp, MVNETA_TX_MTU, val);
1115 /* TX token size and all TXQs token size must be larger that MTU */
1116 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1118 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1121 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1123 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1125 for (queue = 0; queue < txq_number; queue++) {
1126 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1128 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1131 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1133 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1138 /* Set unicast address */
1139 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1142 unsigned int unicast_reg;
1143 unsigned int tbl_offset;
1144 unsigned int reg_offset;
1146 /* Locate the Unicast table entry */
1147 last_nibble = (0xf & last_nibble);
1149 /* offset from unicast tbl base */
1150 tbl_offset = (last_nibble / 4) * 4;
1152 /* offset within the above reg */
1153 reg_offset = last_nibble % 4;
1155 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1158 /* Clear accepts frame bit at specified unicast DA tbl entry */
1159 unicast_reg &= ~(0xff << (8 * reg_offset));
1161 unicast_reg &= ~(0xff << (8 * reg_offset));
1162 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1165 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1168 /* Set mac address */
1169 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1176 mac_l = (addr[4] << 8) | (addr[5]);
1177 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1178 (addr[2] << 8) | (addr[3] << 0);
1180 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1181 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1184 /* Accept frames of this address */
1185 mvneta_set_ucast_addr(pp, addr[5], queue);
1188 /* Set the number of packets that will be received before RX interrupt
1189 * will be generated by HW.
1191 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1192 struct mvneta_rx_queue *rxq, u32 value)
1194 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1195 value | MVNETA_RXQ_NON_OCCUPIED(0));
1196 rxq->pkts_coal = value;
1199 /* Set the time delay in usec before RX interrupt will be generated by
1202 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1203 struct mvneta_rx_queue *rxq, u32 value)
1206 unsigned long clk_rate;
1208 clk_rate = clk_get_rate(pp->clk);
1209 val = (clk_rate / 1000000) * value;
1211 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1212 rxq->time_coal = value;
1215 /* Set threshold for TX_DONE pkts coalescing */
1216 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1217 struct mvneta_tx_queue *txq, u32 value)
1221 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1223 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1224 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1226 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1228 txq->done_pkts_coal = value;
1231 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1232 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1233 u32 phys_addr, u32 cookie)
1235 rx_desc->buf_cookie = cookie;
1236 rx_desc->buf_phys_addr = phys_addr;
1239 /* Decrement sent descriptors counter */
1240 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1241 struct mvneta_tx_queue *txq,
1246 /* Only 255 TX descriptors can be updated at once */
1247 while (sent_desc > 0xff) {
1248 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1249 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1250 sent_desc = sent_desc - 0xff;
1253 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1254 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1257 /* Get number of TX descriptors already sent by HW */
1258 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1259 struct mvneta_tx_queue *txq)
1264 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1265 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1266 MVNETA_TXQ_SENT_DESC_SHIFT;
1271 /* Get number of sent descriptors and decrement counter.
1272 * The number of sent descriptors is returned.
1274 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1275 struct mvneta_tx_queue *txq)
1279 /* Get number of sent descriptors */
1280 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1282 /* Decrement sent descriptors counter */
1284 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1289 /* Set TXQ descriptors fields relevant for CSUM calculation */
1290 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1291 int ip_hdr_len, int l4_proto)
1295 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1296 * G_L4_chk, L4_type; required only for checksum
1299 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1300 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1302 if (l3_proto == htons(ETH_P_IP))
1303 command |= MVNETA_TXD_IP_CSUM;
1305 command |= MVNETA_TX_L3_IP6;
1307 if (l4_proto == IPPROTO_TCP)
1308 command |= MVNETA_TX_L4_CSUM_FULL;
1309 else if (l4_proto == IPPROTO_UDP)
1310 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1312 command |= MVNETA_TX_L4_CSUM_NOT;
1318 /* Display more error info */
1319 static void mvneta_rx_error(struct mvneta_port *pp,
1320 struct mvneta_rx_desc *rx_desc)
1322 u32 status = rx_desc->status;
1324 if (!mvneta_rxq_desc_is_first_last(status)) {
1326 "bad rx status %08x (buffer oversize), size=%d\n",
1327 status, rx_desc->data_size);
1331 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1332 case MVNETA_RXD_ERR_CRC:
1333 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1334 status, rx_desc->data_size);
1336 case MVNETA_RXD_ERR_OVERRUN:
1337 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1338 status, rx_desc->data_size);
1340 case MVNETA_RXD_ERR_LEN:
1341 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1342 status, rx_desc->data_size);
1344 case MVNETA_RXD_ERR_RESOURCE:
1345 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1346 status, rx_desc->data_size);
1351 /* Handle RX checksum offload based on the descriptor's status */
1352 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1353 struct sk_buff *skb)
1355 if ((status & MVNETA_RXD_L3_IP4) &&
1356 (status & MVNETA_RXD_L4_CSUM_OK)) {
1358 skb->ip_summed = CHECKSUM_UNNECESSARY;
1362 skb->ip_summed = CHECKSUM_NONE;
1365 /* Return tx queue pointer (find last set bit) according to <cause> returned
1366 * form tx_done reg. <cause> must not be null. The return value is always a
1367 * valid queue for matching the first one found in <cause>.
1369 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1372 int queue = fls(cause) - 1;
1374 return &pp->txqs[queue];
1377 /* Free tx queue skbuffs */
1378 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1379 struct mvneta_tx_queue *txq, int num)
1383 for (i = 0; i < num; i++) {
1384 struct mvneta_tx_desc *tx_desc = txq->descs +
1386 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1388 mvneta_txq_inc_get(txq);
1390 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1391 dma_unmap_single(pp->dev->dev.parent,
1392 tx_desc->buf_phys_addr,
1393 tx_desc->data_size, DMA_TO_DEVICE);
1396 dev_kfree_skb_any(skb);
1400 /* Handle end of transmission */
1401 static void mvneta_txq_done(struct mvneta_port *pp,
1402 struct mvneta_tx_queue *txq)
1404 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1407 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1411 mvneta_txq_bufs_free(pp, txq, tx_done);
1413 txq->count -= tx_done;
1415 if (netif_tx_queue_stopped(nq)) {
1416 if (txq->count <= txq->tx_wake_threshold)
1417 netif_tx_wake_queue(nq);
1421 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1423 if (likely(pp->frag_size <= PAGE_SIZE))
1424 return netdev_alloc_frag(pp->frag_size);
1426 return kmalloc(pp->frag_size, GFP_ATOMIC);
1429 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1431 if (likely(pp->frag_size <= PAGE_SIZE))
1432 skb_free_frag(data);
1437 /* Refill processing */
1438 static int mvneta_rx_refill(struct mvneta_port *pp,
1439 struct mvneta_rx_desc *rx_desc)
1442 dma_addr_t phys_addr;
1445 data = mvneta_frag_alloc(pp);
1449 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1450 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1452 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1453 mvneta_frag_free(pp, data);
1457 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1461 /* Handle tx checksum */
1462 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1464 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1466 __be16 l3_proto = vlan_get_protocol(skb);
1469 if (l3_proto == htons(ETH_P_IP)) {
1470 struct iphdr *ip4h = ip_hdr(skb);
1472 /* Calculate IPv4 checksum and L4 checksum */
1473 ip_hdr_len = ip4h->ihl;
1474 l4_proto = ip4h->protocol;
1475 } else if (l3_proto == htons(ETH_P_IPV6)) {
1476 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1478 /* Read l4_protocol from one of IPv6 extra headers */
1479 if (skb_network_header_len(skb) > 0)
1480 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1481 l4_proto = ip6h->nexthdr;
1483 return MVNETA_TX_L4_CSUM_NOT;
1485 return mvneta_txq_desc_csum(skb_network_offset(skb),
1486 l3_proto, ip_hdr_len, l4_proto);
1489 return MVNETA_TX_L4_CSUM_NOT;
1492 /* Drop packets received by the RXQ and free buffers */
1493 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1494 struct mvneta_rx_queue *rxq)
1498 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1499 for (i = 0; i < rxq->size; i++) {
1500 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1501 void *data = (void *)rx_desc->buf_cookie;
1503 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1504 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1505 mvneta_frag_free(pp, data);
1509 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1512 /* Main rx processing */
1513 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1514 struct mvneta_rx_queue *rxq)
1516 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1517 struct net_device *dev = pp->dev;
1522 /* Get number of received packets */
1523 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1525 if (rx_todo > rx_done)
1530 /* Fairness NAPI loop */
1531 while (rx_done < rx_todo) {
1532 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1533 struct sk_buff *skb;
1534 unsigned char *data;
1535 dma_addr_t phys_addr;
1540 rx_status = rx_desc->status;
1541 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1542 data = (unsigned char *)rx_desc->buf_cookie;
1543 phys_addr = rx_desc->buf_phys_addr;
1545 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1546 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1548 dev->stats.rx_errors++;
1549 mvneta_rx_error(pp, rx_desc);
1550 /* leave the descriptor untouched */
1554 if (rx_bytes <= rx_copybreak) {
1555 /* better copy a small frame and not unmap the DMA region */
1556 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1558 goto err_drop_frame;
1560 dma_sync_single_range_for_cpu(dev->dev.parent,
1561 rx_desc->buf_phys_addr,
1562 MVNETA_MH_SIZE + NET_SKB_PAD,
1565 memcpy(skb_put(skb, rx_bytes),
1566 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1569 skb->protocol = eth_type_trans(skb, dev);
1570 mvneta_rx_csum(pp, rx_status, skb);
1571 napi_gro_receive(&port->napi, skb);
1574 rcvd_bytes += rx_bytes;
1576 /* leave the descriptor and buffer untouched */
1580 /* Refill processing */
1581 err = mvneta_rx_refill(pp, rx_desc);
1583 netdev_err(dev, "Linux processing - Can't refill\n");
1585 goto err_drop_frame;
1588 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1590 /* After refill old buffer has to be unmapped regardless
1591 * the skb is successfully built or not.
1593 dma_unmap_single(dev->dev.parent, phys_addr,
1594 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1597 goto err_drop_frame;
1600 rcvd_bytes += rx_bytes;
1602 /* Linux processing */
1603 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1604 skb_put(skb, rx_bytes);
1606 skb->protocol = eth_type_trans(skb, dev);
1608 mvneta_rx_csum(pp, rx_status, skb);
1610 napi_gro_receive(&port->napi, skb);
1614 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1616 u64_stats_update_begin(&stats->syncp);
1617 stats->rx_packets += rcvd_pkts;
1618 stats->rx_bytes += rcvd_bytes;
1619 u64_stats_update_end(&stats->syncp);
1622 /* Update rxq management counters */
1623 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1629 mvneta_tso_put_hdr(struct sk_buff *skb,
1630 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1632 struct mvneta_tx_desc *tx_desc;
1633 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1635 txq->tx_skb[txq->txq_put_index] = NULL;
1636 tx_desc = mvneta_txq_next_desc_get(txq);
1637 tx_desc->data_size = hdr_len;
1638 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1639 tx_desc->command |= MVNETA_TXD_F_DESC;
1640 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1641 txq->txq_put_index * TSO_HEADER_SIZE;
1642 mvneta_txq_inc_put(txq);
1646 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1647 struct sk_buff *skb, char *data, int size,
1648 bool last_tcp, bool is_last)
1650 struct mvneta_tx_desc *tx_desc;
1652 tx_desc = mvneta_txq_next_desc_get(txq);
1653 tx_desc->data_size = size;
1654 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1655 size, DMA_TO_DEVICE);
1656 if (unlikely(dma_mapping_error(dev->dev.parent,
1657 tx_desc->buf_phys_addr))) {
1658 mvneta_txq_desc_put(txq);
1662 tx_desc->command = 0;
1663 txq->tx_skb[txq->txq_put_index] = NULL;
1666 /* last descriptor in the TCP packet */
1667 tx_desc->command = MVNETA_TXD_L_DESC;
1669 /* last descriptor in SKB */
1671 txq->tx_skb[txq->txq_put_index] = skb;
1673 mvneta_txq_inc_put(txq);
1677 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1678 struct mvneta_tx_queue *txq)
1680 int total_len, data_left;
1682 struct mvneta_port *pp = netdev_priv(dev);
1684 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1687 /* Count needed descriptors */
1688 if ((txq->count + tso_count_descs(skb)) >= txq->size)
1691 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1692 pr_info("*** Is this even possible???!?!?\n");
1696 /* Initialize the TSO handler, and prepare the first payload */
1697 tso_start(skb, &tso);
1699 total_len = skb->len - hdr_len;
1700 while (total_len > 0) {
1703 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1704 total_len -= data_left;
1707 /* prepare packet headers: MAC + IP + TCP */
1708 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1709 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1711 mvneta_tso_put_hdr(skb, pp, txq);
1713 while (data_left > 0) {
1717 size = min_t(int, tso.size, data_left);
1719 if (mvneta_tso_put_data(dev, txq, skb,
1726 tso_build_data(skb, &tso, size);
1733 /* Release all used data descriptors; header descriptors must not
1736 for (i = desc_count - 1; i >= 0; i--) {
1737 struct mvneta_tx_desc *tx_desc = txq->descs + i;
1738 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1739 dma_unmap_single(pp->dev->dev.parent,
1740 tx_desc->buf_phys_addr,
1743 mvneta_txq_desc_put(txq);
1748 /* Handle tx fragmentation processing */
1749 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1750 struct mvneta_tx_queue *txq)
1752 struct mvneta_tx_desc *tx_desc;
1753 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1755 for (i = 0; i < nr_frags; i++) {
1756 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1757 void *addr = page_address(frag->page.p) + frag->page_offset;
1759 tx_desc = mvneta_txq_next_desc_get(txq);
1760 tx_desc->data_size = frag->size;
1762 tx_desc->buf_phys_addr =
1763 dma_map_single(pp->dev->dev.parent, addr,
1764 tx_desc->data_size, DMA_TO_DEVICE);
1766 if (dma_mapping_error(pp->dev->dev.parent,
1767 tx_desc->buf_phys_addr)) {
1768 mvneta_txq_desc_put(txq);
1772 if (i == nr_frags - 1) {
1773 /* Last descriptor */
1774 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1775 txq->tx_skb[txq->txq_put_index] = skb;
1777 /* Descriptor in the middle: Not First, Not Last */
1778 tx_desc->command = 0;
1779 txq->tx_skb[txq->txq_put_index] = NULL;
1781 mvneta_txq_inc_put(txq);
1787 /* Release all descriptors that were used to map fragments of
1788 * this packet, as well as the corresponding DMA mappings
1790 for (i = i - 1; i >= 0; i--) {
1791 tx_desc = txq->descs + i;
1792 dma_unmap_single(pp->dev->dev.parent,
1793 tx_desc->buf_phys_addr,
1796 mvneta_txq_desc_put(txq);
1802 /* Main tx processing */
1803 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1805 struct mvneta_port *pp = netdev_priv(dev);
1806 u16 txq_id = skb_get_queue_mapping(skb);
1807 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1808 struct mvneta_tx_desc *tx_desc;
1813 if (!netif_running(dev))
1816 if (skb_is_gso(skb)) {
1817 frags = mvneta_tx_tso(skb, dev, txq);
1821 frags = skb_shinfo(skb)->nr_frags + 1;
1823 /* Get a descriptor for the first part of the packet */
1824 tx_desc = mvneta_txq_next_desc_get(txq);
1826 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1828 tx_desc->data_size = skb_headlen(skb);
1830 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1833 if (unlikely(dma_mapping_error(dev->dev.parent,
1834 tx_desc->buf_phys_addr))) {
1835 mvneta_txq_desc_put(txq);
1841 /* First and Last descriptor */
1842 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1843 tx_desc->command = tx_cmd;
1844 txq->tx_skb[txq->txq_put_index] = skb;
1845 mvneta_txq_inc_put(txq);
1847 /* First but not Last */
1848 tx_cmd |= MVNETA_TXD_F_DESC;
1849 txq->tx_skb[txq->txq_put_index] = NULL;
1850 mvneta_txq_inc_put(txq);
1851 tx_desc->command = tx_cmd;
1852 /* Continue with other skb fragments */
1853 if (mvneta_tx_frag_process(pp, skb, txq)) {
1854 dma_unmap_single(dev->dev.parent,
1855 tx_desc->buf_phys_addr,
1858 mvneta_txq_desc_put(txq);
1866 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1867 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1869 txq->count += frags;
1870 mvneta_txq_pend_desc_add(pp, txq, frags);
1872 if (txq->count >= txq->tx_stop_threshold)
1873 netif_tx_stop_queue(nq);
1875 u64_stats_update_begin(&stats->syncp);
1876 stats->tx_packets++;
1877 stats->tx_bytes += len;
1878 u64_stats_update_end(&stats->syncp);
1880 dev->stats.tx_dropped++;
1881 dev_kfree_skb_any(skb);
1884 return NETDEV_TX_OK;
1888 /* Free tx resources, when resetting a port */
1889 static void mvneta_txq_done_force(struct mvneta_port *pp,
1890 struct mvneta_tx_queue *txq)
1893 int tx_done = txq->count;
1895 mvneta_txq_bufs_free(pp, txq, tx_done);
1899 txq->txq_put_index = 0;
1900 txq->txq_get_index = 0;
1903 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1904 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1906 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
1908 struct mvneta_tx_queue *txq;
1909 struct netdev_queue *nq;
1911 while (cause_tx_done) {
1912 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1914 nq = netdev_get_tx_queue(pp->dev, txq->id);
1915 __netif_tx_lock(nq, smp_processor_id());
1918 mvneta_txq_done(pp, txq);
1920 __netif_tx_unlock(nq);
1921 cause_tx_done &= ~((1 << txq->id));
1925 /* Compute crc8 of the specified address, using a unique algorithm ,
1926 * according to hw spec, different than generic crc8 algorithm
1928 static int mvneta_addr_crc(unsigned char *addr)
1933 for (i = 0; i < ETH_ALEN; i++) {
1936 crc = (crc ^ addr[i]) << 8;
1937 for (j = 7; j >= 0; j--) {
1938 if (crc & (0x100 << j))
1946 /* This method controls the net device special MAC multicast support.
1947 * The Special Multicast Table for MAC addresses supports MAC of the form
1948 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1949 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1950 * Table entries in the DA-Filter table. This method set the Special
1951 * Multicast Table appropriate entry.
1953 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1954 unsigned char last_byte,
1957 unsigned int smc_table_reg;
1958 unsigned int tbl_offset;
1959 unsigned int reg_offset;
1961 /* Register offset from SMC table base */
1962 tbl_offset = (last_byte / 4);
1963 /* Entry offset within the above reg */
1964 reg_offset = last_byte % 4;
1966 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1970 smc_table_reg &= ~(0xff << (8 * reg_offset));
1972 smc_table_reg &= ~(0xff << (8 * reg_offset));
1973 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1976 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1980 /* This method controls the network device Other MAC multicast support.
1981 * The Other Multicast Table is used for multicast of another type.
1982 * A CRC-8 is used as an index to the Other Multicast Table entries
1983 * in the DA-Filter table.
1984 * The method gets the CRC-8 value from the calling routine and
1985 * sets the Other Multicast Table appropriate entry according to the
1988 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1992 unsigned int omc_table_reg;
1993 unsigned int tbl_offset;
1994 unsigned int reg_offset;
1996 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1997 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1999 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2002 /* Clear accepts frame bit at specified Other DA table entry */
2003 omc_table_reg &= ~(0xff << (8 * reg_offset));
2005 omc_table_reg &= ~(0xff << (8 * reg_offset));
2006 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2009 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2012 /* The network device supports multicast using two tables:
2013 * 1) Special Multicast Table for MAC addresses of the form
2014 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2015 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2016 * Table entries in the DA-Filter table.
2017 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2018 * is used as an index to the Other Multicast Table entries in the
2021 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2024 unsigned char crc_result = 0;
2026 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2027 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2031 crc_result = mvneta_addr_crc(p_addr);
2033 if (pp->mcast_count[crc_result] == 0) {
2034 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2039 pp->mcast_count[crc_result]--;
2040 if (pp->mcast_count[crc_result] != 0) {
2041 netdev_info(pp->dev,
2042 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2043 pp->mcast_count[crc_result], crc_result);
2047 pp->mcast_count[crc_result]++;
2049 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2054 /* Configure Fitering mode of Ethernet port */
2055 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2058 u32 port_cfg_reg, val;
2060 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2062 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2064 /* Set / Clear UPM bit in port configuration register */
2066 /* Accept all Unicast addresses */
2067 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2068 val |= MVNETA_FORCE_UNI;
2069 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2070 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2072 /* Reject all Unicast addresses */
2073 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2074 val &= ~MVNETA_FORCE_UNI;
2077 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2078 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2081 /* register unicast and multicast addresses */
2082 static void mvneta_set_rx_mode(struct net_device *dev)
2084 struct mvneta_port *pp = netdev_priv(dev);
2085 struct netdev_hw_addr *ha;
2087 if (dev->flags & IFF_PROMISC) {
2088 /* Accept all: Multicast + Unicast */
2089 mvneta_rx_unicast_promisc_set(pp, 1);
2090 mvneta_set_ucast_table(pp, rxq_def);
2091 mvneta_set_special_mcast_table(pp, rxq_def);
2092 mvneta_set_other_mcast_table(pp, rxq_def);
2094 /* Accept single Unicast */
2095 mvneta_rx_unicast_promisc_set(pp, 0);
2096 mvneta_set_ucast_table(pp, -1);
2097 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2099 if (dev->flags & IFF_ALLMULTI) {
2100 /* Accept all multicast */
2101 mvneta_set_special_mcast_table(pp, rxq_def);
2102 mvneta_set_other_mcast_table(pp, rxq_def);
2104 /* Accept only initialized multicast */
2105 mvneta_set_special_mcast_table(pp, -1);
2106 mvneta_set_other_mcast_table(pp, -1);
2108 if (!netdev_mc_empty(dev)) {
2109 netdev_for_each_mc_addr(ha, dev) {
2110 mvneta_mcast_addr_set(pp, ha->addr,
2118 /* Interrupt handling - the callback for request_irq() */
2119 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2121 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2123 disable_percpu_irq(port->pp->dev->irq);
2124 napi_schedule(&port->napi);
2129 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2130 struct phy_device *phy)
2132 struct fixed_phy_status status;
2133 struct fixed_phy_status changed = {};
2134 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2136 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2137 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2138 status.speed = SPEED_1000;
2139 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2140 status.speed = SPEED_100;
2142 status.speed = SPEED_10;
2143 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2147 fixed_phy_update_state(phy, &status, &changed);
2152 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2153 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2154 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2155 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2156 * Each CPU has its own causeRxTx register
2158 static int mvneta_poll(struct napi_struct *napi, int budget)
2162 struct mvneta_port *pp = netdev_priv(napi->dev);
2163 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2165 if (!netif_running(pp->dev)) {
2166 napi_complete(&port->napi);
2170 /* Read cause register */
2171 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2172 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2173 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2175 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2176 if (pp->use_inband_status && (cause_misc &
2177 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2178 MVNETA_CAUSE_LINK_CHANGE |
2179 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2180 mvneta_fixed_link_update(pp, pp->phy_dev);
2184 /* Release Tx descriptors */
2185 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2186 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2187 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2190 /* For the case where the last mvneta_poll did not process all
2193 cause_rx_tx |= port->cause_rx_tx;
2194 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
2199 napi_complete(&port->napi);
2200 enable_percpu_irq(pp->dev->irq, 0);
2203 port->cause_rx_tx = cause_rx_tx;
2207 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2208 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2213 for (i = 0; i < num; i++) {
2214 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2215 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2216 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2217 __func__, rxq->id, i, num);
2222 /* Add this number of RX descriptors as non occupied (ready to
2225 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2230 /* Free all packets pending transmit from all TXQs and reset TX port */
2231 static void mvneta_tx_reset(struct mvneta_port *pp)
2235 /* free the skb's in the tx ring */
2236 for (queue = 0; queue < txq_number; queue++)
2237 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2239 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2240 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2243 static void mvneta_rx_reset(struct mvneta_port *pp)
2245 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2246 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2249 /* Rx/Tx queue initialization/cleanup methods */
2251 /* Create a specified RX queue */
2252 static int mvneta_rxq_init(struct mvneta_port *pp,
2253 struct mvneta_rx_queue *rxq)
2256 rxq->size = pp->rx_ring_size;
2258 /* Allocate memory for RX descriptors */
2259 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2260 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2261 &rxq->descs_phys, GFP_KERNEL);
2262 if (rxq->descs == NULL)
2265 BUG_ON(rxq->descs !=
2266 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2268 rxq->last_desc = rxq->size - 1;
2270 /* Set Rx descriptors queue starting address */
2271 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2272 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2275 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2277 /* Set coalescing pkts and time */
2278 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2279 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2281 /* Fill RXQ with buffers from RX pool */
2282 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2283 mvneta_rxq_bm_disable(pp, rxq);
2284 mvneta_rxq_fill(pp, rxq, rxq->size);
2289 /* Cleanup Rx queue */
2290 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2291 struct mvneta_rx_queue *rxq)
2293 mvneta_rxq_drop_pkts(pp, rxq);
2296 dma_free_coherent(pp->dev->dev.parent,
2297 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2303 rxq->next_desc_to_proc = 0;
2304 rxq->descs_phys = 0;
2307 /* Create and initialize a tx queue */
2308 static int mvneta_txq_init(struct mvneta_port *pp,
2309 struct mvneta_tx_queue *txq)
2311 txq->size = pp->tx_ring_size;
2313 /* A queue must always have room for at least one skb.
2314 * Therefore, stop the queue when the free entries reaches
2315 * the maximum number of descriptors per skb.
2317 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2318 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2321 /* Allocate memory for TX descriptors */
2322 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2323 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2324 &txq->descs_phys, GFP_KERNEL);
2325 if (txq->descs == NULL)
2328 /* Make sure descriptor address is cache line size aligned */
2329 BUG_ON(txq->descs !=
2330 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2332 txq->last_desc = txq->size - 1;
2334 /* Set maximum bandwidth for enabled TXQs */
2335 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2336 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2338 /* Set Tx descriptors queue starting address */
2339 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2340 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2342 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2343 if (txq->tx_skb == NULL) {
2344 dma_free_coherent(pp->dev->dev.parent,
2345 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2346 txq->descs, txq->descs_phys);
2350 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2351 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2352 txq->size * TSO_HEADER_SIZE,
2353 &txq->tso_hdrs_phys, GFP_KERNEL);
2354 if (txq->tso_hdrs == NULL) {
2356 dma_free_coherent(pp->dev->dev.parent,
2357 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2358 txq->descs, txq->descs_phys);
2361 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2366 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2367 static void mvneta_txq_deinit(struct mvneta_port *pp,
2368 struct mvneta_tx_queue *txq)
2373 dma_free_coherent(pp->dev->dev.parent,
2374 txq->size * TSO_HEADER_SIZE,
2375 txq->tso_hdrs, txq->tso_hdrs_phys);
2377 dma_free_coherent(pp->dev->dev.parent,
2378 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2379 txq->descs, txq->descs_phys);
2383 txq->next_desc_to_proc = 0;
2384 txq->descs_phys = 0;
2386 /* Set minimum bandwidth for disabled TXQs */
2387 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2388 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2390 /* Set Tx descriptors queue starting address and size */
2391 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2392 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2395 /* Cleanup all Tx queues */
2396 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2400 for (queue = 0; queue < txq_number; queue++)
2401 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2404 /* Cleanup all Rx queues */
2405 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2407 mvneta_rxq_deinit(pp, &pp->rxqs[rxq_def]);
2411 /* Init all Rx queues */
2412 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2414 int err = mvneta_rxq_init(pp, &pp->rxqs[rxq_def]);
2416 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2418 mvneta_cleanup_rxqs(pp);
2425 /* Init all tx queues */
2426 static int mvneta_setup_txqs(struct mvneta_port *pp)
2430 for (queue = 0; queue < txq_number; queue++) {
2431 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2433 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2435 mvneta_cleanup_txqs(pp);
2443 static void mvneta_start_dev(struct mvneta_port *pp)
2447 mvneta_max_rx_size_set(pp, pp->pkt_size);
2448 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2450 /* start the Rx/Tx activity */
2451 mvneta_port_enable(pp);
2453 /* Enable polling on the port */
2454 for_each_online_cpu(cpu) {
2455 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2457 napi_enable(&port->napi);
2460 /* Unmask interrupts */
2461 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2462 MVNETA_RX_INTR_MASK(rxq_number) |
2463 MVNETA_TX_INTR_MASK(txq_number) |
2464 MVNETA_MISCINTR_INTR_MASK);
2465 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2466 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2467 MVNETA_CAUSE_LINK_CHANGE |
2468 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2470 phy_start(pp->phy_dev);
2471 netif_tx_start_all_queues(pp->dev);
2474 static void mvneta_stop_dev(struct mvneta_port *pp)
2478 phy_stop(pp->phy_dev);
2480 for_each_online_cpu(cpu) {
2481 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2483 napi_disable(&port->napi);
2486 netif_carrier_off(pp->dev);
2488 mvneta_port_down(pp);
2489 netif_tx_stop_all_queues(pp->dev);
2491 /* Stop the port activity */
2492 mvneta_port_disable(pp);
2494 /* Clear all ethernet port interrupts */
2495 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2496 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2498 /* Mask all ethernet port interrupts */
2499 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2500 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2501 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2503 mvneta_tx_reset(pp);
2504 mvneta_rx_reset(pp);
2507 /* Return positive if MTU is valid */
2508 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2511 netdev_err(dev, "cannot change mtu to less than 68\n");
2515 /* 9676 == 9700 - 20 and rounding to 8 */
2517 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2521 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2522 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2523 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2524 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2530 /* Change the device mtu */
2531 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2533 struct mvneta_port *pp = netdev_priv(dev);
2536 mtu = mvneta_check_mtu_valid(dev, mtu);
2542 if (!netif_running(dev)) {
2543 netdev_update_features(dev);
2547 /* The interface is running, so we have to force a
2548 * reallocation of the queues
2550 mvneta_stop_dev(pp);
2552 mvneta_cleanup_txqs(pp);
2553 mvneta_cleanup_rxqs(pp);
2555 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
2556 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2557 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2559 ret = mvneta_setup_rxqs(pp);
2561 netdev_err(dev, "unable to setup rxqs after MTU change\n");
2565 ret = mvneta_setup_txqs(pp);
2567 netdev_err(dev, "unable to setup txqs after MTU change\n");
2571 mvneta_start_dev(pp);
2573 netdev_update_features(dev);
2578 static netdev_features_t mvneta_fix_features(struct net_device *dev,
2579 netdev_features_t features)
2581 struct mvneta_port *pp = netdev_priv(dev);
2583 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
2584 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
2586 "Disable IP checksum for MTU greater than %dB\n",
2593 /* Get mac address */
2594 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2596 u32 mac_addr_l, mac_addr_h;
2598 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2599 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2600 addr[0] = (mac_addr_h >> 24) & 0xFF;
2601 addr[1] = (mac_addr_h >> 16) & 0xFF;
2602 addr[2] = (mac_addr_h >> 8) & 0xFF;
2603 addr[3] = mac_addr_h & 0xFF;
2604 addr[4] = (mac_addr_l >> 8) & 0xFF;
2605 addr[5] = mac_addr_l & 0xFF;
2608 /* Handle setting mac address */
2609 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2611 struct mvneta_port *pp = netdev_priv(dev);
2612 struct sockaddr *sockaddr = addr;
2615 ret = eth_prepare_mac_addr_change(dev, addr);
2618 /* Remove previous address table entry */
2619 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2621 /* Set new addr in hw */
2622 mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def);
2624 eth_commit_mac_addr_change(dev, addr);
2628 static void mvneta_adjust_link(struct net_device *ndev)
2630 struct mvneta_port *pp = netdev_priv(ndev);
2631 struct phy_device *phydev = pp->phy_dev;
2632 int status_change = 0;
2635 if ((pp->speed != phydev->speed) ||
2636 (pp->duplex != phydev->duplex)) {
2639 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2640 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2641 MVNETA_GMAC_CONFIG_GMII_SPEED |
2642 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
2645 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2647 if (phydev->speed == SPEED_1000)
2648 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2649 else if (phydev->speed == SPEED_100)
2650 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2652 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2654 pp->duplex = phydev->duplex;
2655 pp->speed = phydev->speed;
2659 if (phydev->link != pp->link) {
2660 if (!phydev->link) {
2665 pp->link = phydev->link;
2669 if (status_change) {
2671 if (!pp->use_inband_status) {
2672 u32 val = mvreg_read(pp,
2673 MVNETA_GMAC_AUTONEG_CONFIG);
2674 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
2675 val |= MVNETA_GMAC_FORCE_LINK_PASS;
2676 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2681 if (!pp->use_inband_status) {
2682 u32 val = mvreg_read(pp,
2683 MVNETA_GMAC_AUTONEG_CONFIG);
2684 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
2685 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
2686 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2689 mvneta_port_down(pp);
2691 phy_print_status(phydev);
2695 static int mvneta_mdio_probe(struct mvneta_port *pp)
2697 struct phy_device *phy_dev;
2699 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2702 netdev_err(pp->dev, "could not find the PHY\n");
2706 phy_dev->supported &= PHY_GBIT_FEATURES;
2707 phy_dev->advertising = phy_dev->supported;
2709 pp->phy_dev = phy_dev;
2717 static void mvneta_mdio_remove(struct mvneta_port *pp)
2719 phy_disconnect(pp->phy_dev);
2723 static void mvneta_percpu_enable(void *arg)
2725 struct mvneta_port *pp = arg;
2727 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
2730 static void mvneta_percpu_disable(void *arg)
2732 struct mvneta_port *pp = arg;
2734 disable_percpu_irq(pp->dev->irq);
2737 static void mvneta_percpu_elect(struct mvneta_port *pp)
2739 int online_cpu_idx, cpu, i = 0;
2741 online_cpu_idx = rxq_def % num_online_cpus();
2743 for_each_online_cpu(cpu) {
2744 if (i == online_cpu_idx)
2745 /* Enable per-CPU interrupt on the one CPU we
2748 smp_call_function_single(cpu, mvneta_percpu_enable,
2751 /* Disable per-CPU interrupt on all the other CPU */
2752 smp_call_function_single(cpu, mvneta_percpu_disable,
2758 static int mvneta_percpu_notifier(struct notifier_block *nfb,
2759 unsigned long action, void *hcpu)
2761 struct mvneta_port *pp = container_of(nfb, struct mvneta_port,
2763 int cpu = (unsigned long)hcpu, other_cpu;
2764 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2768 case CPU_ONLINE_FROZEN:
2769 netif_tx_stop_all_queues(pp->dev);
2771 /* We have to synchronise on tha napi of each CPU
2772 * except the one just being waked up
2774 for_each_online_cpu(other_cpu) {
2775 if (other_cpu != cpu) {
2776 struct mvneta_pcpu_port *other_port =
2777 per_cpu_ptr(pp->ports, other_cpu);
2779 napi_synchronize(&other_port->napi);
2783 /* Mask all ethernet port interrupts */
2784 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2785 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2786 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2787 napi_enable(&port->napi);
2789 /* Enable per-CPU interrupt on the one CPU we care
2792 mvneta_percpu_elect(pp);
2794 /* Unmask all ethernet port interrupts */
2795 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2796 MVNETA_RX_INTR_MASK(rxq_number) |
2797 MVNETA_TX_INTR_MASK(txq_number) |
2798 MVNETA_MISCINTR_INTR_MASK);
2799 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2800 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2801 MVNETA_CAUSE_LINK_CHANGE |
2802 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2803 netif_tx_start_all_queues(pp->dev);
2805 case CPU_DOWN_PREPARE:
2806 case CPU_DOWN_PREPARE_FROZEN:
2807 netif_tx_stop_all_queues(pp->dev);
2808 /* Mask all ethernet port interrupts */
2809 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2810 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2811 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2813 napi_synchronize(&port->napi);
2814 napi_disable(&port->napi);
2815 /* Disable per-CPU interrupts on the CPU that is
2818 smp_call_function_single(cpu, mvneta_percpu_disable,
2823 case CPU_DEAD_FROZEN:
2824 /* Check if a new CPU must be elected now this on is down */
2825 mvneta_percpu_elect(pp);
2826 /* Unmask all ethernet port interrupts */
2827 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2828 MVNETA_RX_INTR_MASK(rxq_number) |
2829 MVNETA_TX_INTR_MASK(txq_number) |
2830 MVNETA_MISCINTR_INTR_MASK);
2831 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2832 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2833 MVNETA_CAUSE_LINK_CHANGE |
2834 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2835 netif_tx_start_all_queues(pp->dev);
2842 static int mvneta_open(struct net_device *dev)
2844 struct mvneta_port *pp = netdev_priv(dev);
2847 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2848 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2849 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2851 ret = mvneta_setup_rxqs(pp);
2855 ret = mvneta_setup_txqs(pp);
2857 goto err_cleanup_rxqs;
2859 /* Connect to port interrupt line */
2860 ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
2861 MVNETA_DRIVER_NAME, pp->ports);
2863 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2864 goto err_cleanup_txqs;
2867 /* Even though the documentation says that request_percpu_irq
2868 * doesn't enable the interrupts automatically, it actually
2869 * does so on the local CPU.
2871 * Make sure it's disabled.
2873 mvneta_percpu_disable(pp);
2875 /* Elect a CPU to handle our RX queue interrupt */
2876 mvneta_percpu_elect(pp);
2878 /* Register a CPU notifier to handle the case where our CPU
2879 * might be taken offline.
2881 register_cpu_notifier(&pp->cpu_notifier);
2883 /* In default link is down */
2884 netif_carrier_off(pp->dev);
2886 ret = mvneta_mdio_probe(pp);
2888 netdev_err(dev, "cannot probe MDIO bus\n");
2892 mvneta_start_dev(pp);
2897 free_percpu_irq(pp->dev->irq, pp->ports);
2899 mvneta_cleanup_txqs(pp);
2901 mvneta_cleanup_rxqs(pp);
2905 /* Stop the port, free port interrupt line */
2906 static int mvneta_stop(struct net_device *dev)
2908 struct mvneta_port *pp = netdev_priv(dev);
2910 mvneta_stop_dev(pp);
2911 mvneta_mdio_remove(pp);
2912 unregister_cpu_notifier(&pp->cpu_notifier);
2913 on_each_cpu(mvneta_percpu_disable, pp, true);
2914 free_percpu_irq(dev->irq, pp->ports);
2915 mvneta_cleanup_rxqs(pp);
2916 mvneta_cleanup_txqs(pp);
2921 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2923 struct mvneta_port *pp = netdev_priv(dev);
2928 return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2931 /* Ethtool methods */
2933 /* Get settings (phy address, speed) for ethtools */
2934 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2936 struct mvneta_port *pp = netdev_priv(dev);
2941 return phy_ethtool_gset(pp->phy_dev, cmd);
2944 /* Set settings (phy address, speed) for ethtools */
2945 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2947 struct mvneta_port *pp = netdev_priv(dev);
2952 return phy_ethtool_sset(pp->phy_dev, cmd);
2955 /* Set interrupt coalescing for ethtools */
2956 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2957 struct ethtool_coalesce *c)
2959 struct mvneta_port *pp = netdev_priv(dev);
2962 for (queue = 0; queue < rxq_number; queue++) {
2963 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2964 rxq->time_coal = c->rx_coalesce_usecs;
2965 rxq->pkts_coal = c->rx_max_coalesced_frames;
2966 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2967 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2970 for (queue = 0; queue < txq_number; queue++) {
2971 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2972 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2973 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2979 /* get coalescing for ethtools */
2980 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2981 struct ethtool_coalesce *c)
2983 struct mvneta_port *pp = netdev_priv(dev);
2985 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2986 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2988 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2993 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2994 struct ethtool_drvinfo *drvinfo)
2996 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2997 sizeof(drvinfo->driver));
2998 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2999 sizeof(drvinfo->version));
3000 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3001 sizeof(drvinfo->bus_info));
3005 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3006 struct ethtool_ringparam *ring)
3008 struct mvneta_port *pp = netdev_priv(netdev);
3010 ring->rx_max_pending = MVNETA_MAX_RXD;
3011 ring->tx_max_pending = MVNETA_MAX_TXD;
3012 ring->rx_pending = pp->rx_ring_size;
3013 ring->tx_pending = pp->tx_ring_size;
3016 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3017 struct ethtool_ringparam *ring)
3019 struct mvneta_port *pp = netdev_priv(dev);
3021 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3023 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3024 ring->rx_pending : MVNETA_MAX_RXD;
3026 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3027 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3028 if (pp->tx_ring_size != ring->tx_pending)
3029 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3030 pp->tx_ring_size, ring->tx_pending);
3032 if (netif_running(dev)) {
3034 if (mvneta_open(dev)) {
3036 "error on opening device after ring param change\n");
3044 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3047 if (sset == ETH_SS_STATS) {
3050 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3051 memcpy(data + i * ETH_GSTRING_LEN,
3052 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3056 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3058 const struct mvneta_statistic *s;
3059 void __iomem *base = pp->base;
3064 for (i = 0, s = mvneta_statistics;
3065 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3069 val = readl_relaxed(base + s->offset);
3070 pp->ethtool_stats[i] += val;
3073 /* Docs say to read low 32-bit then high */
3074 low = readl_relaxed(base + s->offset);
3075 high = readl_relaxed(base + s->offset + 4);
3076 val64 = (u64)high << 32 | low;
3077 pp->ethtool_stats[i] += val64;
3083 static void mvneta_ethtool_get_stats(struct net_device *dev,
3084 struct ethtool_stats *stats, u64 *data)
3086 struct mvneta_port *pp = netdev_priv(dev);
3089 mvneta_ethtool_update_stats(pp);
3091 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3092 *data++ = pp->ethtool_stats[i];
3095 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3097 if (sset == ETH_SS_STATS)
3098 return ARRAY_SIZE(mvneta_statistics);
3102 static const struct net_device_ops mvneta_netdev_ops = {
3103 .ndo_open = mvneta_open,
3104 .ndo_stop = mvneta_stop,
3105 .ndo_start_xmit = mvneta_tx,
3106 .ndo_set_rx_mode = mvneta_set_rx_mode,
3107 .ndo_set_mac_address = mvneta_set_mac_addr,
3108 .ndo_change_mtu = mvneta_change_mtu,
3109 .ndo_fix_features = mvneta_fix_features,
3110 .ndo_get_stats64 = mvneta_get_stats64,
3111 .ndo_do_ioctl = mvneta_ioctl,
3114 const struct ethtool_ops mvneta_eth_tool_ops = {
3115 .get_link = ethtool_op_get_link,
3116 .get_settings = mvneta_ethtool_get_settings,
3117 .set_settings = mvneta_ethtool_set_settings,
3118 .set_coalesce = mvneta_ethtool_set_coalesce,
3119 .get_coalesce = mvneta_ethtool_get_coalesce,
3120 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3121 .get_ringparam = mvneta_ethtool_get_ringparam,
3122 .set_ringparam = mvneta_ethtool_set_ringparam,
3123 .get_strings = mvneta_ethtool_get_strings,
3124 .get_ethtool_stats = mvneta_ethtool_get_stats,
3125 .get_sset_count = mvneta_ethtool_get_sset_count,
3129 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
3134 mvneta_port_disable(pp);
3136 /* Set port default values */
3137 mvneta_defaults_set(pp);
3139 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3144 /* Initialize TX descriptor rings */
3145 for (queue = 0; queue < txq_number; queue++) {
3146 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3148 txq->size = pp->tx_ring_size;
3149 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3152 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3157 /* Create Rx descriptor rings */
3158 for (queue = 0; queue < rxq_number; queue++) {
3159 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3161 rxq->size = pp->rx_ring_size;
3162 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3163 rxq->time_coal = MVNETA_RX_COAL_USEC;
3169 /* platform glue : initialize decoding windows */
3170 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3171 const struct mbus_dram_target_info *dram)
3177 for (i = 0; i < 6; i++) {
3178 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3179 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3182 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3188 for (i = 0; i < dram->num_cs; i++) {
3189 const struct mbus_dram_window *cs = dram->cs + i;
3190 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3191 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3193 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3194 (cs->size - 1) & 0xffff0000);
3196 win_enable &= ~(1 << i);
3197 win_protect |= 3 << (2 * i);
3200 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
3201 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
3204 /* Power up the port */
3205 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
3209 /* MAC Cause register should be cleared */
3210 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3212 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3214 /* Even though it might look weird, when we're configured in
3215 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3218 case PHY_INTERFACE_MODE_QSGMII:
3219 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3220 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3222 case PHY_INTERFACE_MODE_SGMII:
3223 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3224 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3226 case PHY_INTERFACE_MODE_RGMII:
3227 case PHY_INTERFACE_MODE_RGMII_ID:
3228 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3234 if (pp->use_inband_status)
3235 ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3237 /* Cancel Port Reset */
3238 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3239 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
3241 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3242 MVNETA_GMAC2_PORT_RESET) != 0)
3248 /* Device initialization routine */
3249 static int mvneta_probe(struct platform_device *pdev)
3251 const struct mbus_dram_target_info *dram_target_info;
3252 struct resource *res;
3253 struct device_node *dn = pdev->dev.of_node;
3254 struct device_node *phy_node;
3255 struct mvneta_port *pp;
3256 struct net_device *dev;
3257 const char *dt_mac_addr;
3258 char hw_mac_addr[ETH_ALEN];
3259 const char *mac_from;
3260 const char *managed;
3266 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
3270 dev->irq = irq_of_parse_and_map(dn, 0);
3271 if (dev->irq == 0) {
3273 goto err_free_netdev;
3276 phy_node = of_parse_phandle(dn, "phy", 0);
3278 if (!of_phy_is_fixed_link(dn)) {
3279 dev_err(&pdev->dev, "no PHY specified\n");
3284 err = of_phy_register_fixed_link(dn);
3286 dev_err(&pdev->dev, "cannot register fixed PHY\n");
3290 /* In the case of a fixed PHY, the DT node associated
3291 * to the PHY is the Ethernet MAC DT node.
3293 phy_node = of_node_get(dn);
3296 phy_mode = of_get_phy_mode(dn);
3298 dev_err(&pdev->dev, "incorrect phy-mode\n");
3300 goto err_put_phy_node;
3303 dev->tx_queue_len = MVNETA_MAX_TXD;
3304 dev->watchdog_timeo = 5 * HZ;
3305 dev->netdev_ops = &mvneta_netdev_ops;
3307 dev->ethtool_ops = &mvneta_eth_tool_ops;
3309 pp = netdev_priv(dev);
3310 pp->phy_node = phy_node;
3311 pp->phy_interface = phy_mode;
3313 err = of_property_read_string(dn, "managed", &managed);
3314 pp->use_inband_status = (err == 0 &&
3315 strcmp(managed, "in-band-status") == 0);
3316 pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
3318 pp->clk = devm_clk_get(&pdev->dev, NULL);
3319 if (IS_ERR(pp->clk)) {
3320 err = PTR_ERR(pp->clk);
3321 goto err_put_phy_node;
3324 clk_prepare_enable(pp->clk);
3326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3327 pp->base = devm_ioremap_resource(&pdev->dev, res);
3328 if (IS_ERR(pp->base)) {
3329 err = PTR_ERR(pp->base);
3333 /* Alloc per-cpu port structure */
3334 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
3340 /* Alloc per-cpu stats */
3341 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
3344 goto err_free_ports;
3347 dt_mac_addr = of_get_mac_address(dn);
3349 mac_from = "device tree";
3350 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3352 mvneta_get_mac_addr(pp, hw_mac_addr);
3353 if (is_valid_ether_addr(hw_mac_addr)) {
3354 mac_from = "hardware";
3355 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3357 mac_from = "random";
3358 eth_hw_addr_random(dev);
3362 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
3363 if (tx_csum_limit < 0 ||
3364 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
3365 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
3366 dev_info(&pdev->dev,
3367 "Wrong TX csum limit in DT, set to %dB\n",
3368 MVNETA_TX_CSUM_DEF_SIZE);
3370 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
3371 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
3373 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
3376 pp->tx_csum_limit = tx_csum_limit;
3378 pp->tx_ring_size = MVNETA_MAX_TXD;
3379 pp->rx_ring_size = MVNETA_MAX_RXD;
3382 SET_NETDEV_DEV(dev, &pdev->dev);
3384 err = mvneta_init(&pdev->dev, pp);
3386 goto err_free_stats;
3388 err = mvneta_port_power_up(pp, phy_mode);
3390 dev_err(&pdev->dev, "can't power up port\n");
3391 goto err_free_stats;
3394 dram_target_info = mv_mbus_dram_info();
3395 if (dram_target_info)
3396 mvneta_conf_mbus_windows(pp, dram_target_info);
3398 for_each_present_cpu(cpu) {
3399 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3401 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3405 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3406 dev->hw_features |= dev->features;
3407 dev->vlan_features |= dev->features;
3408 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3409 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
3411 err = register_netdev(dev);
3413 dev_err(&pdev->dev, "failed to register\n");
3414 goto err_free_stats;
3417 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3420 platform_set_drvdata(pdev, pp->dev);
3422 if (pp->use_inband_status) {
3423 struct phy_device *phy = of_phy_find_device(dn);
3425 mvneta_fixed_link_update(pp, phy);
3427 put_device(&phy->dev);
3433 free_percpu(pp->stats);
3435 free_percpu(pp->ports);
3437 clk_disable_unprepare(pp->clk);
3439 of_node_put(phy_node);
3441 irq_dispose_mapping(dev->irq);
3447 /* Device removal routine */
3448 static int mvneta_remove(struct platform_device *pdev)
3450 struct net_device *dev = platform_get_drvdata(pdev);
3451 struct mvneta_port *pp = netdev_priv(dev);
3453 unregister_netdev(dev);
3454 clk_disable_unprepare(pp->clk);
3455 free_percpu(pp->ports);
3456 free_percpu(pp->stats);
3457 irq_dispose_mapping(dev->irq);
3458 of_node_put(pp->phy_node);
3464 static const struct of_device_id mvneta_match[] = {
3465 { .compatible = "marvell,armada-370-neta" },
3466 { .compatible = "marvell,armada-xp-neta" },
3469 MODULE_DEVICE_TABLE(of, mvneta_match);
3471 static struct platform_driver mvneta_driver = {
3472 .probe = mvneta_probe,
3473 .remove = mvneta_remove,
3475 .name = MVNETA_DRIVER_NAME,
3476 .of_match_table = mvneta_match,
3480 module_platform_driver(mvneta_driver);
3482 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3483 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3484 MODULE_LICENSE("GPL");
3486 module_param(rxq_number, int, S_IRUGO);
3487 module_param(txq_number, int, S_IRUGO);
3489 module_param(rxq_def, int, S_IRUGO);
3490 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);