2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/phy_fixed.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
35 #include "mvneta_bm.h"
41 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
42 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
43 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
44 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
45 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
46 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
47 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
48 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
49 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
50 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
51 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
52 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
53 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
54 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
55 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
56 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
57 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
59 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
60 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
61 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
62 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
63 #define MVNETA_PORT_RX_RESET 0x1cc0
64 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
65 #define MVNETA_PHY_ADDR 0x2000
66 #define MVNETA_PHY_ADDR_MASK 0x1f
67 #define MVNETA_MBUS_RETRY 0x2010
68 #define MVNETA_UNIT_INTR_CAUSE 0x2080
69 #define MVNETA_UNIT_CONTROL 0x20B0
70 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
71 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
72 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
73 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
74 #define MVNETA_BASE_ADDR_ENABLE 0x2290
75 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
76 #define MVNETA_PORT_CONFIG 0x2400
77 #define MVNETA_UNI_PROMISC_MODE BIT(0)
78 #define MVNETA_DEF_RXQ(q) ((q) << 1)
79 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
80 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
81 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
82 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
83 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
84 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
85 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
86 MVNETA_DEF_RXQ_ARP(q) | \
87 MVNETA_DEF_RXQ_TCP(q) | \
88 MVNETA_DEF_RXQ_UDP(q) | \
89 MVNETA_DEF_RXQ_BPDU(q) | \
90 MVNETA_TX_UNSET_ERR_SUM | \
91 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
92 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
93 #define MVNETA_MAC_ADDR_LOW 0x2414
94 #define MVNETA_MAC_ADDR_HIGH 0x2418
95 #define MVNETA_SDMA_CONFIG 0x241c
96 #define MVNETA_SDMA_BRST_SIZE_16 4
97 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
98 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
99 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
100 #define MVNETA_DESC_SWAP BIT(6)
101 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
102 #define MVNETA_PORT_STATUS 0x2444
103 #define MVNETA_TX_IN_PRGRS BIT(0)
104 #define MVNETA_TX_FIFO_EMPTY BIT(8)
105 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
106 #define MVNETA_SERDES_CFG 0x24A0
107 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
108 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
109 #define MVNETA_TYPE_PRIO 0x24bc
110 #define MVNETA_FORCE_UNI BIT(21)
111 #define MVNETA_TXQ_CMD_1 0x24e4
112 #define MVNETA_TXQ_CMD 0x2448
113 #define MVNETA_TXQ_DISABLE_SHIFT 8
114 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
115 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
116 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
117 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
118 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
119 #define MVNETA_ACC_MODE 0x2500
120 #define MVNETA_BM_ADDRESS 0x2504
121 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
122 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
123 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
124 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
125 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
126 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
128 /* Exception Interrupt Port/Queue Cause register
130 * Their behavior depend of the mapping done using the PCPX2Q
131 * registers. For a given CPU if the bit associated to a queue is not
132 * set, then for the register a read from this CPU will always return
133 * 0 and a write won't do anything
136 #define MVNETA_INTR_NEW_CAUSE 0x25a0
137 #define MVNETA_INTR_NEW_MASK 0x25a4
139 /* bits 0..7 = TXQ SENT, one bit per queue.
140 * bits 8..15 = RXQ OCCUP, one bit per queue.
141 * bits 16..23 = RXQ FREE, one bit per queue.
142 * bit 29 = OLD_REG_SUM, see old reg ?
143 * bit 30 = TX_ERR_SUM, one bit for 4 ports
144 * bit 31 = MISC_SUM, one bit for 4 ports
146 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
147 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
148 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
149 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
150 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
152 #define MVNETA_INTR_OLD_CAUSE 0x25a8
153 #define MVNETA_INTR_OLD_MASK 0x25ac
155 /* Data Path Port/Queue Cause Register */
156 #define MVNETA_INTR_MISC_CAUSE 0x25b0
157 #define MVNETA_INTR_MISC_MASK 0x25b4
159 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
160 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
161 #define MVNETA_CAUSE_PTP BIT(4)
163 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
164 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
165 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
166 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
167 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
168 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
169 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
170 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
174 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
176 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
177 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
178 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
180 #define MVNETA_INTR_ENABLE 0x25b8
181 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
182 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
184 #define MVNETA_RXQ_CMD 0x2680
185 #define MVNETA_RXQ_DISABLE_SHIFT 8
186 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
187 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
188 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
189 #define MVNETA_GMAC_CTRL_0 0x2c00
190 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
191 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
192 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
193 #define MVNETA_GMAC_CTRL_2 0x2c08
194 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
195 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
196 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
197 #define MVNETA_GMAC2_PORT_RESET BIT(6)
198 #define MVNETA_GMAC_STATUS 0x2c10
199 #define MVNETA_GMAC_LINK_UP BIT(0)
200 #define MVNETA_GMAC_SPEED_1000 BIT(1)
201 #define MVNETA_GMAC_SPEED_100 BIT(2)
202 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
203 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
204 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
205 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
206 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
207 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
208 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
209 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
210 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
211 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
212 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
213 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
214 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
215 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
216 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
217 #define MVNETA_MIB_COUNTERS_BASE 0x3000
218 #define MVNETA_MIB_LATE_COLLISION 0x7c
219 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
220 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
221 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
222 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
223 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
224 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
225 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
226 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
227 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
228 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
229 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
230 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
231 #define MVNETA_PORT_TX_RESET 0x3cf0
232 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
233 #define MVNETA_TX_MTU 0x3e0c
234 #define MVNETA_TX_TOKEN_SIZE 0x3e14
235 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
236 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
237 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
239 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
241 /* Descriptor ring Macros */
242 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
243 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
245 /* Various constants */
248 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
249 #define MVNETA_RX_COAL_PKTS 32
250 #define MVNETA_RX_COAL_USEC 100
252 /* The two bytes Marvell header. Either contains a special value used
253 * by Marvell switches when a specific hardware mode is enabled (not
254 * supported by this driver) or is filled automatically by zeroes on
255 * the RX side. Those two bytes being at the front of the Ethernet
256 * header, they allow to have the IP header aligned on a 4 bytes
257 * boundary automatically: the hardware skips those two bytes on its
260 #define MVNETA_MH_SIZE 2
262 #define MVNETA_VLAN_TAG_LEN 4
264 #define MVNETA_TX_CSUM_DEF_SIZE 1600
265 #define MVNETA_TX_CSUM_MAX_SIZE 9800
266 #define MVNETA_ACC_MODE_EXT1 1
267 #define MVNETA_ACC_MODE_EXT2 2
269 #define MVNETA_MAX_DECODE_WIN 6
271 /* Timeout constants */
272 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
273 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
274 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
276 #define MVNETA_TX_MTU_MAX 0x3ffff
278 /* The RSS lookup table actually has 256 entries but we do not use
281 #define MVNETA_RSS_LU_TABLE_SIZE 1
283 /* TSO header size */
284 #define TSO_HEADER_SIZE 128
286 /* Max number of Rx descriptors */
287 #define MVNETA_MAX_RXD 128
289 /* Max number of Tx descriptors */
290 #define MVNETA_MAX_TXD 532
292 /* Max number of allowed TCP segments for software TSO */
293 #define MVNETA_MAX_TSO_SEGS 100
295 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
297 /* descriptor aligned size */
298 #define MVNETA_DESC_ALIGNED_SIZE 32
300 #define MVNETA_RX_PKT_SIZE(mtu) \
301 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
302 ETH_HLEN + ETH_FCS_LEN, \
305 #define IS_TSO_HEADER(txq, addr) \
306 ((addr >= txq->tso_hdrs_phys) && \
307 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
309 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
310 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
312 struct mvneta_statistic {
313 unsigned short offset;
315 const char name[ETH_GSTRING_LEN];
321 static const struct mvneta_statistic mvneta_statistics[] = {
322 { 0x3000, T_REG_64, "good_octets_received", },
323 { 0x3010, T_REG_32, "good_frames_received", },
324 { 0x3008, T_REG_32, "bad_octets_received", },
325 { 0x3014, T_REG_32, "bad_frames_received", },
326 { 0x3018, T_REG_32, "broadcast_frames_received", },
327 { 0x301c, T_REG_32, "multicast_frames_received", },
328 { 0x3050, T_REG_32, "unrec_mac_control_received", },
329 { 0x3058, T_REG_32, "good_fc_received", },
330 { 0x305c, T_REG_32, "bad_fc_received", },
331 { 0x3060, T_REG_32, "undersize_received", },
332 { 0x3064, T_REG_32, "fragments_received", },
333 { 0x3068, T_REG_32, "oversize_received", },
334 { 0x306c, T_REG_32, "jabber_received", },
335 { 0x3070, T_REG_32, "mac_receive_error", },
336 { 0x3074, T_REG_32, "bad_crc_event", },
337 { 0x3078, T_REG_32, "collision", },
338 { 0x307c, T_REG_32, "late_collision", },
339 { 0x2484, T_REG_32, "rx_discard", },
340 { 0x2488, T_REG_32, "rx_overrun", },
341 { 0x3020, T_REG_32, "frames_64_octets", },
342 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
343 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
344 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
345 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
346 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
347 { 0x3038, T_REG_64, "good_octets_sent", },
348 { 0x3040, T_REG_32, "good_frames_sent", },
349 { 0x3044, T_REG_32, "excessive_collision", },
350 { 0x3048, T_REG_32, "multicast_frames_sent", },
351 { 0x304c, T_REG_32, "broadcast_frames_sent", },
352 { 0x3054, T_REG_32, "fc_sent", },
353 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
356 struct mvneta_pcpu_stats {
357 struct u64_stats_sync syncp;
364 struct mvneta_pcpu_port {
365 /* Pointer to the shared port */
366 struct mvneta_port *pp;
368 /* Pointer to the CPU-local NAPI struct */
369 struct napi_struct napi;
371 /* Cause of the previous interrupt */
377 struct mvneta_pcpu_port __percpu *ports;
378 struct mvneta_pcpu_stats __percpu *stats;
381 unsigned int frag_size;
383 struct mvneta_rx_queue *rxqs;
384 struct mvneta_tx_queue *txqs;
385 struct net_device *dev;
386 struct hlist_node node_online;
387 struct hlist_node node_dead;
389 /* Protect the access to the percpu interrupt registers,
390 * ensuring that the configuration remains coherent.
403 struct mii_bus *mii_bus;
404 phy_interface_t phy_interface;
405 struct device_node *phy_node;
409 unsigned int tx_csum_limit;
410 unsigned int use_inband_status:1;
412 struct mvneta_bm *bm_priv;
413 struct mvneta_bm_pool *pool_long;
414 struct mvneta_bm_pool *pool_short;
417 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
419 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
422 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
423 * layout of the transmit and reception DMA descriptors, and their
424 * layout is therefore defined by the hardware design
427 #define MVNETA_TX_L3_OFF_SHIFT 0
428 #define MVNETA_TX_IP_HLEN_SHIFT 8
429 #define MVNETA_TX_L4_UDP BIT(16)
430 #define MVNETA_TX_L3_IP6 BIT(17)
431 #define MVNETA_TXD_IP_CSUM BIT(18)
432 #define MVNETA_TXD_Z_PAD BIT(19)
433 #define MVNETA_TXD_L_DESC BIT(20)
434 #define MVNETA_TXD_F_DESC BIT(21)
435 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
436 MVNETA_TXD_L_DESC | \
438 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
439 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
441 #define MVNETA_RXD_ERR_CRC 0x0
442 #define MVNETA_RXD_BM_POOL_SHIFT 13
443 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
444 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
445 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
446 #define MVNETA_RXD_ERR_LEN BIT(18)
447 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
448 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
449 #define MVNETA_RXD_L3_IP4 BIT(25)
450 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
451 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
453 #if defined(__LITTLE_ENDIAN)
454 struct mvneta_tx_desc {
455 u32 command; /* Options used by HW for packet transmitting.*/
456 u16 reserverd1; /* csum_l4 (for future use) */
457 u16 data_size; /* Data size of transmitted packet in bytes */
458 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
459 u32 reserved2; /* hw_cmd - (for future use, PMT) */
460 u32 reserved3[4]; /* Reserved - (for future use) */
463 struct mvneta_rx_desc {
464 u32 status; /* Info about received packet */
465 u16 reserved1; /* pnc_info - (for future use, PnC) */
466 u16 data_size; /* Size of received packet in bytes */
468 u32 buf_phys_addr; /* Physical address of the buffer */
469 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
471 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
472 u16 reserved3; /* prefetch_cmd, for future use */
473 u16 reserved4; /* csum_l4 - (for future use, PnC) */
475 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
476 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
479 struct mvneta_tx_desc {
480 u16 data_size; /* Data size of transmitted packet in bytes */
481 u16 reserverd1; /* csum_l4 (for future use) */
482 u32 command; /* Options used by HW for packet transmitting.*/
483 u32 reserved2; /* hw_cmd - (for future use, PMT) */
484 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
485 u32 reserved3[4]; /* Reserved - (for future use) */
488 struct mvneta_rx_desc {
489 u16 data_size; /* Size of received packet in bytes */
490 u16 reserved1; /* pnc_info - (for future use, PnC) */
491 u32 status; /* Info about received packet */
493 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
494 u32 buf_phys_addr; /* Physical address of the buffer */
496 u16 reserved4; /* csum_l4 - (for future use, PnC) */
497 u16 reserved3; /* prefetch_cmd, for future use */
498 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
500 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
501 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
505 struct mvneta_tx_queue {
506 /* Number of this TX queue, in the range 0-7 */
509 /* Number of TX DMA descriptors in the descriptor ring */
512 /* Number of currently used TX DMA descriptor in the
516 int tx_stop_threshold;
517 int tx_wake_threshold;
519 /* Array of transmitted skb */
520 struct sk_buff **tx_skb;
522 /* Index of last TX DMA descriptor that was inserted */
525 /* Index of the TX DMA descriptor to be cleaned up */
530 /* Virtual address of the TX DMA descriptors array */
531 struct mvneta_tx_desc *descs;
533 /* DMA address of the TX DMA descriptors array */
534 dma_addr_t descs_phys;
536 /* Index of the last TX DMA descriptor */
539 /* Index of the next TX DMA descriptor to process */
540 int next_desc_to_proc;
542 /* DMA buffers for TSO headers */
545 /* DMA address of TSO headers */
546 dma_addr_t tso_hdrs_phys;
548 /* Affinity mask for CPUs*/
549 cpumask_t affinity_mask;
552 struct mvneta_rx_queue {
553 /* rx queue number, in the range 0-7 */
556 /* num of rx descriptors in the rx descriptor ring */
559 /* counter of times when mvneta_refill() failed */
565 /* Virtual address of the RX DMA descriptors array */
566 struct mvneta_rx_desc *descs;
568 /* DMA address of the RX DMA descriptors array */
569 dma_addr_t descs_phys;
571 /* Index of the last RX DMA descriptor */
574 /* Index of the next RX DMA descriptor to process */
575 int next_desc_to_proc;
578 static enum cpuhp_state online_hpstate;
579 /* The hardware supports eight (8) rx queues, but we are only allowing
580 * the first one to be used. Therefore, let's just allocate one queue.
582 static int rxq_number = 8;
583 static int txq_number = 8;
587 static int rx_copybreak __read_mostly = 256;
589 /* HW BM need that each port be identify by a unique ID */
590 static int global_port_id;
592 #define MVNETA_DRIVER_NAME "mvneta"
593 #define MVNETA_DRIVER_VERSION "1.0"
595 /* Utility/helper methods */
597 /* Write helper method */
598 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
600 writel(data, pp->base + offset);
603 /* Read helper method */
604 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
606 return readl(pp->base + offset);
609 /* Increment txq get counter */
610 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
612 txq->txq_get_index++;
613 if (txq->txq_get_index == txq->size)
614 txq->txq_get_index = 0;
617 /* Increment txq put counter */
618 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
620 txq->txq_put_index++;
621 if (txq->txq_put_index == txq->size)
622 txq->txq_put_index = 0;
626 /* Clear all MIB counters */
627 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
632 /* Perform dummy reads from MIB counters */
633 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
634 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
635 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
636 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
639 /* Get System Network Statistics */
640 static struct rtnl_link_stats64 *
641 mvneta_get_stats64(struct net_device *dev,
642 struct rtnl_link_stats64 *stats)
644 struct mvneta_port *pp = netdev_priv(dev);
648 for_each_possible_cpu(cpu) {
649 struct mvneta_pcpu_stats *cpu_stats;
655 cpu_stats = per_cpu_ptr(pp->stats, cpu);
657 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
658 rx_packets = cpu_stats->rx_packets;
659 rx_bytes = cpu_stats->rx_bytes;
660 tx_packets = cpu_stats->tx_packets;
661 tx_bytes = cpu_stats->tx_bytes;
662 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
664 stats->rx_packets += rx_packets;
665 stats->rx_bytes += rx_bytes;
666 stats->tx_packets += tx_packets;
667 stats->tx_bytes += tx_bytes;
670 stats->rx_errors = dev->stats.rx_errors;
671 stats->rx_dropped = dev->stats.rx_dropped;
673 stats->tx_dropped = dev->stats.tx_dropped;
678 /* Rx descriptors helper methods */
680 /* Checks whether the RX descriptor having this status is both the first
681 * and the last descriptor for the RX packet. Each RX packet is currently
682 * received through a single RX descriptor, so not having each RX
683 * descriptor with its first and last bits set is an error
685 static int mvneta_rxq_desc_is_first_last(u32 status)
687 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
688 MVNETA_RXD_FIRST_LAST_DESC;
691 /* Add number of descriptors ready to receive new packets */
692 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
693 struct mvneta_rx_queue *rxq,
696 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
699 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
700 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
701 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
702 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
703 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
706 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
707 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
710 /* Get number of RX descriptors occupied by received packets */
711 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
712 struct mvneta_rx_queue *rxq)
716 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
717 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
720 /* Update num of rx desc called upon return from rx path or
721 * from mvneta_rxq_drop_pkts().
723 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
724 struct mvneta_rx_queue *rxq,
725 int rx_done, int rx_filled)
729 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
731 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
732 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
736 /* Only 255 descriptors can be added at once */
737 while ((rx_done > 0) || (rx_filled > 0)) {
738 if (rx_done <= 0xff) {
745 if (rx_filled <= 0xff) {
746 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
749 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
752 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
756 /* Get pointer to next RX descriptor to be processed by SW */
757 static struct mvneta_rx_desc *
758 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
760 int rx_desc = rxq->next_desc_to_proc;
762 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
763 prefetch(rxq->descs + rxq->next_desc_to_proc);
764 return rxq->descs + rx_desc;
767 /* Change maximum receive size of the port. */
768 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
772 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
773 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
774 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
775 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
776 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
780 /* Set rx queue offset */
781 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
782 struct mvneta_rx_queue *rxq,
787 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
788 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
791 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
792 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
796 /* Tx descriptors helper methods */
798 /* Update HW with number of TX descriptors to be sent */
799 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
800 struct mvneta_tx_queue *txq,
805 /* Only 255 descriptors can be added at once ; Assume caller
806 * process TX desriptors in quanta less than 256
809 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
812 /* Get pointer to next TX descriptor to be processed (send) by HW */
813 static struct mvneta_tx_desc *
814 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
816 int tx_desc = txq->next_desc_to_proc;
818 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
819 return txq->descs + tx_desc;
822 /* Release the last allocated TX descriptor. Useful to handle DMA
823 * mapping failures in the TX path.
825 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
827 if (txq->next_desc_to_proc == 0)
828 txq->next_desc_to_proc = txq->last_desc - 1;
830 txq->next_desc_to_proc--;
833 /* Set rxq buf size */
834 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
835 struct mvneta_rx_queue *rxq,
840 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
842 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
843 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
845 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
848 /* Disable buffer management (BM) */
849 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
850 struct mvneta_rx_queue *rxq)
854 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
855 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
856 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
859 /* Enable buffer management (BM) */
860 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
861 struct mvneta_rx_queue *rxq)
865 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
866 val |= MVNETA_RXQ_HW_BUF_ALLOC;
867 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
870 /* Notify HW about port's assignment of pool for bigger packets */
871 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
872 struct mvneta_rx_queue *rxq)
876 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
877 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
878 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
880 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
883 /* Notify HW about port's assignment of pool for smaller packets */
884 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
885 struct mvneta_rx_queue *rxq)
889 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
890 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
891 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
893 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
896 /* Set port's receive buffer size for assigned BM pool */
897 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
903 if (!IS_ALIGNED(buf_size, 8)) {
904 dev_warn(pp->dev->dev.parent,
905 "illegal buf_size value %d, round to %d\n",
906 buf_size, ALIGN(buf_size, 8));
907 buf_size = ALIGN(buf_size, 8);
910 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
911 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
912 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
915 /* Configure MBUS window in order to enable access BM internal SRAM */
916 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
919 u32 win_enable, win_protect;
922 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
924 if (pp->bm_win_id < 0) {
925 /* Find first not occupied window */
926 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
927 if (win_enable & (1 << i)) {
932 if (i == MVNETA_MAX_DECODE_WIN)
938 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
939 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
942 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
944 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
945 (attr << 8) | target);
947 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
949 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
950 win_protect |= 3 << (2 * i);
951 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
953 win_enable &= ~(1 << i);
954 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
959 /* Assign and initialize pools for port. In case of fail
960 * buffer manager will remain disabled for current port.
962 static int mvneta_bm_port_init(struct platform_device *pdev,
963 struct mvneta_port *pp)
965 struct device_node *dn = pdev->dev.of_node;
966 u32 long_pool_id, short_pool_id, wsize;
970 /* Get BM window information */
971 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
978 /* Open NETA -> BM window */
979 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
982 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
986 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
987 netdev_info(pp->dev, "missing long pool id\n");
991 /* Create port's long pool depending on mtu */
992 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
993 MVNETA_BM_LONG, pp->id,
994 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
995 if (!pp->pool_long) {
996 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1000 pp->pool_long->port_map |= 1 << pp->id;
1002 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1005 /* If short pool id is not defined, assume using single pool */
1006 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1007 short_pool_id = long_pool_id;
1009 /* Create port's short pool */
1010 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1011 MVNETA_BM_SHORT, pp->id,
1012 MVNETA_BM_SHORT_PKT_SIZE);
1013 if (!pp->pool_short) {
1014 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1015 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1019 if (short_pool_id != long_pool_id) {
1020 pp->pool_short->port_map |= 1 << pp->id;
1021 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1022 pp->pool_short->id);
1028 /* Update settings of a pool for bigger packets */
1029 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1031 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1032 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1035 /* Release all buffers from long pool */
1036 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1037 if (hwbm_pool->buf_num) {
1038 WARN(1, "cannot free all buffers in pool %d\n",
1043 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1044 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1045 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1046 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1048 /* Fill entire long pool */
1049 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1050 if (num != hwbm_pool->size) {
1051 WARN(1, "pool %d: %d of %d allocated\n",
1052 bm_pool->id, num, hwbm_pool->size);
1055 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1060 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1061 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1064 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1065 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1068 /* Start the Ethernet port RX and TX activity */
1069 static void mvneta_port_up(struct mvneta_port *pp)
1074 /* Enable all initialized TXs. */
1076 for (queue = 0; queue < txq_number; queue++) {
1077 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1078 if (txq->descs != NULL)
1079 q_map |= (1 << queue);
1081 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1084 /* Enable all initialized RXQs. */
1085 for (queue = 0; queue < rxq_number; queue++) {
1086 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1088 if (rxq->descs != NULL)
1089 q_map |= (1 << queue);
1091 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1094 /* Stop the Ethernet port activity */
1095 static void mvneta_port_down(struct mvneta_port *pp)
1100 /* Stop Rx port activity. Check port Rx activity. */
1101 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1103 /* Issue stop command for active channels only */
1105 mvreg_write(pp, MVNETA_RXQ_CMD,
1106 val << MVNETA_RXQ_DISABLE_SHIFT);
1108 /* Wait for all Rx activity to terminate. */
1111 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1112 netdev_warn(pp->dev,
1113 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1119 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1120 } while (val & MVNETA_RXQ_ENABLE_MASK);
1122 /* Stop Tx port activity. Check port Tx activity. Issue stop
1123 * command for active channels only
1125 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1128 mvreg_write(pp, MVNETA_TXQ_CMD,
1129 (val << MVNETA_TXQ_DISABLE_SHIFT));
1131 /* Wait for all Tx activity to terminate. */
1134 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1135 netdev_warn(pp->dev,
1136 "TIMEOUT for TX stopped status=0x%08x\n",
1142 /* Check TX Command reg that all Txqs are stopped */
1143 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1145 } while (val & MVNETA_TXQ_ENABLE_MASK);
1147 /* Double check to verify that TX FIFO is empty */
1150 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1151 netdev_warn(pp->dev,
1152 "TX FIFO empty timeout status=0x%08x\n",
1158 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1159 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1160 (val & MVNETA_TX_IN_PRGRS));
1165 /* Enable the port by setting the port enable bit of the MAC control register */
1166 static void mvneta_port_enable(struct mvneta_port *pp)
1171 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1172 val |= MVNETA_GMAC0_PORT_ENABLE;
1173 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1176 /* Disable the port and wait for about 200 usec before retuning */
1177 static void mvneta_port_disable(struct mvneta_port *pp)
1181 /* Reset the Enable bit in the Serial Control Register */
1182 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1183 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1184 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1193 /* Multicast tables methods */
1195 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1196 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1204 val = 0x1 | (queue << 1);
1205 val |= (val << 24) | (val << 16) | (val << 8);
1208 for (offset = 0; offset <= 0xc; offset += 4)
1209 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1212 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1213 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1221 val = 0x1 | (queue << 1);
1222 val |= (val << 24) | (val << 16) | (val << 8);
1225 for (offset = 0; offset <= 0xfc; offset += 4)
1226 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1230 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1231 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1237 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1240 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1241 val = 0x1 | (queue << 1);
1242 val |= (val << 24) | (val << 16) | (val << 8);
1245 for (offset = 0; offset <= 0xfc; offset += 4)
1246 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1249 static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
1254 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1255 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1256 MVNETA_GMAC_FORCE_LINK_DOWN |
1257 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1258 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1259 MVNETA_GMAC_AN_SPEED_EN |
1260 MVNETA_GMAC_AN_DUPLEX_EN;
1261 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1263 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1264 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1265 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1267 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1268 val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
1269 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1271 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1272 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1273 MVNETA_GMAC_AN_SPEED_EN |
1274 MVNETA_GMAC_AN_DUPLEX_EN);
1275 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1277 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1278 val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
1279 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1281 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1282 val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
1283 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1287 static void mvneta_percpu_unmask_interrupt(void *arg)
1289 struct mvneta_port *pp = arg;
1291 /* All the queue are unmasked, but actually only the ones
1292 * mapped to this CPU will be unmasked
1294 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1295 MVNETA_RX_INTR_MASK_ALL |
1296 MVNETA_TX_INTR_MASK_ALL |
1297 MVNETA_MISCINTR_INTR_MASK);
1300 static void mvneta_percpu_mask_interrupt(void *arg)
1302 struct mvneta_port *pp = arg;
1304 /* All the queue are masked, but actually only the ones
1305 * mapped to this CPU will be masked
1307 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1308 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1309 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1312 static void mvneta_percpu_clear_intr_cause(void *arg)
1314 struct mvneta_port *pp = arg;
1316 /* All the queue are cleared, but actually only the ones
1317 * mapped to this CPU will be cleared
1319 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1320 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1321 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1324 /* This method sets defaults to the NETA port:
1325 * Clears interrupt Cause and Mask registers.
1326 * Clears all MAC tables.
1327 * Sets defaults to all registers.
1328 * Resets RX and TX descriptor rings.
1330 * This method can be called after mvneta_port_down() to return the port
1331 * settings to defaults.
1333 static void mvneta_defaults_set(struct mvneta_port *pp)
1338 int max_cpu = num_present_cpus();
1340 /* Clear all Cause registers */
1341 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1343 /* Mask all interrupts */
1344 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1345 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1347 /* Enable MBUS Retry bit16 */
1348 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1350 /* Set CPU queue access map. CPUs are assigned to the RX and
1351 * TX queues modulo their number. If there is only one TX
1352 * queue then it is assigned to the CPU associated to the
1355 for_each_present_cpu(cpu) {
1356 int rxq_map = 0, txq_map = 0;
1359 for (rxq = 0; rxq < rxq_number; rxq++)
1360 if ((rxq % max_cpu) == cpu)
1361 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1363 for (txq = 0; txq < txq_number; txq++)
1364 if ((txq % max_cpu) == cpu)
1365 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1367 /* With only one TX queue we configure a special case
1368 * which will allow to get all the irq on a single
1371 if (txq_number == 1)
1372 txq_map = (cpu == pp->rxq_def) ?
1373 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1375 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1378 /* Reset RX and TX DMAs */
1379 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1380 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1382 /* Disable Legacy WRR, Disable EJP, Release from reset */
1383 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1384 for (queue = 0; queue < txq_number; queue++) {
1385 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1386 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1389 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1390 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1392 /* Set Port Acceleration Mode */
1394 /* HW buffer management + legacy parser */
1395 val = MVNETA_ACC_MODE_EXT2;
1397 /* SW buffer management + legacy parser */
1398 val = MVNETA_ACC_MODE_EXT1;
1399 mvreg_write(pp, MVNETA_ACC_MODE, val);
1402 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1404 /* Update val of portCfg register accordingly with all RxQueue types */
1405 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1406 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1409 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1410 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1412 /* Build PORT_SDMA_CONFIG_REG */
1415 /* Default burst size */
1416 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1417 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1418 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1420 #if defined(__BIG_ENDIAN)
1421 val |= MVNETA_DESC_SWAP;
1424 /* Assign port SDMA configuration */
1425 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1427 /* Disable PHY polling in hardware, since we're using the
1428 * kernel phylib to do this.
1430 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1431 val &= ~MVNETA_PHY_POLLING_ENABLE;
1432 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1434 mvneta_set_autoneg(pp, pp->use_inband_status);
1435 mvneta_set_ucast_table(pp, -1);
1436 mvneta_set_special_mcast_table(pp, -1);
1437 mvneta_set_other_mcast_table(pp, -1);
1439 /* Set port interrupt enable register - default enable all */
1440 mvreg_write(pp, MVNETA_INTR_ENABLE,
1441 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1442 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1444 mvneta_mib_counters_clear(pp);
1447 /* Set max sizes for tx queues */
1448 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1454 mtu = max_tx_size * 8;
1455 if (mtu > MVNETA_TX_MTU_MAX)
1456 mtu = MVNETA_TX_MTU_MAX;
1459 val = mvreg_read(pp, MVNETA_TX_MTU);
1460 val &= ~MVNETA_TX_MTU_MAX;
1462 mvreg_write(pp, MVNETA_TX_MTU, val);
1464 /* TX token size and all TXQs token size must be larger that MTU */
1465 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1467 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1470 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1472 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1474 for (queue = 0; queue < txq_number; queue++) {
1475 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1477 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1480 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1482 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1487 /* Set unicast address */
1488 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1491 unsigned int unicast_reg;
1492 unsigned int tbl_offset;
1493 unsigned int reg_offset;
1495 /* Locate the Unicast table entry */
1496 last_nibble = (0xf & last_nibble);
1498 /* offset from unicast tbl base */
1499 tbl_offset = (last_nibble / 4) * 4;
1501 /* offset within the above reg */
1502 reg_offset = last_nibble % 4;
1504 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1507 /* Clear accepts frame bit at specified unicast DA tbl entry */
1508 unicast_reg &= ~(0xff << (8 * reg_offset));
1510 unicast_reg &= ~(0xff << (8 * reg_offset));
1511 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1514 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1517 /* Set mac address */
1518 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1525 mac_l = (addr[4] << 8) | (addr[5]);
1526 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1527 (addr[2] << 8) | (addr[3] << 0);
1529 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1530 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1533 /* Accept frames of this address */
1534 mvneta_set_ucast_addr(pp, addr[5], queue);
1537 /* Set the number of packets that will be received before RX interrupt
1538 * will be generated by HW.
1540 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1541 struct mvneta_rx_queue *rxq, u32 value)
1543 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1544 value | MVNETA_RXQ_NON_OCCUPIED(0));
1545 rxq->pkts_coal = value;
1548 /* Set the time delay in usec before RX interrupt will be generated by
1551 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1552 struct mvneta_rx_queue *rxq, u32 value)
1555 unsigned long clk_rate;
1557 clk_rate = clk_get_rate(pp->clk);
1558 val = (clk_rate / 1000000) * value;
1560 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1561 rxq->time_coal = value;
1564 /* Set threshold for TX_DONE pkts coalescing */
1565 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1566 struct mvneta_tx_queue *txq, u32 value)
1570 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1572 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1573 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1575 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1577 txq->done_pkts_coal = value;
1580 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1581 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1582 u32 phys_addr, u32 cookie)
1584 rx_desc->buf_cookie = cookie;
1585 rx_desc->buf_phys_addr = phys_addr;
1588 /* Decrement sent descriptors counter */
1589 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1590 struct mvneta_tx_queue *txq,
1595 /* Only 255 TX descriptors can be updated at once */
1596 while (sent_desc > 0xff) {
1597 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1598 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1599 sent_desc = sent_desc - 0xff;
1602 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1603 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1606 /* Get number of TX descriptors already sent by HW */
1607 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1608 struct mvneta_tx_queue *txq)
1613 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1614 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1615 MVNETA_TXQ_SENT_DESC_SHIFT;
1620 /* Get number of sent descriptors and decrement counter.
1621 * The number of sent descriptors is returned.
1623 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1624 struct mvneta_tx_queue *txq)
1628 /* Get number of sent descriptors */
1629 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1631 /* Decrement sent descriptors counter */
1633 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1638 /* Set TXQ descriptors fields relevant for CSUM calculation */
1639 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1640 int ip_hdr_len, int l4_proto)
1644 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1645 * G_L4_chk, L4_type; required only for checksum
1648 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1649 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1651 if (l3_proto == htons(ETH_P_IP))
1652 command |= MVNETA_TXD_IP_CSUM;
1654 command |= MVNETA_TX_L3_IP6;
1656 if (l4_proto == IPPROTO_TCP)
1657 command |= MVNETA_TX_L4_CSUM_FULL;
1658 else if (l4_proto == IPPROTO_UDP)
1659 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1661 command |= MVNETA_TX_L4_CSUM_NOT;
1667 /* Display more error info */
1668 static void mvneta_rx_error(struct mvneta_port *pp,
1669 struct mvneta_rx_desc *rx_desc)
1671 u32 status = rx_desc->status;
1673 if (!mvneta_rxq_desc_is_first_last(status)) {
1675 "bad rx status %08x (buffer oversize), size=%d\n",
1676 status, rx_desc->data_size);
1680 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1681 case MVNETA_RXD_ERR_CRC:
1682 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1683 status, rx_desc->data_size);
1685 case MVNETA_RXD_ERR_OVERRUN:
1686 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1687 status, rx_desc->data_size);
1689 case MVNETA_RXD_ERR_LEN:
1690 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1691 status, rx_desc->data_size);
1693 case MVNETA_RXD_ERR_RESOURCE:
1694 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1695 status, rx_desc->data_size);
1700 /* Handle RX checksum offload based on the descriptor's status */
1701 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1702 struct sk_buff *skb)
1704 if ((status & MVNETA_RXD_L3_IP4) &&
1705 (status & MVNETA_RXD_L4_CSUM_OK)) {
1707 skb->ip_summed = CHECKSUM_UNNECESSARY;
1711 skb->ip_summed = CHECKSUM_NONE;
1714 /* Return tx queue pointer (find last set bit) according to <cause> returned
1715 * form tx_done reg. <cause> must not be null. The return value is always a
1716 * valid queue for matching the first one found in <cause>.
1718 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1721 int queue = fls(cause) - 1;
1723 return &pp->txqs[queue];
1726 /* Free tx queue skbuffs */
1727 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1728 struct mvneta_tx_queue *txq, int num)
1732 for (i = 0; i < num; i++) {
1733 struct mvneta_tx_desc *tx_desc = txq->descs +
1735 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1737 mvneta_txq_inc_get(txq);
1739 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1740 dma_unmap_single(pp->dev->dev.parent,
1741 tx_desc->buf_phys_addr,
1742 tx_desc->data_size, DMA_TO_DEVICE);
1745 dev_kfree_skb_any(skb);
1749 /* Handle end of transmission */
1750 static void mvneta_txq_done(struct mvneta_port *pp,
1751 struct mvneta_tx_queue *txq)
1753 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1756 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1760 mvneta_txq_bufs_free(pp, txq, tx_done);
1762 txq->count -= tx_done;
1764 if (netif_tx_queue_stopped(nq)) {
1765 if (txq->count <= txq->tx_wake_threshold)
1766 netif_tx_wake_queue(nq);
1770 void *mvneta_frag_alloc(unsigned int frag_size)
1772 if (likely(frag_size <= PAGE_SIZE))
1773 return netdev_alloc_frag(frag_size);
1775 return kmalloc(frag_size, GFP_ATOMIC);
1777 EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
1779 void mvneta_frag_free(unsigned int frag_size, void *data)
1781 if (likely(frag_size <= PAGE_SIZE))
1782 skb_free_frag(data);
1786 EXPORT_SYMBOL_GPL(mvneta_frag_free);
1788 /* Refill processing for SW buffer management */
1789 static int mvneta_rx_refill(struct mvneta_port *pp,
1790 struct mvneta_rx_desc *rx_desc)
1793 dma_addr_t phys_addr;
1796 data = mvneta_frag_alloc(pp->frag_size);
1800 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1801 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1803 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1804 mvneta_frag_free(pp->frag_size, data);
1808 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1812 /* Handle tx checksum */
1813 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1815 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1817 __be16 l3_proto = vlan_get_protocol(skb);
1820 if (l3_proto == htons(ETH_P_IP)) {
1821 struct iphdr *ip4h = ip_hdr(skb);
1823 /* Calculate IPv4 checksum and L4 checksum */
1824 ip_hdr_len = ip4h->ihl;
1825 l4_proto = ip4h->protocol;
1826 } else if (l3_proto == htons(ETH_P_IPV6)) {
1827 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1829 /* Read l4_protocol from one of IPv6 extra headers */
1830 if (skb_network_header_len(skb) > 0)
1831 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1832 l4_proto = ip6h->nexthdr;
1834 return MVNETA_TX_L4_CSUM_NOT;
1836 return mvneta_txq_desc_csum(skb_network_offset(skb),
1837 l3_proto, ip_hdr_len, l4_proto);
1840 return MVNETA_TX_L4_CSUM_NOT;
1843 /* Drop packets received by the RXQ and free buffers */
1844 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1845 struct mvneta_rx_queue *rxq)
1849 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1851 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1854 for (i = 0; i < rx_done; i++) {
1855 struct mvneta_rx_desc *rx_desc =
1856 mvneta_rxq_next_desc_get(rxq);
1857 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1858 struct mvneta_bm_pool *bm_pool;
1860 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1861 /* Return dropped buffer to the pool */
1862 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1863 rx_desc->buf_phys_addr);
1868 for (i = 0; i < rxq->size; i++) {
1869 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1870 void *data = (void *)rx_desc->buf_cookie;
1872 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1873 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1874 mvneta_frag_free(pp->frag_size, data);
1878 /* Main rx processing when using software buffer management */
1879 static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
1880 struct mvneta_rx_queue *rxq)
1882 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1883 struct net_device *dev = pp->dev;
1888 /* Get number of received packets */
1889 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1891 if (rx_todo > rx_done)
1896 /* Fairness NAPI loop */
1897 while (rx_done < rx_todo) {
1898 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1899 struct sk_buff *skb;
1900 unsigned char *data;
1901 dma_addr_t phys_addr;
1902 u32 rx_status, frag_size;
1906 rx_status = rx_desc->status;
1907 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1908 data = (unsigned char *)rx_desc->buf_cookie;
1909 phys_addr = rx_desc->buf_phys_addr;
1911 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1912 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1913 mvneta_rx_error(pp, rx_desc);
1915 dev->stats.rx_errors++;
1916 /* leave the descriptor untouched */
1920 if (rx_bytes <= rx_copybreak) {
1921 /* better copy a small frame and not unmap the DMA region */
1922 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1924 goto err_drop_frame;
1926 dma_sync_single_range_for_cpu(dev->dev.parent,
1927 rx_desc->buf_phys_addr,
1928 MVNETA_MH_SIZE + NET_SKB_PAD,
1931 memcpy(skb_put(skb, rx_bytes),
1932 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1935 skb->protocol = eth_type_trans(skb, dev);
1936 mvneta_rx_csum(pp, rx_status, skb);
1937 napi_gro_receive(&port->napi, skb);
1940 rcvd_bytes += rx_bytes;
1942 /* leave the descriptor and buffer untouched */
1946 /* Refill processing */
1947 err = mvneta_rx_refill(pp, rx_desc);
1949 netdev_err(dev, "Linux processing - Can't refill\n");
1951 goto err_drop_frame;
1954 frag_size = pp->frag_size;
1956 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
1958 /* After refill old buffer has to be unmapped regardless
1959 * the skb is successfully built or not.
1961 dma_unmap_single(dev->dev.parent, phys_addr,
1962 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1966 goto err_drop_frame;
1969 rcvd_bytes += rx_bytes;
1971 /* Linux processing */
1972 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1973 skb_put(skb, rx_bytes);
1975 skb->protocol = eth_type_trans(skb, dev);
1977 mvneta_rx_csum(pp, rx_status, skb);
1979 napi_gro_receive(&port->napi, skb);
1983 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1985 u64_stats_update_begin(&stats->syncp);
1986 stats->rx_packets += rcvd_pkts;
1987 stats->rx_bytes += rcvd_bytes;
1988 u64_stats_update_end(&stats->syncp);
1991 /* Update rxq management counters */
1992 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1997 /* Main rx processing when using hardware buffer management */
1998 static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
1999 struct mvneta_rx_queue *rxq)
2001 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2002 struct net_device *dev = pp->dev;
2007 /* Get number of received packets */
2008 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2010 if (rx_todo > rx_done)
2015 /* Fairness NAPI loop */
2016 while (rx_done < rx_todo) {
2017 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2018 struct mvneta_bm_pool *bm_pool = NULL;
2019 struct sk_buff *skb;
2020 unsigned char *data;
2021 dma_addr_t phys_addr;
2022 u32 rx_status, frag_size;
2027 rx_status = rx_desc->status;
2028 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2029 data = (unsigned char *)rx_desc->buf_cookie;
2030 phys_addr = rx_desc->buf_phys_addr;
2031 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2032 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2034 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2035 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2036 err_drop_frame_ret_pool:
2037 /* Return the buffer to the pool */
2038 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2039 rx_desc->buf_phys_addr);
2041 dev->stats.rx_errors++;
2042 mvneta_rx_error(pp, rx_desc);
2043 /* leave the descriptor untouched */
2047 if (rx_bytes <= rx_copybreak) {
2048 /* better copy a small frame and not unmap the DMA region */
2049 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2051 goto err_drop_frame_ret_pool;
2053 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2054 rx_desc->buf_phys_addr,
2055 MVNETA_MH_SIZE + NET_SKB_PAD,
2058 memcpy(skb_put(skb, rx_bytes),
2059 data + MVNETA_MH_SIZE + NET_SKB_PAD,
2062 skb->protocol = eth_type_trans(skb, dev);
2063 mvneta_rx_csum(pp, rx_status, skb);
2064 napi_gro_receive(&port->napi, skb);
2067 rcvd_bytes += rx_bytes;
2069 /* Return the buffer to the pool */
2070 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2071 rx_desc->buf_phys_addr);
2073 /* leave the descriptor and buffer untouched */
2077 /* Refill processing */
2078 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2080 netdev_err(dev, "Linux processing - Can't refill\n");
2082 goto err_drop_frame_ret_pool;
2085 frag_size = bm_pool->hwbm_pool.frag_size;
2087 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2089 /* After refill old buffer has to be unmapped regardless
2090 * the skb is successfully built or not.
2092 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2093 bm_pool->buf_size, DMA_FROM_DEVICE);
2095 goto err_drop_frame;
2098 rcvd_bytes += rx_bytes;
2100 /* Linux processing */
2101 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2102 skb_put(skb, rx_bytes);
2104 skb->protocol = eth_type_trans(skb, dev);
2106 mvneta_rx_csum(pp, rx_status, skb);
2108 napi_gro_receive(&port->napi, skb);
2112 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2114 u64_stats_update_begin(&stats->syncp);
2115 stats->rx_packets += rcvd_pkts;
2116 stats->rx_bytes += rcvd_bytes;
2117 u64_stats_update_end(&stats->syncp);
2120 /* Update rxq management counters */
2121 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2127 mvneta_tso_put_hdr(struct sk_buff *skb,
2128 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2130 struct mvneta_tx_desc *tx_desc;
2131 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2133 txq->tx_skb[txq->txq_put_index] = NULL;
2134 tx_desc = mvneta_txq_next_desc_get(txq);
2135 tx_desc->data_size = hdr_len;
2136 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2137 tx_desc->command |= MVNETA_TXD_F_DESC;
2138 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2139 txq->txq_put_index * TSO_HEADER_SIZE;
2140 mvneta_txq_inc_put(txq);
2144 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2145 struct sk_buff *skb, char *data, int size,
2146 bool last_tcp, bool is_last)
2148 struct mvneta_tx_desc *tx_desc;
2150 tx_desc = mvneta_txq_next_desc_get(txq);
2151 tx_desc->data_size = size;
2152 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2153 size, DMA_TO_DEVICE);
2154 if (unlikely(dma_mapping_error(dev->dev.parent,
2155 tx_desc->buf_phys_addr))) {
2156 mvneta_txq_desc_put(txq);
2160 tx_desc->command = 0;
2161 txq->tx_skb[txq->txq_put_index] = NULL;
2164 /* last descriptor in the TCP packet */
2165 tx_desc->command = MVNETA_TXD_L_DESC;
2167 /* last descriptor in SKB */
2169 txq->tx_skb[txq->txq_put_index] = skb;
2171 mvneta_txq_inc_put(txq);
2175 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2176 struct mvneta_tx_queue *txq)
2178 int total_len, data_left;
2180 struct mvneta_port *pp = netdev_priv(dev);
2182 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2185 /* Count needed descriptors */
2186 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2189 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2190 pr_info("*** Is this even possible???!?!?\n");
2194 /* Initialize the TSO handler, and prepare the first payload */
2195 tso_start(skb, &tso);
2197 total_len = skb->len - hdr_len;
2198 while (total_len > 0) {
2201 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2202 total_len -= data_left;
2205 /* prepare packet headers: MAC + IP + TCP */
2206 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2207 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2209 mvneta_tso_put_hdr(skb, pp, txq);
2211 while (data_left > 0) {
2215 size = min_t(int, tso.size, data_left);
2217 if (mvneta_tso_put_data(dev, txq, skb,
2224 tso_build_data(skb, &tso, size);
2231 /* Release all used data descriptors; header descriptors must not
2234 for (i = desc_count - 1; i >= 0; i--) {
2235 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2236 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2237 dma_unmap_single(pp->dev->dev.parent,
2238 tx_desc->buf_phys_addr,
2241 mvneta_txq_desc_put(txq);
2246 /* Handle tx fragmentation processing */
2247 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2248 struct mvneta_tx_queue *txq)
2250 struct mvneta_tx_desc *tx_desc;
2251 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2253 for (i = 0; i < nr_frags; i++) {
2254 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2255 void *addr = page_address(frag->page.p) + frag->page_offset;
2257 tx_desc = mvneta_txq_next_desc_get(txq);
2258 tx_desc->data_size = frag->size;
2260 tx_desc->buf_phys_addr =
2261 dma_map_single(pp->dev->dev.parent, addr,
2262 tx_desc->data_size, DMA_TO_DEVICE);
2264 if (dma_mapping_error(pp->dev->dev.parent,
2265 tx_desc->buf_phys_addr)) {
2266 mvneta_txq_desc_put(txq);
2270 if (i == nr_frags - 1) {
2271 /* Last descriptor */
2272 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2273 txq->tx_skb[txq->txq_put_index] = skb;
2275 /* Descriptor in the middle: Not First, Not Last */
2276 tx_desc->command = 0;
2277 txq->tx_skb[txq->txq_put_index] = NULL;
2279 mvneta_txq_inc_put(txq);
2285 /* Release all descriptors that were used to map fragments of
2286 * this packet, as well as the corresponding DMA mappings
2288 for (i = i - 1; i >= 0; i--) {
2289 tx_desc = txq->descs + i;
2290 dma_unmap_single(pp->dev->dev.parent,
2291 tx_desc->buf_phys_addr,
2294 mvneta_txq_desc_put(txq);
2300 /* Main tx processing */
2301 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2303 struct mvneta_port *pp = netdev_priv(dev);
2304 u16 txq_id = skb_get_queue_mapping(skb);
2305 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2306 struct mvneta_tx_desc *tx_desc;
2311 if (!netif_running(dev))
2314 if (skb_is_gso(skb)) {
2315 frags = mvneta_tx_tso(skb, dev, txq);
2319 frags = skb_shinfo(skb)->nr_frags + 1;
2321 /* Get a descriptor for the first part of the packet */
2322 tx_desc = mvneta_txq_next_desc_get(txq);
2324 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2326 tx_desc->data_size = skb_headlen(skb);
2328 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2331 if (unlikely(dma_mapping_error(dev->dev.parent,
2332 tx_desc->buf_phys_addr))) {
2333 mvneta_txq_desc_put(txq);
2339 /* First and Last descriptor */
2340 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2341 tx_desc->command = tx_cmd;
2342 txq->tx_skb[txq->txq_put_index] = skb;
2343 mvneta_txq_inc_put(txq);
2345 /* First but not Last */
2346 tx_cmd |= MVNETA_TXD_F_DESC;
2347 txq->tx_skb[txq->txq_put_index] = NULL;
2348 mvneta_txq_inc_put(txq);
2349 tx_desc->command = tx_cmd;
2350 /* Continue with other skb fragments */
2351 if (mvneta_tx_frag_process(pp, skb, txq)) {
2352 dma_unmap_single(dev->dev.parent,
2353 tx_desc->buf_phys_addr,
2356 mvneta_txq_desc_put(txq);
2364 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2365 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2367 txq->count += frags;
2368 mvneta_txq_pend_desc_add(pp, txq, frags);
2370 if (txq->count >= txq->tx_stop_threshold)
2371 netif_tx_stop_queue(nq);
2373 u64_stats_update_begin(&stats->syncp);
2374 stats->tx_packets++;
2375 stats->tx_bytes += len;
2376 u64_stats_update_end(&stats->syncp);
2378 dev->stats.tx_dropped++;
2379 dev_kfree_skb_any(skb);
2382 return NETDEV_TX_OK;
2386 /* Free tx resources, when resetting a port */
2387 static void mvneta_txq_done_force(struct mvneta_port *pp,
2388 struct mvneta_tx_queue *txq)
2391 int tx_done = txq->count;
2393 mvneta_txq_bufs_free(pp, txq, tx_done);
2397 txq->txq_put_index = 0;
2398 txq->txq_get_index = 0;
2401 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2402 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2404 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2406 struct mvneta_tx_queue *txq;
2407 struct netdev_queue *nq;
2409 while (cause_tx_done) {
2410 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2412 nq = netdev_get_tx_queue(pp->dev, txq->id);
2413 __netif_tx_lock(nq, smp_processor_id());
2416 mvneta_txq_done(pp, txq);
2418 __netif_tx_unlock(nq);
2419 cause_tx_done &= ~((1 << txq->id));
2423 /* Compute crc8 of the specified address, using a unique algorithm ,
2424 * according to hw spec, different than generic crc8 algorithm
2426 static int mvneta_addr_crc(unsigned char *addr)
2431 for (i = 0; i < ETH_ALEN; i++) {
2434 crc = (crc ^ addr[i]) << 8;
2435 for (j = 7; j >= 0; j--) {
2436 if (crc & (0x100 << j))
2444 /* This method controls the net device special MAC multicast support.
2445 * The Special Multicast Table for MAC addresses supports MAC of the form
2446 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2447 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2448 * Table entries in the DA-Filter table. This method set the Special
2449 * Multicast Table appropriate entry.
2451 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2452 unsigned char last_byte,
2455 unsigned int smc_table_reg;
2456 unsigned int tbl_offset;
2457 unsigned int reg_offset;
2459 /* Register offset from SMC table base */
2460 tbl_offset = (last_byte / 4);
2461 /* Entry offset within the above reg */
2462 reg_offset = last_byte % 4;
2464 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2468 smc_table_reg &= ~(0xff << (8 * reg_offset));
2470 smc_table_reg &= ~(0xff << (8 * reg_offset));
2471 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2474 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2478 /* This method controls the network device Other MAC multicast support.
2479 * The Other Multicast Table is used for multicast of another type.
2480 * A CRC-8 is used as an index to the Other Multicast Table entries
2481 * in the DA-Filter table.
2482 * The method gets the CRC-8 value from the calling routine and
2483 * sets the Other Multicast Table appropriate entry according to the
2486 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2490 unsigned int omc_table_reg;
2491 unsigned int tbl_offset;
2492 unsigned int reg_offset;
2494 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2495 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2497 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2500 /* Clear accepts frame bit at specified Other DA table entry */
2501 omc_table_reg &= ~(0xff << (8 * reg_offset));
2503 omc_table_reg &= ~(0xff << (8 * reg_offset));
2504 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2507 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2510 /* The network device supports multicast using two tables:
2511 * 1) Special Multicast Table for MAC addresses of the form
2512 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2513 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2514 * Table entries in the DA-Filter table.
2515 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2516 * is used as an index to the Other Multicast Table entries in the
2519 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2522 unsigned char crc_result = 0;
2524 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2525 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2529 crc_result = mvneta_addr_crc(p_addr);
2531 if (pp->mcast_count[crc_result] == 0) {
2532 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2537 pp->mcast_count[crc_result]--;
2538 if (pp->mcast_count[crc_result] != 0) {
2539 netdev_info(pp->dev,
2540 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2541 pp->mcast_count[crc_result], crc_result);
2545 pp->mcast_count[crc_result]++;
2547 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2552 /* Configure Fitering mode of Ethernet port */
2553 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2556 u32 port_cfg_reg, val;
2558 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2560 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2562 /* Set / Clear UPM bit in port configuration register */
2564 /* Accept all Unicast addresses */
2565 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2566 val |= MVNETA_FORCE_UNI;
2567 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2568 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2570 /* Reject all Unicast addresses */
2571 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2572 val &= ~MVNETA_FORCE_UNI;
2575 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2576 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2579 /* register unicast and multicast addresses */
2580 static void mvneta_set_rx_mode(struct net_device *dev)
2582 struct mvneta_port *pp = netdev_priv(dev);
2583 struct netdev_hw_addr *ha;
2585 if (dev->flags & IFF_PROMISC) {
2586 /* Accept all: Multicast + Unicast */
2587 mvneta_rx_unicast_promisc_set(pp, 1);
2588 mvneta_set_ucast_table(pp, pp->rxq_def);
2589 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2590 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2592 /* Accept single Unicast */
2593 mvneta_rx_unicast_promisc_set(pp, 0);
2594 mvneta_set_ucast_table(pp, -1);
2595 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2597 if (dev->flags & IFF_ALLMULTI) {
2598 /* Accept all multicast */
2599 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2600 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2602 /* Accept only initialized multicast */
2603 mvneta_set_special_mcast_table(pp, -1);
2604 mvneta_set_other_mcast_table(pp, -1);
2606 if (!netdev_mc_empty(dev)) {
2607 netdev_for_each_mc_addr(ha, dev) {
2608 mvneta_mcast_addr_set(pp, ha->addr,
2616 /* Interrupt handling - the callback for request_irq() */
2617 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2619 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2621 disable_percpu_irq(port->pp->dev->irq);
2622 napi_schedule(&port->napi);
2627 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2628 struct phy_device *phy)
2630 struct fixed_phy_status status;
2631 struct fixed_phy_status changed = {};
2632 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2634 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2635 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2636 status.speed = SPEED_1000;
2637 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2638 status.speed = SPEED_100;
2640 status.speed = SPEED_10;
2641 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2645 fixed_phy_update_state(phy, &status, &changed);
2650 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2651 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2652 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2653 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2654 * Each CPU has its own causeRxTx register
2656 static int mvneta_poll(struct napi_struct *napi, int budget)
2661 struct mvneta_port *pp = netdev_priv(napi->dev);
2662 struct net_device *ndev = pp->dev;
2663 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2665 if (!netif_running(pp->dev)) {
2666 napi_complete(&port->napi);
2670 /* Read cause register */
2671 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2672 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2673 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2675 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2676 if (pp->use_inband_status && (cause_misc &
2677 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2678 MVNETA_CAUSE_LINK_CHANGE |
2679 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2680 mvneta_fixed_link_update(pp, ndev->phydev);
2684 /* Release Tx descriptors */
2685 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2686 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2687 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2690 /* For the case where the last mvneta_poll did not process all
2693 cause_rx_tx |= port->cause_rx_tx;
2695 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2697 rx_queue = rx_queue - 1;
2699 rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
2701 rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
2708 napi_complete(&port->napi);
2709 enable_percpu_irq(pp->dev->irq, 0);
2712 port->cause_rx_tx = cause_rx_tx;
2716 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2717 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2722 for (i = 0; i < num; i++) {
2723 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2724 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2725 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2726 __func__, rxq->id, i, num);
2731 /* Add this number of RX descriptors as non occupied (ready to
2734 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2739 /* Free all packets pending transmit from all TXQs and reset TX port */
2740 static void mvneta_tx_reset(struct mvneta_port *pp)
2744 /* free the skb's in the tx ring */
2745 for (queue = 0; queue < txq_number; queue++)
2746 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2748 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2749 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2752 static void mvneta_rx_reset(struct mvneta_port *pp)
2754 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2755 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2758 /* Rx/Tx queue initialization/cleanup methods */
2760 /* Create a specified RX queue */
2761 static int mvneta_rxq_init(struct mvneta_port *pp,
2762 struct mvneta_rx_queue *rxq)
2765 rxq->size = pp->rx_ring_size;
2767 /* Allocate memory for RX descriptors */
2768 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2769 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2770 &rxq->descs_phys, GFP_KERNEL);
2771 if (rxq->descs == NULL)
2774 rxq->last_desc = rxq->size - 1;
2776 /* Set Rx descriptors queue starting address */
2777 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2778 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2781 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2783 /* Set coalescing pkts and time */
2784 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2785 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2788 /* Fill RXQ with buffers from RX pool */
2789 mvneta_rxq_buf_size_set(pp, rxq,
2790 MVNETA_RX_BUF_SIZE(pp->pkt_size));
2791 mvneta_rxq_bm_disable(pp, rxq);
2793 mvneta_rxq_bm_enable(pp, rxq);
2794 mvneta_rxq_long_pool_set(pp, rxq);
2795 mvneta_rxq_short_pool_set(pp, rxq);
2798 mvneta_rxq_fill(pp, rxq, rxq->size);
2803 /* Cleanup Rx queue */
2804 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2805 struct mvneta_rx_queue *rxq)
2807 mvneta_rxq_drop_pkts(pp, rxq);
2810 dma_free_coherent(pp->dev->dev.parent,
2811 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2817 rxq->next_desc_to_proc = 0;
2818 rxq->descs_phys = 0;
2821 /* Create and initialize a tx queue */
2822 static int mvneta_txq_init(struct mvneta_port *pp,
2823 struct mvneta_tx_queue *txq)
2827 txq->size = pp->tx_ring_size;
2829 /* A queue must always have room for at least one skb.
2830 * Therefore, stop the queue when the free entries reaches
2831 * the maximum number of descriptors per skb.
2833 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2834 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2837 /* Allocate memory for TX descriptors */
2838 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2839 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2840 &txq->descs_phys, GFP_KERNEL);
2841 if (txq->descs == NULL)
2844 txq->last_desc = txq->size - 1;
2846 /* Set maximum bandwidth for enabled TXQs */
2847 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2848 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2850 /* Set Tx descriptors queue starting address */
2851 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2852 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2854 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2855 if (txq->tx_skb == NULL) {
2856 dma_free_coherent(pp->dev->dev.parent,
2857 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2858 txq->descs, txq->descs_phys);
2862 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2863 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2864 txq->size * TSO_HEADER_SIZE,
2865 &txq->tso_hdrs_phys, GFP_KERNEL);
2866 if (txq->tso_hdrs == NULL) {
2868 dma_free_coherent(pp->dev->dev.parent,
2869 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2870 txq->descs, txq->descs_phys);
2873 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2875 /* Setup XPS mapping */
2877 cpu = txq->id % num_present_cpus();
2879 cpu = pp->rxq_def % num_present_cpus();
2880 cpumask_set_cpu(cpu, &txq->affinity_mask);
2881 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2886 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2887 static void mvneta_txq_deinit(struct mvneta_port *pp,
2888 struct mvneta_tx_queue *txq)
2893 dma_free_coherent(pp->dev->dev.parent,
2894 txq->size * TSO_HEADER_SIZE,
2895 txq->tso_hdrs, txq->tso_hdrs_phys);
2897 dma_free_coherent(pp->dev->dev.parent,
2898 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2899 txq->descs, txq->descs_phys);
2903 txq->next_desc_to_proc = 0;
2904 txq->descs_phys = 0;
2906 /* Set minimum bandwidth for disabled TXQs */
2907 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2908 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2910 /* Set Tx descriptors queue starting address and size */
2911 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2912 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2915 /* Cleanup all Tx queues */
2916 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2920 for (queue = 0; queue < txq_number; queue++)
2921 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2924 /* Cleanup all Rx queues */
2925 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2929 for (queue = 0; queue < rxq_number; queue++)
2930 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2934 /* Init all Rx queues */
2935 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2939 for (queue = 0; queue < rxq_number; queue++) {
2940 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2943 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2945 mvneta_cleanup_rxqs(pp);
2953 /* Init all tx queues */
2954 static int mvneta_setup_txqs(struct mvneta_port *pp)
2958 for (queue = 0; queue < txq_number; queue++) {
2959 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2961 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2963 mvneta_cleanup_txqs(pp);
2971 static void mvneta_start_dev(struct mvneta_port *pp)
2974 struct net_device *ndev = pp->dev;
2976 mvneta_max_rx_size_set(pp, pp->pkt_size);
2977 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2979 /* start the Rx/Tx activity */
2980 mvneta_port_enable(pp);
2982 /* Enable polling on the port */
2983 for_each_online_cpu(cpu) {
2984 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2986 napi_enable(&port->napi);
2989 /* Unmask interrupts. It has to be done from each CPU */
2990 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
2992 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2993 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2994 MVNETA_CAUSE_LINK_CHANGE |
2995 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2997 phy_start(ndev->phydev);
2998 netif_tx_start_all_queues(pp->dev);
3001 static void mvneta_stop_dev(struct mvneta_port *pp)
3004 struct net_device *ndev = pp->dev;
3006 phy_stop(ndev->phydev);
3008 for_each_online_cpu(cpu) {
3009 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3011 napi_disable(&port->napi);
3014 netif_carrier_off(pp->dev);
3016 mvneta_port_down(pp);
3017 netif_tx_stop_all_queues(pp->dev);
3019 /* Stop the port activity */
3020 mvneta_port_disable(pp);
3022 /* Clear all ethernet port interrupts */
3023 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3025 /* Mask all ethernet port interrupts */
3026 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3028 mvneta_tx_reset(pp);
3029 mvneta_rx_reset(pp);
3032 /* Return positive if MTU is valid */
3033 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
3036 netdev_err(dev, "cannot change mtu to less than 68\n");
3040 /* 9676 == 9700 - 20 and rounding to 8 */
3042 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
3046 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3047 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3048 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3049 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3055 static void mvneta_percpu_enable(void *arg)
3057 struct mvneta_port *pp = arg;
3059 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3062 static void mvneta_percpu_disable(void *arg)
3064 struct mvneta_port *pp = arg;
3066 disable_percpu_irq(pp->dev->irq);
3069 /* Change the device mtu */
3070 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3072 struct mvneta_port *pp = netdev_priv(dev);
3075 mtu = mvneta_check_mtu_valid(dev, mtu);
3081 if (!netif_running(dev)) {
3083 mvneta_bm_update_mtu(pp, mtu);
3085 netdev_update_features(dev);
3089 /* The interface is running, so we have to force a
3090 * reallocation of the queues
3092 mvneta_stop_dev(pp);
3093 on_each_cpu(mvneta_percpu_disable, pp, true);
3095 mvneta_cleanup_txqs(pp);
3096 mvneta_cleanup_rxqs(pp);
3099 mvneta_bm_update_mtu(pp, mtu);
3101 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3102 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3103 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3105 ret = mvneta_setup_rxqs(pp);
3107 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3111 ret = mvneta_setup_txqs(pp);
3113 netdev_err(dev, "unable to setup txqs after MTU change\n");
3117 on_each_cpu(mvneta_percpu_enable, pp, true);
3118 mvneta_start_dev(pp);
3120 netdev_update_features(dev);
3125 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3126 netdev_features_t features)
3128 struct mvneta_port *pp = netdev_priv(dev);
3130 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3131 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3133 "Disable IP checksum for MTU greater than %dB\n",
3140 /* Get mac address */
3141 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3143 u32 mac_addr_l, mac_addr_h;
3145 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3146 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3147 addr[0] = (mac_addr_h >> 24) & 0xFF;
3148 addr[1] = (mac_addr_h >> 16) & 0xFF;
3149 addr[2] = (mac_addr_h >> 8) & 0xFF;
3150 addr[3] = mac_addr_h & 0xFF;
3151 addr[4] = (mac_addr_l >> 8) & 0xFF;
3152 addr[5] = mac_addr_l & 0xFF;
3155 /* Handle setting mac address */
3156 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3158 struct mvneta_port *pp = netdev_priv(dev);
3159 struct sockaddr *sockaddr = addr;
3162 ret = eth_prepare_mac_addr_change(dev, addr);
3165 /* Remove previous address table entry */
3166 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3168 /* Set new addr in hw */
3169 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3171 eth_commit_mac_addr_change(dev, addr);
3175 static void mvneta_adjust_link(struct net_device *ndev)
3177 struct mvneta_port *pp = netdev_priv(ndev);
3178 struct phy_device *phydev = ndev->phydev;
3179 int status_change = 0;
3182 if ((pp->speed != phydev->speed) ||
3183 (pp->duplex != phydev->duplex)) {
3186 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3187 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3188 MVNETA_GMAC_CONFIG_GMII_SPEED |
3189 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3192 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3194 if (phydev->speed == SPEED_1000)
3195 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3196 else if (phydev->speed == SPEED_100)
3197 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3199 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3201 pp->duplex = phydev->duplex;
3202 pp->speed = phydev->speed;
3206 if (phydev->link != pp->link) {
3207 if (!phydev->link) {
3212 pp->link = phydev->link;
3216 if (status_change) {
3218 if (!pp->use_inband_status) {
3219 u32 val = mvreg_read(pp,
3220 MVNETA_GMAC_AUTONEG_CONFIG);
3221 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3222 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3223 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3228 if (!pp->use_inband_status) {
3229 u32 val = mvreg_read(pp,
3230 MVNETA_GMAC_AUTONEG_CONFIG);
3231 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3232 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3233 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3236 mvneta_port_down(pp);
3238 phy_print_status(phydev);
3242 static int mvneta_mdio_probe(struct mvneta_port *pp)
3244 struct phy_device *phy_dev;
3246 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
3249 netdev_err(pp->dev, "could not find the PHY\n");
3253 phy_dev->supported &= PHY_GBIT_FEATURES;
3254 phy_dev->advertising = phy_dev->supported;
3263 static void mvneta_mdio_remove(struct mvneta_port *pp)
3265 struct net_device *ndev = pp->dev;
3267 phy_disconnect(ndev->phydev);
3270 /* Electing a CPU must be done in an atomic way: it should be done
3271 * after or before the removal/insertion of a CPU and this function is
3274 static void mvneta_percpu_elect(struct mvneta_port *pp)
3276 int elected_cpu = 0, max_cpu, cpu, i = 0;
3278 /* Use the cpu associated to the rxq when it is online, in all
3279 * the other cases, use the cpu 0 which can't be offline.
3281 if (cpu_online(pp->rxq_def))
3282 elected_cpu = pp->rxq_def;
3284 max_cpu = num_present_cpus();
3286 for_each_online_cpu(cpu) {
3287 int rxq_map = 0, txq_map = 0;
3290 for (rxq = 0; rxq < rxq_number; rxq++)
3291 if ((rxq % max_cpu) == cpu)
3292 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3294 if (cpu == elected_cpu)
3295 /* Map the default receive queue queue to the
3298 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3300 /* We update the TX queue map only if we have one
3301 * queue. In this case we associate the TX queue to
3302 * the CPU bound to the default RX queue
3304 if (txq_number == 1)
3305 txq_map = (cpu == elected_cpu) ?
3306 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3308 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3309 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3311 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3313 /* Update the interrupt mask on each CPU according the
3316 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3323 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3326 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3328 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3331 spin_lock(&pp->lock);
3333 * Configuring the driver for a new CPU while the driver is
3334 * stopping is racy, so just avoid it.
3336 if (pp->is_stopped) {
3337 spin_unlock(&pp->lock);
3340 netif_tx_stop_all_queues(pp->dev);
3343 * We have to synchronise on tha napi of each CPU except the one
3344 * just being woken up
3346 for_each_online_cpu(other_cpu) {
3347 if (other_cpu != cpu) {
3348 struct mvneta_pcpu_port *other_port =
3349 per_cpu_ptr(pp->ports, other_cpu);
3351 napi_synchronize(&other_port->napi);
3355 /* Mask all ethernet port interrupts */
3356 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3357 napi_enable(&port->napi);
3360 * Enable per-CPU interrupts on the CPU that is
3363 mvneta_percpu_enable(pp);
3366 * Enable per-CPU interrupt on the one CPU we care
3369 mvneta_percpu_elect(pp);
3371 /* Unmask all ethernet port interrupts */
3372 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3373 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3374 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3375 MVNETA_CAUSE_LINK_CHANGE |
3376 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3377 netif_tx_start_all_queues(pp->dev);
3378 spin_unlock(&pp->lock);
3382 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3384 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3386 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3389 * Thanks to this lock we are sure that any pending cpu election is
3392 spin_lock(&pp->lock);
3393 /* Mask all ethernet port interrupts */
3394 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3395 spin_unlock(&pp->lock);
3397 napi_synchronize(&port->napi);
3398 napi_disable(&port->napi);
3399 /* Disable per-CPU interrupts on the CPU that is brought down. */
3400 mvneta_percpu_disable(pp);
3404 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3406 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3409 /* Check if a new CPU must be elected now this on is down */
3410 spin_lock(&pp->lock);
3411 mvneta_percpu_elect(pp);
3412 spin_unlock(&pp->lock);
3413 /* Unmask all ethernet port interrupts */
3414 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3415 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3416 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3417 MVNETA_CAUSE_LINK_CHANGE |
3418 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3419 netif_tx_start_all_queues(pp->dev);
3423 static int mvneta_open(struct net_device *dev)
3425 struct mvneta_port *pp = netdev_priv(dev);
3428 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3429 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3430 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3432 ret = mvneta_setup_rxqs(pp);
3436 ret = mvneta_setup_txqs(pp);
3438 goto err_cleanup_rxqs;
3440 /* Connect to port interrupt line */
3441 ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
3442 MVNETA_DRIVER_NAME, pp->ports);
3444 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3445 goto err_cleanup_txqs;
3448 /* Enable per-CPU interrupt on all the CPU to handle our RX
3451 on_each_cpu(mvneta_percpu_enable, pp, true);
3453 pp->is_stopped = false;
3454 /* Register a CPU notifier to handle the case where our CPU
3455 * might be taken offline.
3457 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3462 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3465 goto err_free_online_hp;
3467 /* In default link is down */
3468 netif_carrier_off(pp->dev);
3470 ret = mvneta_mdio_probe(pp);
3472 netdev_err(dev, "cannot probe MDIO bus\n");
3473 goto err_free_dead_hp;
3476 mvneta_start_dev(pp);
3481 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3484 cpuhp_state_remove_instance_nocalls(online_hpstate, &pp->node_online);
3486 on_each_cpu(mvneta_percpu_disable, pp, true);
3487 free_percpu_irq(pp->dev->irq, pp->ports);
3489 mvneta_cleanup_txqs(pp);
3491 mvneta_cleanup_rxqs(pp);
3495 /* Stop the port, free port interrupt line */
3496 static int mvneta_stop(struct net_device *dev)
3498 struct mvneta_port *pp = netdev_priv(dev);
3500 /* Inform that we are stopping so we don't want to setup the
3501 * driver for new CPUs in the notifiers. The code of the
3502 * notifier for CPU online is protected by the same spinlock,
3503 * so when we get the lock, the notifer work is done.
3505 spin_lock(&pp->lock);
3506 pp->is_stopped = true;
3507 spin_unlock(&pp->lock);
3509 mvneta_stop_dev(pp);
3510 mvneta_mdio_remove(pp);
3512 cpuhp_state_remove_instance_nocalls(online_hpstate, &pp->node_online);
3513 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3515 on_each_cpu(mvneta_percpu_disable, pp, true);
3516 free_percpu_irq(dev->irq, pp->ports);
3517 mvneta_cleanup_rxqs(pp);
3518 mvneta_cleanup_txqs(pp);
3523 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3528 return phy_mii_ioctl(dev->phydev, ifr, cmd);
3531 /* Ethtool methods */
3533 /* Set link ksettings (phy address, speed) for ethtools */
3535 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3536 const struct ethtool_link_ksettings *cmd)
3538 struct mvneta_port *pp = netdev_priv(ndev);
3539 struct phy_device *phydev = ndev->phydev;
3544 if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
3547 mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE);
3549 if (cmd->base.autoneg == AUTONEG_DISABLE) {
3550 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3551 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3552 MVNETA_GMAC_CONFIG_GMII_SPEED |
3553 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3556 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3558 if (phydev->speed == SPEED_1000)
3559 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3560 else if (phydev->speed == SPEED_100)
3561 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3563 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3566 pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE);
3567 netdev_info(pp->dev, "autoneg status set to %i\n",
3568 pp->use_inband_status);
3570 if (netif_running(ndev)) {
3571 mvneta_port_down(pp);
3576 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
3579 /* Set interrupt coalescing for ethtools */
3580 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3581 struct ethtool_coalesce *c)
3583 struct mvneta_port *pp = netdev_priv(dev);
3586 for (queue = 0; queue < rxq_number; queue++) {
3587 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3588 rxq->time_coal = c->rx_coalesce_usecs;
3589 rxq->pkts_coal = c->rx_max_coalesced_frames;
3590 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3591 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3594 for (queue = 0; queue < txq_number; queue++) {
3595 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3596 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3597 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3603 /* get coalescing for ethtools */
3604 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3605 struct ethtool_coalesce *c)
3607 struct mvneta_port *pp = netdev_priv(dev);
3609 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3610 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3612 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3617 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3618 struct ethtool_drvinfo *drvinfo)
3620 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3621 sizeof(drvinfo->driver));
3622 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3623 sizeof(drvinfo->version));
3624 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3625 sizeof(drvinfo->bus_info));
3629 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3630 struct ethtool_ringparam *ring)
3632 struct mvneta_port *pp = netdev_priv(netdev);
3634 ring->rx_max_pending = MVNETA_MAX_RXD;
3635 ring->tx_max_pending = MVNETA_MAX_TXD;
3636 ring->rx_pending = pp->rx_ring_size;
3637 ring->tx_pending = pp->tx_ring_size;
3640 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3641 struct ethtool_ringparam *ring)
3643 struct mvneta_port *pp = netdev_priv(dev);
3645 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3647 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3648 ring->rx_pending : MVNETA_MAX_RXD;
3650 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3651 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3652 if (pp->tx_ring_size != ring->tx_pending)
3653 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3654 pp->tx_ring_size, ring->tx_pending);
3656 if (netif_running(dev)) {
3658 if (mvneta_open(dev)) {
3660 "error on opening device after ring param change\n");
3668 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3671 if (sset == ETH_SS_STATS) {
3674 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3675 memcpy(data + i * ETH_GSTRING_LEN,
3676 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3680 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3682 const struct mvneta_statistic *s;
3683 void __iomem *base = pp->base;
3688 for (i = 0, s = mvneta_statistics;
3689 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3693 val = readl_relaxed(base + s->offset);
3694 pp->ethtool_stats[i] += val;
3697 /* Docs say to read low 32-bit then high */
3698 low = readl_relaxed(base + s->offset);
3699 high = readl_relaxed(base + s->offset + 4);
3700 val64 = (u64)high << 32 | low;
3701 pp->ethtool_stats[i] += val64;
3707 static void mvneta_ethtool_get_stats(struct net_device *dev,
3708 struct ethtool_stats *stats, u64 *data)
3710 struct mvneta_port *pp = netdev_priv(dev);
3713 mvneta_ethtool_update_stats(pp);
3715 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3716 *data++ = pp->ethtool_stats[i];
3719 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3721 if (sset == ETH_SS_STATS)
3722 return ARRAY_SIZE(mvneta_statistics);
3726 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3728 return MVNETA_RSS_LU_TABLE_SIZE;
3731 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3732 struct ethtool_rxnfc *info,
3733 u32 *rules __always_unused)
3735 switch (info->cmd) {
3736 case ETHTOOL_GRXRINGS:
3737 info->data = rxq_number;
3746 static int mvneta_config_rss(struct mvneta_port *pp)
3751 netif_tx_stop_all_queues(pp->dev);
3753 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3755 /* We have to synchronise on the napi of each CPU */
3756 for_each_online_cpu(cpu) {
3757 struct mvneta_pcpu_port *pcpu_port =
3758 per_cpu_ptr(pp->ports, cpu);
3760 napi_synchronize(&pcpu_port->napi);
3761 napi_disable(&pcpu_port->napi);
3764 pp->rxq_def = pp->indir[0];
3766 /* Update unicast mapping */
3767 mvneta_set_rx_mode(pp->dev);
3769 /* Update val of portCfg register accordingly with all RxQueue types */
3770 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3771 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3773 /* Update the elected CPU matching the new rxq_def */
3774 spin_lock(&pp->lock);
3775 mvneta_percpu_elect(pp);
3776 spin_unlock(&pp->lock);
3778 /* We have to synchronise on the napi of each CPU */
3779 for_each_online_cpu(cpu) {
3780 struct mvneta_pcpu_port *pcpu_port =
3781 per_cpu_ptr(pp->ports, cpu);
3783 napi_enable(&pcpu_port->napi);
3786 netif_tx_start_all_queues(pp->dev);
3791 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3792 const u8 *key, const u8 hfunc)
3794 struct mvneta_port *pp = netdev_priv(dev);
3795 /* We require at least one supported parameter to be changed
3796 * and no change in any of the unsupported parameters
3799 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3805 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
3807 return mvneta_config_rss(pp);
3810 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3813 struct mvneta_port *pp = netdev_priv(dev);
3816 *hfunc = ETH_RSS_HASH_TOP;
3821 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
3826 static const struct net_device_ops mvneta_netdev_ops = {
3827 .ndo_open = mvneta_open,
3828 .ndo_stop = mvneta_stop,
3829 .ndo_start_xmit = mvneta_tx,
3830 .ndo_set_rx_mode = mvneta_set_rx_mode,
3831 .ndo_set_mac_address = mvneta_set_mac_addr,
3832 .ndo_change_mtu = mvneta_change_mtu,
3833 .ndo_fix_features = mvneta_fix_features,
3834 .ndo_get_stats64 = mvneta_get_stats64,
3835 .ndo_do_ioctl = mvneta_ioctl,
3838 const struct ethtool_ops mvneta_eth_tool_ops = {
3839 .get_link = ethtool_op_get_link,
3840 .set_coalesce = mvneta_ethtool_set_coalesce,
3841 .get_coalesce = mvneta_ethtool_get_coalesce,
3842 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3843 .get_ringparam = mvneta_ethtool_get_ringparam,
3844 .set_ringparam = mvneta_ethtool_set_ringparam,
3845 .get_strings = mvneta_ethtool_get_strings,
3846 .get_ethtool_stats = mvneta_ethtool_get_stats,
3847 .get_sset_count = mvneta_ethtool_get_sset_count,
3848 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
3849 .get_rxnfc = mvneta_ethtool_get_rxnfc,
3850 .get_rxfh = mvneta_ethtool_get_rxfh,
3851 .set_rxfh = mvneta_ethtool_set_rxfh,
3852 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3853 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
3857 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
3862 mvneta_port_disable(pp);
3864 /* Set port default values */
3865 mvneta_defaults_set(pp);
3867 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3872 /* Initialize TX descriptor rings */
3873 for (queue = 0; queue < txq_number; queue++) {
3874 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3876 txq->size = pp->tx_ring_size;
3877 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3880 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3885 /* Create Rx descriptor rings */
3886 for (queue = 0; queue < rxq_number; queue++) {
3887 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3889 rxq->size = pp->rx_ring_size;
3890 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3891 rxq->time_coal = MVNETA_RX_COAL_USEC;
3897 /* platform glue : initialize decoding windows */
3898 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3899 const struct mbus_dram_target_info *dram)
3905 for (i = 0; i < 6; i++) {
3906 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3907 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3910 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3916 for (i = 0; i < dram->num_cs; i++) {
3917 const struct mbus_dram_window *cs = dram->cs + i;
3918 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3919 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3921 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3922 (cs->size - 1) & 0xffff0000);
3924 win_enable &= ~(1 << i);
3925 win_protect |= 3 << (2 * i);
3928 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
3929 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
3932 /* Power up the port */
3933 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
3937 /* MAC Cause register should be cleared */
3938 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3940 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3942 /* Even though it might look weird, when we're configured in
3943 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3946 case PHY_INTERFACE_MODE_QSGMII:
3947 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3948 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3950 case PHY_INTERFACE_MODE_SGMII:
3951 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3952 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3954 case PHY_INTERFACE_MODE_RGMII:
3955 case PHY_INTERFACE_MODE_RGMII_ID:
3956 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3962 /* Cancel Port Reset */
3963 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3964 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
3966 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3967 MVNETA_GMAC2_PORT_RESET) != 0)
3973 /* Device initialization routine */
3974 static int mvneta_probe(struct platform_device *pdev)
3976 const struct mbus_dram_target_info *dram_target_info;
3977 struct resource *res;
3978 struct device_node *dn = pdev->dev.of_node;
3979 struct device_node *phy_node;
3980 struct device_node *bm_node;
3981 struct mvneta_port *pp;
3982 struct net_device *dev;
3983 const char *dt_mac_addr;
3984 char hw_mac_addr[ETH_ALEN];
3985 const char *mac_from;
3986 const char *managed;
3992 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
3996 dev->irq = irq_of_parse_and_map(dn, 0);
3997 if (dev->irq == 0) {
3999 goto err_free_netdev;
4002 phy_node = of_parse_phandle(dn, "phy", 0);
4004 if (!of_phy_is_fixed_link(dn)) {
4005 dev_err(&pdev->dev, "no PHY specified\n");
4010 err = of_phy_register_fixed_link(dn);
4012 dev_err(&pdev->dev, "cannot register fixed PHY\n");
4016 /* In the case of a fixed PHY, the DT node associated
4017 * to the PHY is the Ethernet MAC DT node.
4019 phy_node = of_node_get(dn);
4022 phy_mode = of_get_phy_mode(dn);
4024 dev_err(&pdev->dev, "incorrect phy-mode\n");
4026 goto err_put_phy_node;
4029 dev->tx_queue_len = MVNETA_MAX_TXD;
4030 dev->watchdog_timeo = 5 * HZ;
4031 dev->netdev_ops = &mvneta_netdev_ops;
4033 dev->ethtool_ops = &mvneta_eth_tool_ops;
4035 pp = netdev_priv(dev);
4036 spin_lock_init(&pp->lock);
4037 pp->phy_node = phy_node;
4038 pp->phy_interface = phy_mode;
4040 err = of_property_read_string(dn, "managed", &managed);
4041 pp->use_inband_status = (err == 0 &&
4042 strcmp(managed, "in-band-status") == 0);
4044 pp->rxq_def = rxq_def;
4046 pp->indir[0] = rxq_def;
4048 pp->clk = devm_clk_get(&pdev->dev, "core");
4049 if (IS_ERR(pp->clk))
4050 pp->clk = devm_clk_get(&pdev->dev, NULL);
4051 if (IS_ERR(pp->clk)) {
4052 err = PTR_ERR(pp->clk);
4053 goto err_put_phy_node;
4056 clk_prepare_enable(pp->clk);
4058 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4059 if (!IS_ERR(pp->clk_bus))
4060 clk_prepare_enable(pp->clk_bus);
4062 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4063 pp->base = devm_ioremap_resource(&pdev->dev, res);
4064 if (IS_ERR(pp->base)) {
4065 err = PTR_ERR(pp->base);
4069 /* Alloc per-cpu port structure */
4070 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4076 /* Alloc per-cpu stats */
4077 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4080 goto err_free_ports;
4083 dt_mac_addr = of_get_mac_address(dn);
4085 mac_from = "device tree";
4086 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4088 mvneta_get_mac_addr(pp, hw_mac_addr);
4089 if (is_valid_ether_addr(hw_mac_addr)) {
4090 mac_from = "hardware";
4091 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4093 mac_from = "random";
4094 eth_hw_addr_random(dev);
4098 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4099 if (tx_csum_limit < 0 ||
4100 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4101 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4102 dev_info(&pdev->dev,
4103 "Wrong TX csum limit in DT, set to %dB\n",
4104 MVNETA_TX_CSUM_DEF_SIZE);
4106 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4107 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4109 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4112 pp->tx_csum_limit = tx_csum_limit;
4114 dram_target_info = mv_mbus_dram_info();
4115 if (dram_target_info)
4116 mvneta_conf_mbus_windows(pp, dram_target_info);
4118 pp->tx_ring_size = MVNETA_MAX_TXD;
4119 pp->rx_ring_size = MVNETA_MAX_RXD;
4122 SET_NETDEV_DEV(dev, &pdev->dev);
4124 pp->id = global_port_id++;
4126 /* Obtain access to BM resources if enabled and already initialized */
4127 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4128 if (bm_node && bm_node->data) {
4129 pp->bm_priv = bm_node->data;
4130 err = mvneta_bm_port_init(pdev, pp);
4132 dev_info(&pdev->dev, "use SW buffer management\n");
4136 of_node_put(bm_node);
4138 err = mvneta_init(&pdev->dev, pp);
4142 err = mvneta_port_power_up(pp, phy_mode);
4144 dev_err(&pdev->dev, "can't power up port\n");
4148 for_each_present_cpu(cpu) {
4149 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4151 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4155 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
4156 dev->hw_features |= dev->features;
4157 dev->vlan_features |= dev->features;
4158 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4159 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4161 err = register_netdev(dev);
4163 dev_err(&pdev->dev, "failed to register\n");
4167 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4170 platform_set_drvdata(pdev, pp->dev);
4172 if (pp->use_inband_status) {
4173 struct phy_device *phy = of_phy_find_device(dn);
4175 mvneta_fixed_link_update(pp, phy);
4177 put_device(&phy->mdio.dev);
4184 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4185 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4188 free_percpu(pp->stats);
4190 free_percpu(pp->ports);
4192 clk_disable_unprepare(pp->clk_bus);
4193 clk_disable_unprepare(pp->clk);
4195 of_node_put(phy_node);
4196 if (of_phy_is_fixed_link(dn))
4197 of_phy_deregister_fixed_link(dn);
4199 irq_dispose_mapping(dev->irq);
4205 /* Device removal routine */
4206 static int mvneta_remove(struct platform_device *pdev)
4208 struct net_device *dev = platform_get_drvdata(pdev);
4209 struct device_node *dn = pdev->dev.of_node;
4210 struct mvneta_port *pp = netdev_priv(dev);
4212 unregister_netdev(dev);
4213 clk_disable_unprepare(pp->clk_bus);
4214 clk_disable_unprepare(pp->clk);
4215 free_percpu(pp->ports);
4216 free_percpu(pp->stats);
4217 if (of_phy_is_fixed_link(dn))
4218 of_phy_deregister_fixed_link(dn);
4219 irq_dispose_mapping(dev->irq);
4220 of_node_put(pp->phy_node);
4224 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4225 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4232 static const struct of_device_id mvneta_match[] = {
4233 { .compatible = "marvell,armada-370-neta" },
4234 { .compatible = "marvell,armada-xp-neta" },
4237 MODULE_DEVICE_TABLE(of, mvneta_match);
4239 static struct platform_driver mvneta_driver = {
4240 .probe = mvneta_probe,
4241 .remove = mvneta_remove,
4243 .name = MVNETA_DRIVER_NAME,
4244 .of_match_table = mvneta_match,
4248 static int __init mvneta_driver_init(void)
4252 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4254 mvneta_cpu_down_prepare);
4257 online_hpstate = ret;
4258 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4259 NULL, mvneta_cpu_dead);
4263 ret = platform_driver_register(&mvneta_driver);
4269 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4271 cpuhp_remove_multi_state(online_hpstate);
4275 module_init(mvneta_driver_init);
4277 static void __exit mvneta_driver_exit(void)
4279 platform_driver_unregister(&mvneta_driver);
4280 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4281 cpuhp_remove_multi_state(online_hpstate);
4283 module_exit(mvneta_driver_exit);
4285 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4286 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4287 MODULE_LICENSE("GPL");
4289 module_param(rxq_number, int, S_IRUGO);
4290 module_param(txq_number, int, S_IRUGO);
4292 module_param(rxq_def, int, S_IRUGO);
4293 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);