2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/phylink.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
35 #include "mvneta_bm.h"
41 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
42 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
43 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
44 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
45 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
46 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
47 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
48 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
49 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
50 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
51 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
52 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
53 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
54 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
55 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
56 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
57 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
59 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
60 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
61 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
62 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
63 #define MVNETA_PORT_RX_RESET 0x1cc0
64 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
65 #define MVNETA_PHY_ADDR 0x2000
66 #define MVNETA_PHY_ADDR_MASK 0x1f
67 #define MVNETA_MBUS_RETRY 0x2010
68 #define MVNETA_UNIT_INTR_CAUSE 0x2080
69 #define MVNETA_UNIT_CONTROL 0x20B0
70 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
71 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
72 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
73 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
74 #define MVNETA_BASE_ADDR_ENABLE 0x2290
75 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
76 #define MVNETA_PORT_CONFIG 0x2400
77 #define MVNETA_UNI_PROMISC_MODE BIT(0)
78 #define MVNETA_DEF_RXQ(q) ((q) << 1)
79 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
80 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
81 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
82 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
83 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
84 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
85 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
86 MVNETA_DEF_RXQ_ARP(q) | \
87 MVNETA_DEF_RXQ_TCP(q) | \
88 MVNETA_DEF_RXQ_UDP(q) | \
89 MVNETA_DEF_RXQ_BPDU(q) | \
90 MVNETA_TX_UNSET_ERR_SUM | \
91 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
92 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
93 #define MVNETA_MAC_ADDR_LOW 0x2414
94 #define MVNETA_MAC_ADDR_HIGH 0x2418
95 #define MVNETA_SDMA_CONFIG 0x241c
96 #define MVNETA_SDMA_BRST_SIZE_16 4
97 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
98 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
99 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
100 #define MVNETA_DESC_SWAP BIT(6)
101 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
102 #define MVNETA_PORT_STATUS 0x2444
103 #define MVNETA_TX_IN_PRGRS BIT(0)
104 #define MVNETA_TX_FIFO_EMPTY BIT(8)
105 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
106 #define MVNETA_SERDES_CFG 0x24A0
107 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
108 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
109 #define MVNETA_TYPE_PRIO 0x24bc
110 #define MVNETA_FORCE_UNI BIT(21)
111 #define MVNETA_TXQ_CMD_1 0x24e4
112 #define MVNETA_TXQ_CMD 0x2448
113 #define MVNETA_TXQ_DISABLE_SHIFT 8
114 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
115 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
116 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
117 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
118 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
119 #define MVNETA_ACC_MODE 0x2500
120 #define MVNETA_BM_ADDRESS 0x2504
121 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
122 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
123 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
124 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
125 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
126 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
128 /* Exception Interrupt Port/Queue Cause register
130 * Their behavior depend of the mapping done using the PCPX2Q
131 * registers. For a given CPU if the bit associated to a queue is not
132 * set, then for the register a read from this CPU will always return
133 * 0 and a write won't do anything
136 #define MVNETA_INTR_NEW_CAUSE 0x25a0
137 #define MVNETA_INTR_NEW_MASK 0x25a4
139 /* bits 0..7 = TXQ SENT, one bit per queue.
140 * bits 8..15 = RXQ OCCUP, one bit per queue.
141 * bits 16..23 = RXQ FREE, one bit per queue.
142 * bit 29 = OLD_REG_SUM, see old reg ?
143 * bit 30 = TX_ERR_SUM, one bit for 4 ports
144 * bit 31 = MISC_SUM, one bit for 4 ports
146 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
147 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
148 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
149 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
150 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
152 #define MVNETA_INTR_OLD_CAUSE 0x25a8
153 #define MVNETA_INTR_OLD_MASK 0x25ac
155 /* Data Path Port/Queue Cause Register */
156 #define MVNETA_INTR_MISC_CAUSE 0x25b0
157 #define MVNETA_INTR_MISC_MASK 0x25b4
159 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
160 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
161 #define MVNETA_CAUSE_PTP BIT(4)
163 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
164 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
165 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
166 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
167 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
168 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
169 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
170 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
174 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
176 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
177 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
178 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
180 #define MVNETA_INTR_ENABLE 0x25b8
181 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
182 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
184 #define MVNETA_RXQ_CMD 0x2680
185 #define MVNETA_RXQ_DISABLE_SHIFT 8
186 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
187 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
188 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
189 #define MVNETA_GMAC_CTRL_0 0x2c00
190 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
191 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
192 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
193 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
194 #define MVNETA_GMAC_CTRL_2 0x2c08
195 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
196 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
197 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
198 #define MVNETA_GMAC2_PORT_RESET BIT(6)
199 #define MVNETA_GMAC_STATUS 0x2c10
200 #define MVNETA_GMAC_LINK_UP BIT(0)
201 #define MVNETA_GMAC_SPEED_1000 BIT(1)
202 #define MVNETA_GMAC_SPEED_100 BIT(2)
203 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
204 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
205 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
206 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
207 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
208 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
209 #define MVNETA_GMAC_SYNC_OK BIT(14)
210 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
211 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
212 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
213 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
214 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
215 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
216 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
217 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
218 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
219 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
220 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
221 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
222 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
223 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
224 #define MVNETA_MIB_COUNTERS_BASE 0x3000
225 #define MVNETA_MIB_LATE_COLLISION 0x7c
226 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
227 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
228 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
229 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
230 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
231 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
232 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
233 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
234 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
235 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
236 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
237 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
238 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
239 #define MVNETA_PORT_TX_RESET 0x3cf0
240 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
241 #define MVNETA_TX_MTU 0x3e0c
242 #define MVNETA_TX_TOKEN_SIZE 0x3e14
243 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
244 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
245 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
247 #define MVNETA_LPI_CTRL_0 0x2cc0
248 #define MVNETA_LPI_CTRL_1 0x2cc4
249 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
250 #define MVNETA_LPI_CTRL_2 0x2cc8
251 #define MVNETA_LPI_STATUS 0x2ccc
253 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
255 /* Descriptor ring Macros */
256 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
257 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
259 /* Various constants */
262 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
263 #define MVNETA_RX_COAL_PKTS 32
264 #define MVNETA_RX_COAL_USEC 100
266 /* The two bytes Marvell header. Either contains a special value used
267 * by Marvell switches when a specific hardware mode is enabled (not
268 * supported by this driver) or is filled automatically by zeroes on
269 * the RX side. Those two bytes being at the front of the Ethernet
270 * header, they allow to have the IP header aligned on a 4 bytes
271 * boundary automatically: the hardware skips those two bytes on its
274 #define MVNETA_MH_SIZE 2
276 #define MVNETA_VLAN_TAG_LEN 4
278 #define MVNETA_TX_CSUM_DEF_SIZE 1600
279 #define MVNETA_TX_CSUM_MAX_SIZE 9800
280 #define MVNETA_ACC_MODE_EXT1 1
281 #define MVNETA_ACC_MODE_EXT2 2
283 #define MVNETA_MAX_DECODE_WIN 6
285 /* Timeout constants */
286 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
287 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
288 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
290 #define MVNETA_TX_MTU_MAX 0x3ffff
292 /* The RSS lookup table actually has 256 entries but we do not use
295 #define MVNETA_RSS_LU_TABLE_SIZE 1
297 /* Max number of Rx descriptors */
298 #define MVNETA_MAX_RXD 512
300 /* Max number of Tx descriptors */
301 #define MVNETA_MAX_TXD 1024
303 /* Max number of allowed TCP segments for software TSO */
304 #define MVNETA_MAX_TSO_SEGS 100
306 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
308 /* descriptor aligned size */
309 #define MVNETA_DESC_ALIGNED_SIZE 32
311 /* Number of bytes to be taken into account by HW when putting incoming data
312 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
313 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
315 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
317 #define MVNETA_RX_PKT_SIZE(mtu) \
318 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
319 ETH_HLEN + ETH_FCS_LEN, \
322 #define IS_TSO_HEADER(txq, addr) \
323 ((addr >= txq->tso_hdrs_phys) && \
324 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
326 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
327 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
330 ETHTOOL_STAT_EEE_WAKEUP,
331 ETHTOOL_STAT_SKB_ALLOC_ERR,
332 ETHTOOL_STAT_REFILL_ERR,
336 struct mvneta_statistic {
337 unsigned short offset;
339 const char name[ETH_GSTRING_LEN];
346 static const struct mvneta_statistic mvneta_statistics[] = {
347 { 0x3000, T_REG_64, "good_octets_received", },
348 { 0x3010, T_REG_32, "good_frames_received", },
349 { 0x3008, T_REG_32, "bad_octets_received", },
350 { 0x3014, T_REG_32, "bad_frames_received", },
351 { 0x3018, T_REG_32, "broadcast_frames_received", },
352 { 0x301c, T_REG_32, "multicast_frames_received", },
353 { 0x3050, T_REG_32, "unrec_mac_control_received", },
354 { 0x3058, T_REG_32, "good_fc_received", },
355 { 0x305c, T_REG_32, "bad_fc_received", },
356 { 0x3060, T_REG_32, "undersize_received", },
357 { 0x3064, T_REG_32, "fragments_received", },
358 { 0x3068, T_REG_32, "oversize_received", },
359 { 0x306c, T_REG_32, "jabber_received", },
360 { 0x3070, T_REG_32, "mac_receive_error", },
361 { 0x3074, T_REG_32, "bad_crc_event", },
362 { 0x3078, T_REG_32, "collision", },
363 { 0x307c, T_REG_32, "late_collision", },
364 { 0x2484, T_REG_32, "rx_discard", },
365 { 0x2488, T_REG_32, "rx_overrun", },
366 { 0x3020, T_REG_32, "frames_64_octets", },
367 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
368 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
369 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
370 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
371 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
372 { 0x3038, T_REG_64, "good_octets_sent", },
373 { 0x3040, T_REG_32, "good_frames_sent", },
374 { 0x3044, T_REG_32, "excessive_collision", },
375 { 0x3048, T_REG_32, "multicast_frames_sent", },
376 { 0x304c, T_REG_32, "broadcast_frames_sent", },
377 { 0x3054, T_REG_32, "fc_sent", },
378 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
379 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
380 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", },
381 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", },
384 struct mvneta_pcpu_stats {
385 struct u64_stats_sync syncp;
394 struct mvneta_pcpu_port {
395 /* Pointer to the shared port */
396 struct mvneta_port *pp;
398 /* Pointer to the CPU-local NAPI struct */
399 struct napi_struct napi;
401 /* Cause of the previous interrupt */
407 struct mvneta_pcpu_port __percpu *ports;
408 struct mvneta_pcpu_stats __percpu *stats;
412 struct mvneta_rx_queue *rxqs;
413 struct mvneta_tx_queue *txqs;
414 struct net_device *dev;
415 struct hlist_node node_online;
416 struct hlist_node node_dead;
418 /* Protect the access to the percpu interrupt registers,
419 * ensuring that the configuration remains coherent.
425 struct napi_struct napi;
435 phy_interface_t phy_interface;
436 struct device_node *dn;
437 unsigned int tx_csum_limit;
438 struct phylink *phylink;
440 struct mvneta_bm *bm_priv;
441 struct mvneta_bm_pool *pool_long;
442 struct mvneta_bm_pool *pool_short;
449 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
451 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
453 /* Flags for special SoC configurations */
454 bool neta_armada3700;
455 u16 rx_offset_correction;
456 const struct mbus_dram_target_info *dram_target_info;
459 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
460 * layout of the transmit and reception DMA descriptors, and their
461 * layout is therefore defined by the hardware design
464 #define MVNETA_TX_L3_OFF_SHIFT 0
465 #define MVNETA_TX_IP_HLEN_SHIFT 8
466 #define MVNETA_TX_L4_UDP BIT(16)
467 #define MVNETA_TX_L3_IP6 BIT(17)
468 #define MVNETA_TXD_IP_CSUM BIT(18)
469 #define MVNETA_TXD_Z_PAD BIT(19)
470 #define MVNETA_TXD_L_DESC BIT(20)
471 #define MVNETA_TXD_F_DESC BIT(21)
472 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
473 MVNETA_TXD_L_DESC | \
475 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
476 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
478 #define MVNETA_RXD_ERR_CRC 0x0
479 #define MVNETA_RXD_BM_POOL_SHIFT 13
480 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
481 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
482 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
483 #define MVNETA_RXD_ERR_LEN BIT(18)
484 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
485 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
486 #define MVNETA_RXD_L3_IP4 BIT(25)
487 #define MVNETA_RXD_LAST_DESC BIT(26)
488 #define MVNETA_RXD_FIRST_DESC BIT(27)
489 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
490 MVNETA_RXD_LAST_DESC)
491 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
493 #if defined(__LITTLE_ENDIAN)
494 struct mvneta_tx_desc {
495 u32 command; /* Options used by HW for packet transmitting.*/
496 u16 reserverd1; /* csum_l4 (for future use) */
497 u16 data_size; /* Data size of transmitted packet in bytes */
498 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
499 u32 reserved2; /* hw_cmd - (for future use, PMT) */
500 u32 reserved3[4]; /* Reserved - (for future use) */
503 struct mvneta_rx_desc {
504 u32 status; /* Info about received packet */
505 u16 reserved1; /* pnc_info - (for future use, PnC) */
506 u16 data_size; /* Size of received packet in bytes */
508 u32 buf_phys_addr; /* Physical address of the buffer */
509 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
511 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
512 u16 reserved3; /* prefetch_cmd, for future use */
513 u16 reserved4; /* csum_l4 - (for future use, PnC) */
515 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
516 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
519 struct mvneta_tx_desc {
520 u16 data_size; /* Data size of transmitted packet in bytes */
521 u16 reserverd1; /* csum_l4 (for future use) */
522 u32 command; /* Options used by HW for packet transmitting.*/
523 u32 reserved2; /* hw_cmd - (for future use, PMT) */
524 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
525 u32 reserved3[4]; /* Reserved - (for future use) */
528 struct mvneta_rx_desc {
529 u16 data_size; /* Size of received packet in bytes */
530 u16 reserved1; /* pnc_info - (for future use, PnC) */
531 u32 status; /* Info about received packet */
533 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
534 u32 buf_phys_addr; /* Physical address of the buffer */
536 u16 reserved4; /* csum_l4 - (for future use, PnC) */
537 u16 reserved3; /* prefetch_cmd, for future use */
538 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
540 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
541 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
545 struct mvneta_tx_queue {
546 /* Number of this TX queue, in the range 0-7 */
549 /* Number of TX DMA descriptors in the descriptor ring */
552 /* Number of currently used TX DMA descriptor in the
557 int tx_stop_threshold;
558 int tx_wake_threshold;
560 /* Array of transmitted skb */
561 struct sk_buff **tx_skb;
563 /* Index of last TX DMA descriptor that was inserted */
566 /* Index of the TX DMA descriptor to be cleaned up */
571 /* Virtual address of the TX DMA descriptors array */
572 struct mvneta_tx_desc *descs;
574 /* DMA address of the TX DMA descriptors array */
575 dma_addr_t descs_phys;
577 /* Index of the last TX DMA descriptor */
580 /* Index of the next TX DMA descriptor to process */
581 int next_desc_to_proc;
583 /* DMA buffers for TSO headers */
586 /* DMA address of TSO headers */
587 dma_addr_t tso_hdrs_phys;
589 /* Affinity mask for CPUs*/
590 cpumask_t affinity_mask;
593 struct mvneta_rx_queue {
594 /* rx queue number, in the range 0-7 */
597 /* num of rx descriptors in the rx descriptor ring */
603 /* Virtual address of the RX buffer */
604 void **buf_virt_addr;
606 /* Virtual address of the RX DMA descriptors array */
607 struct mvneta_rx_desc *descs;
609 /* DMA address of the RX DMA descriptors array */
610 dma_addr_t descs_phys;
612 /* Index of the last RX DMA descriptor */
615 /* Index of the next RX DMA descriptor to process */
616 int next_desc_to_proc;
618 /* Index of first RX DMA descriptor to refill */
622 /* pointer to uncomplete skb buffer */
631 static enum cpuhp_state online_hpstate;
632 /* The hardware supports eight (8) rx queues, but we are only allowing
633 * the first one to be used. Therefore, let's just allocate one queue.
635 static int rxq_number = 8;
636 static int txq_number = 8;
640 static int rx_copybreak __read_mostly = 256;
641 static int rx_header_size __read_mostly = 128;
643 /* HW BM need that each port be identify by a unique ID */
644 static int global_port_id;
646 #define MVNETA_DRIVER_NAME "mvneta"
647 #define MVNETA_DRIVER_VERSION "1.0"
649 /* Utility/helper methods */
651 /* Write helper method */
652 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
654 writel(data, pp->base + offset);
657 /* Read helper method */
658 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
660 return readl(pp->base + offset);
663 /* Increment txq get counter */
664 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
666 txq->txq_get_index++;
667 if (txq->txq_get_index == txq->size)
668 txq->txq_get_index = 0;
671 /* Increment txq put counter */
672 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
674 txq->txq_put_index++;
675 if (txq->txq_put_index == txq->size)
676 txq->txq_put_index = 0;
680 /* Clear all MIB counters */
681 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
686 /* Perform dummy reads from MIB counters */
687 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
688 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
689 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
690 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
693 /* Get System Network Statistics */
695 mvneta_get_stats64(struct net_device *dev,
696 struct rtnl_link_stats64 *stats)
698 struct mvneta_port *pp = netdev_priv(dev);
702 for_each_possible_cpu(cpu) {
703 struct mvneta_pcpu_stats *cpu_stats;
711 cpu_stats = per_cpu_ptr(pp->stats, cpu);
713 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
714 rx_packets = cpu_stats->rx_packets;
715 rx_bytes = cpu_stats->rx_bytes;
716 rx_dropped = cpu_stats->rx_dropped;
717 rx_errors = cpu_stats->rx_errors;
718 tx_packets = cpu_stats->tx_packets;
719 tx_bytes = cpu_stats->tx_bytes;
720 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
722 stats->rx_packets += rx_packets;
723 stats->rx_bytes += rx_bytes;
724 stats->rx_dropped += rx_dropped;
725 stats->rx_errors += rx_errors;
726 stats->tx_packets += tx_packets;
727 stats->tx_bytes += tx_bytes;
730 stats->tx_dropped = dev->stats.tx_dropped;
733 /* Rx descriptors helper methods */
735 /* Checks whether the RX descriptor having this status is both the first
736 * and the last descriptor for the RX packet. Each RX packet is currently
737 * received through a single RX descriptor, so not having each RX
738 * descriptor with its first and last bits set is an error
740 static int mvneta_rxq_desc_is_first_last(u32 status)
742 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
743 MVNETA_RXD_FIRST_LAST_DESC;
746 /* Add number of descriptors ready to receive new packets */
747 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
748 struct mvneta_rx_queue *rxq,
751 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
754 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
755 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
756 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
757 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
758 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
761 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
762 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
765 /* Get number of RX descriptors occupied by received packets */
766 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
767 struct mvneta_rx_queue *rxq)
771 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
772 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
775 /* Update num of rx desc called upon return from rx path or
776 * from mvneta_rxq_drop_pkts().
778 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
779 struct mvneta_rx_queue *rxq,
780 int rx_done, int rx_filled)
784 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
786 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
787 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
791 /* Only 255 descriptors can be added at once */
792 while ((rx_done > 0) || (rx_filled > 0)) {
793 if (rx_done <= 0xff) {
800 if (rx_filled <= 0xff) {
801 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
804 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
807 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
811 /* Get pointer to next RX descriptor to be processed by SW */
812 static struct mvneta_rx_desc *
813 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
815 int rx_desc = rxq->next_desc_to_proc;
817 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
818 prefetch(rxq->descs + rxq->next_desc_to_proc);
819 return rxq->descs + rx_desc;
822 /* Change maximum receive size of the port. */
823 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
827 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
828 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
829 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
830 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
831 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
835 /* Set rx queue offset */
836 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
837 struct mvneta_rx_queue *rxq,
842 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
843 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
846 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
847 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
851 /* Tx descriptors helper methods */
853 /* Update HW with number of TX descriptors to be sent */
854 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
855 struct mvneta_tx_queue *txq,
860 pend_desc += txq->pending;
862 /* Only 255 Tx descriptors can be added at once */
864 val = min(pend_desc, 255);
865 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
867 } while (pend_desc > 0);
871 /* Get pointer to next TX descriptor to be processed (send) by HW */
872 static struct mvneta_tx_desc *
873 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
875 int tx_desc = txq->next_desc_to_proc;
877 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
878 return txq->descs + tx_desc;
881 /* Release the last allocated TX descriptor. Useful to handle DMA
882 * mapping failures in the TX path.
884 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
886 if (txq->next_desc_to_proc == 0)
887 txq->next_desc_to_proc = txq->last_desc - 1;
889 txq->next_desc_to_proc--;
892 /* Set rxq buf size */
893 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
894 struct mvneta_rx_queue *rxq,
899 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
901 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
902 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
904 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
907 /* Disable buffer management (BM) */
908 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
909 struct mvneta_rx_queue *rxq)
913 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
914 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
915 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
918 /* Enable buffer management (BM) */
919 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
920 struct mvneta_rx_queue *rxq)
924 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
925 val |= MVNETA_RXQ_HW_BUF_ALLOC;
926 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
929 /* Notify HW about port's assignment of pool for bigger packets */
930 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
931 struct mvneta_rx_queue *rxq)
935 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
936 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
937 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
939 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
942 /* Notify HW about port's assignment of pool for smaller packets */
943 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
944 struct mvneta_rx_queue *rxq)
948 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
949 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
950 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
952 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
955 /* Set port's receive buffer size for assigned BM pool */
956 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
962 if (!IS_ALIGNED(buf_size, 8)) {
963 dev_warn(pp->dev->dev.parent,
964 "illegal buf_size value %d, round to %d\n",
965 buf_size, ALIGN(buf_size, 8));
966 buf_size = ALIGN(buf_size, 8);
969 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
970 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
971 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
974 /* Configure MBUS window in order to enable access BM internal SRAM */
975 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
978 u32 win_enable, win_protect;
981 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
983 if (pp->bm_win_id < 0) {
984 /* Find first not occupied window */
985 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
986 if (win_enable & (1 << i)) {
991 if (i == MVNETA_MAX_DECODE_WIN)
997 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
998 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1001 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1003 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1004 (attr << 8) | target);
1006 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1008 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1009 win_protect |= 3 << (2 * i);
1010 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1012 win_enable &= ~(1 << i);
1013 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1018 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1024 /* Get BM window information */
1025 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1032 /* Open NETA -> BM window */
1033 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1036 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1042 /* Assign and initialize pools for port. In case of fail
1043 * buffer manager will remain disabled for current port.
1045 static int mvneta_bm_port_init(struct platform_device *pdev,
1046 struct mvneta_port *pp)
1048 struct device_node *dn = pdev->dev.of_node;
1049 u32 long_pool_id, short_pool_id;
1051 if (!pp->neta_armada3700) {
1054 ret = mvneta_bm_port_mbus_init(pp);
1059 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1060 netdev_info(pp->dev, "missing long pool id\n");
1064 /* Create port's long pool depending on mtu */
1065 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1066 MVNETA_BM_LONG, pp->id,
1067 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1068 if (!pp->pool_long) {
1069 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1073 pp->pool_long->port_map |= 1 << pp->id;
1075 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1078 /* If short pool id is not defined, assume using single pool */
1079 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1080 short_pool_id = long_pool_id;
1082 /* Create port's short pool */
1083 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1084 MVNETA_BM_SHORT, pp->id,
1085 MVNETA_BM_SHORT_PKT_SIZE);
1086 if (!pp->pool_short) {
1087 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1088 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1092 if (short_pool_id != long_pool_id) {
1093 pp->pool_short->port_map |= 1 << pp->id;
1094 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1095 pp->pool_short->id);
1101 /* Update settings of a pool for bigger packets */
1102 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1104 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1105 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1108 /* Release all buffers from long pool */
1109 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1110 if (hwbm_pool->buf_num) {
1111 WARN(1, "cannot free all buffers in pool %d\n",
1116 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1117 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1118 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1119 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1121 /* Fill entire long pool */
1122 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1123 if (num != hwbm_pool->size) {
1124 WARN(1, "pool %d: %d of %d allocated\n",
1125 bm_pool->id, num, hwbm_pool->size);
1128 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1133 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1134 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1137 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1138 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1141 /* Start the Ethernet port RX and TX activity */
1142 static void mvneta_port_up(struct mvneta_port *pp)
1147 /* Enable all initialized TXs. */
1149 for (queue = 0; queue < txq_number; queue++) {
1150 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1152 q_map |= (1 << queue);
1154 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1157 /* Enable all initialized RXQs. */
1158 for (queue = 0; queue < rxq_number; queue++) {
1159 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1162 q_map |= (1 << queue);
1164 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1167 /* Stop the Ethernet port activity */
1168 static void mvneta_port_down(struct mvneta_port *pp)
1173 /* Stop Rx port activity. Check port Rx activity. */
1174 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1176 /* Issue stop command for active channels only */
1178 mvreg_write(pp, MVNETA_RXQ_CMD,
1179 val << MVNETA_RXQ_DISABLE_SHIFT);
1181 /* Wait for all Rx activity to terminate. */
1184 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1185 netdev_warn(pp->dev,
1186 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1192 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1193 } while (val & MVNETA_RXQ_ENABLE_MASK);
1195 /* Stop Tx port activity. Check port Tx activity. Issue stop
1196 * command for active channels only
1198 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1201 mvreg_write(pp, MVNETA_TXQ_CMD,
1202 (val << MVNETA_TXQ_DISABLE_SHIFT));
1204 /* Wait for all Tx activity to terminate. */
1207 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1208 netdev_warn(pp->dev,
1209 "TIMEOUT for TX stopped status=0x%08x\n",
1215 /* Check TX Command reg that all Txqs are stopped */
1216 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1218 } while (val & MVNETA_TXQ_ENABLE_MASK);
1220 /* Double check to verify that TX FIFO is empty */
1223 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1224 netdev_warn(pp->dev,
1225 "TX FIFO empty timeout status=0x%08x\n",
1231 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1232 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1233 (val & MVNETA_TX_IN_PRGRS));
1238 /* Enable the port by setting the port enable bit of the MAC control register */
1239 static void mvneta_port_enable(struct mvneta_port *pp)
1244 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1245 val |= MVNETA_GMAC0_PORT_ENABLE;
1246 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1249 /* Disable the port and wait for about 200 usec before retuning */
1250 static void mvneta_port_disable(struct mvneta_port *pp)
1254 /* Reset the Enable bit in the Serial Control Register */
1255 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1256 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1257 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1262 /* Multicast tables methods */
1264 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1265 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1273 val = 0x1 | (queue << 1);
1274 val |= (val << 24) | (val << 16) | (val << 8);
1277 for (offset = 0; offset <= 0xc; offset += 4)
1278 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1281 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1282 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1290 val = 0x1 | (queue << 1);
1291 val |= (val << 24) | (val << 16) | (val << 8);
1294 for (offset = 0; offset <= 0xfc; offset += 4)
1295 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1299 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1300 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1306 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1309 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1310 val = 0x1 | (queue << 1);
1311 val |= (val << 24) | (val << 16) | (val << 8);
1314 for (offset = 0; offset <= 0xfc; offset += 4)
1315 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1318 static void mvneta_percpu_unmask_interrupt(void *arg)
1320 struct mvneta_port *pp = arg;
1322 /* All the queue are unmasked, but actually only the ones
1323 * mapped to this CPU will be unmasked
1325 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1326 MVNETA_RX_INTR_MASK_ALL |
1327 MVNETA_TX_INTR_MASK_ALL |
1328 MVNETA_MISCINTR_INTR_MASK);
1331 static void mvneta_percpu_mask_interrupt(void *arg)
1333 struct mvneta_port *pp = arg;
1335 /* All the queue are masked, but actually only the ones
1336 * mapped to this CPU will be masked
1338 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1339 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1340 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1343 static void mvneta_percpu_clear_intr_cause(void *arg)
1345 struct mvneta_port *pp = arg;
1347 /* All the queue are cleared, but actually only the ones
1348 * mapped to this CPU will be cleared
1350 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1351 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1352 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1355 /* This method sets defaults to the NETA port:
1356 * Clears interrupt Cause and Mask registers.
1357 * Clears all MAC tables.
1358 * Sets defaults to all registers.
1359 * Resets RX and TX descriptor rings.
1361 * This method can be called after mvneta_port_down() to return the port
1362 * settings to defaults.
1364 static void mvneta_defaults_set(struct mvneta_port *pp)
1369 int max_cpu = num_present_cpus();
1371 /* Clear all Cause registers */
1372 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1374 /* Mask all interrupts */
1375 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1376 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1378 /* Enable MBUS Retry bit16 */
1379 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1381 /* Set CPU queue access map. CPUs are assigned to the RX and
1382 * TX queues modulo their number. If there is only one TX
1383 * queue then it is assigned to the CPU associated to the
1386 for_each_present_cpu(cpu) {
1387 int rxq_map = 0, txq_map = 0;
1389 if (!pp->neta_armada3700) {
1390 for (rxq = 0; rxq < rxq_number; rxq++)
1391 if ((rxq % max_cpu) == cpu)
1392 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1394 for (txq = 0; txq < txq_number; txq++)
1395 if ((txq % max_cpu) == cpu)
1396 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1398 /* With only one TX queue we configure a special case
1399 * which will allow to get all the irq on a single
1402 if (txq_number == 1)
1403 txq_map = (cpu == pp->rxq_def) ?
1404 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1407 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1408 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1411 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1414 /* Reset RX and TX DMAs */
1415 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1416 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1418 /* Disable Legacy WRR, Disable EJP, Release from reset */
1419 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1420 for (queue = 0; queue < txq_number; queue++) {
1421 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1422 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1425 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1426 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1428 /* Set Port Acceleration Mode */
1430 /* HW buffer management + legacy parser */
1431 val = MVNETA_ACC_MODE_EXT2;
1433 /* SW buffer management + legacy parser */
1434 val = MVNETA_ACC_MODE_EXT1;
1435 mvreg_write(pp, MVNETA_ACC_MODE, val);
1438 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1440 /* Update val of portCfg register accordingly with all RxQueue types */
1441 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1442 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1445 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1446 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1448 /* Build PORT_SDMA_CONFIG_REG */
1451 /* Default burst size */
1452 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1453 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1454 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1456 #if defined(__BIG_ENDIAN)
1457 val |= MVNETA_DESC_SWAP;
1460 /* Assign port SDMA configuration */
1461 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1463 /* Disable PHY polling in hardware, since we're using the
1464 * kernel phylib to do this.
1466 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1467 val &= ~MVNETA_PHY_POLLING_ENABLE;
1468 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1470 mvneta_set_ucast_table(pp, -1);
1471 mvneta_set_special_mcast_table(pp, -1);
1472 mvneta_set_other_mcast_table(pp, -1);
1474 /* Set port interrupt enable register - default enable all */
1475 mvreg_write(pp, MVNETA_INTR_ENABLE,
1476 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1477 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1479 mvneta_mib_counters_clear(pp);
1482 /* Set max sizes for tx queues */
1483 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1489 mtu = max_tx_size * 8;
1490 if (mtu > MVNETA_TX_MTU_MAX)
1491 mtu = MVNETA_TX_MTU_MAX;
1494 val = mvreg_read(pp, MVNETA_TX_MTU);
1495 val &= ~MVNETA_TX_MTU_MAX;
1497 mvreg_write(pp, MVNETA_TX_MTU, val);
1499 /* TX token size and all TXQs token size must be larger that MTU */
1500 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1502 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1505 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1507 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1509 for (queue = 0; queue < txq_number; queue++) {
1510 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1512 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1515 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1517 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1522 /* Set unicast address */
1523 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1526 unsigned int unicast_reg;
1527 unsigned int tbl_offset;
1528 unsigned int reg_offset;
1530 /* Locate the Unicast table entry */
1531 last_nibble = (0xf & last_nibble);
1533 /* offset from unicast tbl base */
1534 tbl_offset = (last_nibble / 4) * 4;
1536 /* offset within the above reg */
1537 reg_offset = last_nibble % 4;
1539 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1542 /* Clear accepts frame bit at specified unicast DA tbl entry */
1543 unicast_reg &= ~(0xff << (8 * reg_offset));
1545 unicast_reg &= ~(0xff << (8 * reg_offset));
1546 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1549 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1552 /* Set mac address */
1553 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1560 mac_l = (addr[4] << 8) | (addr[5]);
1561 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1562 (addr[2] << 8) | (addr[3] << 0);
1564 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1565 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1568 /* Accept frames of this address */
1569 mvneta_set_ucast_addr(pp, addr[5], queue);
1572 /* Set the number of packets that will be received before RX interrupt
1573 * will be generated by HW.
1575 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1576 struct mvneta_rx_queue *rxq, u32 value)
1578 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1579 value | MVNETA_RXQ_NON_OCCUPIED(0));
1582 /* Set the time delay in usec before RX interrupt will be generated by
1585 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1586 struct mvneta_rx_queue *rxq, u32 value)
1589 unsigned long clk_rate;
1591 clk_rate = clk_get_rate(pp->clk);
1592 val = (clk_rate / 1000000) * value;
1594 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1597 /* Set threshold for TX_DONE pkts coalescing */
1598 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1599 struct mvneta_tx_queue *txq, u32 value)
1603 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1605 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1606 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1608 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1611 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1612 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1613 u32 phys_addr, void *virt_addr,
1614 struct mvneta_rx_queue *rxq)
1618 rx_desc->buf_phys_addr = phys_addr;
1619 i = rx_desc - rxq->descs;
1620 rxq->buf_virt_addr[i] = virt_addr;
1623 /* Decrement sent descriptors counter */
1624 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1625 struct mvneta_tx_queue *txq,
1630 /* Only 255 TX descriptors can be updated at once */
1631 while (sent_desc > 0xff) {
1632 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1633 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1634 sent_desc = sent_desc - 0xff;
1637 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1638 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1641 /* Get number of TX descriptors already sent by HW */
1642 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1643 struct mvneta_tx_queue *txq)
1648 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1649 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1650 MVNETA_TXQ_SENT_DESC_SHIFT;
1655 /* Get number of sent descriptors and decrement counter.
1656 * The number of sent descriptors is returned.
1658 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1659 struct mvneta_tx_queue *txq)
1663 /* Get number of sent descriptors */
1664 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1666 /* Decrement sent descriptors counter */
1668 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1673 /* Set TXQ descriptors fields relevant for CSUM calculation */
1674 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1675 int ip_hdr_len, int l4_proto)
1679 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1680 * G_L4_chk, L4_type; required only for checksum
1683 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1684 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1686 if (l3_proto == htons(ETH_P_IP))
1687 command |= MVNETA_TXD_IP_CSUM;
1689 command |= MVNETA_TX_L3_IP6;
1691 if (l4_proto == IPPROTO_TCP)
1692 command |= MVNETA_TX_L4_CSUM_FULL;
1693 else if (l4_proto == IPPROTO_UDP)
1694 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1696 command |= MVNETA_TX_L4_CSUM_NOT;
1702 /* Display more error info */
1703 static void mvneta_rx_error(struct mvneta_port *pp,
1704 struct mvneta_rx_desc *rx_desc)
1706 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1707 u32 status = rx_desc->status;
1709 /* update per-cpu counter */
1710 u64_stats_update_begin(&stats->syncp);
1712 u64_stats_update_end(&stats->syncp);
1714 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1715 case MVNETA_RXD_ERR_CRC:
1716 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1717 status, rx_desc->data_size);
1719 case MVNETA_RXD_ERR_OVERRUN:
1720 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1721 status, rx_desc->data_size);
1723 case MVNETA_RXD_ERR_LEN:
1724 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1725 status, rx_desc->data_size);
1727 case MVNETA_RXD_ERR_RESOURCE:
1728 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1729 status, rx_desc->data_size);
1734 /* Handle RX checksum offload based on the descriptor's status */
1735 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1736 struct sk_buff *skb)
1738 if ((pp->dev->features & NETIF_F_RXCSUM) &&
1739 (status & MVNETA_RXD_L3_IP4) &&
1740 (status & MVNETA_RXD_L4_CSUM_OK)) {
1742 skb->ip_summed = CHECKSUM_UNNECESSARY;
1746 skb->ip_summed = CHECKSUM_NONE;
1749 /* Return tx queue pointer (find last set bit) according to <cause> returned
1750 * form tx_done reg. <cause> must not be null. The return value is always a
1751 * valid queue for matching the first one found in <cause>.
1753 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1756 int queue = fls(cause) - 1;
1758 return &pp->txqs[queue];
1761 /* Free tx queue skbuffs */
1762 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1763 struct mvneta_tx_queue *txq, int num,
1764 struct netdev_queue *nq)
1766 unsigned int bytes_compl = 0, pkts_compl = 0;
1769 for (i = 0; i < num; i++) {
1770 struct mvneta_tx_desc *tx_desc = txq->descs +
1772 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1775 bytes_compl += skb->len;
1779 mvneta_txq_inc_get(txq);
1781 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1782 dma_unmap_single(pp->dev->dev.parent,
1783 tx_desc->buf_phys_addr,
1784 tx_desc->data_size, DMA_TO_DEVICE);
1787 dev_kfree_skb_any(skb);
1790 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1793 /* Handle end of transmission */
1794 static void mvneta_txq_done(struct mvneta_port *pp,
1795 struct mvneta_tx_queue *txq)
1797 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1800 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1804 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1806 txq->count -= tx_done;
1808 if (netif_tx_queue_stopped(nq)) {
1809 if (txq->count <= txq->tx_wake_threshold)
1810 netif_tx_wake_queue(nq);
1814 /* Refill processing for SW buffer management */
1815 /* Allocate page per descriptor */
1816 static int mvneta_rx_refill(struct mvneta_port *pp,
1817 struct mvneta_rx_desc *rx_desc,
1818 struct mvneta_rx_queue *rxq,
1821 dma_addr_t phys_addr;
1824 page = __dev_alloc_page(gfp_mask);
1828 /* map page for use */
1829 phys_addr = dma_map_page(pp->dev->dev.parent, page, 0, PAGE_SIZE,
1831 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1836 phys_addr += pp->rx_offset_correction;
1837 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq);
1841 /* Handle tx checksum */
1842 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1844 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1846 __be16 l3_proto = vlan_get_protocol(skb);
1849 if (l3_proto == htons(ETH_P_IP)) {
1850 struct iphdr *ip4h = ip_hdr(skb);
1852 /* Calculate IPv4 checksum and L4 checksum */
1853 ip_hdr_len = ip4h->ihl;
1854 l4_proto = ip4h->protocol;
1855 } else if (l3_proto == htons(ETH_P_IPV6)) {
1856 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1858 /* Read l4_protocol from one of IPv6 extra headers */
1859 if (skb_network_header_len(skb) > 0)
1860 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1861 l4_proto = ip6h->nexthdr;
1863 return MVNETA_TX_L4_CSUM_NOT;
1865 return mvneta_txq_desc_csum(skb_network_offset(skb),
1866 l3_proto, ip_hdr_len, l4_proto);
1869 return MVNETA_TX_L4_CSUM_NOT;
1872 /* Drop packets received by the RXQ and free buffers */
1873 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1874 struct mvneta_rx_queue *rxq)
1878 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1880 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1883 for (i = 0; i < rx_done; i++) {
1884 struct mvneta_rx_desc *rx_desc =
1885 mvneta_rxq_next_desc_get(rxq);
1886 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1887 struct mvneta_bm_pool *bm_pool;
1889 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1890 /* Return dropped buffer to the pool */
1891 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1892 rx_desc->buf_phys_addr);
1897 for (i = 0; i < rxq->size; i++) {
1898 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1899 void *data = rxq->buf_virt_addr[i];
1900 if (!data || !(rx_desc->buf_phys_addr))
1903 dma_unmap_page(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1904 PAGE_SIZE, DMA_FROM_DEVICE);
1910 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq)
1912 struct mvneta_rx_desc *rx_desc;
1913 int curr_desc = rxq->first_to_refill;
1916 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) {
1917 rx_desc = rxq->descs + curr_desc;
1918 if (!(rx_desc->buf_phys_addr)) {
1919 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) {
1920 pr_err("Can't refill queue %d. Done %d from %d\n",
1921 rxq->id, i, rxq->refill_num);
1926 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc);
1928 rxq->refill_num -= i;
1929 rxq->first_to_refill = curr_desc;
1934 /* Main rx processing when using software buffer management */
1935 static int mvneta_rx_swbm(struct napi_struct *napi,
1936 struct mvneta_port *pp, int budget,
1937 struct mvneta_rx_queue *rxq)
1939 struct net_device *dev = pp->dev;
1940 int rx_todo, rx_proc;
1945 /* Get number of received packets */
1946 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq);
1949 /* Fairness NAPI loop */
1950 while ((rcvd_pkts < budget) && (rx_proc < rx_todo)) {
1951 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1952 unsigned char *data;
1954 dma_addr_t phys_addr;
1955 u32 rx_status, index;
1956 int rx_bytes, skb_size, copy_size;
1957 int frag_num, frag_size, frag_offset;
1959 index = rx_desc - rxq->descs;
1960 page = (struct page *)rxq->buf_virt_addr[index];
1961 data = page_address(page);
1962 /* Prefetch header */
1965 phys_addr = rx_desc->buf_phys_addr;
1966 rx_status = rx_desc->status;
1970 if (rx_status & MVNETA_RXD_FIRST_DESC) {
1971 /* Check errors only for FIRST descriptor */
1972 if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
1973 mvneta_rx_error(pp, rx_desc);
1974 /* leave the descriptor untouched */
1977 rx_bytes = rx_desc->data_size -
1978 (ETH_FCS_LEN + MVNETA_MH_SIZE);
1980 /* Allocate small skb for each new packet */
1981 skb_size = max(rx_copybreak, rx_header_size);
1982 rxq->skb = netdev_alloc_skb_ip_align(dev, skb_size);
1983 if (unlikely(!rxq->skb)) {
1984 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1987 "Can't allocate skb on queue %d\n",
1990 rxq->skb_alloc_err++;
1992 u64_stats_update_begin(&stats->syncp);
1993 stats->rx_dropped++;
1994 u64_stats_update_end(&stats->syncp);
1997 copy_size = min(skb_size, rx_bytes);
1999 /* Copy data from buffer to SKB, skip Marvell header */
2000 memcpy(rxq->skb->data, data + MVNETA_MH_SIZE,
2002 skb_put(rxq->skb, copy_size);
2003 rxq->left_size = rx_bytes - copy_size;
2005 mvneta_rx_csum(pp, rx_status, rxq->skb);
2006 if (rxq->left_size == 0) {
2007 int size = copy_size + MVNETA_MH_SIZE;
2009 dma_sync_single_range_for_cpu(dev->dev.parent,
2014 /* leave the descriptor and buffer untouched */
2016 /* refill descriptor with new buffer later */
2017 rx_desc->buf_phys_addr = 0;
2020 frag_offset = copy_size + MVNETA_MH_SIZE;
2021 frag_size = min(rxq->left_size,
2022 (int)(PAGE_SIZE - frag_offset));
2023 skb_add_rx_frag(rxq->skb, frag_num, page,
2024 frag_offset, frag_size,
2026 dma_unmap_page(dev->dev.parent, phys_addr,
2027 PAGE_SIZE, DMA_FROM_DEVICE);
2028 rxq->left_size -= frag_size;
2031 /* Middle or Last descriptor */
2032 if (unlikely(!rxq->skb)) {
2033 pr_debug("no skb for rx_status 0x%x\n",
2037 if (!rxq->left_size) {
2038 /* last descriptor has only FCS */
2039 /* and can be discarded */
2040 dma_sync_single_range_for_cpu(dev->dev.parent,
2044 /* leave the descriptor and buffer untouched */
2046 /* refill descriptor with new buffer later */
2047 rx_desc->buf_phys_addr = 0;
2049 frag_num = skb_shinfo(rxq->skb)->nr_frags;
2051 frag_size = min(rxq->left_size,
2052 (int)(PAGE_SIZE - frag_offset));
2053 skb_add_rx_frag(rxq->skb, frag_num, page,
2054 frag_offset, frag_size,
2057 dma_unmap_page(dev->dev.parent, phys_addr,
2058 PAGE_SIZE, DMA_FROM_DEVICE);
2060 rxq->left_size -= frag_size;
2062 } /* Middle or Last descriptor */
2064 if (!(rx_status & MVNETA_RXD_LAST_DESC))
2065 /* no last descriptor this time */
2068 if (rxq->left_size) {
2069 pr_err("get last desc, but left_size (%d) != 0\n",
2071 dev_kfree_skb_any(rxq->skb);
2077 rcvd_bytes += rxq->skb->len;
2079 /* Linux processing */
2080 rxq->skb->protocol = eth_type_trans(rxq->skb, dev);
2082 if (dev->features & NETIF_F_GRO)
2083 napi_gro_receive(napi, rxq->skb);
2085 netif_receive_skb(rxq->skb);
2087 /* clean uncomplete skb pointer in queue */
2093 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2095 u64_stats_update_begin(&stats->syncp);
2096 stats->rx_packets += rcvd_pkts;
2097 stats->rx_bytes += rcvd_bytes;
2098 u64_stats_update_end(&stats->syncp);
2101 /* return some buffers to hardware queue, one at a time is too slow */
2102 refill = mvneta_rx_refill_queue(pp, rxq);
2104 /* Update rxq management counters */
2105 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill);
2110 /* Main rx processing when using hardware buffer management */
2111 static int mvneta_rx_hwbm(struct napi_struct *napi,
2112 struct mvneta_port *pp, int rx_todo,
2113 struct mvneta_rx_queue *rxq)
2115 struct net_device *dev = pp->dev;
2120 /* Get number of received packets */
2121 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2123 if (rx_todo > rx_done)
2128 /* Fairness NAPI loop */
2129 while (rx_done < rx_todo) {
2130 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2131 struct mvneta_bm_pool *bm_pool = NULL;
2132 struct sk_buff *skb;
2133 unsigned char *data;
2134 dma_addr_t phys_addr;
2135 u32 rx_status, frag_size;
2140 rx_status = rx_desc->status;
2141 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2142 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2143 phys_addr = rx_desc->buf_phys_addr;
2144 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2145 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2147 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2148 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2149 err_drop_frame_ret_pool:
2150 /* Return the buffer to the pool */
2151 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2152 rx_desc->buf_phys_addr);
2154 mvneta_rx_error(pp, rx_desc);
2155 /* leave the descriptor untouched */
2159 if (rx_bytes <= rx_copybreak) {
2160 /* better copy a small frame and not unmap the DMA region */
2161 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2163 goto err_drop_frame_ret_pool;
2165 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2166 rx_desc->buf_phys_addr,
2167 MVNETA_MH_SIZE + NET_SKB_PAD,
2170 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2173 skb->protocol = eth_type_trans(skb, dev);
2174 mvneta_rx_csum(pp, rx_status, skb);
2175 napi_gro_receive(napi, skb);
2178 rcvd_bytes += rx_bytes;
2180 /* Return the buffer to the pool */
2181 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2182 rx_desc->buf_phys_addr);
2184 /* leave the descriptor and buffer untouched */
2188 /* Refill processing */
2189 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2191 netdev_err(dev, "Linux processing - Can't refill\n");
2193 goto err_drop_frame_ret_pool;
2196 frag_size = bm_pool->hwbm_pool.frag_size;
2198 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2200 /* After refill old buffer has to be unmapped regardless
2201 * the skb is successfully built or not.
2203 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2204 bm_pool->buf_size, DMA_FROM_DEVICE);
2206 goto err_drop_frame;
2209 rcvd_bytes += rx_bytes;
2211 /* Linux processing */
2212 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2213 skb_put(skb, rx_bytes);
2215 skb->protocol = eth_type_trans(skb, dev);
2217 mvneta_rx_csum(pp, rx_status, skb);
2219 napi_gro_receive(napi, skb);
2223 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2225 u64_stats_update_begin(&stats->syncp);
2226 stats->rx_packets += rcvd_pkts;
2227 stats->rx_bytes += rcvd_bytes;
2228 u64_stats_update_end(&stats->syncp);
2231 /* Update rxq management counters */
2232 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2238 mvneta_tso_put_hdr(struct sk_buff *skb,
2239 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2241 struct mvneta_tx_desc *tx_desc;
2242 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2244 txq->tx_skb[txq->txq_put_index] = NULL;
2245 tx_desc = mvneta_txq_next_desc_get(txq);
2246 tx_desc->data_size = hdr_len;
2247 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2248 tx_desc->command |= MVNETA_TXD_F_DESC;
2249 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2250 txq->txq_put_index * TSO_HEADER_SIZE;
2251 mvneta_txq_inc_put(txq);
2255 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2256 struct sk_buff *skb, char *data, int size,
2257 bool last_tcp, bool is_last)
2259 struct mvneta_tx_desc *tx_desc;
2261 tx_desc = mvneta_txq_next_desc_get(txq);
2262 tx_desc->data_size = size;
2263 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2264 size, DMA_TO_DEVICE);
2265 if (unlikely(dma_mapping_error(dev->dev.parent,
2266 tx_desc->buf_phys_addr))) {
2267 mvneta_txq_desc_put(txq);
2271 tx_desc->command = 0;
2272 txq->tx_skb[txq->txq_put_index] = NULL;
2275 /* last descriptor in the TCP packet */
2276 tx_desc->command = MVNETA_TXD_L_DESC;
2278 /* last descriptor in SKB */
2280 txq->tx_skb[txq->txq_put_index] = skb;
2282 mvneta_txq_inc_put(txq);
2286 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2287 struct mvneta_tx_queue *txq)
2289 int total_len, data_left;
2291 struct mvneta_port *pp = netdev_priv(dev);
2293 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2296 /* Count needed descriptors */
2297 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2300 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2301 pr_info("*** Is this even possible???!?!?\n");
2305 /* Initialize the TSO handler, and prepare the first payload */
2306 tso_start(skb, &tso);
2308 total_len = skb->len - hdr_len;
2309 while (total_len > 0) {
2312 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2313 total_len -= data_left;
2316 /* prepare packet headers: MAC + IP + TCP */
2317 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2318 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2320 mvneta_tso_put_hdr(skb, pp, txq);
2322 while (data_left > 0) {
2326 size = min_t(int, tso.size, data_left);
2328 if (mvneta_tso_put_data(dev, txq, skb,
2335 tso_build_data(skb, &tso, size);
2342 /* Release all used data descriptors; header descriptors must not
2345 for (i = desc_count - 1; i >= 0; i--) {
2346 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2347 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2348 dma_unmap_single(pp->dev->dev.parent,
2349 tx_desc->buf_phys_addr,
2352 mvneta_txq_desc_put(txq);
2357 /* Handle tx fragmentation processing */
2358 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2359 struct mvneta_tx_queue *txq)
2361 struct mvneta_tx_desc *tx_desc;
2362 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2364 for (i = 0; i < nr_frags; i++) {
2365 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2366 void *addr = page_address(frag->page.p) + frag->page_offset;
2368 tx_desc = mvneta_txq_next_desc_get(txq);
2369 tx_desc->data_size = frag->size;
2371 tx_desc->buf_phys_addr =
2372 dma_map_single(pp->dev->dev.parent, addr,
2373 tx_desc->data_size, DMA_TO_DEVICE);
2375 if (dma_mapping_error(pp->dev->dev.parent,
2376 tx_desc->buf_phys_addr)) {
2377 mvneta_txq_desc_put(txq);
2381 if (i == nr_frags - 1) {
2382 /* Last descriptor */
2383 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2384 txq->tx_skb[txq->txq_put_index] = skb;
2386 /* Descriptor in the middle: Not First, Not Last */
2387 tx_desc->command = 0;
2388 txq->tx_skb[txq->txq_put_index] = NULL;
2390 mvneta_txq_inc_put(txq);
2396 /* Release all descriptors that were used to map fragments of
2397 * this packet, as well as the corresponding DMA mappings
2399 for (i = i - 1; i >= 0; i--) {
2400 tx_desc = txq->descs + i;
2401 dma_unmap_single(pp->dev->dev.parent,
2402 tx_desc->buf_phys_addr,
2405 mvneta_txq_desc_put(txq);
2411 /* Main tx processing */
2412 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2414 struct mvneta_port *pp = netdev_priv(dev);
2415 u16 txq_id = skb_get_queue_mapping(skb);
2416 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2417 struct mvneta_tx_desc *tx_desc;
2422 if (!netif_running(dev))
2425 if (skb_is_gso(skb)) {
2426 frags = mvneta_tx_tso(skb, dev, txq);
2430 frags = skb_shinfo(skb)->nr_frags + 1;
2432 /* Get a descriptor for the first part of the packet */
2433 tx_desc = mvneta_txq_next_desc_get(txq);
2435 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2437 tx_desc->data_size = skb_headlen(skb);
2439 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2442 if (unlikely(dma_mapping_error(dev->dev.parent,
2443 tx_desc->buf_phys_addr))) {
2444 mvneta_txq_desc_put(txq);
2450 /* First and Last descriptor */
2451 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2452 tx_desc->command = tx_cmd;
2453 txq->tx_skb[txq->txq_put_index] = skb;
2454 mvneta_txq_inc_put(txq);
2456 /* First but not Last */
2457 tx_cmd |= MVNETA_TXD_F_DESC;
2458 txq->tx_skb[txq->txq_put_index] = NULL;
2459 mvneta_txq_inc_put(txq);
2460 tx_desc->command = tx_cmd;
2461 /* Continue with other skb fragments */
2462 if (mvneta_tx_frag_process(pp, skb, txq)) {
2463 dma_unmap_single(dev->dev.parent,
2464 tx_desc->buf_phys_addr,
2467 mvneta_txq_desc_put(txq);
2475 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2476 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2478 netdev_tx_sent_queue(nq, len);
2480 txq->count += frags;
2481 if (txq->count >= txq->tx_stop_threshold)
2482 netif_tx_stop_queue(nq);
2484 if (!skb->xmit_more || netif_xmit_stopped(nq) ||
2485 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2486 mvneta_txq_pend_desc_add(pp, txq, frags);
2488 txq->pending += frags;
2490 u64_stats_update_begin(&stats->syncp);
2491 stats->tx_packets++;
2492 stats->tx_bytes += len;
2493 u64_stats_update_end(&stats->syncp);
2495 dev->stats.tx_dropped++;
2496 dev_kfree_skb_any(skb);
2499 return NETDEV_TX_OK;
2503 /* Free tx resources, when resetting a port */
2504 static void mvneta_txq_done_force(struct mvneta_port *pp,
2505 struct mvneta_tx_queue *txq)
2508 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2509 int tx_done = txq->count;
2511 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2515 txq->txq_put_index = 0;
2516 txq->txq_get_index = 0;
2519 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2520 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2522 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2524 struct mvneta_tx_queue *txq;
2525 struct netdev_queue *nq;
2527 while (cause_tx_done) {
2528 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2530 nq = netdev_get_tx_queue(pp->dev, txq->id);
2531 __netif_tx_lock(nq, smp_processor_id());
2534 mvneta_txq_done(pp, txq);
2536 __netif_tx_unlock(nq);
2537 cause_tx_done &= ~((1 << txq->id));
2541 /* Compute crc8 of the specified address, using a unique algorithm ,
2542 * according to hw spec, different than generic crc8 algorithm
2544 static int mvneta_addr_crc(unsigned char *addr)
2549 for (i = 0; i < ETH_ALEN; i++) {
2552 crc = (crc ^ addr[i]) << 8;
2553 for (j = 7; j >= 0; j--) {
2554 if (crc & (0x100 << j))
2562 /* This method controls the net device special MAC multicast support.
2563 * The Special Multicast Table for MAC addresses supports MAC of the form
2564 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2565 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2566 * Table entries in the DA-Filter table. This method set the Special
2567 * Multicast Table appropriate entry.
2569 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2570 unsigned char last_byte,
2573 unsigned int smc_table_reg;
2574 unsigned int tbl_offset;
2575 unsigned int reg_offset;
2577 /* Register offset from SMC table base */
2578 tbl_offset = (last_byte / 4);
2579 /* Entry offset within the above reg */
2580 reg_offset = last_byte % 4;
2582 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2586 smc_table_reg &= ~(0xff << (8 * reg_offset));
2588 smc_table_reg &= ~(0xff << (8 * reg_offset));
2589 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2592 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2596 /* This method controls the network device Other MAC multicast support.
2597 * The Other Multicast Table is used for multicast of another type.
2598 * A CRC-8 is used as an index to the Other Multicast Table entries
2599 * in the DA-Filter table.
2600 * The method gets the CRC-8 value from the calling routine and
2601 * sets the Other Multicast Table appropriate entry according to the
2604 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2608 unsigned int omc_table_reg;
2609 unsigned int tbl_offset;
2610 unsigned int reg_offset;
2612 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2613 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2615 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2618 /* Clear accepts frame bit at specified Other DA table entry */
2619 omc_table_reg &= ~(0xff << (8 * reg_offset));
2621 omc_table_reg &= ~(0xff << (8 * reg_offset));
2622 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2625 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2628 /* The network device supports multicast using two tables:
2629 * 1) Special Multicast Table for MAC addresses of the form
2630 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2631 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2632 * Table entries in the DA-Filter table.
2633 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2634 * is used as an index to the Other Multicast Table entries in the
2637 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2640 unsigned char crc_result = 0;
2642 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2643 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2647 crc_result = mvneta_addr_crc(p_addr);
2649 if (pp->mcast_count[crc_result] == 0) {
2650 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2655 pp->mcast_count[crc_result]--;
2656 if (pp->mcast_count[crc_result] != 0) {
2657 netdev_info(pp->dev,
2658 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2659 pp->mcast_count[crc_result], crc_result);
2663 pp->mcast_count[crc_result]++;
2665 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2670 /* Configure Fitering mode of Ethernet port */
2671 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2674 u32 port_cfg_reg, val;
2676 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2678 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2680 /* Set / Clear UPM bit in port configuration register */
2682 /* Accept all Unicast addresses */
2683 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2684 val |= MVNETA_FORCE_UNI;
2685 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2686 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2688 /* Reject all Unicast addresses */
2689 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2690 val &= ~MVNETA_FORCE_UNI;
2693 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2694 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2697 /* register unicast and multicast addresses */
2698 static void mvneta_set_rx_mode(struct net_device *dev)
2700 struct mvneta_port *pp = netdev_priv(dev);
2701 struct netdev_hw_addr *ha;
2703 if (dev->flags & IFF_PROMISC) {
2704 /* Accept all: Multicast + Unicast */
2705 mvneta_rx_unicast_promisc_set(pp, 1);
2706 mvneta_set_ucast_table(pp, pp->rxq_def);
2707 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2708 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2710 /* Accept single Unicast */
2711 mvneta_rx_unicast_promisc_set(pp, 0);
2712 mvneta_set_ucast_table(pp, -1);
2713 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2715 if (dev->flags & IFF_ALLMULTI) {
2716 /* Accept all multicast */
2717 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2718 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2720 /* Accept only initialized multicast */
2721 mvneta_set_special_mcast_table(pp, -1);
2722 mvneta_set_other_mcast_table(pp, -1);
2724 if (!netdev_mc_empty(dev)) {
2725 netdev_for_each_mc_addr(ha, dev) {
2726 mvneta_mcast_addr_set(pp, ha->addr,
2734 /* Interrupt handling - the callback for request_irq() */
2735 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2737 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2739 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2740 napi_schedule(&pp->napi);
2745 /* Interrupt handling - the callback for request_percpu_irq() */
2746 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
2748 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2750 disable_percpu_irq(port->pp->dev->irq);
2751 napi_schedule(&port->napi);
2756 static void mvneta_link_change(struct mvneta_port *pp)
2758 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2760 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
2764 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2765 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2766 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2767 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2768 * Each CPU has its own causeRxTx register
2770 static int mvneta_poll(struct napi_struct *napi, int budget)
2775 struct mvneta_port *pp = netdev_priv(napi->dev);
2776 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2778 if (!netif_running(pp->dev)) {
2779 napi_complete(napi);
2783 /* Read cause register */
2784 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2785 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2786 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2788 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2790 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2791 MVNETA_CAUSE_LINK_CHANGE))
2792 mvneta_link_change(pp);
2795 /* Release Tx descriptors */
2796 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2797 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2798 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2801 /* For the case where the last mvneta_poll did not process all
2804 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
2807 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2809 rx_queue = rx_queue - 1;
2811 rx_done = mvneta_rx_hwbm(napi, pp, budget,
2812 &pp->rxqs[rx_queue]);
2814 rx_done = mvneta_rx_swbm(napi, pp, budget,
2815 &pp->rxqs[rx_queue]);
2818 if (rx_done < budget) {
2820 napi_complete_done(napi, rx_done);
2822 if (pp->neta_armada3700) {
2823 unsigned long flags;
2825 local_irq_save(flags);
2826 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2827 MVNETA_RX_INTR_MASK(rxq_number) |
2828 MVNETA_TX_INTR_MASK(txq_number) |
2829 MVNETA_MISCINTR_INTR_MASK);
2830 local_irq_restore(flags);
2832 enable_percpu_irq(pp->dev->irq, 0);
2836 if (pp->neta_armada3700)
2837 pp->cause_rx_tx = cause_rx_tx;
2839 port->cause_rx_tx = cause_rx_tx;
2844 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2845 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2850 for (i = 0; i < num; i++) {
2851 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2852 if (mvneta_rx_refill(pp, rxq->descs + i, rxq,
2855 "%s:rxq %d, %d of %d buffs filled\n",
2856 __func__, rxq->id, i, num);
2861 /* Add this number of RX descriptors as non occupied (ready to
2864 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2869 /* Free all packets pending transmit from all TXQs and reset TX port */
2870 static void mvneta_tx_reset(struct mvneta_port *pp)
2874 /* free the skb's in the tx ring */
2875 for (queue = 0; queue < txq_number; queue++)
2876 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2878 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2879 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2882 static void mvneta_rx_reset(struct mvneta_port *pp)
2884 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2885 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2888 /* Rx/Tx queue initialization/cleanup methods */
2890 static int mvneta_rxq_sw_init(struct mvneta_port *pp,
2891 struct mvneta_rx_queue *rxq)
2893 rxq->size = pp->rx_ring_size;
2895 /* Allocate memory for RX descriptors */
2896 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2897 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2898 &rxq->descs_phys, GFP_KERNEL);
2902 rxq->last_desc = rxq->size - 1;
2907 static void mvneta_rxq_hw_init(struct mvneta_port *pp,
2908 struct mvneta_rx_queue *rxq)
2910 /* Set Rx descriptors queue starting address */
2911 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2912 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2914 /* Set coalescing pkts and time */
2915 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2916 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2920 mvneta_rxq_offset_set(pp, rxq, 0);
2921 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
2923 MVNETA_RX_BUF_SIZE(pp->pkt_size));
2924 mvneta_rxq_bm_disable(pp, rxq);
2925 mvneta_rxq_fill(pp, rxq, rxq->size);
2928 mvneta_rxq_offset_set(pp, rxq,
2929 NET_SKB_PAD - pp->rx_offset_correction);
2931 mvneta_rxq_bm_enable(pp, rxq);
2932 /* Fill RXQ with buffers from RX pool */
2933 mvneta_rxq_long_pool_set(pp, rxq);
2934 mvneta_rxq_short_pool_set(pp, rxq);
2935 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
2939 /* Create a specified RX queue */
2940 static int mvneta_rxq_init(struct mvneta_port *pp,
2941 struct mvneta_rx_queue *rxq)
2946 ret = mvneta_rxq_sw_init(pp, rxq);
2950 mvneta_rxq_hw_init(pp, rxq);
2955 /* Cleanup Rx queue */
2956 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2957 struct mvneta_rx_queue *rxq)
2959 mvneta_rxq_drop_pkts(pp, rxq);
2962 dev_kfree_skb_any(rxq->skb);
2965 dma_free_coherent(pp->dev->dev.parent,
2966 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2972 rxq->next_desc_to_proc = 0;
2973 rxq->descs_phys = 0;
2974 rxq->first_to_refill = 0;
2975 rxq->refill_num = 0;
2980 static int mvneta_txq_sw_init(struct mvneta_port *pp,
2981 struct mvneta_tx_queue *txq)
2985 txq->size = pp->tx_ring_size;
2987 /* A queue must always have room for at least one skb.
2988 * Therefore, stop the queue when the free entries reaches
2989 * the maximum number of descriptors per skb.
2991 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2992 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2994 /* Allocate memory for TX descriptors */
2995 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2996 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2997 &txq->descs_phys, GFP_KERNEL);
3001 txq->last_desc = txq->size - 1;
3003 txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb),
3006 dma_free_coherent(pp->dev->dev.parent,
3007 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3008 txq->descs, txq->descs_phys);
3012 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3013 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
3014 txq->size * TSO_HEADER_SIZE,
3015 &txq->tso_hdrs_phys, GFP_KERNEL);
3016 if (!txq->tso_hdrs) {
3018 dma_free_coherent(pp->dev->dev.parent,
3019 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3020 txq->descs, txq->descs_phys);
3024 /* Setup XPS mapping */
3025 if (pp->neta_armada3700)
3027 else if (txq_number > 1)
3028 cpu = txq->id % num_present_cpus();
3030 cpu = pp->rxq_def % num_present_cpus();
3031 cpumask_set_cpu(cpu, &txq->affinity_mask);
3032 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
3037 static void mvneta_txq_hw_init(struct mvneta_port *pp,
3038 struct mvneta_tx_queue *txq)
3040 /* Set maximum bandwidth for enabled TXQs */
3041 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3042 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3044 /* Set Tx descriptors queue starting address */
3045 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3046 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3048 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3051 /* Create and initialize a tx queue */
3052 static int mvneta_txq_init(struct mvneta_port *pp,
3053 struct mvneta_tx_queue *txq)
3057 ret = mvneta_txq_sw_init(pp, txq);
3061 mvneta_txq_hw_init(pp, txq);
3066 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3067 static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
3068 struct mvneta_tx_queue *txq)
3070 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
3075 dma_free_coherent(pp->dev->dev.parent,
3076 txq->size * TSO_HEADER_SIZE,
3077 txq->tso_hdrs, txq->tso_hdrs_phys);
3079 dma_free_coherent(pp->dev->dev.parent,
3080 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3081 txq->descs, txq->descs_phys);
3083 netdev_tx_reset_queue(nq);
3087 txq->next_desc_to_proc = 0;
3088 txq->descs_phys = 0;
3091 static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
3092 struct mvneta_tx_queue *txq)
3094 /* Set minimum bandwidth for disabled TXQs */
3095 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3096 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3098 /* Set Tx descriptors queue starting address and size */
3099 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3100 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3103 static void mvneta_txq_deinit(struct mvneta_port *pp,
3104 struct mvneta_tx_queue *txq)
3106 mvneta_txq_sw_deinit(pp, txq);
3107 mvneta_txq_hw_deinit(pp, txq);
3110 /* Cleanup all Tx queues */
3111 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3115 for (queue = 0; queue < txq_number; queue++)
3116 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3119 /* Cleanup all Rx queues */
3120 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3124 for (queue = 0; queue < rxq_number; queue++)
3125 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3129 /* Init all Rx queues */
3130 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3134 for (queue = 0; queue < rxq_number; queue++) {
3135 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3138 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3140 mvneta_cleanup_rxqs(pp);
3148 /* Init all tx queues */
3149 static int mvneta_setup_txqs(struct mvneta_port *pp)
3153 for (queue = 0; queue < txq_number; queue++) {
3154 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3156 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3158 mvneta_cleanup_txqs(pp);
3166 static void mvneta_start_dev(struct mvneta_port *pp)
3170 mvneta_max_rx_size_set(pp, pp->pkt_size);
3171 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3173 /* start the Rx/Tx activity */
3174 mvneta_port_enable(pp);
3176 if (!pp->neta_armada3700) {
3177 /* Enable polling on the port */
3178 for_each_online_cpu(cpu) {
3179 struct mvneta_pcpu_port *port =
3180 per_cpu_ptr(pp->ports, cpu);
3182 napi_enable(&port->napi);
3185 napi_enable(&pp->napi);
3188 /* Unmask interrupts. It has to be done from each CPU */
3189 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3191 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3192 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3193 MVNETA_CAUSE_LINK_CHANGE);
3195 phylink_start(pp->phylink);
3196 netif_tx_start_all_queues(pp->dev);
3199 static void mvneta_stop_dev(struct mvneta_port *pp)
3203 phylink_stop(pp->phylink);
3205 if (!pp->neta_armada3700) {
3206 for_each_online_cpu(cpu) {
3207 struct mvneta_pcpu_port *port =
3208 per_cpu_ptr(pp->ports, cpu);
3210 napi_disable(&port->napi);
3213 napi_disable(&pp->napi);
3216 netif_carrier_off(pp->dev);
3218 mvneta_port_down(pp);
3219 netif_tx_stop_all_queues(pp->dev);
3221 /* Stop the port activity */
3222 mvneta_port_disable(pp);
3224 /* Clear all ethernet port interrupts */
3225 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3227 /* Mask all ethernet port interrupts */
3228 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3230 mvneta_tx_reset(pp);
3231 mvneta_rx_reset(pp);
3234 static void mvneta_percpu_enable(void *arg)
3236 struct mvneta_port *pp = arg;
3238 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3241 static void mvneta_percpu_disable(void *arg)
3243 struct mvneta_port *pp = arg;
3245 disable_percpu_irq(pp->dev->irq);
3248 /* Change the device mtu */
3249 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3251 struct mvneta_port *pp = netdev_priv(dev);
3254 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3255 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3256 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3257 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3262 if (!netif_running(dev)) {
3264 mvneta_bm_update_mtu(pp, mtu);
3266 netdev_update_features(dev);
3270 /* The interface is running, so we have to force a
3271 * reallocation of the queues
3273 mvneta_stop_dev(pp);
3274 on_each_cpu(mvneta_percpu_disable, pp, true);
3276 mvneta_cleanup_txqs(pp);
3277 mvneta_cleanup_rxqs(pp);
3280 mvneta_bm_update_mtu(pp, mtu);
3282 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3284 ret = mvneta_setup_rxqs(pp);
3286 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3290 ret = mvneta_setup_txqs(pp);
3292 netdev_err(dev, "unable to setup txqs after MTU change\n");
3296 on_each_cpu(mvneta_percpu_enable, pp, true);
3297 mvneta_start_dev(pp);
3299 netdev_update_features(dev);
3304 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3305 netdev_features_t features)
3307 struct mvneta_port *pp = netdev_priv(dev);
3309 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3310 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3312 "Disable IP checksum for MTU greater than %dB\n",
3319 /* Get mac address */
3320 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3322 u32 mac_addr_l, mac_addr_h;
3324 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3325 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3326 addr[0] = (mac_addr_h >> 24) & 0xFF;
3327 addr[1] = (mac_addr_h >> 16) & 0xFF;
3328 addr[2] = (mac_addr_h >> 8) & 0xFF;
3329 addr[3] = mac_addr_h & 0xFF;
3330 addr[4] = (mac_addr_l >> 8) & 0xFF;
3331 addr[5] = mac_addr_l & 0xFF;
3334 /* Handle setting mac address */
3335 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3337 struct mvneta_port *pp = netdev_priv(dev);
3338 struct sockaddr *sockaddr = addr;
3341 ret = eth_prepare_mac_addr_change(dev, addr);
3344 /* Remove previous address table entry */
3345 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3347 /* Set new addr in hw */
3348 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3350 eth_commit_mac_addr_change(dev, addr);
3354 static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
3355 struct phylink_link_state *state)
3357 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
3359 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3360 if (state->interface != PHY_INTERFACE_MODE_NA &&
3361 state->interface != PHY_INTERFACE_MODE_QSGMII &&
3362 state->interface != PHY_INTERFACE_MODE_SGMII &&
3363 !phy_interface_mode_is_8023z(state->interface) &&
3364 !phy_interface_mode_is_rgmii(state->interface)) {
3365 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
3369 /* Allow all the expected bits */
3370 phylink_set(mask, Autoneg);
3371 phylink_set_port_modes(mask);
3373 /* Asymmetric pause is unsupported */
3374 phylink_set(mask, Pause);
3375 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3376 phylink_set(mask, 1000baseT_Full);
3377 phylink_set(mask, 1000baseX_Full);
3379 if (!phy_interface_mode_is_8023z(state->interface)) {
3380 /* 10M and 100M are only supported in non-802.3z mode */
3381 phylink_set(mask, 10baseT_Half);
3382 phylink_set(mask, 10baseT_Full);
3383 phylink_set(mask, 100baseT_Half);
3384 phylink_set(mask, 100baseT_Full);
3387 bitmap_and(supported, supported, mask,
3388 __ETHTOOL_LINK_MODE_MASK_NBITS);
3389 bitmap_and(state->advertising, state->advertising, mask,
3390 __ETHTOOL_LINK_MODE_MASK_NBITS);
3393 static int mvneta_mac_link_state(struct net_device *ndev,
3394 struct phylink_link_state *state)
3396 struct mvneta_port *pp = netdev_priv(ndev);
3399 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3401 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3402 state->speed = SPEED_1000;
3403 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3404 state->speed = SPEED_100;
3406 state->speed = SPEED_10;
3408 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3409 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3410 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3413 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
3414 state->pause |= MLO_PAUSE_RX;
3415 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
3416 state->pause |= MLO_PAUSE_TX;
3421 static void mvneta_mac_an_restart(struct net_device *ndev)
3423 struct mvneta_port *pp = netdev_priv(ndev);
3424 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3426 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3427 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
3428 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3429 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
3432 static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
3433 const struct phylink_link_state *state)
3435 struct mvneta_port *pp = netdev_priv(ndev);
3436 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3437 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3438 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3439 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3441 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
3442 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
3443 MVNETA_GMAC2_PORT_RESET);
3444 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
3445 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
3446 MVNETA_GMAC_INBAND_RESTART_AN |
3447 MVNETA_GMAC_CONFIG_MII_SPEED |
3448 MVNETA_GMAC_CONFIG_GMII_SPEED |
3449 MVNETA_GMAC_AN_SPEED_EN |
3450 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
3451 MVNETA_GMAC_CONFIG_FLOW_CTRL |
3452 MVNETA_GMAC_AN_FLOW_CTRL_EN |
3453 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
3454 MVNETA_GMAC_AN_DUPLEX_EN);
3456 /* Even though it might look weird, when we're configured in
3457 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3459 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
3461 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
3462 state->interface == PHY_INTERFACE_MODE_SGMII ||
3463 phy_interface_mode_is_8023z(state->interface))
3464 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
3466 if (phylink_test(state->advertising, Pause))
3467 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
3468 if (state->pause & MLO_PAUSE_TXRX_MASK)
3469 new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
3471 if (!phylink_autoneg_inband(mode)) {
3472 /* Phy or fixed speed */
3474 new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3476 if (state->speed == SPEED_1000)
3477 new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3478 else if (state->speed == SPEED_100)
3479 new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
3480 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3481 /* SGMII mode receives the state from the PHY */
3482 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3483 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3484 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3485 MVNETA_GMAC_FORCE_LINK_PASS)) |
3486 MVNETA_GMAC_INBAND_AN_ENABLE |
3487 MVNETA_GMAC_AN_SPEED_EN |
3488 MVNETA_GMAC_AN_DUPLEX_EN;
3490 /* 802.3z negotiation - only 1000base-X */
3491 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
3492 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3493 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3494 MVNETA_GMAC_FORCE_LINK_PASS)) |
3495 MVNETA_GMAC_INBAND_AN_ENABLE |
3496 MVNETA_GMAC_CONFIG_GMII_SPEED |
3497 /* The MAC only supports FD mode */
3498 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3500 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
3501 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
3504 /* Armada 370 documentation says we can only change the port mode
3505 * and in-band enable when the link is down, so force it down
3506 * while making these changes. We also do this for GMAC_CTRL2 */
3507 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
3508 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
3509 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
3510 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3511 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
3512 MVNETA_GMAC_FORCE_LINK_DOWN);
3515 if (new_ctrl0 != gmac_ctrl0)
3516 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
3517 if (new_ctrl2 != gmac_ctrl2)
3518 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
3519 if (new_clk != gmac_clk)
3520 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
3521 if (new_an != gmac_an)
3522 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
3524 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
3525 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3526 MVNETA_GMAC2_PORT_RESET) != 0)
3531 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
3535 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
3537 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
3539 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
3540 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
3543 static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode,
3544 phy_interface_t interface)
3546 struct mvneta_port *pp = netdev_priv(ndev);
3549 mvneta_port_down(pp);
3551 if (!phylink_autoneg_inband(mode)) {
3552 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3553 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3554 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3555 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3558 pp->eee_active = false;
3559 mvneta_set_eee(pp, false);
3562 static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
3563 phy_interface_t interface,
3564 struct phy_device *phy)
3566 struct mvneta_port *pp = netdev_priv(ndev);
3569 if (!phylink_autoneg_inband(mode)) {
3570 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3571 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3572 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3573 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3578 if (phy && pp->eee_enabled) {
3579 pp->eee_active = phy_init_eee(phy, 0) >= 0;
3580 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
3584 static const struct phylink_mac_ops mvneta_phylink_ops = {
3585 .validate = mvneta_validate,
3586 .mac_link_state = mvneta_mac_link_state,
3587 .mac_an_restart = mvneta_mac_an_restart,
3588 .mac_config = mvneta_mac_config,
3589 .mac_link_down = mvneta_mac_link_down,
3590 .mac_link_up = mvneta_mac_link_up,
3593 static int mvneta_mdio_probe(struct mvneta_port *pp)
3595 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
3596 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
3599 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
3601 phylink_ethtool_get_wol(pp->phylink, &wol);
3602 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
3607 static void mvneta_mdio_remove(struct mvneta_port *pp)
3609 phylink_disconnect_phy(pp->phylink);
3612 /* Electing a CPU must be done in an atomic way: it should be done
3613 * after or before the removal/insertion of a CPU and this function is
3616 static void mvneta_percpu_elect(struct mvneta_port *pp)
3618 int elected_cpu = 0, max_cpu, cpu, i = 0;
3620 /* Use the cpu associated to the rxq when it is online, in all
3621 * the other cases, use the cpu 0 which can't be offline.
3623 if (cpu_online(pp->rxq_def))
3624 elected_cpu = pp->rxq_def;
3626 max_cpu = num_present_cpus();
3628 for_each_online_cpu(cpu) {
3629 int rxq_map = 0, txq_map = 0;
3632 for (rxq = 0; rxq < rxq_number; rxq++)
3633 if ((rxq % max_cpu) == cpu)
3634 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3636 if (cpu == elected_cpu)
3637 /* Map the default receive queue queue to the
3640 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3642 /* We update the TX queue map only if we have one
3643 * queue. In this case we associate the TX queue to
3644 * the CPU bound to the default RX queue
3646 if (txq_number == 1)
3647 txq_map = (cpu == elected_cpu) ?
3648 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3650 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3651 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3653 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3655 /* Update the interrupt mask on each CPU according the
3658 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3665 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3668 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3670 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3672 /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts
3673 * are routed to CPU 0, so we don't need all the cpu-hotplug support
3675 if (pp->neta_armada3700)
3678 spin_lock(&pp->lock);
3680 * Configuring the driver for a new CPU while the driver is
3681 * stopping is racy, so just avoid it.
3683 if (pp->is_stopped) {
3684 spin_unlock(&pp->lock);
3687 netif_tx_stop_all_queues(pp->dev);
3690 * We have to synchronise on tha napi of each CPU except the one
3691 * just being woken up
3693 for_each_online_cpu(other_cpu) {
3694 if (other_cpu != cpu) {
3695 struct mvneta_pcpu_port *other_port =
3696 per_cpu_ptr(pp->ports, other_cpu);
3698 napi_synchronize(&other_port->napi);
3702 /* Mask all ethernet port interrupts */
3703 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3704 napi_enable(&port->napi);
3707 * Enable per-CPU interrupts on the CPU that is
3710 mvneta_percpu_enable(pp);
3713 * Enable per-CPU interrupt on the one CPU we care
3716 mvneta_percpu_elect(pp);
3718 /* Unmask all ethernet port interrupts */
3719 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3720 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3721 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3722 MVNETA_CAUSE_LINK_CHANGE);
3723 netif_tx_start_all_queues(pp->dev);
3724 spin_unlock(&pp->lock);
3728 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3730 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3732 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3735 * Thanks to this lock we are sure that any pending cpu election is
3738 spin_lock(&pp->lock);
3739 /* Mask all ethernet port interrupts */
3740 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3741 spin_unlock(&pp->lock);
3743 napi_synchronize(&port->napi);
3744 napi_disable(&port->napi);
3745 /* Disable per-CPU interrupts on the CPU that is brought down. */
3746 mvneta_percpu_disable(pp);
3750 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3752 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3755 /* Check if a new CPU must be elected now this on is down */
3756 spin_lock(&pp->lock);
3757 mvneta_percpu_elect(pp);
3758 spin_unlock(&pp->lock);
3759 /* Unmask all ethernet port interrupts */
3760 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3761 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3762 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3763 MVNETA_CAUSE_LINK_CHANGE);
3764 netif_tx_start_all_queues(pp->dev);
3768 static int mvneta_open(struct net_device *dev)
3770 struct mvneta_port *pp = netdev_priv(dev);
3773 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3775 ret = mvneta_setup_rxqs(pp);
3779 ret = mvneta_setup_txqs(pp);
3781 goto err_cleanup_rxqs;
3783 /* Connect to port interrupt line */
3784 if (pp->neta_armada3700)
3785 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
3788 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
3789 dev->name, pp->ports);
3791 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3792 goto err_cleanup_txqs;
3795 if (!pp->neta_armada3700) {
3796 /* Enable per-CPU interrupt on all the CPU to handle our RX
3799 on_each_cpu(mvneta_percpu_enable, pp, true);
3801 pp->is_stopped = false;
3802 /* Register a CPU notifier to handle the case where our CPU
3803 * might be taken offline.
3805 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3810 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3813 goto err_free_online_hp;
3816 /* In default link is down */
3817 netif_carrier_off(pp->dev);
3819 ret = mvneta_mdio_probe(pp);
3821 netdev_err(dev, "cannot probe MDIO bus\n");
3822 goto err_free_dead_hp;
3825 mvneta_start_dev(pp);
3830 if (!pp->neta_armada3700)
3831 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3834 if (!pp->neta_armada3700)
3835 cpuhp_state_remove_instance_nocalls(online_hpstate,
3838 if (pp->neta_armada3700) {
3839 free_irq(pp->dev->irq, pp);
3841 on_each_cpu(mvneta_percpu_disable, pp, true);
3842 free_percpu_irq(pp->dev->irq, pp->ports);
3845 mvneta_cleanup_txqs(pp);
3847 mvneta_cleanup_rxqs(pp);
3851 /* Stop the port, free port interrupt line */
3852 static int mvneta_stop(struct net_device *dev)
3854 struct mvneta_port *pp = netdev_priv(dev);
3856 if (!pp->neta_armada3700) {
3857 /* Inform that we are stopping so we don't want to setup the
3858 * driver for new CPUs in the notifiers. The code of the
3859 * notifier for CPU online is protected by the same spinlock,
3860 * so when we get the lock, the notifer work is done.
3862 spin_lock(&pp->lock);
3863 pp->is_stopped = true;
3864 spin_unlock(&pp->lock);
3866 mvneta_stop_dev(pp);
3867 mvneta_mdio_remove(pp);
3869 cpuhp_state_remove_instance_nocalls(online_hpstate,
3871 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3873 on_each_cpu(mvneta_percpu_disable, pp, true);
3874 free_percpu_irq(dev->irq, pp->ports);
3876 mvneta_stop_dev(pp);
3877 mvneta_mdio_remove(pp);
3878 free_irq(dev->irq, pp);
3881 mvneta_cleanup_rxqs(pp);
3882 mvneta_cleanup_txqs(pp);
3887 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3889 struct mvneta_port *pp = netdev_priv(dev);
3891 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
3894 /* Ethtool methods */
3896 /* Set link ksettings (phy address, speed) for ethtools */
3898 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3899 const struct ethtool_link_ksettings *cmd)
3901 struct mvneta_port *pp = netdev_priv(ndev);
3903 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
3906 /* Get link ksettings for ethtools */
3908 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
3909 struct ethtool_link_ksettings *cmd)
3911 struct mvneta_port *pp = netdev_priv(ndev);
3913 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
3916 static int mvneta_ethtool_nway_reset(struct net_device *dev)
3918 struct mvneta_port *pp = netdev_priv(dev);
3920 return phylink_ethtool_nway_reset(pp->phylink);
3923 /* Set interrupt coalescing for ethtools */
3924 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3925 struct ethtool_coalesce *c)
3927 struct mvneta_port *pp = netdev_priv(dev);
3930 for (queue = 0; queue < rxq_number; queue++) {
3931 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3932 rxq->time_coal = c->rx_coalesce_usecs;
3933 rxq->pkts_coal = c->rx_max_coalesced_frames;
3934 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3935 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3938 for (queue = 0; queue < txq_number; queue++) {
3939 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3940 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3941 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3947 /* get coalescing for ethtools */
3948 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3949 struct ethtool_coalesce *c)
3951 struct mvneta_port *pp = netdev_priv(dev);
3953 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3954 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3956 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3961 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3962 struct ethtool_drvinfo *drvinfo)
3964 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3965 sizeof(drvinfo->driver));
3966 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3967 sizeof(drvinfo->version));
3968 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3969 sizeof(drvinfo->bus_info));
3973 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3974 struct ethtool_ringparam *ring)
3976 struct mvneta_port *pp = netdev_priv(netdev);
3978 ring->rx_max_pending = MVNETA_MAX_RXD;
3979 ring->tx_max_pending = MVNETA_MAX_TXD;
3980 ring->rx_pending = pp->rx_ring_size;
3981 ring->tx_pending = pp->tx_ring_size;
3984 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3985 struct ethtool_ringparam *ring)
3987 struct mvneta_port *pp = netdev_priv(dev);
3989 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3991 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3992 ring->rx_pending : MVNETA_MAX_RXD;
3994 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3995 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3996 if (pp->tx_ring_size != ring->tx_pending)
3997 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3998 pp->tx_ring_size, ring->tx_pending);
4000 if (netif_running(dev)) {
4002 if (mvneta_open(dev)) {
4004 "error on opening device after ring param change\n");
4012 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
4013 struct ethtool_pauseparam *pause)
4015 struct mvneta_port *pp = netdev_priv(dev);
4017 phylink_ethtool_get_pauseparam(pp->phylink, pause);
4020 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
4021 struct ethtool_pauseparam *pause)
4023 struct mvneta_port *pp = netdev_priv(dev);
4025 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
4028 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
4031 if (sset == ETH_SS_STATS) {
4034 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4035 memcpy(data + i * ETH_GSTRING_LEN,
4036 mvneta_statistics[i].name, ETH_GSTRING_LEN);
4040 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
4042 const struct mvneta_statistic *s;
4043 void __iomem *base = pp->base;
4048 for (i = 0, s = mvneta_statistics;
4049 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
4055 val = readl_relaxed(base + s->offset);
4058 /* Docs say to read low 32-bit then high */
4059 low = readl_relaxed(base + s->offset);
4060 high = readl_relaxed(base + s->offset + 4);
4061 val = (u64)high << 32 | low;
4064 switch (s->offset) {
4065 case ETHTOOL_STAT_EEE_WAKEUP:
4066 val = phylink_get_eee_err(pp->phylink);
4068 case ETHTOOL_STAT_SKB_ALLOC_ERR:
4069 val = pp->rxqs[0].skb_alloc_err;
4071 case ETHTOOL_STAT_REFILL_ERR:
4072 val = pp->rxqs[0].refill_err;
4078 pp->ethtool_stats[i] += val;
4082 static void mvneta_ethtool_get_stats(struct net_device *dev,
4083 struct ethtool_stats *stats, u64 *data)
4085 struct mvneta_port *pp = netdev_priv(dev);
4088 mvneta_ethtool_update_stats(pp);
4090 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4091 *data++ = pp->ethtool_stats[i];
4094 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
4096 if (sset == ETH_SS_STATS)
4097 return ARRAY_SIZE(mvneta_statistics);
4101 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
4103 return MVNETA_RSS_LU_TABLE_SIZE;
4106 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
4107 struct ethtool_rxnfc *info,
4108 u32 *rules __always_unused)
4110 switch (info->cmd) {
4111 case ETHTOOL_GRXRINGS:
4112 info->data = rxq_number;
4121 static int mvneta_config_rss(struct mvneta_port *pp)
4126 netif_tx_stop_all_queues(pp->dev);
4128 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4130 if (!pp->neta_armada3700) {
4131 /* We have to synchronise on the napi of each CPU */
4132 for_each_online_cpu(cpu) {
4133 struct mvneta_pcpu_port *pcpu_port =
4134 per_cpu_ptr(pp->ports, cpu);
4136 napi_synchronize(&pcpu_port->napi);
4137 napi_disable(&pcpu_port->napi);
4140 napi_synchronize(&pp->napi);
4141 napi_disable(&pp->napi);
4144 pp->rxq_def = pp->indir[0];
4146 /* Update unicast mapping */
4147 mvneta_set_rx_mode(pp->dev);
4149 /* Update val of portCfg register accordingly with all RxQueue types */
4150 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
4151 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4153 /* Update the elected CPU matching the new rxq_def */
4154 spin_lock(&pp->lock);
4155 mvneta_percpu_elect(pp);
4156 spin_unlock(&pp->lock);
4158 if (!pp->neta_armada3700) {
4159 /* We have to synchronise on the napi of each CPU */
4160 for_each_online_cpu(cpu) {
4161 struct mvneta_pcpu_port *pcpu_port =
4162 per_cpu_ptr(pp->ports, cpu);
4164 napi_enable(&pcpu_port->napi);
4167 napi_enable(&pp->napi);
4170 netif_tx_start_all_queues(pp->dev);
4175 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4176 const u8 *key, const u8 hfunc)
4178 struct mvneta_port *pp = netdev_priv(dev);
4180 /* Current code for Armada 3700 doesn't support RSS features yet */
4181 if (pp->neta_armada3700)
4184 /* We require at least one supported parameter to be changed
4185 * and no change in any of the unsupported parameters
4188 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
4194 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
4196 return mvneta_config_rss(pp);
4199 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4202 struct mvneta_port *pp = netdev_priv(dev);
4204 /* Current code for Armada 3700 doesn't support RSS features yet */
4205 if (pp->neta_armada3700)
4209 *hfunc = ETH_RSS_HASH_TOP;
4214 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
4219 static void mvneta_ethtool_get_wol(struct net_device *dev,
4220 struct ethtool_wolinfo *wol)
4222 struct mvneta_port *pp = netdev_priv(dev);
4224 phylink_ethtool_get_wol(pp->phylink, wol);
4227 static int mvneta_ethtool_set_wol(struct net_device *dev,
4228 struct ethtool_wolinfo *wol)
4230 struct mvneta_port *pp = netdev_priv(dev);
4233 ret = phylink_ethtool_set_wol(pp->phylink, wol);
4235 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
4240 static int mvneta_ethtool_get_eee(struct net_device *dev,
4241 struct ethtool_eee *eee)
4243 struct mvneta_port *pp = netdev_priv(dev);
4246 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4248 eee->eee_enabled = pp->eee_enabled;
4249 eee->eee_active = pp->eee_active;
4250 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
4251 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
4253 return phylink_ethtool_get_eee(pp->phylink, eee);
4256 static int mvneta_ethtool_set_eee(struct net_device *dev,
4257 struct ethtool_eee *eee)
4259 struct mvneta_port *pp = netdev_priv(dev);
4262 /* The Armada 37x documents do not give limits for this other than
4263 * it being an 8-bit register. */
4264 if (eee->tx_lpi_enabled &&
4265 (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
4268 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4269 lpi_ctl0 &= ~(0xff << 8);
4270 lpi_ctl0 |= eee->tx_lpi_timer << 8;
4271 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
4273 pp->eee_enabled = eee->eee_enabled;
4274 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
4276 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
4278 return phylink_ethtool_set_eee(pp->phylink, eee);
4281 static const struct net_device_ops mvneta_netdev_ops = {
4282 .ndo_open = mvneta_open,
4283 .ndo_stop = mvneta_stop,
4284 .ndo_start_xmit = mvneta_tx,
4285 .ndo_set_rx_mode = mvneta_set_rx_mode,
4286 .ndo_set_mac_address = mvneta_set_mac_addr,
4287 .ndo_change_mtu = mvneta_change_mtu,
4288 .ndo_fix_features = mvneta_fix_features,
4289 .ndo_get_stats64 = mvneta_get_stats64,
4290 .ndo_do_ioctl = mvneta_ioctl,
4293 static const struct ethtool_ops mvneta_eth_tool_ops = {
4294 .nway_reset = mvneta_ethtool_nway_reset,
4295 .get_link = ethtool_op_get_link,
4296 .set_coalesce = mvneta_ethtool_set_coalesce,
4297 .get_coalesce = mvneta_ethtool_get_coalesce,
4298 .get_drvinfo = mvneta_ethtool_get_drvinfo,
4299 .get_ringparam = mvneta_ethtool_get_ringparam,
4300 .set_ringparam = mvneta_ethtool_set_ringparam,
4301 .get_pauseparam = mvneta_ethtool_get_pauseparam,
4302 .set_pauseparam = mvneta_ethtool_set_pauseparam,
4303 .get_strings = mvneta_ethtool_get_strings,
4304 .get_ethtool_stats = mvneta_ethtool_get_stats,
4305 .get_sset_count = mvneta_ethtool_get_sset_count,
4306 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
4307 .get_rxnfc = mvneta_ethtool_get_rxnfc,
4308 .get_rxfh = mvneta_ethtool_get_rxfh,
4309 .set_rxfh = mvneta_ethtool_set_rxfh,
4310 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
4311 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
4312 .get_wol = mvneta_ethtool_get_wol,
4313 .set_wol = mvneta_ethtool_set_wol,
4314 .get_eee = mvneta_ethtool_get_eee,
4315 .set_eee = mvneta_ethtool_set_eee,
4319 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4324 mvneta_port_disable(pp);
4326 /* Set port default values */
4327 mvneta_defaults_set(pp);
4329 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4333 /* Initialize TX descriptor rings */
4334 for (queue = 0; queue < txq_number; queue++) {
4335 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4337 txq->size = pp->tx_ring_size;
4338 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4341 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4345 /* Create Rx descriptor rings */
4346 for (queue = 0; queue < rxq_number; queue++) {
4347 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4349 rxq->size = pp->rx_ring_size;
4350 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4351 rxq->time_coal = MVNETA_RX_COAL_USEC;
4353 = devm_kmalloc_array(pp->dev->dev.parent,
4355 sizeof(*rxq->buf_virt_addr),
4357 if (!rxq->buf_virt_addr)
4364 /* platform glue : initialize decoding windows */
4365 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
4366 const struct mbus_dram_target_info *dram)
4372 for (i = 0; i < 6; i++) {
4373 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
4374 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
4377 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4384 for (i = 0; i < dram->num_cs; i++) {
4385 const struct mbus_dram_window *cs = dram->cs + i;
4387 mvreg_write(pp, MVNETA_WIN_BASE(i),
4388 (cs->base & 0xffff0000) |
4389 (cs->mbus_attr << 8) |
4390 dram->mbus_dram_target_id);
4392 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4393 (cs->size - 1) & 0xffff0000);
4395 win_enable &= ~(1 << i);
4396 win_protect |= 3 << (2 * i);
4399 /* For Armada3700 open default 4GB Mbus window, leaving
4400 * arbitration of target/attribute to a different layer
4403 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4404 win_enable &= ~BIT(0);
4408 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4409 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4412 /* Power up the port */
4413 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4415 /* MAC Cause register should be cleared */
4416 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4418 if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
4419 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4420 else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
4421 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
4422 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4423 else if (!phy_interface_mode_is_rgmii(phy_mode))
4429 /* Device initialization routine */
4430 static int mvneta_probe(struct platform_device *pdev)
4432 struct resource *res;
4433 struct device_node *dn = pdev->dev.of_node;
4434 struct device_node *bm_node;
4435 struct mvneta_port *pp;
4436 struct net_device *dev;
4437 struct phylink *phylink;
4438 const char *dt_mac_addr;
4439 char hw_mac_addr[ETH_ALEN];
4440 const char *mac_from;
4446 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
4450 dev->irq = irq_of_parse_and_map(dn, 0);
4451 if (dev->irq == 0) {
4453 goto err_free_netdev;
4456 phy_mode = of_get_phy_mode(dn);
4458 dev_err(&pdev->dev, "incorrect phy-mode\n");
4463 phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
4464 &mvneta_phylink_ops);
4465 if (IS_ERR(phylink)) {
4466 err = PTR_ERR(phylink);
4470 dev->tx_queue_len = MVNETA_MAX_TXD;
4471 dev->watchdog_timeo = 5 * HZ;
4472 dev->netdev_ops = &mvneta_netdev_ops;
4474 dev->ethtool_ops = &mvneta_eth_tool_ops;
4476 pp = netdev_priv(dev);
4477 spin_lock_init(&pp->lock);
4478 pp->phylink = phylink;
4479 pp->phy_interface = phy_mode;
4482 pp->rxq_def = rxq_def;
4483 pp->indir[0] = rxq_def;
4485 /* Get special SoC configurations */
4486 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
4487 pp->neta_armada3700 = true;
4489 pp->clk = devm_clk_get(&pdev->dev, "core");
4490 if (IS_ERR(pp->clk))
4491 pp->clk = devm_clk_get(&pdev->dev, NULL);
4492 if (IS_ERR(pp->clk)) {
4493 err = PTR_ERR(pp->clk);
4494 goto err_free_phylink;
4497 clk_prepare_enable(pp->clk);
4499 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4500 if (!IS_ERR(pp->clk_bus))
4501 clk_prepare_enable(pp->clk_bus);
4503 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4504 pp->base = devm_ioremap_resource(&pdev->dev, res);
4505 if (IS_ERR(pp->base)) {
4506 err = PTR_ERR(pp->base);
4510 /* Alloc per-cpu port structure */
4511 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4517 /* Alloc per-cpu stats */
4518 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4521 goto err_free_ports;
4524 dt_mac_addr = of_get_mac_address(dn);
4526 mac_from = "device tree";
4527 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4529 mvneta_get_mac_addr(pp, hw_mac_addr);
4530 if (is_valid_ether_addr(hw_mac_addr)) {
4531 mac_from = "hardware";
4532 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4534 mac_from = "random";
4535 eth_hw_addr_random(dev);
4539 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4540 if (tx_csum_limit < 0 ||
4541 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4542 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4543 dev_info(&pdev->dev,
4544 "Wrong TX csum limit in DT, set to %dB\n",
4545 MVNETA_TX_CSUM_DEF_SIZE);
4547 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4548 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4550 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4553 pp->tx_csum_limit = tx_csum_limit;
4555 pp->dram_target_info = mv_mbus_dram_info();
4556 /* Armada3700 requires setting default configuration of Mbus
4557 * windows, however without using filled mbus_dram_target_info
4560 if (pp->dram_target_info || pp->neta_armada3700)
4561 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4563 pp->tx_ring_size = MVNETA_MAX_TXD;
4564 pp->rx_ring_size = MVNETA_MAX_RXD;
4567 SET_NETDEV_DEV(dev, &pdev->dev);
4569 pp->id = global_port_id++;
4570 pp->rx_offset_correction = 0; /* not relevant for SW BM */
4572 /* Obtain access to BM resources if enabled and already initialized */
4573 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4575 pp->bm_priv = mvneta_bm_get(bm_node);
4577 err = mvneta_bm_port_init(pdev, pp);
4579 dev_info(&pdev->dev,
4580 "use SW buffer management\n");
4581 mvneta_bm_put(pp->bm_priv);
4585 /* Set RX packet offset correction for platforms, whose
4586 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
4587 * platforms and 0B for 32-bit ones.
4589 pp->rx_offset_correction = max(0,
4591 MVNETA_RX_PKT_OFFSET_CORRECTION);
4593 of_node_put(bm_node);
4595 err = mvneta_init(&pdev->dev, pp);
4599 err = mvneta_port_power_up(pp, phy_mode);
4601 dev_err(&pdev->dev, "can't power up port\n");
4605 /* Armada3700 network controller does not support per-cpu
4606 * operation, so only single NAPI should be initialized.
4608 if (pp->neta_armada3700) {
4609 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4611 for_each_present_cpu(cpu) {
4612 struct mvneta_pcpu_port *port =
4613 per_cpu_ptr(pp->ports, cpu);
4615 netif_napi_add(dev, &port->napi, mvneta_poll,
4621 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO;
4622 dev->hw_features |= dev->features;
4623 dev->vlan_features |= dev->features;
4624 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4625 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4627 /* MTU range: 68 - 9676 */
4628 dev->min_mtu = ETH_MIN_MTU;
4629 /* 9676 == 9700 - 20 and rounding to 8 */
4630 dev->max_mtu = 9676;
4632 err = register_netdev(dev);
4634 dev_err(&pdev->dev, "failed to register\n");
4638 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4641 platform_set_drvdata(pdev, pp->dev);
4647 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4648 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4650 mvneta_bm_put(pp->bm_priv);
4652 free_percpu(pp->stats);
4654 free_percpu(pp->ports);
4656 clk_disable_unprepare(pp->clk_bus);
4657 clk_disable_unprepare(pp->clk);
4660 phylink_destroy(pp->phylink);
4662 irq_dispose_mapping(dev->irq);
4668 /* Device removal routine */
4669 static int mvneta_remove(struct platform_device *pdev)
4671 struct net_device *dev = platform_get_drvdata(pdev);
4672 struct mvneta_port *pp = netdev_priv(dev);
4674 unregister_netdev(dev);
4675 clk_disable_unprepare(pp->clk_bus);
4676 clk_disable_unprepare(pp->clk);
4677 free_percpu(pp->ports);
4678 free_percpu(pp->stats);
4679 irq_dispose_mapping(dev->irq);
4680 phylink_destroy(pp->phylink);
4684 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4685 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4687 mvneta_bm_put(pp->bm_priv);
4693 #ifdef CONFIG_PM_SLEEP
4694 static int mvneta_suspend(struct device *device)
4697 struct net_device *dev = dev_get_drvdata(device);
4698 struct mvneta_port *pp = netdev_priv(dev);
4700 if (!netif_running(dev))
4703 if (!pp->neta_armada3700) {
4704 spin_lock(&pp->lock);
4705 pp->is_stopped = true;
4706 spin_unlock(&pp->lock);
4708 cpuhp_state_remove_instance_nocalls(online_hpstate,
4710 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4715 mvneta_stop_dev(pp);
4718 for (queue = 0; queue < rxq_number; queue++) {
4719 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4721 mvneta_rxq_drop_pkts(pp, rxq);
4724 for (queue = 0; queue < txq_number; queue++) {
4725 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4727 mvneta_txq_hw_deinit(pp, txq);
4731 netif_device_detach(dev);
4732 clk_disable_unprepare(pp->clk_bus);
4733 clk_disable_unprepare(pp->clk);
4738 static int mvneta_resume(struct device *device)
4740 struct platform_device *pdev = to_platform_device(device);
4741 struct net_device *dev = dev_get_drvdata(device);
4742 struct mvneta_port *pp = netdev_priv(dev);
4745 clk_prepare_enable(pp->clk);
4746 if (!IS_ERR(pp->clk_bus))
4747 clk_prepare_enable(pp->clk_bus);
4748 if (pp->dram_target_info || pp->neta_armada3700)
4749 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
4751 err = mvneta_bm_port_init(pdev, pp);
4753 dev_info(&pdev->dev, "use SW buffer management\n");
4757 mvneta_defaults_set(pp);
4758 err = mvneta_port_power_up(pp, pp->phy_interface);
4760 dev_err(device, "can't power up port\n");
4764 netif_device_attach(dev);
4766 if (!netif_running(dev))
4769 for (queue = 0; queue < rxq_number; queue++) {
4770 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4772 rxq->next_desc_to_proc = 0;
4773 mvneta_rxq_hw_init(pp, rxq);
4776 for (queue = 0; queue < txq_number; queue++) {
4777 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4779 txq->next_desc_to_proc = 0;
4780 mvneta_txq_hw_init(pp, txq);
4783 if (!pp->neta_armada3700) {
4784 spin_lock(&pp->lock);
4785 pp->is_stopped = false;
4786 spin_unlock(&pp->lock);
4787 cpuhp_state_add_instance_nocalls(online_hpstate,
4789 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4794 mvneta_start_dev(pp);
4796 mvneta_set_rx_mode(dev);
4802 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
4804 static const struct of_device_id mvneta_match[] = {
4805 { .compatible = "marvell,armada-370-neta" },
4806 { .compatible = "marvell,armada-xp-neta" },
4807 { .compatible = "marvell,armada-3700-neta" },
4810 MODULE_DEVICE_TABLE(of, mvneta_match);
4812 static struct platform_driver mvneta_driver = {
4813 .probe = mvneta_probe,
4814 .remove = mvneta_remove,
4816 .name = MVNETA_DRIVER_NAME,
4817 .of_match_table = mvneta_match,
4818 .pm = &mvneta_pm_ops,
4822 static int __init mvneta_driver_init(void)
4826 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4828 mvneta_cpu_down_prepare);
4831 online_hpstate = ret;
4832 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4833 NULL, mvneta_cpu_dead);
4837 ret = platform_driver_register(&mvneta_driver);
4843 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4845 cpuhp_remove_multi_state(online_hpstate);
4849 module_init(mvneta_driver_init);
4851 static void __exit mvneta_driver_exit(void)
4853 platform_driver_unregister(&mvneta_driver);
4854 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4855 cpuhp_remove_multi_state(online_hpstate);
4857 module_exit(mvneta_driver_exit);
4859 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4860 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4861 MODULE_LICENSE("GPL");
4863 module_param(rxq_number, int, 0444);
4864 module_param(txq_number, int, 0444);
4866 module_param(rxq_def, int, 0444);
4867 module_param(rx_copybreak, int, 0644);