2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
73 * Registers shared between all ports.
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 512
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
186 #define TSO_HEADER_SIZE 128
188 /* Max number of allowed TCP segments for software TSO */
189 #define MV643XX_MAX_TSO_SEGS 100
190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
192 #define IS_TSO_HEADER(txq, addr) \
193 ((addr >= txq->tso_hdrs_dma) && \
194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
196 #define DESC_DMA_MAP_SINGLE 0
197 #define DESC_DMA_MAP_PAGE 1
202 #if defined(__BIG_ENDIAN)
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u16 buf_size; /* Buffer size */
206 u32 cmd_sts; /* Descriptor command status */
207 u32 next_desc_ptr; /* Next descriptor pointer */
208 u32 buf_ptr; /* Descriptor buffer pointer */
212 u16 byte_cnt; /* buffer byte count */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u32 cmd_sts; /* Command/status field */
215 u32 next_desc_ptr; /* Pointer to next descriptor */
216 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 #elif defined(__LITTLE_ENDIAN)
220 u32 cmd_sts; /* Descriptor command status */
221 u16 buf_size; /* Buffer size */
222 u16 byte_cnt; /* Descriptor buffer byte count */
223 u32 buf_ptr; /* Descriptor buffer pointer */
224 u32 next_desc_ptr; /* Next descriptor pointer */
228 u32 cmd_sts; /* Command/status field */
229 u16 l4i_chk; /* CPU provided TCP checksum */
230 u16 byte_cnt; /* buffer byte count */
231 u32 buf_ptr; /* pointer to buffer for this descriptor*/
232 u32 next_desc_ptr; /* Pointer to next descriptor */
235 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
238 /* RX & TX descriptor command */
239 #define BUFFER_OWNED_BY_DMA 0x80000000
241 /* RX & TX descriptor status */
242 #define ERROR_SUMMARY 0x00000001
244 /* RX descriptor status */
245 #define LAYER_4_CHECKSUM_OK 0x40000000
246 #define RX_ENABLE_INTERRUPT 0x20000000
247 #define RX_FIRST_DESC 0x08000000
248 #define RX_LAST_DESC 0x04000000
249 #define RX_IP_HDR_OK 0x02000000
250 #define RX_PKT_IS_IPV4 0x01000000
251 #define RX_PKT_IS_ETHERNETV2 0x00800000
252 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
253 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
254 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
256 /* TX descriptor command */
257 #define TX_ENABLE_INTERRUPT 0x00800000
258 #define GEN_CRC 0x00400000
259 #define TX_FIRST_DESC 0x00200000
260 #define TX_LAST_DESC 0x00100000
261 #define ZERO_PADDING 0x00080000
262 #define GEN_IP_V4_CHECKSUM 0x00040000
263 #define GEN_TCP_UDP_CHECKSUM 0x00020000
264 #define UDP_FRAME 0x00010000
265 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
266 #define GEN_TCP_UDP_CHK_FULL 0x00000400
267 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
269 #define TX_IHL_SHIFT 11
272 /* global *******************************************************************/
273 struct mv643xx_eth_shared_private {
275 * Ethernet controller base address.
280 * Per-port MBUS window access register value.
285 * Hardware-specific parameters.
287 int extended_rx_coal_limit;
293 #define TX_BW_CONTROL_ABSENT 0
294 #define TX_BW_CONTROL_OLD_LAYOUT 1
295 #define TX_BW_CONTROL_NEW_LAYOUT 2
297 static int mv643xx_eth_open(struct net_device *dev);
298 static int mv643xx_eth_stop(struct net_device *dev);
301 /* per-port *****************************************************************/
302 struct mib_counters {
303 u64 good_octets_received;
304 u32 bad_octets_received;
305 u32 internal_mac_transmit_err;
306 u32 good_frames_received;
307 u32 bad_frames_received;
308 u32 broadcast_frames_received;
309 u32 multicast_frames_received;
310 u32 frames_64_octets;
311 u32 frames_65_to_127_octets;
312 u32 frames_128_to_255_octets;
313 u32 frames_256_to_511_octets;
314 u32 frames_512_to_1023_octets;
315 u32 frames_1024_to_max_octets;
316 u64 good_octets_sent;
317 u32 good_frames_sent;
318 u32 excessive_collision;
319 u32 multicast_frames_sent;
320 u32 broadcast_frames_sent;
321 u32 unrec_mac_control_received;
323 u32 good_fc_received;
325 u32 undersize_received;
326 u32 fragments_received;
327 u32 oversize_received;
329 u32 mac_receive_error;
333 /* Non MIB hardware counters */
347 struct rx_desc *rx_desc_area;
348 dma_addr_t rx_desc_dma;
349 int rx_desc_area_size;
350 struct sk_buff **rx_skb;
362 int tx_stop_threshold;
363 int tx_wake_threshold;
366 dma_addr_t tso_hdrs_dma;
368 struct tx_desc *tx_desc_area;
369 char *tx_desc_mapping; /* array to track the type of the dma mapping */
370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
373 struct sk_buff_head tx_skb;
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
380 struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
385 struct net_device *dev;
387 struct phy_device *phy;
389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
391 struct mib_counters mib_counters;
393 struct work_struct tx_timeout_task;
395 struct napi_struct napi;
410 unsigned long rx_desc_sram_addr;
411 int rx_desc_sram_size;
413 struct timer_list rx_oom;
414 struct rx_queue rxq[8];
420 unsigned long tx_desc_sram_addr;
421 int tx_desc_sram_size;
423 struct tx_queue txq[8];
426 * Hardware-specific parameters.
433 /* port register accessors **************************************************/
434 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
436 return readl(mp->shared->base + offset);
439 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
441 return readl(mp->base + offset);
444 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
446 writel(data, mp->shared->base + offset);
449 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
451 writel(data, mp->base + offset);
455 /* rxq/txq helper functions *************************************************/
456 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
458 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
461 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
463 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
466 static void rxq_enable(struct rx_queue *rxq)
468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
469 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
472 static void rxq_disable(struct rx_queue *rxq)
474 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
475 u8 mask = 1 << rxq->index;
477 wrlp(mp, RXQ_COMMAND, mask << 8);
478 while (rdlp(mp, RXQ_COMMAND) & mask)
482 static void txq_reset_hw_ptr(struct tx_queue *txq)
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
487 addr = (u32)txq->tx_desc_dma;
488 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
489 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
492 static void txq_enable(struct tx_queue *txq)
494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
498 static void txq_disable(struct tx_queue *txq)
500 struct mv643xx_eth_private *mp = txq_to_mp(txq);
501 u8 mask = 1 << txq->index;
503 wrlp(mp, TXQ_COMMAND, mask << 8);
504 while (rdlp(mp, TXQ_COMMAND) & mask)
508 static void txq_maybe_wake(struct tx_queue *txq)
510 struct mv643xx_eth_private *mp = txq_to_mp(txq);
511 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
513 if (netif_tx_queue_stopped(nq)) {
514 __netif_tx_lock(nq, smp_processor_id());
515 if (txq->tx_desc_count <= txq->tx_wake_threshold)
516 netif_tx_wake_queue(nq);
517 __netif_tx_unlock(nq);
521 static int rxq_process(struct rx_queue *rxq, int budget)
523 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
524 struct net_device_stats *stats = &mp->dev->stats;
528 while (rx < budget && rxq->rx_desc_count) {
529 struct rx_desc *rx_desc;
530 unsigned int cmd_sts;
534 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
536 cmd_sts = rx_desc->cmd_sts;
537 if (cmd_sts & BUFFER_OWNED_BY_DMA)
541 skb = rxq->rx_skb[rxq->rx_curr_desc];
542 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
545 if (rxq->rx_curr_desc == rxq->rx_ring_size)
546 rxq->rx_curr_desc = 0;
548 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
549 rx_desc->buf_size, DMA_FROM_DEVICE);
550 rxq->rx_desc_count--;
553 mp->work_rx_refill |= 1 << rxq->index;
555 byte_cnt = rx_desc->byte_cnt;
560 * Note that the descriptor byte count includes 2 dummy
561 * bytes automatically inserted by the hardware at the
562 * start of the packet (which we don't count), and a 4
563 * byte CRC at the end of the packet (which we do count).
566 stats->rx_bytes += byte_cnt - 2;
569 * In case we received a packet without first / last bits
570 * on, or the error summary bit is set, the packet needs
573 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
574 != (RX_FIRST_DESC | RX_LAST_DESC))
578 * The -4 is for the CRC in the trailer of the
581 skb_put(skb, byte_cnt - 2 - 4);
583 if (cmd_sts & LAYER_4_CHECKSUM_OK)
584 skb->ip_summed = CHECKSUM_UNNECESSARY;
585 skb->protocol = eth_type_trans(skb, mp->dev);
587 napi_gro_receive(&mp->napi, skb);
594 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
595 (RX_FIRST_DESC | RX_LAST_DESC)) {
598 "received packet spanning multiple descriptors\n");
601 if (cmd_sts & ERROR_SUMMARY)
608 mp->work_rx &= ~(1 << rxq->index);
613 static int rxq_refill(struct rx_queue *rxq, int budget)
615 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
619 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
622 struct rx_desc *rx_desc;
625 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
633 skb_reserve(skb, SKB_DMA_REALIGN);
636 rxq->rx_desc_count++;
638 rx = rxq->rx_used_desc++;
639 if (rxq->rx_used_desc == rxq->rx_ring_size)
640 rxq->rx_used_desc = 0;
642 rx_desc = rxq->rx_desc_area + rx;
644 size = skb_end_pointer(skb) - skb->data;
645 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
648 rx_desc->buf_size = size;
649 rxq->rx_skb[rx] = skb;
651 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
655 * The hardware automatically prepends 2 bytes of
656 * dummy data to each received packet, so that the
657 * IP header ends up 16-byte aligned.
662 if (refilled < budget)
663 mp->work_rx_refill &= ~(1 << rxq->index);
670 /* tx ***********************************************************************/
671 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
675 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
676 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
678 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
685 static inline __be16 sum16_as_be(__sum16 sum)
687 return (__force __be16)sum;
690 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
691 u16 *l4i_chk, u32 *command, int length)
696 if (skb->ip_summed == CHECKSUM_PARTIAL) {
700 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
701 skb->protocol != htons(ETH_P_8021Q));
703 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
704 tag_bytes = hdr_len - ETH_HLEN;
706 if (length - hdr_len > mp->shared->tx_csum_limit ||
707 unlikely(tag_bytes & ~12)) {
708 ret = skb_checksum_help(skb);
715 cmd |= MAC_HDR_EXTRA_4_BYTES;
717 cmd |= MAC_HDR_EXTRA_8_BYTES;
719 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
721 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
723 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
724 * it seems we don't need to pass the initial checksum. */
725 switch (ip_hdr(skb)->protocol) {
734 WARN(1, "protocol not supported");
738 /* Errata BTS #50, IHL must be 5 if no HW checksum */
739 cmd |= 5 << TX_IHL_SHIFT;
746 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
747 struct sk_buff *skb, char *data, int length,
748 bool last_tcp, bool is_last)
752 struct tx_desc *desc;
754 tx_index = txq->tx_curr_desc++;
755 if (txq->tx_curr_desc == txq->tx_ring_size)
756 txq->tx_curr_desc = 0;
757 desc = &txq->tx_desc_area[tx_index];
758 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
761 desc->byte_cnt = length;
763 if (length <= 8 && (uintptr_t)data & 0x7) {
764 /* Copy unaligned small data fragment to TSO header data area */
765 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
767 desc->buf_ptr = txq->tso_hdrs_dma
768 + tx_index * TSO_HEADER_SIZE;
770 /* Alignment is okay, map buffer and hand off to hardware */
771 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
772 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
773 length, DMA_TO_DEVICE);
774 if (unlikely(dma_mapping_error(dev->dev.parent,
776 WARN(1, "dma_map_single failed!\n");
781 cmd_sts = BUFFER_OWNED_BY_DMA;
783 /* last descriptor in the TCP packet */
784 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
785 /* last descriptor in SKB */
787 cmd_sts |= TX_ENABLE_INTERRUPT;
789 desc->cmd_sts = cmd_sts;
794 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
795 u32 *first_cmd_sts, bool first_desc)
797 struct mv643xx_eth_private *mp = txq_to_mp(txq);
798 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
800 struct tx_desc *desc;
806 tx_index = txq->tx_curr_desc;
807 desc = &txq->tx_desc_area[tx_index];
809 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
811 WARN(1, "failed to prepare checksum!");
813 /* Should we set this? Can't use the value from skb_tx_csum()
814 * as it's not the correct initial L4 checksum to use. */
817 desc->byte_cnt = hdr_len;
818 desc->buf_ptr = txq->tso_hdrs_dma +
819 txq->tx_curr_desc * TSO_HEADER_SIZE;
820 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
823 /* Defer updating the first command descriptor until all
824 * following descriptors have been written.
827 *first_cmd_sts = cmd_sts;
829 desc->cmd_sts = cmd_sts;
832 if (txq->tx_curr_desc == txq->tx_ring_size)
833 txq->tx_curr_desc = 0;
836 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
837 struct net_device *dev)
839 struct mv643xx_eth_private *mp = txq_to_mp(txq);
840 int total_len, data_left, ret;
843 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
844 struct tx_desc *first_tx_desc;
845 u32 first_cmd_sts = 0;
847 /* Count needed descriptors */
848 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
849 netdev_dbg(dev, "not enough descriptors for TSO!\n");
853 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
855 /* Initialize the TSO handler, and prepare the first payload */
856 tso_start(skb, &tso);
858 total_len = skb->len - hdr_len;
859 while (total_len > 0) {
860 bool first_desc = (desc_count == 0);
863 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
864 total_len -= data_left;
867 /* prepare packet headers: MAC + IP + TCP */
868 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
869 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
870 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
873 while (data_left > 0) {
877 size = min_t(int, tso.size, data_left);
878 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
884 tso_build_data(skb, &tso, size);
888 __skb_queue_tail(&txq->tx_skb, skb);
889 skb_tx_timestamp(skb);
891 /* ensure all other descriptors are written before first cmd_sts */
893 first_tx_desc->cmd_sts = first_cmd_sts;
895 /* clear TX_END status */
896 mp->work_tx_end &= ~(1 << txq->index);
898 /* ensure all descriptors are written before poking hardware */
901 txq->tx_desc_count += desc_count;
904 /* TODO: Release all used data descriptors; header descriptors must not
910 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
912 struct mv643xx_eth_private *mp = txq_to_mp(txq);
913 int nr_frags = skb_shinfo(skb)->nr_frags;
916 for (frag = 0; frag < nr_frags; frag++) {
917 skb_frag_t *this_frag;
919 struct tx_desc *desc;
921 this_frag = &skb_shinfo(skb)->frags[frag];
922 tx_index = txq->tx_curr_desc++;
923 if (txq->tx_curr_desc == txq->tx_ring_size)
924 txq->tx_curr_desc = 0;
925 desc = &txq->tx_desc_area[tx_index];
926 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
929 * The last fragment will generate an interrupt
930 * which will free the skb on TX completion.
932 if (frag == nr_frags - 1) {
933 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
934 ZERO_PADDING | TX_LAST_DESC |
937 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
941 desc->byte_cnt = skb_frag_size(this_frag);
942 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
943 this_frag, 0, desc->byte_cnt,
948 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
949 struct net_device *dev)
951 struct mv643xx_eth_private *mp = txq_to_mp(txq);
952 int nr_frags = skb_shinfo(skb)->nr_frags;
954 struct tx_desc *desc;
962 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
964 netdev_err(dev, "tx queue full?!\n");
968 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
971 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
973 tx_index = txq->tx_curr_desc++;
974 if (txq->tx_curr_desc == txq->tx_ring_size)
975 txq->tx_curr_desc = 0;
976 desc = &txq->tx_desc_area[tx_index];
977 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
980 txq_submit_frag_skb(txq, skb);
981 length = skb_headlen(skb);
983 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
987 desc->l4i_chk = l4i_chk;
988 desc->byte_cnt = length;
989 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
990 length, DMA_TO_DEVICE);
992 __skb_queue_tail(&txq->tx_skb, skb);
994 skb_tx_timestamp(skb);
996 /* ensure all other descriptors are written before first cmd_sts */
998 desc->cmd_sts = cmd_sts;
1000 /* clear TX_END status */
1001 mp->work_tx_end &= ~(1 << txq->index);
1003 /* ensure all descriptors are written before poking hardware */
1007 txq->tx_desc_count += nr_frags + 1;
1012 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1014 struct mv643xx_eth_private *mp = netdev_priv(dev);
1015 int length, queue, ret;
1016 struct tx_queue *txq;
1017 struct netdev_queue *nq;
1019 queue = skb_get_queue_mapping(skb);
1020 txq = mp->txq + queue;
1021 nq = netdev_get_tx_queue(dev, queue);
1023 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1024 netdev_printk(KERN_DEBUG, dev,
1025 "failed to linearize skb with tiny unaligned fragment\n");
1026 return NETDEV_TX_BUSY;
1031 if (skb_is_gso(skb))
1032 ret = txq_submit_tso(txq, skb, dev);
1034 ret = txq_submit_skb(txq, skb, dev);
1036 txq->tx_bytes += length;
1039 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1040 netif_tx_stop_queue(nq);
1043 dev_kfree_skb_any(skb);
1046 return NETDEV_TX_OK;
1050 /* tx napi ******************************************************************/
1051 static void txq_kick(struct tx_queue *txq)
1053 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1054 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1058 __netif_tx_lock(nq, smp_processor_id());
1060 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1063 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1064 expected_ptr = (u32)txq->tx_desc_dma +
1065 txq->tx_curr_desc * sizeof(struct tx_desc);
1067 if (hw_desc_ptr != expected_ptr)
1071 __netif_tx_unlock(nq);
1073 mp->work_tx_end &= ~(1 << txq->index);
1076 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1078 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1079 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1082 __netif_tx_lock_bh(nq);
1085 while (reclaimed < budget && txq->tx_desc_count > 0) {
1087 struct tx_desc *desc;
1091 tx_index = txq->tx_used_desc;
1092 desc = &txq->tx_desc_area[tx_index];
1093 desc_dma_map = txq->tx_desc_mapping[tx_index];
1095 cmd_sts = desc->cmd_sts;
1097 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1100 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1103 txq->tx_used_desc = tx_index + 1;
1104 if (txq->tx_used_desc == txq->tx_ring_size)
1105 txq->tx_used_desc = 0;
1108 txq->tx_desc_count--;
1110 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1112 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1113 dma_unmap_page(mp->dev->dev.parent,
1118 dma_unmap_single(mp->dev->dev.parent,
1124 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1125 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1131 if (cmd_sts & ERROR_SUMMARY) {
1132 netdev_info(mp->dev, "tx error\n");
1133 mp->dev->stats.tx_errors++;
1138 __netif_tx_unlock_bh(nq);
1140 if (reclaimed < budget)
1141 mp->work_tx &= ~(1 << txq->index);
1147 /* tx rate control **********************************************************/
1149 * Set total maximum TX rate (shared by all TX queues for this port)
1150 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1152 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1158 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1159 if (token_rate > 1023)
1162 mtu = (mp->dev->mtu + 255) >> 8;
1166 bucket_size = (burst + 255) >> 8;
1167 if (bucket_size > 65535)
1168 bucket_size = 65535;
1170 switch (mp->shared->tx_bw_control) {
1171 case TX_BW_CONTROL_OLD_LAYOUT:
1172 wrlp(mp, TX_BW_RATE, token_rate);
1173 wrlp(mp, TX_BW_MTU, mtu);
1174 wrlp(mp, TX_BW_BURST, bucket_size);
1176 case TX_BW_CONTROL_NEW_LAYOUT:
1177 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1178 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1179 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1184 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1186 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1190 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1191 if (token_rate > 1023)
1194 bucket_size = (burst + 255) >> 8;
1195 if (bucket_size > 65535)
1196 bucket_size = 65535;
1198 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1199 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1202 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1204 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1209 * Turn on fixed priority mode.
1212 switch (mp->shared->tx_bw_control) {
1213 case TX_BW_CONTROL_OLD_LAYOUT:
1214 off = TXQ_FIX_PRIO_CONF;
1216 case TX_BW_CONTROL_NEW_LAYOUT:
1217 off = TXQ_FIX_PRIO_CONF_MOVED;
1222 val = rdlp(mp, off);
1223 val |= 1 << txq->index;
1229 /* mii management interface *************************************************/
1230 static void mv643xx_eth_adjust_link(struct net_device *dev)
1232 struct mv643xx_eth_private *mp = netdev_priv(dev);
1233 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1234 u32 autoneg_disable = FORCE_LINK_PASS |
1235 DISABLE_AUTO_NEG_SPEED_GMII |
1236 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1237 DISABLE_AUTO_NEG_FOR_DUPLEX;
1239 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1240 /* enable auto negotiation */
1241 pscr &= ~autoneg_disable;
1245 pscr |= autoneg_disable;
1247 if (mp->phy->speed == SPEED_1000) {
1248 /* force gigabit, half duplex not supported */
1249 pscr |= SET_GMII_SPEED_TO_1000;
1250 pscr |= SET_FULL_DUPLEX_MODE;
1254 pscr &= ~SET_GMII_SPEED_TO_1000;
1256 if (mp->phy->speed == SPEED_100)
1257 pscr |= SET_MII_SPEED_TO_100;
1259 pscr &= ~SET_MII_SPEED_TO_100;
1261 if (mp->phy->duplex == DUPLEX_FULL)
1262 pscr |= SET_FULL_DUPLEX_MODE;
1264 pscr &= ~SET_FULL_DUPLEX_MODE;
1267 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1270 /* statistics ***************************************************************/
1271 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1273 struct mv643xx_eth_private *mp = netdev_priv(dev);
1274 struct net_device_stats *stats = &dev->stats;
1275 unsigned long tx_packets = 0;
1276 unsigned long tx_bytes = 0;
1277 unsigned long tx_dropped = 0;
1280 for (i = 0; i < mp->txq_count; i++) {
1281 struct tx_queue *txq = mp->txq + i;
1283 tx_packets += txq->tx_packets;
1284 tx_bytes += txq->tx_bytes;
1285 tx_dropped += txq->tx_dropped;
1288 stats->tx_packets = tx_packets;
1289 stats->tx_bytes = tx_bytes;
1290 stats->tx_dropped = tx_dropped;
1295 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1297 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1300 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1304 for (i = 0; i < 0x80; i += 4)
1307 /* Clear non MIB hw counters also */
1308 rdlp(mp, RX_DISCARD_FRAME_CNT);
1309 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1312 static void mib_counters_update(struct mv643xx_eth_private *mp)
1314 struct mib_counters *p = &mp->mib_counters;
1316 spin_lock_bh(&mp->mib_counters_lock);
1317 p->good_octets_received += mib_read(mp, 0x00);
1318 p->bad_octets_received += mib_read(mp, 0x08);
1319 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1320 p->good_frames_received += mib_read(mp, 0x10);
1321 p->bad_frames_received += mib_read(mp, 0x14);
1322 p->broadcast_frames_received += mib_read(mp, 0x18);
1323 p->multicast_frames_received += mib_read(mp, 0x1c);
1324 p->frames_64_octets += mib_read(mp, 0x20);
1325 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1326 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1327 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1328 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1329 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1330 p->good_octets_sent += mib_read(mp, 0x38);
1331 p->good_frames_sent += mib_read(mp, 0x40);
1332 p->excessive_collision += mib_read(mp, 0x44);
1333 p->multicast_frames_sent += mib_read(mp, 0x48);
1334 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1335 p->unrec_mac_control_received += mib_read(mp, 0x50);
1336 p->fc_sent += mib_read(mp, 0x54);
1337 p->good_fc_received += mib_read(mp, 0x58);
1338 p->bad_fc_received += mib_read(mp, 0x5c);
1339 p->undersize_received += mib_read(mp, 0x60);
1340 p->fragments_received += mib_read(mp, 0x64);
1341 p->oversize_received += mib_read(mp, 0x68);
1342 p->jabber_received += mib_read(mp, 0x6c);
1343 p->mac_receive_error += mib_read(mp, 0x70);
1344 p->bad_crc_event += mib_read(mp, 0x74);
1345 p->collision += mib_read(mp, 0x78);
1346 p->late_collision += mib_read(mp, 0x7c);
1347 /* Non MIB hardware counters */
1348 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1349 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1350 spin_unlock_bh(&mp->mib_counters_lock);
1353 static void mib_counters_timer_wrapper(unsigned long _mp)
1355 struct mv643xx_eth_private *mp = (void *)_mp;
1356 mib_counters_update(mp);
1357 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1361 /* interrupt coalescing *****************************************************/
1363 * Hardware coalescing parameters are set in units of 64 t_clk
1366 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1368 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1370 * In the ->set*() methods, we round the computed register value
1371 * to the nearest integer.
1373 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1375 u32 val = rdlp(mp, SDMA_CONFIG);
1378 if (mp->shared->extended_rx_coal_limit)
1379 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1381 temp = (val & 0x003fff00) >> 8;
1384 temp += mp->t_clk / 2;
1385 do_div(temp, mp->t_clk);
1387 return (unsigned int)temp;
1390 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1395 temp = (u64)usec * mp->t_clk;
1397 do_div(temp, 64000000);
1399 val = rdlp(mp, SDMA_CONFIG);
1400 if (mp->shared->extended_rx_coal_limit) {
1404 val |= (temp & 0x8000) << 10;
1405 val |= (temp & 0x7fff) << 7;
1410 val |= (temp & 0x3fff) << 8;
1412 wrlp(mp, SDMA_CONFIG, val);
1415 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1419 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1421 temp += mp->t_clk / 2;
1422 do_div(temp, mp->t_clk);
1424 return (unsigned int)temp;
1427 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1431 temp = (u64)usec * mp->t_clk;
1433 do_div(temp, 64000000);
1438 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1442 /* ethtool ******************************************************************/
1443 struct mv643xx_eth_stats {
1444 char stat_string[ETH_GSTRING_LEN];
1451 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1452 offsetof(struct net_device, stats.m), -1 }
1454 #define MIBSTAT(m) \
1455 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1456 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1458 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1467 MIBSTAT(good_octets_received),
1468 MIBSTAT(bad_octets_received),
1469 MIBSTAT(internal_mac_transmit_err),
1470 MIBSTAT(good_frames_received),
1471 MIBSTAT(bad_frames_received),
1472 MIBSTAT(broadcast_frames_received),
1473 MIBSTAT(multicast_frames_received),
1474 MIBSTAT(frames_64_octets),
1475 MIBSTAT(frames_65_to_127_octets),
1476 MIBSTAT(frames_128_to_255_octets),
1477 MIBSTAT(frames_256_to_511_octets),
1478 MIBSTAT(frames_512_to_1023_octets),
1479 MIBSTAT(frames_1024_to_max_octets),
1480 MIBSTAT(good_octets_sent),
1481 MIBSTAT(good_frames_sent),
1482 MIBSTAT(excessive_collision),
1483 MIBSTAT(multicast_frames_sent),
1484 MIBSTAT(broadcast_frames_sent),
1485 MIBSTAT(unrec_mac_control_received),
1487 MIBSTAT(good_fc_received),
1488 MIBSTAT(bad_fc_received),
1489 MIBSTAT(undersize_received),
1490 MIBSTAT(fragments_received),
1491 MIBSTAT(oversize_received),
1492 MIBSTAT(jabber_received),
1493 MIBSTAT(mac_receive_error),
1494 MIBSTAT(bad_crc_event),
1496 MIBSTAT(late_collision),
1497 MIBSTAT(rx_discard),
1498 MIBSTAT(rx_overrun),
1502 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1503 struct ethtool_cmd *cmd)
1507 err = phy_read_status(mp->phy);
1509 err = phy_ethtool_gset(mp->phy, cmd);
1512 * The MAC does not support 1000baseT_Half.
1514 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1515 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1521 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1522 struct ethtool_cmd *cmd)
1526 port_status = rdlp(mp, PORT_STATUS);
1528 cmd->supported = SUPPORTED_MII;
1529 cmd->advertising = ADVERTISED_MII;
1530 switch (port_status & PORT_SPEED_MASK) {
1532 ethtool_cmd_speed_set(cmd, SPEED_10);
1534 case PORT_SPEED_100:
1535 ethtool_cmd_speed_set(cmd, SPEED_100);
1537 case PORT_SPEED_1000:
1538 ethtool_cmd_speed_set(cmd, SPEED_1000);
1544 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1545 cmd->port = PORT_MII;
1546 cmd->phy_address = 0;
1547 cmd->transceiver = XCVR_INTERNAL;
1548 cmd->autoneg = AUTONEG_DISABLE;
1556 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1558 struct mv643xx_eth_private *mp = netdev_priv(dev);
1562 phy_ethtool_get_wol(mp->phy, wol);
1566 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1568 struct mv643xx_eth_private *mp = netdev_priv(dev);
1571 if (mp->phy == NULL)
1574 err = phy_ethtool_set_wol(mp->phy, wol);
1575 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1576 * this debugging hint is useful to have.
1578 if (err == -EOPNOTSUPP)
1579 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1584 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1586 struct mv643xx_eth_private *mp = netdev_priv(dev);
1588 if (mp->phy != NULL)
1589 return mv643xx_eth_get_settings_phy(mp, cmd);
1591 return mv643xx_eth_get_settings_phyless(mp, cmd);
1595 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1597 struct mv643xx_eth_private *mp = netdev_priv(dev);
1600 if (mp->phy == NULL)
1604 * The MAC does not support 1000baseT_Half.
1606 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1608 ret = phy_ethtool_sset(mp->phy, cmd);
1610 mv643xx_eth_adjust_link(dev);
1614 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1615 struct ethtool_drvinfo *drvinfo)
1617 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1618 sizeof(drvinfo->driver));
1619 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1620 sizeof(drvinfo->version));
1621 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1622 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1625 static int mv643xx_eth_nway_reset(struct net_device *dev)
1627 struct mv643xx_eth_private *mp = netdev_priv(dev);
1629 if (mp->phy == NULL)
1632 return genphy_restart_aneg(mp->phy);
1636 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1638 struct mv643xx_eth_private *mp = netdev_priv(dev);
1640 ec->rx_coalesce_usecs = get_rx_coal(mp);
1641 ec->tx_coalesce_usecs = get_tx_coal(mp);
1647 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1649 struct mv643xx_eth_private *mp = netdev_priv(dev);
1651 set_rx_coal(mp, ec->rx_coalesce_usecs);
1652 set_tx_coal(mp, ec->tx_coalesce_usecs);
1658 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1660 struct mv643xx_eth_private *mp = netdev_priv(dev);
1662 er->rx_max_pending = 4096;
1663 er->tx_max_pending = 4096;
1665 er->rx_pending = mp->rx_ring_size;
1666 er->tx_pending = mp->tx_ring_size;
1670 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1672 struct mv643xx_eth_private *mp = netdev_priv(dev);
1674 if (er->rx_mini_pending || er->rx_jumbo_pending)
1677 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1678 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1679 MV643XX_MAX_SKB_DESCS * 2, 4096);
1680 if (mp->tx_ring_size != er->tx_pending)
1681 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1682 mp->tx_ring_size, er->tx_pending);
1684 if (netif_running(dev)) {
1685 mv643xx_eth_stop(dev);
1686 if (mv643xx_eth_open(dev)) {
1688 "fatal error on re-opening device after ring param change\n");
1698 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1700 struct mv643xx_eth_private *mp = netdev_priv(dev);
1701 bool rx_csum = features & NETIF_F_RXCSUM;
1703 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1708 static void mv643xx_eth_get_strings(struct net_device *dev,
1709 uint32_t stringset, uint8_t *data)
1713 if (stringset == ETH_SS_STATS) {
1714 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1715 memcpy(data + i * ETH_GSTRING_LEN,
1716 mv643xx_eth_stats[i].stat_string,
1722 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1723 struct ethtool_stats *stats,
1726 struct mv643xx_eth_private *mp = netdev_priv(dev);
1729 mv643xx_eth_get_stats(dev);
1730 mib_counters_update(mp);
1732 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1733 const struct mv643xx_eth_stats *stat;
1736 stat = mv643xx_eth_stats + i;
1738 if (stat->netdev_off >= 0)
1739 p = ((void *)mp->dev) + stat->netdev_off;
1741 p = ((void *)mp) + stat->mp_off;
1743 data[i] = (stat->sizeof_stat == 8) ?
1744 *(uint64_t *)p : *(uint32_t *)p;
1748 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1750 if (sset == ETH_SS_STATS)
1751 return ARRAY_SIZE(mv643xx_eth_stats);
1756 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1757 .get_settings = mv643xx_eth_get_settings,
1758 .set_settings = mv643xx_eth_set_settings,
1759 .get_drvinfo = mv643xx_eth_get_drvinfo,
1760 .nway_reset = mv643xx_eth_nway_reset,
1761 .get_link = ethtool_op_get_link,
1762 .get_coalesce = mv643xx_eth_get_coalesce,
1763 .set_coalesce = mv643xx_eth_set_coalesce,
1764 .get_ringparam = mv643xx_eth_get_ringparam,
1765 .set_ringparam = mv643xx_eth_set_ringparam,
1766 .get_strings = mv643xx_eth_get_strings,
1767 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1768 .get_sset_count = mv643xx_eth_get_sset_count,
1769 .get_ts_info = ethtool_op_get_ts_info,
1770 .get_wol = mv643xx_eth_get_wol,
1771 .set_wol = mv643xx_eth_set_wol,
1775 /* address handling *********************************************************/
1776 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1778 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1779 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1781 addr[0] = (mac_h >> 24) & 0xff;
1782 addr[1] = (mac_h >> 16) & 0xff;
1783 addr[2] = (mac_h >> 8) & 0xff;
1784 addr[3] = mac_h & 0xff;
1785 addr[4] = (mac_l >> 8) & 0xff;
1786 addr[5] = mac_l & 0xff;
1789 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1791 wrlp(mp, MAC_ADDR_HIGH,
1792 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1793 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1796 static u32 uc_addr_filter_mask(struct net_device *dev)
1798 struct netdev_hw_addr *ha;
1801 if (dev->flags & IFF_PROMISC)
1804 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1805 netdev_for_each_uc_addr(ha, dev) {
1806 if (memcmp(dev->dev_addr, ha->addr, 5))
1808 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1811 nibbles |= 1 << (ha->addr[5] & 0x0f);
1817 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1819 struct mv643xx_eth_private *mp = netdev_priv(dev);
1824 uc_addr_set(mp, dev->dev_addr);
1826 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1828 nibbles = uc_addr_filter_mask(dev);
1830 port_config |= UNICAST_PROMISCUOUS_MODE;
1834 for (i = 0; i < 16; i += 4) {
1835 int off = UNICAST_TABLE(mp->port_num) + i;
1852 wrlp(mp, PORT_CONFIG, port_config);
1855 static int addr_crc(unsigned char *addr)
1860 for (i = 0; i < 6; i++) {
1863 crc = (crc ^ addr[i]) << 8;
1864 for (j = 7; j >= 0; j--) {
1865 if (crc & (0x100 << j))
1873 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1875 struct mv643xx_eth_private *mp = netdev_priv(dev);
1878 struct netdev_hw_addr *ha;
1881 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1884 /* Allocate both mc_spec and mc_other tables */
1885 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1888 mc_other = &mc_spec[64];
1890 netdev_for_each_mc_addr(ha, dev) {
1895 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1900 entry = addr_crc(a);
1903 table[entry >> 2] |= 1 << (8 * (entry & 3));
1906 for (i = 0; i < 64; i++) {
1907 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1909 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1917 for (i = 0; i < 64; i++) {
1918 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1920 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1925 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1927 mv643xx_eth_program_unicast_filter(dev);
1928 mv643xx_eth_program_multicast_filter(dev);
1931 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1933 struct sockaddr *sa = addr;
1935 if (!is_valid_ether_addr(sa->sa_data))
1936 return -EADDRNOTAVAIL;
1938 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1940 netif_addr_lock_bh(dev);
1941 mv643xx_eth_program_unicast_filter(dev);
1942 netif_addr_unlock_bh(dev);
1948 /* rx/tx queue initialisation ***********************************************/
1949 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1951 struct rx_queue *rxq = mp->rxq + index;
1952 struct rx_desc *rx_desc;
1958 rxq->rx_ring_size = mp->rx_ring_size;
1960 rxq->rx_desc_count = 0;
1961 rxq->rx_curr_desc = 0;
1962 rxq->rx_used_desc = 0;
1964 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1966 if (index == 0 && size <= mp->rx_desc_sram_size) {
1967 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1968 mp->rx_desc_sram_size);
1969 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1971 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1972 size, &rxq->rx_desc_dma,
1976 if (rxq->rx_desc_area == NULL) {
1978 "can't allocate rx ring (%d bytes)\n", size);
1981 memset(rxq->rx_desc_area, 0, size);
1983 rxq->rx_desc_area_size = size;
1984 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1986 if (rxq->rx_skb == NULL)
1989 rx_desc = rxq->rx_desc_area;
1990 for (i = 0; i < rxq->rx_ring_size; i++) {
1994 if (nexti == rxq->rx_ring_size)
1997 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1998 nexti * sizeof(struct rx_desc);
2005 if (index == 0 && size <= mp->rx_desc_sram_size)
2006 iounmap(rxq->rx_desc_area);
2008 dma_free_coherent(mp->dev->dev.parent, size,
2016 static void rxq_deinit(struct rx_queue *rxq)
2018 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2023 for (i = 0; i < rxq->rx_ring_size; i++) {
2024 if (rxq->rx_skb[i]) {
2025 dev_kfree_skb(rxq->rx_skb[i]);
2026 rxq->rx_desc_count--;
2030 if (rxq->rx_desc_count) {
2031 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2032 rxq->rx_desc_count);
2035 if (rxq->index == 0 &&
2036 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2037 iounmap(rxq->rx_desc_area);
2039 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2040 rxq->rx_desc_area, rxq->rx_desc_dma);
2045 static int txq_init(struct mv643xx_eth_private *mp, int index)
2047 struct tx_queue *txq = mp->txq + index;
2048 struct tx_desc *tx_desc;
2055 txq->tx_ring_size = mp->tx_ring_size;
2057 /* A queue must always have room for at least one skb.
2058 * Therefore, stop the queue when the free entries reaches
2059 * the maximum number of descriptors per skb.
2061 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2062 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2064 txq->tx_desc_count = 0;
2065 txq->tx_curr_desc = 0;
2066 txq->tx_used_desc = 0;
2068 size = txq->tx_ring_size * sizeof(struct tx_desc);
2070 if (index == 0 && size <= mp->tx_desc_sram_size) {
2071 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2072 mp->tx_desc_sram_size);
2073 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2075 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2076 size, &txq->tx_desc_dma,
2080 if (txq->tx_desc_area == NULL) {
2082 "can't allocate tx ring (%d bytes)\n", size);
2085 memset(txq->tx_desc_area, 0, size);
2087 txq->tx_desc_area_size = size;
2089 tx_desc = txq->tx_desc_area;
2090 for (i = 0; i < txq->tx_ring_size; i++) {
2091 struct tx_desc *txd = tx_desc + i;
2095 if (nexti == txq->tx_ring_size)
2099 txd->next_desc_ptr = txq->tx_desc_dma +
2100 nexti * sizeof(struct tx_desc);
2103 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2105 if (!txq->tx_desc_mapping) {
2107 goto err_free_desc_area;
2110 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2111 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2112 txq->tx_ring_size * TSO_HEADER_SIZE,
2113 &txq->tso_hdrs_dma, GFP_KERNEL);
2114 if (txq->tso_hdrs == NULL) {
2116 goto err_free_desc_mapping;
2118 skb_queue_head_init(&txq->tx_skb);
2122 err_free_desc_mapping:
2123 kfree(txq->tx_desc_mapping);
2125 if (index == 0 && size <= mp->tx_desc_sram_size)
2126 iounmap(txq->tx_desc_area);
2128 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2129 txq->tx_desc_area, txq->tx_desc_dma);
2133 static void txq_deinit(struct tx_queue *txq)
2135 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2138 txq_reclaim(txq, txq->tx_ring_size, 1);
2140 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2142 if (txq->index == 0 &&
2143 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2144 iounmap(txq->tx_desc_area);
2146 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2147 txq->tx_desc_area, txq->tx_desc_dma);
2148 kfree(txq->tx_desc_mapping);
2151 dma_free_coherent(mp->dev->dev.parent,
2152 txq->tx_ring_size * TSO_HEADER_SIZE,
2153 txq->tso_hdrs, txq->tso_hdrs_dma);
2157 /* netdev ops and related ***************************************************/
2158 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2163 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2168 if (int_cause & INT_EXT) {
2169 int_cause &= ~INT_EXT;
2170 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2174 wrlp(mp, INT_CAUSE, ~int_cause);
2175 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2176 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2177 mp->work_rx |= (int_cause & INT_RX) >> 2;
2180 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2181 if (int_cause_ext) {
2182 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2183 if (int_cause_ext & INT_EXT_LINK_PHY)
2185 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2191 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2193 struct net_device *dev = (struct net_device *)dev_id;
2194 struct mv643xx_eth_private *mp = netdev_priv(dev);
2196 if (unlikely(!mv643xx_eth_collect_events(mp)))
2199 wrlp(mp, INT_MASK, 0);
2200 napi_schedule(&mp->napi);
2205 static void handle_link_event(struct mv643xx_eth_private *mp)
2207 struct net_device *dev = mp->dev;
2213 port_status = rdlp(mp, PORT_STATUS);
2214 if (!(port_status & LINK_UP)) {
2215 if (netif_carrier_ok(dev)) {
2218 netdev_info(dev, "link down\n");
2220 netif_carrier_off(dev);
2222 for (i = 0; i < mp->txq_count; i++) {
2223 struct tx_queue *txq = mp->txq + i;
2225 txq_reclaim(txq, txq->tx_ring_size, 1);
2226 txq_reset_hw_ptr(txq);
2232 switch (port_status & PORT_SPEED_MASK) {
2236 case PORT_SPEED_100:
2239 case PORT_SPEED_1000:
2246 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2247 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2249 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2250 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2252 if (!netif_carrier_ok(dev))
2253 netif_carrier_on(dev);
2256 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2258 struct mv643xx_eth_private *mp;
2261 mp = container_of(napi, struct mv643xx_eth_private, napi);
2263 if (unlikely(mp->oom)) {
2265 del_timer(&mp->rx_oom);
2269 while (work_done < budget) {
2274 if (mp->work_link) {
2276 handle_link_event(mp);
2281 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2282 if (likely(!mp->oom))
2283 queue_mask |= mp->work_rx_refill;
2286 if (mv643xx_eth_collect_events(mp))
2291 queue = fls(queue_mask) - 1;
2292 queue_mask = 1 << queue;
2294 work_tbd = budget - work_done;
2298 if (mp->work_tx_end & queue_mask) {
2299 txq_kick(mp->txq + queue);
2300 } else if (mp->work_tx & queue_mask) {
2301 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2302 txq_maybe_wake(mp->txq + queue);
2303 } else if (mp->work_rx & queue_mask) {
2304 work_done += rxq_process(mp->rxq + queue, work_tbd);
2305 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2306 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2312 if (work_done < budget) {
2314 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2315 napi_complete(napi);
2316 wrlp(mp, INT_MASK, mp->int_mask);
2322 static inline void oom_timer_wrapper(unsigned long data)
2324 struct mv643xx_eth_private *mp = (void *)data;
2326 napi_schedule(&mp->napi);
2329 static void port_start(struct mv643xx_eth_private *mp)
2335 * Perform PHY reset, if there is a PHY.
2337 if (mp->phy != NULL) {
2338 struct ethtool_cmd cmd;
2340 mv643xx_eth_get_settings(mp->dev, &cmd);
2341 phy_init_hw(mp->phy);
2342 mv643xx_eth_set_settings(mp->dev, &cmd);
2347 * Configure basic link parameters.
2349 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2351 pscr |= SERIAL_PORT_ENABLE;
2352 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2354 pscr |= DO_NOT_FORCE_LINK_FAIL;
2355 if (mp->phy == NULL)
2356 pscr |= FORCE_LINK_PASS;
2357 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2360 * Configure TX path and queues.
2362 tx_set_rate(mp, 1000000000, 16777216);
2363 for (i = 0; i < mp->txq_count; i++) {
2364 struct tx_queue *txq = mp->txq + i;
2366 txq_reset_hw_ptr(txq);
2367 txq_set_rate(txq, 1000000000, 16777216);
2368 txq_set_fixed_prio_mode(txq);
2372 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2373 * frames to RX queue #0, and include the pseudo-header when
2374 * calculating receive checksums.
2376 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2379 * Treat BPDUs as normal multicasts, and disable partition mode.
2381 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2384 * Add configured unicast addresses to address filter table.
2386 mv643xx_eth_program_unicast_filter(mp->dev);
2389 * Enable the receive queues.
2391 for (i = 0; i < mp->rxq_count; i++) {
2392 struct rx_queue *rxq = mp->rxq + i;
2395 addr = (u32)rxq->rx_desc_dma;
2396 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2397 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2403 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2408 * Reserve 2+14 bytes for an ethernet header (the hardware
2409 * automatically prepends 2 bytes of dummy data to each
2410 * received packet), 16 bytes for up to four VLAN tags, and
2411 * 4 bytes for the trailing FCS -- 36 bytes total.
2413 skb_size = mp->dev->mtu + 36;
2416 * Make sure that the skb size is a multiple of 8 bytes, as
2417 * the lower three bits of the receive descriptor's buffer
2418 * size field are ignored by the hardware.
2420 mp->skb_size = (skb_size + 7) & ~7;
2423 * If NET_SKB_PAD is smaller than a cache line,
2424 * netdev_alloc_skb() will cause skb->data to be misaligned
2425 * to a cache line boundary. If this is the case, include
2426 * some extra space to allow re-aligning the data area.
2428 mp->skb_size += SKB_DMA_REALIGN;
2431 static int mv643xx_eth_open(struct net_device *dev)
2433 struct mv643xx_eth_private *mp = netdev_priv(dev);
2437 wrlp(mp, INT_CAUSE, 0);
2438 wrlp(mp, INT_CAUSE_EXT, 0);
2439 rdlp(mp, INT_CAUSE_EXT);
2441 err = request_irq(dev->irq, mv643xx_eth_irq,
2442 IRQF_SHARED, dev->name, dev);
2444 netdev_err(dev, "can't assign irq\n");
2448 mv643xx_eth_recalc_skb_size(mp);
2450 napi_enable(&mp->napi);
2452 mp->int_mask = INT_EXT;
2454 for (i = 0; i < mp->rxq_count; i++) {
2455 err = rxq_init(mp, i);
2458 rxq_deinit(mp->rxq + i);
2462 rxq_refill(mp->rxq + i, INT_MAX);
2463 mp->int_mask |= INT_RX_0 << i;
2467 mp->rx_oom.expires = jiffies + (HZ / 10);
2468 add_timer(&mp->rx_oom);
2471 for (i = 0; i < mp->txq_count; i++) {
2472 err = txq_init(mp, i);
2475 txq_deinit(mp->txq + i);
2478 mp->int_mask |= INT_TX_END_0 << i;
2481 add_timer(&mp->mib_counters_timer);
2484 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2485 wrlp(mp, INT_MASK, mp->int_mask);
2491 for (i = 0; i < mp->rxq_count; i++)
2492 rxq_deinit(mp->rxq + i);
2494 free_irq(dev->irq, dev);
2499 static void port_reset(struct mv643xx_eth_private *mp)
2504 for (i = 0; i < mp->rxq_count; i++)
2505 rxq_disable(mp->rxq + i);
2506 for (i = 0; i < mp->txq_count; i++)
2507 txq_disable(mp->txq + i);
2510 u32 ps = rdlp(mp, PORT_STATUS);
2512 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2517 /* Reset the Enable bit in the Configuration Register */
2518 data = rdlp(mp, PORT_SERIAL_CONTROL);
2519 data &= ~(SERIAL_PORT_ENABLE |
2520 DO_NOT_FORCE_LINK_FAIL |
2522 wrlp(mp, PORT_SERIAL_CONTROL, data);
2525 static int mv643xx_eth_stop(struct net_device *dev)
2527 struct mv643xx_eth_private *mp = netdev_priv(dev);
2530 wrlp(mp, INT_MASK_EXT, 0x00000000);
2531 wrlp(mp, INT_MASK, 0x00000000);
2534 napi_disable(&mp->napi);
2536 del_timer_sync(&mp->rx_oom);
2538 netif_carrier_off(dev);
2541 free_irq(dev->irq, dev);
2544 mv643xx_eth_get_stats(dev);
2545 mib_counters_update(mp);
2546 del_timer_sync(&mp->mib_counters_timer);
2548 for (i = 0; i < mp->rxq_count; i++)
2549 rxq_deinit(mp->rxq + i);
2550 for (i = 0; i < mp->txq_count; i++)
2551 txq_deinit(mp->txq + i);
2556 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2558 struct mv643xx_eth_private *mp = netdev_priv(dev);
2561 if (mp->phy == NULL)
2564 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2566 mv643xx_eth_adjust_link(dev);
2570 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2572 struct mv643xx_eth_private *mp = netdev_priv(dev);
2574 if (new_mtu < 64 || new_mtu > 9500)
2578 mv643xx_eth_recalc_skb_size(mp);
2579 tx_set_rate(mp, 1000000000, 16777216);
2581 if (!netif_running(dev))
2585 * Stop and then re-open the interface. This will allocate RX
2586 * skbs of the new MTU.
2587 * There is a possible danger that the open will not succeed,
2588 * due to memory being full.
2590 mv643xx_eth_stop(dev);
2591 if (mv643xx_eth_open(dev)) {
2593 "fatal error on re-opening device after MTU change\n");
2599 static void tx_timeout_task(struct work_struct *ugly)
2601 struct mv643xx_eth_private *mp;
2603 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2604 if (netif_running(mp->dev)) {
2605 netif_tx_stop_all_queues(mp->dev);
2608 netif_tx_wake_all_queues(mp->dev);
2612 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2614 struct mv643xx_eth_private *mp = netdev_priv(dev);
2616 netdev_info(dev, "tx timeout\n");
2618 schedule_work(&mp->tx_timeout_task);
2621 #ifdef CONFIG_NET_POLL_CONTROLLER
2622 static void mv643xx_eth_netpoll(struct net_device *dev)
2624 struct mv643xx_eth_private *mp = netdev_priv(dev);
2626 wrlp(mp, INT_MASK, 0x00000000);
2629 mv643xx_eth_irq(dev->irq, dev);
2631 wrlp(mp, INT_MASK, mp->int_mask);
2636 /* platform glue ************************************************************/
2638 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2639 const struct mbus_dram_target_info *dram)
2641 void __iomem *base = msp->base;
2646 for (i = 0; i < 6; i++) {
2647 writel(0, base + WINDOW_BASE(i));
2648 writel(0, base + WINDOW_SIZE(i));
2650 writel(0, base + WINDOW_REMAP_HIGH(i));
2656 for (i = 0; i < dram->num_cs; i++) {
2657 const struct mbus_dram_window *cs = dram->cs + i;
2659 writel((cs->base & 0xffff0000) |
2660 (cs->mbus_attr << 8) |
2661 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2662 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2664 win_enable &= ~(1 << i);
2665 win_protect |= 3 << (2 * i);
2668 writel(win_enable, base + WINDOW_BAR_ENABLE);
2669 msp->win_protect = win_protect;
2672 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2675 * Check whether we have a 14-bit coal limit field in bits
2676 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2677 * SDMA config register.
2679 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2680 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2681 msp->extended_rx_coal_limit = 1;
2683 msp->extended_rx_coal_limit = 0;
2686 * Check whether the MAC supports TX rate control, and if
2687 * yes, whether its associated registers are in the old or
2690 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2691 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2692 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2694 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2695 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2696 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2698 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2702 #if defined(CONFIG_OF)
2703 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2704 { .compatible = "marvell,orion-eth", },
2705 { .compatible = "marvell,kirkwood-eth", },
2708 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2711 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2712 #define mv643xx_eth_property(_np, _name, _v) \
2715 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2719 static struct platform_device *port_platdev[3];
2721 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2722 struct device_node *pnp)
2724 struct platform_device *ppdev;
2725 struct mv643xx_eth_platform_data ppd;
2726 struct resource res;
2727 const char *mac_addr;
2731 memset(&ppd, 0, sizeof(ppd));
2734 memset(&res, 0, sizeof(res));
2735 if (!of_irq_to_resource(pnp, 0, &res)) {
2736 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2740 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2741 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2745 if (ppd.port_number >= 3) {
2746 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2750 while (dev_num < 3 && port_platdev[dev_num])
2754 dev_err(&pdev->dev, "too many ports registered\n");
2758 mac_addr = of_get_mac_address(pnp);
2760 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2762 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2763 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2764 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2765 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2766 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2767 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2769 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2770 if (!ppd.phy_node) {
2771 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2772 of_property_read_u32(pnp, "speed", &ppd.speed);
2773 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2776 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2779 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2780 ppdev->dev.of_node = pnp;
2782 ret = platform_device_add_resources(ppdev, &res, 1);
2786 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2790 ret = platform_device_add(ppdev);
2794 port_platdev[dev_num] = ppdev;
2799 platform_device_put(ppdev);
2803 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2805 struct mv643xx_eth_shared_platform_data *pd;
2806 struct device_node *pnp, *np = pdev->dev.of_node;
2809 /* bail out if not registered from DT */
2813 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2816 pdev->dev.platform_data = pd;
2818 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2820 for_each_available_child_of_node(np, pnp) {
2821 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2830 static void mv643xx_eth_shared_of_remove(void)
2834 for (n = 0; n < 3; n++) {
2835 platform_device_del(port_platdev[n]);
2836 port_platdev[n] = NULL;
2840 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2845 static inline void mv643xx_eth_shared_of_remove(void)
2850 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2852 static int mv643xx_eth_version_printed;
2853 struct mv643xx_eth_shared_platform_data *pd;
2854 struct mv643xx_eth_shared_private *msp;
2855 const struct mbus_dram_target_info *dram;
2856 struct resource *res;
2859 if (!mv643xx_eth_version_printed++)
2860 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2861 mv643xx_eth_driver_version);
2863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2867 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2870 platform_set_drvdata(pdev, msp);
2872 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2873 if (msp->base == NULL)
2876 msp->clk = devm_clk_get(&pdev->dev, NULL);
2877 if (!IS_ERR(msp->clk))
2878 clk_prepare_enable(msp->clk);
2881 * (Re-)program MBUS remapping windows if we are asked to.
2883 dram = mv_mbus_dram_info();
2885 mv643xx_eth_conf_mbus_windows(msp, dram);
2887 ret = mv643xx_eth_shared_of_probe(pdev);
2890 pd = dev_get_platdata(&pdev->dev);
2892 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2893 pd->tx_csum_limit : 9 * 1024;
2894 infer_hw_params(msp);
2899 if (!IS_ERR(msp->clk))
2900 clk_disable_unprepare(msp->clk);
2904 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2906 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2908 mv643xx_eth_shared_of_remove();
2909 if (!IS_ERR(msp->clk))
2910 clk_disable_unprepare(msp->clk);
2914 static struct platform_driver mv643xx_eth_shared_driver = {
2915 .probe = mv643xx_eth_shared_probe,
2916 .remove = mv643xx_eth_shared_remove,
2918 .name = MV643XX_ETH_SHARED_NAME,
2919 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2923 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2925 int addr_shift = 5 * mp->port_num;
2928 data = rdl(mp, PHY_ADDR);
2929 data &= ~(0x1f << addr_shift);
2930 data |= (phy_addr & 0x1f) << addr_shift;
2931 wrl(mp, PHY_ADDR, data);
2934 static int phy_addr_get(struct mv643xx_eth_private *mp)
2938 data = rdl(mp, PHY_ADDR);
2940 return (data >> (5 * mp->port_num)) & 0x1f;
2943 static void set_params(struct mv643xx_eth_private *mp,
2944 struct mv643xx_eth_platform_data *pd)
2946 struct net_device *dev = mp->dev;
2947 unsigned int tx_ring_size;
2949 if (is_valid_ether_addr(pd->mac_addr))
2950 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2952 uc_addr_get(mp, dev->dev_addr);
2954 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2955 if (pd->rx_queue_size)
2956 mp->rx_ring_size = pd->rx_queue_size;
2957 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2958 mp->rx_desc_sram_size = pd->rx_sram_size;
2960 mp->rxq_count = pd->rx_queue_count ? : 1;
2962 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2963 if (pd->tx_queue_size)
2964 tx_ring_size = pd->tx_queue_size;
2966 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2967 MV643XX_MAX_SKB_DESCS * 2, 4096);
2968 if (mp->tx_ring_size != tx_ring_size)
2969 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2970 mp->tx_ring_size, tx_ring_size);
2972 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2973 mp->tx_desc_sram_size = pd->tx_sram_size;
2975 mp->txq_count = pd->tx_queue_count ? : 1;
2978 static int get_phy_mode(struct mv643xx_eth_private *mp)
2980 struct device *dev = mp->dev->dev.parent;
2984 iface = of_get_phy_mode(dev->of_node);
2986 /* Historical default if unspecified. We could also read/write
2987 * the interface state in the PSC1
2990 iface = PHY_INTERFACE_MODE_GMII;
2994 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2997 struct phy_device *phydev;
3001 char phy_id[MII_BUS_ID_SIZE + 3];
3003 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
3004 start = phy_addr_get(mp) & 0x1f;
3007 start = phy_addr & 0x1f;
3011 /* Attempt to connect to the PHY using orion-mdio */
3012 phydev = ERR_PTR(-ENODEV);
3013 for (i = 0; i < num; i++) {
3014 int addr = (start + i) & 0x1f;
3016 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
3017 "orion-mdio-mii", addr);
3019 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3021 if (!IS_ERR(phydev)) {
3022 phy_addr_set(mp, addr);
3030 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3032 struct phy_device *phy = mp->phy;
3035 phy->autoneg = AUTONEG_ENABLE;
3038 phy->advertising = phy->supported | ADVERTISED_Autoneg;
3040 phy->autoneg = AUTONEG_DISABLE;
3041 phy->advertising = 0;
3043 phy->duplex = duplex;
3045 phy_start_aneg(phy);
3048 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3052 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3053 if (pscr & SERIAL_PORT_ENABLE) {
3054 pscr &= ~SERIAL_PORT_ENABLE;
3055 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3058 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3059 if (mp->phy == NULL) {
3060 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3061 if (speed == SPEED_1000)
3062 pscr |= SET_GMII_SPEED_TO_1000;
3063 else if (speed == SPEED_100)
3064 pscr |= SET_MII_SPEED_TO_100;
3066 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3068 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3069 if (duplex == DUPLEX_FULL)
3070 pscr |= SET_FULL_DUPLEX_MODE;
3073 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3076 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3077 .ndo_open = mv643xx_eth_open,
3078 .ndo_stop = mv643xx_eth_stop,
3079 .ndo_start_xmit = mv643xx_eth_xmit,
3080 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3081 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3082 .ndo_validate_addr = eth_validate_addr,
3083 .ndo_do_ioctl = mv643xx_eth_ioctl,
3084 .ndo_change_mtu = mv643xx_eth_change_mtu,
3085 .ndo_set_features = mv643xx_eth_set_features,
3086 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3087 .ndo_get_stats = mv643xx_eth_get_stats,
3088 #ifdef CONFIG_NET_POLL_CONTROLLER
3089 .ndo_poll_controller = mv643xx_eth_netpoll,
3093 static int mv643xx_eth_probe(struct platform_device *pdev)
3095 struct mv643xx_eth_platform_data *pd;
3096 struct mv643xx_eth_private *mp;
3097 struct net_device *dev;
3098 struct resource *res;
3101 pd = dev_get_platdata(&pdev->dev);
3103 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3107 if (pd->shared == NULL) {
3108 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3112 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3116 SET_NETDEV_DEV(dev, &pdev->dev);
3117 mp = netdev_priv(dev);
3118 platform_set_drvdata(pdev, mp);
3120 mp->shared = platform_get_drvdata(pd->shared);
3121 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3122 mp->port_num = pd->port_number;
3126 /* Kirkwood resets some registers on gated clocks. Especially
3127 * CLK125_BYPASS_EN must be cleared but is not available on
3128 * all other SoCs/System Controllers using this driver.
3130 if (of_device_is_compatible(pdev->dev.of_node,
3131 "marvell,kirkwood-eth-port"))
3132 wrlp(mp, PORT_SERIAL_CONTROL1,
3133 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3136 * Start with a default rate, and if there is a clock, allow
3137 * it to override the default.
3139 mp->t_clk = 133000000;
3140 mp->clk = devm_clk_get(&pdev->dev, NULL);
3141 if (!IS_ERR(mp->clk)) {
3142 clk_prepare_enable(mp->clk);
3143 mp->t_clk = clk_get_rate(mp->clk);
3144 } else if (!IS_ERR(mp->shared->clk)) {
3145 mp->t_clk = clk_get_rate(mp->shared->clk);
3149 netif_set_real_num_tx_queues(dev, mp->txq_count);
3150 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3154 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
3155 mv643xx_eth_adjust_link, 0,
3160 phy_addr_set(mp, mp->phy->mdio.addr);
3161 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3162 mp->phy = phy_scan(mp, pd->phy_addr);
3164 if (IS_ERR(mp->phy))
3165 err = PTR_ERR(mp->phy);
3167 phy_init(mp, pd->speed, pd->duplex);
3169 if (err == -ENODEV) {
3170 err = -EPROBE_DEFER;
3176 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3178 init_pscr(mp, pd->speed, pd->duplex);
3181 mib_counters_clear(mp);
3183 setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper,
3185 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3187 spin_lock_init(&mp->mib_counters_lock);
3189 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3191 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3193 setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp);
3196 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3198 dev->irq = res->start;
3200 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3202 dev->watchdog_timeo = 2 * HZ;
3205 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3206 dev->vlan_features = dev->features;
3208 dev->features |= NETIF_F_RXCSUM;
3209 dev->hw_features = dev->features;
3211 dev->priv_flags |= IFF_UNICAST_FLT;
3212 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3214 if (mp->shared->win_protect)
3215 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3217 netif_carrier_off(dev);
3219 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3221 set_rx_coal(mp, 250);
3224 err = register_netdev(dev);
3228 netdev_notice(dev, "port %d with MAC address %pM\n",
3229 mp->port_num, dev->dev_addr);
3231 if (mp->tx_desc_sram_size > 0)
3232 netdev_notice(dev, "configured with sram\n");
3237 if (!IS_ERR(mp->clk))
3238 clk_disable_unprepare(mp->clk);
3244 static int mv643xx_eth_remove(struct platform_device *pdev)
3246 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3248 unregister_netdev(mp->dev);
3249 if (mp->phy != NULL)
3250 phy_disconnect(mp->phy);
3251 cancel_work_sync(&mp->tx_timeout_task);
3253 if (!IS_ERR(mp->clk))
3254 clk_disable_unprepare(mp->clk);
3256 free_netdev(mp->dev);
3261 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3263 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3265 /* Mask all interrupts on ethernet port */
3266 wrlp(mp, INT_MASK, 0);
3269 if (netif_running(mp->dev))
3273 static struct platform_driver mv643xx_eth_driver = {
3274 .probe = mv643xx_eth_probe,
3275 .remove = mv643xx_eth_remove,
3276 .shutdown = mv643xx_eth_shutdown,
3278 .name = MV643XX_ETH_NAME,
3282 static struct platform_driver * const drivers[] = {
3283 &mv643xx_eth_shared_driver,
3284 &mv643xx_eth_driver,
3287 static int __init mv643xx_eth_init_module(void)
3289 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3291 module_init(mv643xx_eth_init_module);
3293 static void __exit mv643xx_eth_cleanup_module(void)
3295 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3297 module_exit(mv643xx_eth_cleanup_module);
3299 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3300 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3301 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3302 MODULE_LICENSE("GPL");
3303 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3304 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);