2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
73 * Registers shared between all ports.
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 512
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
186 /* Max number of allowed TCP segments for software TSO */
187 #define MV643XX_MAX_TSO_SEGS 100
188 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
190 #define IS_TSO_HEADER(txq, addr) \
191 ((addr >= txq->tso_hdrs_dma) && \
192 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
194 #define DESC_DMA_MAP_SINGLE 0
195 #define DESC_DMA_MAP_PAGE 1
200 #if defined(__BIG_ENDIAN)
202 u16 byte_cnt; /* Descriptor buffer byte count */
203 u16 buf_size; /* Buffer size */
204 u32 cmd_sts; /* Descriptor command status */
205 u32 next_desc_ptr; /* Next descriptor pointer */
206 u32 buf_ptr; /* Descriptor buffer pointer */
210 u16 byte_cnt; /* buffer byte count */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u32 cmd_sts; /* Command/status field */
213 u32 next_desc_ptr; /* Pointer to next descriptor */
214 u32 buf_ptr; /* pointer to buffer for this descriptor*/
216 #elif defined(__LITTLE_ENDIAN)
218 u32 cmd_sts; /* Descriptor command status */
219 u16 buf_size; /* Buffer size */
220 u16 byte_cnt; /* Descriptor buffer byte count */
221 u32 buf_ptr; /* Descriptor buffer pointer */
222 u32 next_desc_ptr; /* Next descriptor pointer */
226 u32 cmd_sts; /* Command/status field */
227 u16 l4i_chk; /* CPU provided TCP checksum */
228 u16 byte_cnt; /* buffer byte count */
229 u32 buf_ptr; /* pointer to buffer for this descriptor*/
230 u32 next_desc_ptr; /* Pointer to next descriptor */
233 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
236 /* RX & TX descriptor command */
237 #define BUFFER_OWNED_BY_DMA 0x80000000
239 /* RX & TX descriptor status */
240 #define ERROR_SUMMARY 0x00000001
242 /* RX descriptor status */
243 #define LAYER_4_CHECKSUM_OK 0x40000000
244 #define RX_ENABLE_INTERRUPT 0x20000000
245 #define RX_FIRST_DESC 0x08000000
246 #define RX_LAST_DESC 0x04000000
247 #define RX_IP_HDR_OK 0x02000000
248 #define RX_PKT_IS_IPV4 0x01000000
249 #define RX_PKT_IS_ETHERNETV2 0x00800000
250 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
251 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
252 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
254 /* TX descriptor command */
255 #define TX_ENABLE_INTERRUPT 0x00800000
256 #define GEN_CRC 0x00400000
257 #define TX_FIRST_DESC 0x00200000
258 #define TX_LAST_DESC 0x00100000
259 #define ZERO_PADDING 0x00080000
260 #define GEN_IP_V4_CHECKSUM 0x00040000
261 #define GEN_TCP_UDP_CHECKSUM 0x00020000
262 #define UDP_FRAME 0x00010000
263 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
264 #define GEN_TCP_UDP_CHK_FULL 0x00000400
265 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
267 #define TX_IHL_SHIFT 11
270 /* global *******************************************************************/
271 struct mv643xx_eth_shared_private {
273 * Ethernet controller base address.
278 * Per-port MBUS window access register value.
283 * Hardware-specific parameters.
285 int extended_rx_coal_limit;
291 #define TX_BW_CONTROL_ABSENT 0
292 #define TX_BW_CONTROL_OLD_LAYOUT 1
293 #define TX_BW_CONTROL_NEW_LAYOUT 2
295 static int mv643xx_eth_open(struct net_device *dev);
296 static int mv643xx_eth_stop(struct net_device *dev);
299 /* per-port *****************************************************************/
300 struct mib_counters {
301 u64 good_octets_received;
302 u32 bad_octets_received;
303 u32 internal_mac_transmit_err;
304 u32 good_frames_received;
305 u32 bad_frames_received;
306 u32 broadcast_frames_received;
307 u32 multicast_frames_received;
308 u32 frames_64_octets;
309 u32 frames_65_to_127_octets;
310 u32 frames_128_to_255_octets;
311 u32 frames_256_to_511_octets;
312 u32 frames_512_to_1023_octets;
313 u32 frames_1024_to_max_octets;
314 u64 good_octets_sent;
315 u32 good_frames_sent;
316 u32 excessive_collision;
317 u32 multicast_frames_sent;
318 u32 broadcast_frames_sent;
319 u32 unrec_mac_control_received;
321 u32 good_fc_received;
323 u32 undersize_received;
324 u32 fragments_received;
325 u32 oversize_received;
327 u32 mac_receive_error;
331 /* Non MIB hardware counters */
345 struct rx_desc *rx_desc_area;
346 dma_addr_t rx_desc_dma;
347 int rx_desc_area_size;
348 struct sk_buff **rx_skb;
360 int tx_stop_threshold;
361 int tx_wake_threshold;
364 dma_addr_t tso_hdrs_dma;
366 struct tx_desc *tx_desc_area;
367 char *tx_desc_mapping; /* array to track the type of the dma mapping */
368 dma_addr_t tx_desc_dma;
369 int tx_desc_area_size;
371 struct sk_buff_head tx_skb;
373 unsigned long tx_packets;
374 unsigned long tx_bytes;
375 unsigned long tx_dropped;
378 struct mv643xx_eth_private {
379 struct mv643xx_eth_shared_private *shared;
383 struct net_device *dev;
385 struct timer_list mib_counters_timer;
386 spinlock_t mib_counters_lock;
387 struct mib_counters mib_counters;
389 struct work_struct tx_timeout_task;
391 struct napi_struct napi;
406 unsigned long rx_desc_sram_addr;
407 int rx_desc_sram_size;
409 struct timer_list rx_oom;
410 struct rx_queue rxq[8];
416 unsigned long tx_desc_sram_addr;
417 int tx_desc_sram_size;
419 struct tx_queue txq[8];
422 * Hardware-specific parameters.
429 /* port register accessors **************************************************/
430 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
432 return readl(mp->shared->base + offset);
435 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
437 return readl(mp->base + offset);
440 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
442 writel(data, mp->shared->base + offset);
445 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
447 writel(data, mp->base + offset);
451 /* rxq/txq helper functions *************************************************/
452 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
454 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
457 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
459 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
462 static void rxq_enable(struct rx_queue *rxq)
464 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
465 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
468 static void rxq_disable(struct rx_queue *rxq)
470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
471 u8 mask = 1 << rxq->index;
473 wrlp(mp, RXQ_COMMAND, mask << 8);
474 while (rdlp(mp, RXQ_COMMAND) & mask)
478 static void txq_reset_hw_ptr(struct tx_queue *txq)
480 struct mv643xx_eth_private *mp = txq_to_mp(txq);
483 addr = (u32)txq->tx_desc_dma;
484 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
485 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
488 static void txq_enable(struct tx_queue *txq)
490 struct mv643xx_eth_private *mp = txq_to_mp(txq);
491 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
494 static void txq_disable(struct tx_queue *txq)
496 struct mv643xx_eth_private *mp = txq_to_mp(txq);
497 u8 mask = 1 << txq->index;
499 wrlp(mp, TXQ_COMMAND, mask << 8);
500 while (rdlp(mp, TXQ_COMMAND) & mask)
504 static void txq_maybe_wake(struct tx_queue *txq)
506 struct mv643xx_eth_private *mp = txq_to_mp(txq);
507 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
509 if (netif_tx_queue_stopped(nq)) {
510 __netif_tx_lock(nq, smp_processor_id());
511 if (txq->tx_desc_count <= txq->tx_wake_threshold)
512 netif_tx_wake_queue(nq);
513 __netif_tx_unlock(nq);
517 static int rxq_process(struct rx_queue *rxq, int budget)
519 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
520 struct net_device_stats *stats = &mp->dev->stats;
524 while (rx < budget && rxq->rx_desc_count) {
525 struct rx_desc *rx_desc;
526 unsigned int cmd_sts;
530 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
532 cmd_sts = rx_desc->cmd_sts;
533 if (cmd_sts & BUFFER_OWNED_BY_DMA)
537 skb = rxq->rx_skb[rxq->rx_curr_desc];
538 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
541 if (rxq->rx_curr_desc == rxq->rx_ring_size)
542 rxq->rx_curr_desc = 0;
544 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
545 rx_desc->buf_size, DMA_FROM_DEVICE);
546 rxq->rx_desc_count--;
549 mp->work_rx_refill |= 1 << rxq->index;
551 byte_cnt = rx_desc->byte_cnt;
556 * Note that the descriptor byte count includes 2 dummy
557 * bytes automatically inserted by the hardware at the
558 * start of the packet (which we don't count), and a 4
559 * byte CRC at the end of the packet (which we do count).
562 stats->rx_bytes += byte_cnt - 2;
565 * In case we received a packet without first / last bits
566 * on, or the error summary bit is set, the packet needs
569 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
570 != (RX_FIRST_DESC | RX_LAST_DESC))
574 * The -4 is for the CRC in the trailer of the
577 skb_put(skb, byte_cnt - 2 - 4);
579 if (cmd_sts & LAYER_4_CHECKSUM_OK)
580 skb->ip_summed = CHECKSUM_UNNECESSARY;
581 skb->protocol = eth_type_trans(skb, mp->dev);
583 napi_gro_receive(&mp->napi, skb);
590 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
591 (RX_FIRST_DESC | RX_LAST_DESC)) {
594 "received packet spanning multiple descriptors\n");
597 if (cmd_sts & ERROR_SUMMARY)
604 mp->work_rx &= ~(1 << rxq->index);
609 static int rxq_refill(struct rx_queue *rxq, int budget)
611 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
615 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
618 struct rx_desc *rx_desc;
621 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
629 skb_reserve(skb, SKB_DMA_REALIGN);
632 rxq->rx_desc_count++;
634 rx = rxq->rx_used_desc++;
635 if (rxq->rx_used_desc == rxq->rx_ring_size)
636 rxq->rx_used_desc = 0;
638 rx_desc = rxq->rx_desc_area + rx;
640 size = skb_end_pointer(skb) - skb->data;
641 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
644 rx_desc->buf_size = size;
645 rxq->rx_skb[rx] = skb;
647 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
651 * The hardware automatically prepends 2 bytes of
652 * dummy data to each received packet, so that the
653 * IP header ends up 16-byte aligned.
658 if (refilled < budget)
659 mp->work_rx_refill &= ~(1 << rxq->index);
666 /* tx ***********************************************************************/
667 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
671 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
672 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
674 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
681 static inline __be16 sum16_as_be(__sum16 sum)
683 return (__force __be16)sum;
686 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
687 u16 *l4i_chk, u32 *command, int length)
692 if (skb->ip_summed == CHECKSUM_PARTIAL) {
696 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
697 skb->protocol != htons(ETH_P_8021Q));
699 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
700 tag_bytes = hdr_len - ETH_HLEN;
702 if (length - hdr_len > mp->shared->tx_csum_limit ||
703 unlikely(tag_bytes & ~12)) {
704 ret = skb_checksum_help(skb);
711 cmd |= MAC_HDR_EXTRA_4_BYTES;
713 cmd |= MAC_HDR_EXTRA_8_BYTES;
715 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
717 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
719 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
720 * it seems we don't need to pass the initial checksum. */
721 switch (ip_hdr(skb)->protocol) {
730 WARN(1, "protocol not supported");
734 /* Errata BTS #50, IHL must be 5 if no HW checksum */
735 cmd |= 5 << TX_IHL_SHIFT;
742 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
743 struct sk_buff *skb, char *data, int length,
744 bool last_tcp, bool is_last)
748 struct tx_desc *desc;
750 tx_index = txq->tx_curr_desc++;
751 if (txq->tx_curr_desc == txq->tx_ring_size)
752 txq->tx_curr_desc = 0;
753 desc = &txq->tx_desc_area[tx_index];
754 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
757 desc->byte_cnt = length;
759 if (length <= 8 && (uintptr_t)data & 0x7) {
760 /* Copy unaligned small data fragment to TSO header data area */
761 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
763 desc->buf_ptr = txq->tso_hdrs_dma
764 + tx_index * TSO_HEADER_SIZE;
766 /* Alignment is okay, map buffer and hand off to hardware */
767 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
768 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
769 length, DMA_TO_DEVICE);
770 if (unlikely(dma_mapping_error(dev->dev.parent,
772 WARN(1, "dma_map_single failed!\n");
777 cmd_sts = BUFFER_OWNED_BY_DMA;
779 /* last descriptor in the TCP packet */
780 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
781 /* last descriptor in SKB */
783 cmd_sts |= TX_ENABLE_INTERRUPT;
785 desc->cmd_sts = cmd_sts;
790 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
791 u32 *first_cmd_sts, bool first_desc)
793 struct mv643xx_eth_private *mp = txq_to_mp(txq);
794 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
796 struct tx_desc *desc;
802 tx_index = txq->tx_curr_desc;
803 desc = &txq->tx_desc_area[tx_index];
805 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
807 WARN(1, "failed to prepare checksum!");
809 /* Should we set this? Can't use the value from skb_tx_csum()
810 * as it's not the correct initial L4 checksum to use. */
813 desc->byte_cnt = hdr_len;
814 desc->buf_ptr = txq->tso_hdrs_dma +
815 txq->tx_curr_desc * TSO_HEADER_SIZE;
816 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
819 /* Defer updating the first command descriptor until all
820 * following descriptors have been written.
823 *first_cmd_sts = cmd_sts;
825 desc->cmd_sts = cmd_sts;
828 if (txq->tx_curr_desc == txq->tx_ring_size)
829 txq->tx_curr_desc = 0;
832 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
833 struct net_device *dev)
835 struct mv643xx_eth_private *mp = txq_to_mp(txq);
836 int total_len, data_left, ret;
839 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
840 struct tx_desc *first_tx_desc;
841 u32 first_cmd_sts = 0;
843 /* Count needed descriptors */
844 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
845 netdev_dbg(dev, "not enough descriptors for TSO!\n");
849 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
851 /* Initialize the TSO handler, and prepare the first payload */
852 tso_start(skb, &tso);
854 total_len = skb->len - hdr_len;
855 while (total_len > 0) {
856 bool first_desc = (desc_count == 0);
859 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
860 total_len -= data_left;
863 /* prepare packet headers: MAC + IP + TCP */
864 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
865 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
866 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
869 while (data_left > 0) {
873 size = min_t(int, tso.size, data_left);
874 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
880 tso_build_data(skb, &tso, size);
884 __skb_queue_tail(&txq->tx_skb, skb);
885 skb_tx_timestamp(skb);
887 /* ensure all other descriptors are written before first cmd_sts */
889 first_tx_desc->cmd_sts = first_cmd_sts;
891 /* clear TX_END status */
892 mp->work_tx_end &= ~(1 << txq->index);
894 /* ensure all descriptors are written before poking hardware */
897 txq->tx_desc_count += desc_count;
900 /* TODO: Release all used data descriptors; header descriptors must not
906 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
908 struct mv643xx_eth_private *mp = txq_to_mp(txq);
909 int nr_frags = skb_shinfo(skb)->nr_frags;
912 for (frag = 0; frag < nr_frags; frag++) {
913 skb_frag_t *this_frag;
915 struct tx_desc *desc;
917 this_frag = &skb_shinfo(skb)->frags[frag];
918 tx_index = txq->tx_curr_desc++;
919 if (txq->tx_curr_desc == txq->tx_ring_size)
920 txq->tx_curr_desc = 0;
921 desc = &txq->tx_desc_area[tx_index];
922 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
925 * The last fragment will generate an interrupt
926 * which will free the skb on TX completion.
928 if (frag == nr_frags - 1) {
929 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
930 ZERO_PADDING | TX_LAST_DESC |
933 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
937 desc->byte_cnt = skb_frag_size(this_frag);
938 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
939 this_frag, 0, desc->byte_cnt,
944 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
945 struct net_device *dev)
947 struct mv643xx_eth_private *mp = txq_to_mp(txq);
948 int nr_frags = skb_shinfo(skb)->nr_frags;
950 struct tx_desc *desc;
958 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
960 netdev_err(dev, "tx queue full?!\n");
964 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
967 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
969 tx_index = txq->tx_curr_desc++;
970 if (txq->tx_curr_desc == txq->tx_ring_size)
971 txq->tx_curr_desc = 0;
972 desc = &txq->tx_desc_area[tx_index];
973 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
976 txq_submit_frag_skb(txq, skb);
977 length = skb_headlen(skb);
979 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
983 desc->l4i_chk = l4i_chk;
984 desc->byte_cnt = length;
985 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
986 length, DMA_TO_DEVICE);
988 __skb_queue_tail(&txq->tx_skb, skb);
990 skb_tx_timestamp(skb);
992 /* ensure all other descriptors are written before first cmd_sts */
994 desc->cmd_sts = cmd_sts;
996 /* clear TX_END status */
997 mp->work_tx_end &= ~(1 << txq->index);
999 /* ensure all descriptors are written before poking hardware */
1003 txq->tx_desc_count += nr_frags + 1;
1008 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1010 struct mv643xx_eth_private *mp = netdev_priv(dev);
1011 int length, queue, ret;
1012 struct tx_queue *txq;
1013 struct netdev_queue *nq;
1015 queue = skb_get_queue_mapping(skb);
1016 txq = mp->txq + queue;
1017 nq = netdev_get_tx_queue(dev, queue);
1019 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1020 netdev_printk(KERN_DEBUG, dev,
1021 "failed to linearize skb with tiny unaligned fragment\n");
1022 return NETDEV_TX_BUSY;
1027 if (skb_is_gso(skb))
1028 ret = txq_submit_tso(txq, skb, dev);
1030 ret = txq_submit_skb(txq, skb, dev);
1032 txq->tx_bytes += length;
1035 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1036 netif_tx_stop_queue(nq);
1039 dev_kfree_skb_any(skb);
1042 return NETDEV_TX_OK;
1046 /* tx napi ******************************************************************/
1047 static void txq_kick(struct tx_queue *txq)
1049 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1050 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1054 __netif_tx_lock(nq, smp_processor_id());
1056 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1059 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1060 expected_ptr = (u32)txq->tx_desc_dma +
1061 txq->tx_curr_desc * sizeof(struct tx_desc);
1063 if (hw_desc_ptr != expected_ptr)
1067 __netif_tx_unlock(nq);
1069 mp->work_tx_end &= ~(1 << txq->index);
1072 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1074 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1075 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1078 __netif_tx_lock_bh(nq);
1081 while (reclaimed < budget && txq->tx_desc_count > 0) {
1083 struct tx_desc *desc;
1087 tx_index = txq->tx_used_desc;
1088 desc = &txq->tx_desc_area[tx_index];
1089 desc_dma_map = txq->tx_desc_mapping[tx_index];
1091 cmd_sts = desc->cmd_sts;
1093 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1096 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1099 txq->tx_used_desc = tx_index + 1;
1100 if (txq->tx_used_desc == txq->tx_ring_size)
1101 txq->tx_used_desc = 0;
1104 txq->tx_desc_count--;
1106 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1108 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1109 dma_unmap_page(mp->dev->dev.parent,
1114 dma_unmap_single(mp->dev->dev.parent,
1120 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1121 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1124 dev_consume_skb_any(skb);
1127 if (cmd_sts & ERROR_SUMMARY) {
1128 netdev_info(mp->dev, "tx error\n");
1129 mp->dev->stats.tx_errors++;
1134 __netif_tx_unlock_bh(nq);
1136 if (reclaimed < budget)
1137 mp->work_tx &= ~(1 << txq->index);
1143 /* tx rate control **********************************************************/
1145 * Set total maximum TX rate (shared by all TX queues for this port)
1146 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1148 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1154 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1155 if (token_rate > 1023)
1158 mtu = (mp->dev->mtu + 255) >> 8;
1162 bucket_size = (burst + 255) >> 8;
1163 if (bucket_size > 65535)
1164 bucket_size = 65535;
1166 switch (mp->shared->tx_bw_control) {
1167 case TX_BW_CONTROL_OLD_LAYOUT:
1168 wrlp(mp, TX_BW_RATE, token_rate);
1169 wrlp(mp, TX_BW_MTU, mtu);
1170 wrlp(mp, TX_BW_BURST, bucket_size);
1172 case TX_BW_CONTROL_NEW_LAYOUT:
1173 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1174 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1175 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1180 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1182 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1186 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1187 if (token_rate > 1023)
1190 bucket_size = (burst + 255) >> 8;
1191 if (bucket_size > 65535)
1192 bucket_size = 65535;
1194 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1195 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1198 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1200 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1205 * Turn on fixed priority mode.
1208 switch (mp->shared->tx_bw_control) {
1209 case TX_BW_CONTROL_OLD_LAYOUT:
1210 off = TXQ_FIX_PRIO_CONF;
1212 case TX_BW_CONTROL_NEW_LAYOUT:
1213 off = TXQ_FIX_PRIO_CONF_MOVED;
1218 val = rdlp(mp, off);
1219 val |= 1 << txq->index;
1225 /* mii management interface *************************************************/
1226 static void mv643xx_eth_adjust_link(struct net_device *dev)
1228 struct mv643xx_eth_private *mp = netdev_priv(dev);
1229 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1230 u32 autoneg_disable = FORCE_LINK_PASS |
1231 DISABLE_AUTO_NEG_SPEED_GMII |
1232 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1233 DISABLE_AUTO_NEG_FOR_DUPLEX;
1235 if (dev->phydev->autoneg == AUTONEG_ENABLE) {
1236 /* enable auto negotiation */
1237 pscr &= ~autoneg_disable;
1241 pscr |= autoneg_disable;
1243 if (dev->phydev->speed == SPEED_1000) {
1244 /* force gigabit, half duplex not supported */
1245 pscr |= SET_GMII_SPEED_TO_1000;
1246 pscr |= SET_FULL_DUPLEX_MODE;
1250 pscr &= ~SET_GMII_SPEED_TO_1000;
1252 if (dev->phydev->speed == SPEED_100)
1253 pscr |= SET_MII_SPEED_TO_100;
1255 pscr &= ~SET_MII_SPEED_TO_100;
1257 if (dev->phydev->duplex == DUPLEX_FULL)
1258 pscr |= SET_FULL_DUPLEX_MODE;
1260 pscr &= ~SET_FULL_DUPLEX_MODE;
1263 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1266 /* statistics ***************************************************************/
1267 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1269 struct mv643xx_eth_private *mp = netdev_priv(dev);
1270 struct net_device_stats *stats = &dev->stats;
1271 unsigned long tx_packets = 0;
1272 unsigned long tx_bytes = 0;
1273 unsigned long tx_dropped = 0;
1276 for (i = 0; i < mp->txq_count; i++) {
1277 struct tx_queue *txq = mp->txq + i;
1279 tx_packets += txq->tx_packets;
1280 tx_bytes += txq->tx_bytes;
1281 tx_dropped += txq->tx_dropped;
1284 stats->tx_packets = tx_packets;
1285 stats->tx_bytes = tx_bytes;
1286 stats->tx_dropped = tx_dropped;
1291 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1293 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1296 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1300 for (i = 0; i < 0x80; i += 4)
1303 /* Clear non MIB hw counters also */
1304 rdlp(mp, RX_DISCARD_FRAME_CNT);
1305 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1308 static void mib_counters_update(struct mv643xx_eth_private *mp)
1310 struct mib_counters *p = &mp->mib_counters;
1312 spin_lock_bh(&mp->mib_counters_lock);
1313 p->good_octets_received += mib_read(mp, 0x00);
1314 p->bad_octets_received += mib_read(mp, 0x08);
1315 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1316 p->good_frames_received += mib_read(mp, 0x10);
1317 p->bad_frames_received += mib_read(mp, 0x14);
1318 p->broadcast_frames_received += mib_read(mp, 0x18);
1319 p->multicast_frames_received += mib_read(mp, 0x1c);
1320 p->frames_64_octets += mib_read(mp, 0x20);
1321 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1322 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1323 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1324 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1325 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1326 p->good_octets_sent += mib_read(mp, 0x38);
1327 p->good_frames_sent += mib_read(mp, 0x40);
1328 p->excessive_collision += mib_read(mp, 0x44);
1329 p->multicast_frames_sent += mib_read(mp, 0x48);
1330 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1331 p->unrec_mac_control_received += mib_read(mp, 0x50);
1332 p->fc_sent += mib_read(mp, 0x54);
1333 p->good_fc_received += mib_read(mp, 0x58);
1334 p->bad_fc_received += mib_read(mp, 0x5c);
1335 p->undersize_received += mib_read(mp, 0x60);
1336 p->fragments_received += mib_read(mp, 0x64);
1337 p->oversize_received += mib_read(mp, 0x68);
1338 p->jabber_received += mib_read(mp, 0x6c);
1339 p->mac_receive_error += mib_read(mp, 0x70);
1340 p->bad_crc_event += mib_read(mp, 0x74);
1341 p->collision += mib_read(mp, 0x78);
1342 p->late_collision += mib_read(mp, 0x7c);
1343 /* Non MIB hardware counters */
1344 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1345 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1346 spin_unlock_bh(&mp->mib_counters_lock);
1349 static void mib_counters_timer_wrapper(unsigned long _mp)
1351 struct mv643xx_eth_private *mp = (void *)_mp;
1352 mib_counters_update(mp);
1353 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1357 /* interrupt coalescing *****************************************************/
1359 * Hardware coalescing parameters are set in units of 64 t_clk
1362 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1364 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1366 * In the ->set*() methods, we round the computed register value
1367 * to the nearest integer.
1369 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1371 u32 val = rdlp(mp, SDMA_CONFIG);
1374 if (mp->shared->extended_rx_coal_limit)
1375 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1377 temp = (val & 0x003fff00) >> 8;
1380 temp += mp->t_clk / 2;
1381 do_div(temp, mp->t_clk);
1383 return (unsigned int)temp;
1386 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1391 temp = (u64)usec * mp->t_clk;
1393 do_div(temp, 64000000);
1395 val = rdlp(mp, SDMA_CONFIG);
1396 if (mp->shared->extended_rx_coal_limit) {
1400 val |= (temp & 0x8000) << 10;
1401 val |= (temp & 0x7fff) << 7;
1406 val |= (temp & 0x3fff) << 8;
1408 wrlp(mp, SDMA_CONFIG, val);
1411 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1415 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1417 temp += mp->t_clk / 2;
1418 do_div(temp, mp->t_clk);
1420 return (unsigned int)temp;
1423 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1427 temp = (u64)usec * mp->t_clk;
1429 do_div(temp, 64000000);
1434 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1438 /* ethtool ******************************************************************/
1439 struct mv643xx_eth_stats {
1440 char stat_string[ETH_GSTRING_LEN];
1447 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1448 offsetof(struct net_device, stats.m), -1 }
1450 #define MIBSTAT(m) \
1451 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1452 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1454 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1463 MIBSTAT(good_octets_received),
1464 MIBSTAT(bad_octets_received),
1465 MIBSTAT(internal_mac_transmit_err),
1466 MIBSTAT(good_frames_received),
1467 MIBSTAT(bad_frames_received),
1468 MIBSTAT(broadcast_frames_received),
1469 MIBSTAT(multicast_frames_received),
1470 MIBSTAT(frames_64_octets),
1471 MIBSTAT(frames_65_to_127_octets),
1472 MIBSTAT(frames_128_to_255_octets),
1473 MIBSTAT(frames_256_to_511_octets),
1474 MIBSTAT(frames_512_to_1023_octets),
1475 MIBSTAT(frames_1024_to_max_octets),
1476 MIBSTAT(good_octets_sent),
1477 MIBSTAT(good_frames_sent),
1478 MIBSTAT(excessive_collision),
1479 MIBSTAT(multicast_frames_sent),
1480 MIBSTAT(broadcast_frames_sent),
1481 MIBSTAT(unrec_mac_control_received),
1483 MIBSTAT(good_fc_received),
1484 MIBSTAT(bad_fc_received),
1485 MIBSTAT(undersize_received),
1486 MIBSTAT(fragments_received),
1487 MIBSTAT(oversize_received),
1488 MIBSTAT(jabber_received),
1489 MIBSTAT(mac_receive_error),
1490 MIBSTAT(bad_crc_event),
1492 MIBSTAT(late_collision),
1493 MIBSTAT(rx_discard),
1494 MIBSTAT(rx_overrun),
1498 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1499 struct ethtool_link_ksettings *cmd)
1501 struct net_device *dev = mp->dev;
1502 u32 supported, advertising;
1504 phy_ethtool_ksettings_get(dev->phydev, cmd);
1507 * The MAC does not support 1000baseT_Half.
1509 ethtool_convert_link_mode_to_legacy_u32(&supported,
1510 cmd->link_modes.supported);
1511 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1512 cmd->link_modes.advertising);
1513 supported &= ~SUPPORTED_1000baseT_Half;
1514 advertising &= ~ADVERTISED_1000baseT_Half;
1515 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1517 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1524 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1525 struct ethtool_link_ksettings *cmd)
1528 u32 supported, advertising;
1530 port_status = rdlp(mp, PORT_STATUS);
1532 supported = SUPPORTED_MII;
1533 advertising = ADVERTISED_MII;
1534 switch (port_status & PORT_SPEED_MASK) {
1536 cmd->base.speed = SPEED_10;
1538 case PORT_SPEED_100:
1539 cmd->base.speed = SPEED_100;
1541 case PORT_SPEED_1000:
1542 cmd->base.speed = SPEED_1000;
1545 cmd->base.speed = -1;
1548 cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1549 DUPLEX_FULL : DUPLEX_HALF;
1550 cmd->base.port = PORT_MII;
1551 cmd->base.phy_address = 0;
1552 cmd->base.autoneg = AUTONEG_DISABLE;
1554 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1556 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1563 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1568 phy_ethtool_get_wol(dev->phydev, wol);
1572 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1579 err = phy_ethtool_set_wol(dev->phydev, wol);
1580 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1581 * this debugging hint is useful to have.
1583 if (err == -EOPNOTSUPP)
1584 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1589 mv643xx_eth_get_link_ksettings(struct net_device *dev,
1590 struct ethtool_link_ksettings *cmd)
1592 struct mv643xx_eth_private *mp = netdev_priv(dev);
1595 return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
1597 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
1601 mv643xx_eth_set_link_ksettings(struct net_device *dev,
1602 const struct ethtool_link_ksettings *cmd)
1604 struct ethtool_link_ksettings c = *cmd;
1612 * The MAC does not support 1000baseT_Half.
1614 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1615 c.link_modes.advertising);
1616 advertising &= ~ADVERTISED_1000baseT_Half;
1617 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1620 ret = phy_ethtool_ksettings_set(dev->phydev, &c);
1622 mv643xx_eth_adjust_link(dev);
1626 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1627 struct ethtool_drvinfo *drvinfo)
1629 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1630 sizeof(drvinfo->driver));
1631 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1632 sizeof(drvinfo->version));
1633 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1634 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1638 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1640 struct mv643xx_eth_private *mp = netdev_priv(dev);
1642 ec->rx_coalesce_usecs = get_rx_coal(mp);
1643 ec->tx_coalesce_usecs = get_tx_coal(mp);
1649 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1651 struct mv643xx_eth_private *mp = netdev_priv(dev);
1653 set_rx_coal(mp, ec->rx_coalesce_usecs);
1654 set_tx_coal(mp, ec->tx_coalesce_usecs);
1660 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1662 struct mv643xx_eth_private *mp = netdev_priv(dev);
1664 er->rx_max_pending = 4096;
1665 er->tx_max_pending = 4096;
1667 er->rx_pending = mp->rx_ring_size;
1668 er->tx_pending = mp->tx_ring_size;
1672 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1674 struct mv643xx_eth_private *mp = netdev_priv(dev);
1676 if (er->rx_mini_pending || er->rx_jumbo_pending)
1679 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1680 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1681 MV643XX_MAX_SKB_DESCS * 2, 4096);
1682 if (mp->tx_ring_size != er->tx_pending)
1683 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1684 mp->tx_ring_size, er->tx_pending);
1686 if (netif_running(dev)) {
1687 mv643xx_eth_stop(dev);
1688 if (mv643xx_eth_open(dev)) {
1690 "fatal error on re-opening device after ring param change\n");
1700 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1702 struct mv643xx_eth_private *mp = netdev_priv(dev);
1703 bool rx_csum = features & NETIF_F_RXCSUM;
1705 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1710 static void mv643xx_eth_get_strings(struct net_device *dev,
1711 uint32_t stringset, uint8_t *data)
1715 if (stringset == ETH_SS_STATS) {
1716 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1717 memcpy(data + i * ETH_GSTRING_LEN,
1718 mv643xx_eth_stats[i].stat_string,
1724 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1725 struct ethtool_stats *stats,
1728 struct mv643xx_eth_private *mp = netdev_priv(dev);
1731 mv643xx_eth_get_stats(dev);
1732 mib_counters_update(mp);
1734 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1735 const struct mv643xx_eth_stats *stat;
1738 stat = mv643xx_eth_stats + i;
1740 if (stat->netdev_off >= 0)
1741 p = ((void *)mp->dev) + stat->netdev_off;
1743 p = ((void *)mp) + stat->mp_off;
1745 data[i] = (stat->sizeof_stat == 8) ?
1746 *(uint64_t *)p : *(uint32_t *)p;
1750 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1752 if (sset == ETH_SS_STATS)
1753 return ARRAY_SIZE(mv643xx_eth_stats);
1758 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1759 .get_drvinfo = mv643xx_eth_get_drvinfo,
1760 .nway_reset = phy_ethtool_nway_reset,
1761 .get_link = ethtool_op_get_link,
1762 .get_coalesce = mv643xx_eth_get_coalesce,
1763 .set_coalesce = mv643xx_eth_set_coalesce,
1764 .get_ringparam = mv643xx_eth_get_ringparam,
1765 .set_ringparam = mv643xx_eth_set_ringparam,
1766 .get_strings = mv643xx_eth_get_strings,
1767 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1768 .get_sset_count = mv643xx_eth_get_sset_count,
1769 .get_ts_info = ethtool_op_get_ts_info,
1770 .get_wol = mv643xx_eth_get_wol,
1771 .set_wol = mv643xx_eth_set_wol,
1772 .get_link_ksettings = mv643xx_eth_get_link_ksettings,
1773 .set_link_ksettings = mv643xx_eth_set_link_ksettings,
1777 /* address handling *********************************************************/
1778 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1780 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1781 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1783 addr[0] = (mac_h >> 24) & 0xff;
1784 addr[1] = (mac_h >> 16) & 0xff;
1785 addr[2] = (mac_h >> 8) & 0xff;
1786 addr[3] = mac_h & 0xff;
1787 addr[4] = (mac_l >> 8) & 0xff;
1788 addr[5] = mac_l & 0xff;
1791 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1793 wrlp(mp, MAC_ADDR_HIGH,
1794 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1795 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1798 static u32 uc_addr_filter_mask(struct net_device *dev)
1800 struct netdev_hw_addr *ha;
1803 if (dev->flags & IFF_PROMISC)
1806 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1807 netdev_for_each_uc_addr(ha, dev) {
1808 if (memcmp(dev->dev_addr, ha->addr, 5))
1810 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1813 nibbles |= 1 << (ha->addr[5] & 0x0f);
1819 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1821 struct mv643xx_eth_private *mp = netdev_priv(dev);
1826 uc_addr_set(mp, dev->dev_addr);
1828 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1830 nibbles = uc_addr_filter_mask(dev);
1832 port_config |= UNICAST_PROMISCUOUS_MODE;
1836 for (i = 0; i < 16; i += 4) {
1837 int off = UNICAST_TABLE(mp->port_num) + i;
1854 wrlp(mp, PORT_CONFIG, port_config);
1857 static int addr_crc(unsigned char *addr)
1862 for (i = 0; i < 6; i++) {
1865 crc = (crc ^ addr[i]) << 8;
1866 for (j = 7; j >= 0; j--) {
1867 if (crc & (0x100 << j))
1875 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1877 struct mv643xx_eth_private *mp = netdev_priv(dev);
1880 struct netdev_hw_addr *ha;
1883 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1886 /* Allocate both mc_spec and mc_other tables */
1887 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1890 mc_other = &mc_spec[64];
1892 netdev_for_each_mc_addr(ha, dev) {
1897 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1902 entry = addr_crc(a);
1905 table[entry >> 2] |= 1 << (8 * (entry & 3));
1908 for (i = 0; i < 64; i++) {
1909 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1911 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1919 for (i = 0; i < 64; i++) {
1920 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1922 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1927 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1929 mv643xx_eth_program_unicast_filter(dev);
1930 mv643xx_eth_program_multicast_filter(dev);
1933 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1935 struct sockaddr *sa = addr;
1937 if (!is_valid_ether_addr(sa->sa_data))
1938 return -EADDRNOTAVAIL;
1940 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1942 netif_addr_lock_bh(dev);
1943 mv643xx_eth_program_unicast_filter(dev);
1944 netif_addr_unlock_bh(dev);
1950 /* rx/tx queue initialisation ***********************************************/
1951 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1953 struct rx_queue *rxq = mp->rxq + index;
1954 struct rx_desc *rx_desc;
1960 rxq->rx_ring_size = mp->rx_ring_size;
1962 rxq->rx_desc_count = 0;
1963 rxq->rx_curr_desc = 0;
1964 rxq->rx_used_desc = 0;
1966 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1968 if (index == 0 && size <= mp->rx_desc_sram_size) {
1969 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1970 mp->rx_desc_sram_size);
1971 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1973 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1974 size, &rxq->rx_desc_dma,
1978 if (rxq->rx_desc_area == NULL) {
1980 "can't allocate rx ring (%d bytes)\n", size);
1983 memset(rxq->rx_desc_area, 0, size);
1985 rxq->rx_desc_area_size = size;
1986 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1988 if (rxq->rx_skb == NULL)
1991 rx_desc = rxq->rx_desc_area;
1992 for (i = 0; i < rxq->rx_ring_size; i++) {
1996 if (nexti == rxq->rx_ring_size)
1999 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
2000 nexti * sizeof(struct rx_desc);
2007 if (index == 0 && size <= mp->rx_desc_sram_size)
2008 iounmap(rxq->rx_desc_area);
2010 dma_free_coherent(mp->dev->dev.parent, size,
2018 static void rxq_deinit(struct rx_queue *rxq)
2020 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2025 for (i = 0; i < rxq->rx_ring_size; i++) {
2026 if (rxq->rx_skb[i]) {
2027 dev_consume_skb_any(rxq->rx_skb[i]);
2028 rxq->rx_desc_count--;
2032 if (rxq->rx_desc_count) {
2033 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2034 rxq->rx_desc_count);
2037 if (rxq->index == 0 &&
2038 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2039 iounmap(rxq->rx_desc_area);
2041 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2042 rxq->rx_desc_area, rxq->rx_desc_dma);
2047 static int txq_init(struct mv643xx_eth_private *mp, int index)
2049 struct tx_queue *txq = mp->txq + index;
2050 struct tx_desc *tx_desc;
2057 txq->tx_ring_size = mp->tx_ring_size;
2059 /* A queue must always have room for at least one skb.
2060 * Therefore, stop the queue when the free entries reaches
2061 * the maximum number of descriptors per skb.
2063 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2064 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2066 txq->tx_desc_count = 0;
2067 txq->tx_curr_desc = 0;
2068 txq->tx_used_desc = 0;
2070 size = txq->tx_ring_size * sizeof(struct tx_desc);
2072 if (index == 0 && size <= mp->tx_desc_sram_size) {
2073 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2074 mp->tx_desc_sram_size);
2075 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2077 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2078 size, &txq->tx_desc_dma,
2082 if (txq->tx_desc_area == NULL) {
2084 "can't allocate tx ring (%d bytes)\n", size);
2087 memset(txq->tx_desc_area, 0, size);
2089 txq->tx_desc_area_size = size;
2091 tx_desc = txq->tx_desc_area;
2092 for (i = 0; i < txq->tx_ring_size; i++) {
2093 struct tx_desc *txd = tx_desc + i;
2097 if (nexti == txq->tx_ring_size)
2101 txd->next_desc_ptr = txq->tx_desc_dma +
2102 nexti * sizeof(struct tx_desc);
2105 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2107 if (!txq->tx_desc_mapping) {
2109 goto err_free_desc_area;
2112 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2113 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2114 txq->tx_ring_size * TSO_HEADER_SIZE,
2115 &txq->tso_hdrs_dma, GFP_KERNEL);
2116 if (txq->tso_hdrs == NULL) {
2118 goto err_free_desc_mapping;
2120 skb_queue_head_init(&txq->tx_skb);
2124 err_free_desc_mapping:
2125 kfree(txq->tx_desc_mapping);
2127 if (index == 0 && size <= mp->tx_desc_sram_size)
2128 iounmap(txq->tx_desc_area);
2130 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2131 txq->tx_desc_area, txq->tx_desc_dma);
2135 static void txq_deinit(struct tx_queue *txq)
2137 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2140 txq_reclaim(txq, txq->tx_ring_size, 1);
2142 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2144 if (txq->index == 0 &&
2145 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2146 iounmap(txq->tx_desc_area);
2148 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2149 txq->tx_desc_area, txq->tx_desc_dma);
2150 kfree(txq->tx_desc_mapping);
2153 dma_free_coherent(mp->dev->dev.parent,
2154 txq->tx_ring_size * TSO_HEADER_SIZE,
2155 txq->tso_hdrs, txq->tso_hdrs_dma);
2159 /* netdev ops and related ***************************************************/
2160 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2165 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2170 if (int_cause & INT_EXT) {
2171 int_cause &= ~INT_EXT;
2172 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2176 wrlp(mp, INT_CAUSE, ~int_cause);
2177 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2178 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2179 mp->work_rx |= (int_cause & INT_RX) >> 2;
2182 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2183 if (int_cause_ext) {
2184 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2185 if (int_cause_ext & INT_EXT_LINK_PHY)
2187 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2193 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2195 struct net_device *dev = (struct net_device *)dev_id;
2196 struct mv643xx_eth_private *mp = netdev_priv(dev);
2198 if (unlikely(!mv643xx_eth_collect_events(mp)))
2201 wrlp(mp, INT_MASK, 0);
2202 napi_schedule(&mp->napi);
2207 static void handle_link_event(struct mv643xx_eth_private *mp)
2209 struct net_device *dev = mp->dev;
2215 port_status = rdlp(mp, PORT_STATUS);
2216 if (!(port_status & LINK_UP)) {
2217 if (netif_carrier_ok(dev)) {
2220 netdev_info(dev, "link down\n");
2222 netif_carrier_off(dev);
2224 for (i = 0; i < mp->txq_count; i++) {
2225 struct tx_queue *txq = mp->txq + i;
2227 txq_reclaim(txq, txq->tx_ring_size, 1);
2228 txq_reset_hw_ptr(txq);
2234 switch (port_status & PORT_SPEED_MASK) {
2238 case PORT_SPEED_100:
2241 case PORT_SPEED_1000:
2248 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2249 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2251 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2252 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2254 if (!netif_carrier_ok(dev))
2255 netif_carrier_on(dev);
2258 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2260 struct mv643xx_eth_private *mp;
2263 mp = container_of(napi, struct mv643xx_eth_private, napi);
2265 if (unlikely(mp->oom)) {
2267 del_timer(&mp->rx_oom);
2271 while (work_done < budget) {
2276 if (mp->work_link) {
2278 handle_link_event(mp);
2283 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2284 if (likely(!mp->oom))
2285 queue_mask |= mp->work_rx_refill;
2288 if (mv643xx_eth_collect_events(mp))
2293 queue = fls(queue_mask) - 1;
2294 queue_mask = 1 << queue;
2296 work_tbd = budget - work_done;
2300 if (mp->work_tx_end & queue_mask) {
2301 txq_kick(mp->txq + queue);
2302 } else if (mp->work_tx & queue_mask) {
2303 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2304 txq_maybe_wake(mp->txq + queue);
2305 } else if (mp->work_rx & queue_mask) {
2306 work_done += rxq_process(mp->rxq + queue, work_tbd);
2307 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2308 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2314 if (work_done < budget) {
2316 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2317 napi_complete_done(napi, work_done);
2318 wrlp(mp, INT_MASK, mp->int_mask);
2324 static inline void oom_timer_wrapper(unsigned long data)
2326 struct mv643xx_eth_private *mp = (void *)data;
2328 napi_schedule(&mp->napi);
2331 static void port_start(struct mv643xx_eth_private *mp)
2333 struct net_device *dev = mp->dev;
2338 * Perform PHY reset, if there is a PHY.
2341 struct ethtool_link_ksettings cmd;
2343 mv643xx_eth_get_link_ksettings(dev, &cmd);
2344 phy_init_hw(dev->phydev);
2345 mv643xx_eth_set_link_ksettings(
2346 dev, (const struct ethtool_link_ksettings *)&cmd);
2347 phy_start(dev->phydev);
2351 * Configure basic link parameters.
2353 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2355 pscr |= SERIAL_PORT_ENABLE;
2356 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2358 pscr |= DO_NOT_FORCE_LINK_FAIL;
2360 pscr |= FORCE_LINK_PASS;
2361 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2364 * Configure TX path and queues.
2366 tx_set_rate(mp, 1000000000, 16777216);
2367 for (i = 0; i < mp->txq_count; i++) {
2368 struct tx_queue *txq = mp->txq + i;
2370 txq_reset_hw_ptr(txq);
2371 txq_set_rate(txq, 1000000000, 16777216);
2372 txq_set_fixed_prio_mode(txq);
2376 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2377 * frames to RX queue #0, and include the pseudo-header when
2378 * calculating receive checksums.
2380 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2383 * Treat BPDUs as normal multicasts, and disable partition mode.
2385 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2388 * Add configured unicast addresses to address filter table.
2390 mv643xx_eth_program_unicast_filter(mp->dev);
2393 * Enable the receive queues.
2395 for (i = 0; i < mp->rxq_count; i++) {
2396 struct rx_queue *rxq = mp->rxq + i;
2399 addr = (u32)rxq->rx_desc_dma;
2400 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2401 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2407 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2412 * Reserve 2+14 bytes for an ethernet header (the hardware
2413 * automatically prepends 2 bytes of dummy data to each
2414 * received packet), 16 bytes for up to four VLAN tags, and
2415 * 4 bytes for the trailing FCS -- 36 bytes total.
2417 skb_size = mp->dev->mtu + 36;
2420 * Make sure that the skb size is a multiple of 8 bytes, as
2421 * the lower three bits of the receive descriptor's buffer
2422 * size field are ignored by the hardware.
2424 mp->skb_size = (skb_size + 7) & ~7;
2427 * If NET_SKB_PAD is smaller than a cache line,
2428 * netdev_alloc_skb() will cause skb->data to be misaligned
2429 * to a cache line boundary. If this is the case, include
2430 * some extra space to allow re-aligning the data area.
2432 mp->skb_size += SKB_DMA_REALIGN;
2435 static int mv643xx_eth_open(struct net_device *dev)
2437 struct mv643xx_eth_private *mp = netdev_priv(dev);
2441 wrlp(mp, INT_CAUSE, 0);
2442 wrlp(mp, INT_CAUSE_EXT, 0);
2443 rdlp(mp, INT_CAUSE_EXT);
2445 err = request_irq(dev->irq, mv643xx_eth_irq,
2446 IRQF_SHARED, dev->name, dev);
2448 netdev_err(dev, "can't assign irq\n");
2452 mv643xx_eth_recalc_skb_size(mp);
2454 napi_enable(&mp->napi);
2456 mp->int_mask = INT_EXT;
2458 for (i = 0; i < mp->rxq_count; i++) {
2459 err = rxq_init(mp, i);
2462 rxq_deinit(mp->rxq + i);
2466 rxq_refill(mp->rxq + i, INT_MAX);
2467 mp->int_mask |= INT_RX_0 << i;
2471 mp->rx_oom.expires = jiffies + (HZ / 10);
2472 add_timer(&mp->rx_oom);
2475 for (i = 0; i < mp->txq_count; i++) {
2476 err = txq_init(mp, i);
2479 txq_deinit(mp->txq + i);
2482 mp->int_mask |= INT_TX_END_0 << i;
2485 add_timer(&mp->mib_counters_timer);
2488 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2489 wrlp(mp, INT_MASK, mp->int_mask);
2495 for (i = 0; i < mp->rxq_count; i++)
2496 rxq_deinit(mp->rxq + i);
2498 free_irq(dev->irq, dev);
2503 static void port_reset(struct mv643xx_eth_private *mp)
2508 for (i = 0; i < mp->rxq_count; i++)
2509 rxq_disable(mp->rxq + i);
2510 for (i = 0; i < mp->txq_count; i++)
2511 txq_disable(mp->txq + i);
2514 u32 ps = rdlp(mp, PORT_STATUS);
2516 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2521 /* Reset the Enable bit in the Configuration Register */
2522 data = rdlp(mp, PORT_SERIAL_CONTROL);
2523 data &= ~(SERIAL_PORT_ENABLE |
2524 DO_NOT_FORCE_LINK_FAIL |
2526 wrlp(mp, PORT_SERIAL_CONTROL, data);
2529 static int mv643xx_eth_stop(struct net_device *dev)
2531 struct mv643xx_eth_private *mp = netdev_priv(dev);
2534 wrlp(mp, INT_MASK_EXT, 0x00000000);
2535 wrlp(mp, INT_MASK, 0x00000000);
2538 napi_disable(&mp->napi);
2540 del_timer_sync(&mp->rx_oom);
2542 netif_carrier_off(dev);
2544 phy_stop(dev->phydev);
2545 free_irq(dev->irq, dev);
2548 mv643xx_eth_get_stats(dev);
2549 mib_counters_update(mp);
2550 del_timer_sync(&mp->mib_counters_timer);
2552 for (i = 0; i < mp->rxq_count; i++)
2553 rxq_deinit(mp->rxq + i);
2554 for (i = 0; i < mp->txq_count; i++)
2555 txq_deinit(mp->txq + i);
2560 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2567 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
2569 mv643xx_eth_adjust_link(dev);
2573 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2575 struct mv643xx_eth_private *mp = netdev_priv(dev);
2578 mv643xx_eth_recalc_skb_size(mp);
2579 tx_set_rate(mp, 1000000000, 16777216);
2581 if (!netif_running(dev))
2585 * Stop and then re-open the interface. This will allocate RX
2586 * skbs of the new MTU.
2587 * There is a possible danger that the open will not succeed,
2588 * due to memory being full.
2590 mv643xx_eth_stop(dev);
2591 if (mv643xx_eth_open(dev)) {
2593 "fatal error on re-opening device after MTU change\n");
2599 static void tx_timeout_task(struct work_struct *ugly)
2601 struct mv643xx_eth_private *mp;
2603 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2604 if (netif_running(mp->dev)) {
2605 netif_tx_stop_all_queues(mp->dev);
2608 netif_tx_wake_all_queues(mp->dev);
2612 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2614 struct mv643xx_eth_private *mp = netdev_priv(dev);
2616 netdev_info(dev, "tx timeout\n");
2618 schedule_work(&mp->tx_timeout_task);
2621 #ifdef CONFIG_NET_POLL_CONTROLLER
2622 static void mv643xx_eth_netpoll(struct net_device *dev)
2624 struct mv643xx_eth_private *mp = netdev_priv(dev);
2626 wrlp(mp, INT_MASK, 0x00000000);
2629 mv643xx_eth_irq(dev->irq, dev);
2631 wrlp(mp, INT_MASK, mp->int_mask);
2636 /* platform glue ************************************************************/
2638 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2639 const struct mbus_dram_target_info *dram)
2641 void __iomem *base = msp->base;
2646 for (i = 0; i < 6; i++) {
2647 writel(0, base + WINDOW_BASE(i));
2648 writel(0, base + WINDOW_SIZE(i));
2650 writel(0, base + WINDOW_REMAP_HIGH(i));
2656 for (i = 0; i < dram->num_cs; i++) {
2657 const struct mbus_dram_window *cs = dram->cs + i;
2659 writel((cs->base & 0xffff0000) |
2660 (cs->mbus_attr << 8) |
2661 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2662 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2664 win_enable &= ~(1 << i);
2665 win_protect |= 3 << (2 * i);
2668 writel(win_enable, base + WINDOW_BAR_ENABLE);
2669 msp->win_protect = win_protect;
2672 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2675 * Check whether we have a 14-bit coal limit field in bits
2676 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2677 * SDMA config register.
2679 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2680 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2681 msp->extended_rx_coal_limit = 1;
2683 msp->extended_rx_coal_limit = 0;
2686 * Check whether the MAC supports TX rate control, and if
2687 * yes, whether its associated registers are in the old or
2690 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2691 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2692 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2694 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2695 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2696 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2698 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2702 #if defined(CONFIG_OF)
2703 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2704 { .compatible = "marvell,orion-eth", },
2705 { .compatible = "marvell,kirkwood-eth", },
2708 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2711 #if defined(CONFIG_OF_IRQ) && !defined(CONFIG_MV64X60)
2712 #define mv643xx_eth_property(_np, _name, _v) \
2715 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2719 static struct platform_device *port_platdev[3];
2721 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2722 struct device_node *pnp)
2724 struct platform_device *ppdev;
2725 struct mv643xx_eth_platform_data ppd;
2726 struct resource res;
2727 const char *mac_addr;
2731 memset(&ppd, 0, sizeof(ppd));
2734 memset(&res, 0, sizeof(res));
2735 if (of_irq_to_resource(pnp, 0, &res) <= 0) {
2736 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2740 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2741 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2745 if (ppd.port_number >= 3) {
2746 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2750 while (dev_num < 3 && port_platdev[dev_num])
2754 dev_err(&pdev->dev, "too many ports registered\n");
2758 mac_addr = of_get_mac_address(pnp);
2760 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2762 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2763 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2764 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2765 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2766 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2767 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2769 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2770 if (!ppd.phy_node) {
2771 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2772 of_property_read_u32(pnp, "speed", &ppd.speed);
2773 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2776 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2779 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2780 ppdev->dev.of_node = pnp;
2782 ret = platform_device_add_resources(ppdev, &res, 1);
2786 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2790 ret = platform_device_add(ppdev);
2794 port_platdev[dev_num] = ppdev;
2799 platform_device_put(ppdev);
2803 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2805 struct mv643xx_eth_shared_platform_data *pd;
2806 struct device_node *pnp, *np = pdev->dev.of_node;
2809 /* bail out if not registered from DT */
2813 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2816 pdev->dev.platform_data = pd;
2818 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2820 for_each_available_child_of_node(np, pnp) {
2821 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2830 static void mv643xx_eth_shared_of_remove(void)
2834 for (n = 0; n < 3; n++) {
2835 platform_device_del(port_platdev[n]);
2836 port_platdev[n] = NULL;
2840 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2845 static inline void mv643xx_eth_shared_of_remove(void)
2850 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2852 static int mv643xx_eth_version_printed;
2853 struct mv643xx_eth_shared_platform_data *pd;
2854 struct mv643xx_eth_shared_private *msp;
2855 const struct mbus_dram_target_info *dram;
2856 struct resource *res;
2859 if (!mv643xx_eth_version_printed++)
2860 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2861 mv643xx_eth_driver_version);
2863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2867 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2870 platform_set_drvdata(pdev, msp);
2872 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2873 if (msp->base == NULL)
2876 msp->clk = devm_clk_get(&pdev->dev, NULL);
2877 if (!IS_ERR(msp->clk))
2878 clk_prepare_enable(msp->clk);
2881 * (Re-)program MBUS remapping windows if we are asked to.
2883 dram = mv_mbus_dram_info();
2885 mv643xx_eth_conf_mbus_windows(msp, dram);
2887 ret = mv643xx_eth_shared_of_probe(pdev);
2890 pd = dev_get_platdata(&pdev->dev);
2892 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2893 pd->tx_csum_limit : 9 * 1024;
2894 infer_hw_params(msp);
2899 if (!IS_ERR(msp->clk))
2900 clk_disable_unprepare(msp->clk);
2904 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2906 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2908 mv643xx_eth_shared_of_remove();
2909 if (!IS_ERR(msp->clk))
2910 clk_disable_unprepare(msp->clk);
2914 static struct platform_driver mv643xx_eth_shared_driver = {
2915 .probe = mv643xx_eth_shared_probe,
2916 .remove = mv643xx_eth_shared_remove,
2918 .name = MV643XX_ETH_SHARED_NAME,
2919 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2923 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2925 int addr_shift = 5 * mp->port_num;
2928 data = rdl(mp, PHY_ADDR);
2929 data &= ~(0x1f << addr_shift);
2930 data |= (phy_addr & 0x1f) << addr_shift;
2931 wrl(mp, PHY_ADDR, data);
2934 static int phy_addr_get(struct mv643xx_eth_private *mp)
2938 data = rdl(mp, PHY_ADDR);
2940 return (data >> (5 * mp->port_num)) & 0x1f;
2943 static void set_params(struct mv643xx_eth_private *mp,
2944 struct mv643xx_eth_platform_data *pd)
2946 struct net_device *dev = mp->dev;
2947 unsigned int tx_ring_size;
2949 if (is_valid_ether_addr(pd->mac_addr))
2950 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2952 uc_addr_get(mp, dev->dev_addr);
2954 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2955 if (pd->rx_queue_size)
2956 mp->rx_ring_size = pd->rx_queue_size;
2957 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2958 mp->rx_desc_sram_size = pd->rx_sram_size;
2960 mp->rxq_count = pd->rx_queue_count ? : 1;
2962 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2963 if (pd->tx_queue_size)
2964 tx_ring_size = pd->tx_queue_size;
2966 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2967 MV643XX_MAX_SKB_DESCS * 2, 4096);
2968 if (mp->tx_ring_size != tx_ring_size)
2969 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2970 mp->tx_ring_size, tx_ring_size);
2972 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2973 mp->tx_desc_sram_size = pd->tx_sram_size;
2975 mp->txq_count = pd->tx_queue_count ? : 1;
2978 static int get_phy_mode(struct mv643xx_eth_private *mp)
2980 struct device *dev = mp->dev->dev.parent;
2984 iface = of_get_phy_mode(dev->of_node);
2986 /* Historical default if unspecified. We could also read/write
2987 * the interface state in the PSC1
2990 iface = PHY_INTERFACE_MODE_GMII;
2994 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2997 struct phy_device *phydev;
3001 char phy_id[MII_BUS_ID_SIZE + 3];
3003 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
3004 start = phy_addr_get(mp) & 0x1f;
3007 start = phy_addr & 0x1f;
3011 /* Attempt to connect to the PHY using orion-mdio */
3012 phydev = ERR_PTR(-ENODEV);
3013 for (i = 0; i < num; i++) {
3014 int addr = (start + i) & 0x1f;
3016 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
3017 "orion-mdio-mii", addr);
3019 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3021 if (!IS_ERR(phydev)) {
3022 phy_addr_set(mp, addr);
3030 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3032 struct net_device *dev = mp->dev;
3033 struct phy_device *phy = dev->phydev;
3036 phy->autoneg = AUTONEG_ENABLE;
3039 phy->advertising = phy->supported | ADVERTISED_Autoneg;
3041 phy->autoneg = AUTONEG_DISABLE;
3042 phy->advertising = 0;
3044 phy->duplex = duplex;
3046 phy_start_aneg(phy);
3049 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3051 struct net_device *dev = mp->dev;
3054 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3055 if (pscr & SERIAL_PORT_ENABLE) {
3056 pscr &= ~SERIAL_PORT_ENABLE;
3057 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3060 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3062 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3063 if (speed == SPEED_1000)
3064 pscr |= SET_GMII_SPEED_TO_1000;
3065 else if (speed == SPEED_100)
3066 pscr |= SET_MII_SPEED_TO_100;
3068 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3070 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3071 if (duplex == DUPLEX_FULL)
3072 pscr |= SET_FULL_DUPLEX_MODE;
3075 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3078 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3079 .ndo_open = mv643xx_eth_open,
3080 .ndo_stop = mv643xx_eth_stop,
3081 .ndo_start_xmit = mv643xx_eth_xmit,
3082 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3083 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3084 .ndo_validate_addr = eth_validate_addr,
3085 .ndo_do_ioctl = mv643xx_eth_ioctl,
3086 .ndo_change_mtu = mv643xx_eth_change_mtu,
3087 .ndo_set_features = mv643xx_eth_set_features,
3088 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3089 .ndo_get_stats = mv643xx_eth_get_stats,
3090 #ifdef CONFIG_NET_POLL_CONTROLLER
3091 .ndo_poll_controller = mv643xx_eth_netpoll,
3095 static int mv643xx_eth_probe(struct platform_device *pdev)
3097 struct mv643xx_eth_platform_data *pd;
3098 struct mv643xx_eth_private *mp;
3099 struct net_device *dev;
3100 struct phy_device *phydev = NULL;
3101 struct resource *res;
3104 pd = dev_get_platdata(&pdev->dev);
3106 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3110 if (pd->shared == NULL) {
3111 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3115 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3119 SET_NETDEV_DEV(dev, &pdev->dev);
3120 mp = netdev_priv(dev);
3121 platform_set_drvdata(pdev, mp);
3123 mp->shared = platform_get_drvdata(pd->shared);
3124 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3125 mp->port_num = pd->port_number;
3129 /* Kirkwood resets some registers on gated clocks. Especially
3130 * CLK125_BYPASS_EN must be cleared but is not available on
3131 * all other SoCs/System Controllers using this driver.
3133 if (of_device_is_compatible(pdev->dev.of_node,
3134 "marvell,kirkwood-eth-port"))
3135 wrlp(mp, PORT_SERIAL_CONTROL1,
3136 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3139 * Start with a default rate, and if there is a clock, allow
3140 * it to override the default.
3142 mp->t_clk = 133000000;
3143 mp->clk = devm_clk_get(&pdev->dev, NULL);
3144 if (!IS_ERR(mp->clk)) {
3145 clk_prepare_enable(mp->clk);
3146 mp->t_clk = clk_get_rate(mp->clk);
3147 } else if (!IS_ERR(mp->shared->clk)) {
3148 mp->t_clk = clk_get_rate(mp->shared->clk);
3152 netif_set_real_num_tx_queues(dev, mp->txq_count);
3153 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3157 phydev = of_phy_connect(mp->dev, pd->phy_node,
3158 mv643xx_eth_adjust_link, 0,
3163 phy_addr_set(mp, phydev->mdio.addr);
3164 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3165 phydev = phy_scan(mp, pd->phy_addr);
3168 err = PTR_ERR(phydev);
3170 phy_init(mp, pd->speed, pd->duplex);
3172 if (err == -ENODEV) {
3173 err = -EPROBE_DEFER;
3179 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3181 init_pscr(mp, pd->speed, pd->duplex);
3184 mib_counters_clear(mp);
3186 setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper,
3188 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3190 spin_lock_init(&mp->mib_counters_lock);
3192 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3194 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3196 setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp);
3199 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3201 dev->irq = res->start;
3203 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3205 dev->watchdog_timeo = 2 * HZ;
3208 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3209 dev->vlan_features = dev->features;
3211 dev->features |= NETIF_F_RXCSUM;
3212 dev->hw_features = dev->features;
3214 dev->priv_flags |= IFF_UNICAST_FLT;
3215 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3217 /* MTU range: 64 - 9500 */
3219 dev->max_mtu = 9500;
3221 if (mp->shared->win_protect)
3222 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3224 netif_carrier_off(dev);
3226 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3228 set_rx_coal(mp, 250);
3231 err = register_netdev(dev);
3235 netdev_notice(dev, "port %d with MAC address %pM\n",
3236 mp->port_num, dev->dev_addr);
3238 if (mp->tx_desc_sram_size > 0)
3239 netdev_notice(dev, "configured with sram\n");
3244 if (!IS_ERR(mp->clk))
3245 clk_disable_unprepare(mp->clk);
3251 static int mv643xx_eth_remove(struct platform_device *pdev)
3253 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3254 struct net_device *dev = mp->dev;
3256 unregister_netdev(mp->dev);
3258 phy_disconnect(dev->phydev);
3259 cancel_work_sync(&mp->tx_timeout_task);
3261 if (!IS_ERR(mp->clk))
3262 clk_disable_unprepare(mp->clk);
3264 free_netdev(mp->dev);
3269 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3271 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3273 /* Mask all interrupts on ethernet port */
3274 wrlp(mp, INT_MASK, 0);
3277 if (netif_running(mp->dev))
3281 static struct platform_driver mv643xx_eth_driver = {
3282 .probe = mv643xx_eth_probe,
3283 .remove = mv643xx_eth_remove,
3284 .shutdown = mv643xx_eth_shutdown,
3286 .name = MV643XX_ETH_NAME,
3290 static struct platform_driver * const drivers[] = {
3291 &mv643xx_eth_shared_driver,
3292 &mv643xx_eth_driver,
3295 static int __init mv643xx_eth_init_module(void)
3297 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3299 module_init(mv643xx_eth_init_module);
3301 static void __exit mv643xx_eth_cleanup_module(void)
3303 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3305 module_exit(mv643xx_eth_cleanup_module);
3307 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3308 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3309 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3310 MODULE_LICENSE("GPL");
3311 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3312 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);