1 // SPDX-License-Identifier: GPL-2.0
3 * Lantiq / Intel PMAC driver for XRX200 SoCs
5 * Copyright (C) 2010 Lantiq Deutschland
6 * Copyright (C) 2012 John Crispin <john@phrozen.org>
7 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
10 #include <linux/etherdevice.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/interrupt.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
17 #include <linux/of_net.h>
18 #include <linux/of_platform.h>
23 #define XRX200_DMA_DATA_LEN 0x600
24 #define XRX200_DMA_RX 0
25 #define XRX200_DMA_TX 1
28 #define PMAC_RX_IPG 0x0024
29 #define PMAC_RX_IPG_MASK 0xf
31 #define PMAC_HD_CTL 0x0000
32 /* Add Ethernet header to packets from DMA to PMAC */
33 #define PMAC_HD_CTL_ADD BIT(0)
34 /* Add VLAN tag to Packets from DMA to PMAC */
35 #define PMAC_HD_CTL_TAG BIT(1)
36 /* Add CRC to packets from DMA to PMAC */
37 #define PMAC_HD_CTL_AC BIT(2)
38 /* Add status header to packets from PMAC to DMA */
39 #define PMAC_HD_CTL_AS BIT(3)
40 /* Remove CRC from packets from PMAC to DMA */
41 #define PMAC_HD_CTL_RC BIT(4)
42 /* Remove Layer-2 header from packets from PMAC to DMA */
43 #define PMAC_HD_CTL_RL2 BIT(5)
44 /* Status header is present from DMA to PMAC */
45 #define PMAC_HD_CTL_RXSH BIT(6)
46 /* Add special tag from PMAC to switch */
47 #define PMAC_HD_CTL_AST BIT(7)
48 /* Remove specail Tag from PMAC to DMA */
49 #define PMAC_HD_CTL_RST BIT(8)
50 /* Check CRC from DMA to PMAC */
51 #define PMAC_HD_CTL_CCRC BIT(9)
52 /* Enable reaction to Pause frames in the PMAC */
53 #define PMAC_HD_CTL_FC BIT(10)
58 struct napi_struct napi;
59 struct ltq_dma_channel dma;
60 struct sk_buff *skb[LTQ_DESC_NUM];
62 struct xrx200_priv *priv;
68 struct xrx200_chan chan_tx;
69 struct xrx200_chan chan_rx;
71 struct net_device *net_dev;
74 __iomem void *pmac_reg;
77 static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset)
79 return __raw_readl(priv->pmac_reg + offset);
82 static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset)
84 __raw_writel(val, priv->pmac_reg + offset);
87 static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set,
90 u32 val = xrx200_pmac_r32(priv, offset);
94 xrx200_pmac_w32(priv, val, offset);
97 /* drop all the packets from the DMA ring */
98 static void xrx200_flush_dma(struct xrx200_chan *ch)
102 for (i = 0; i < LTQ_DESC_NUM; i++) {
103 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
105 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
108 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
111 ch->dma.desc %= LTQ_DESC_NUM;
115 static int xrx200_open(struct net_device *net_dev)
117 struct xrx200_priv *priv = netdev_priv(net_dev);
119 napi_enable(&priv->chan_tx.napi);
120 ltq_dma_open(&priv->chan_tx.dma);
121 ltq_dma_enable_irq(&priv->chan_tx.dma);
123 napi_enable(&priv->chan_rx.napi);
124 ltq_dma_open(&priv->chan_rx.dma);
125 /* The boot loader does not always deactivate the receiving of frames
126 * on the ports and then some packets queue up in the PPE buffers.
127 * They already passed the PMAC so they do not have the tags
128 * configured here. Read the these packets here and drop them.
129 * The HW should have written them into memory after 10us
131 usleep_range(20, 40);
132 xrx200_flush_dma(&priv->chan_rx);
133 ltq_dma_enable_irq(&priv->chan_rx.dma);
135 netif_wake_queue(net_dev);
140 static int xrx200_close(struct net_device *net_dev)
142 struct xrx200_priv *priv = netdev_priv(net_dev);
144 netif_stop_queue(net_dev);
146 napi_disable(&priv->chan_rx.napi);
147 ltq_dma_close(&priv->chan_rx.dma);
149 napi_disable(&priv->chan_tx.napi);
150 ltq_dma_close(&priv->chan_tx.dma);
155 static int xrx200_alloc_skb(struct xrx200_chan *ch)
157 struct sk_buff *skb = ch->skb[ch->dma.desc];
161 ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev,
162 XRX200_DMA_DATA_LEN);
163 if (!ch->skb[ch->dma.desc]) {
168 mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data,
169 XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE);
170 if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) {
171 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
172 ch->skb[ch->dma.desc] = skb;
177 ch->dma.desc_base[ch->dma.desc].addr = mapping;
178 /* Make sure the address is written before we give it to HW */
181 ch->dma.desc_base[ch->dma.desc].ctl =
182 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
188 static int xrx200_hw_receive(struct xrx200_chan *ch)
190 struct xrx200_priv *priv = ch->priv;
191 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
192 struct sk_buff *skb = ch->skb[ch->dma.desc];
193 int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
194 struct net_device *net_dev = priv->net_dev;
197 ret = xrx200_alloc_skb(ch);
200 ch->dma.desc %= LTQ_DESC_NUM;
203 net_dev->stats.rx_dropped++;
204 netdev_err(net_dev, "failed to allocate new rx buffer\n");
209 skb->protocol = eth_type_trans(skb, net_dev);
210 netif_receive_skb(skb);
211 net_dev->stats.rx_packets++;
212 net_dev->stats.rx_bytes += len;
217 static int xrx200_poll_rx(struct napi_struct *napi, int budget)
219 struct xrx200_chan *ch = container_of(napi,
220 struct xrx200_chan, napi);
224 while (rx < budget) {
225 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
227 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
228 ret = xrx200_hw_receive(ch);
238 if (napi_complete_done(&ch->napi, rx))
239 ltq_dma_enable_irq(&ch->dma);
245 static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget)
247 struct xrx200_chan *ch = container_of(napi,
248 struct xrx200_chan, napi);
249 struct net_device *net_dev = ch->priv->net_dev;
253 netif_tx_lock(net_dev);
254 while (pkts < budget) {
255 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free];
257 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
258 struct sk_buff *skb = ch->skb[ch->tx_free];
262 ch->skb[ch->tx_free] = NULL;
264 memset(&ch->dma.desc_base[ch->tx_free], 0,
265 sizeof(struct ltq_dma_desc));
267 ch->tx_free %= LTQ_DESC_NUM;
273 net_dev->stats.tx_packets += pkts;
274 net_dev->stats.tx_bytes += bytes;
275 netdev_completed_queue(ch->priv->net_dev, pkts, bytes);
277 netif_tx_unlock(net_dev);
278 if (netif_queue_stopped(net_dev))
279 netif_wake_queue(net_dev);
282 if (napi_complete_done(&ch->napi, pkts))
283 ltq_dma_enable_irq(&ch->dma);
289 static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
290 struct net_device *net_dev)
292 struct xrx200_priv *priv = netdev_priv(net_dev);
293 struct xrx200_chan *ch = &priv->chan_tx;
294 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
300 if (skb_put_padto(skb, ETH_ZLEN)) {
301 net_dev->stats.tx_dropped++;
307 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
308 netdev_err(net_dev, "tx ring full\n");
309 netif_stop_queue(net_dev);
310 return NETDEV_TX_BUSY;
313 ch->skb[ch->dma.desc] = skb;
315 mapping = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
316 if (unlikely(dma_mapping_error(priv->dev, mapping)))
319 /* dma needs to start on a 16 byte aligned address */
320 byte_offset = mapping % 16;
322 desc->addr = mapping - byte_offset;
323 /* Make sure the address is written before we give it to HW */
325 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
326 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
328 ch->dma.desc %= LTQ_DESC_NUM;
329 if (ch->dma.desc == ch->tx_free)
330 netif_stop_queue(net_dev);
332 netdev_sent_queue(net_dev, len);
338 net_dev->stats.tx_dropped++;
339 net_dev->stats.tx_errors++;
343 static const struct net_device_ops xrx200_netdev_ops = {
344 .ndo_open = xrx200_open,
345 .ndo_stop = xrx200_close,
346 .ndo_start_xmit = xrx200_start_xmit,
347 .ndo_set_mac_address = eth_mac_addr,
348 .ndo_validate_addr = eth_validate_addr,
351 static irqreturn_t xrx200_dma_irq(int irq, void *ptr)
353 struct xrx200_chan *ch = ptr;
355 if (napi_schedule_prep(&ch->napi)) {
356 ltq_dma_disable_irq(&ch->dma);
357 __napi_schedule(&ch->napi);
360 ltq_dma_ack_irq(&ch->dma);
365 static int xrx200_dma_init(struct xrx200_priv *priv)
367 struct xrx200_chan *ch_rx = &priv->chan_rx;
368 struct xrx200_chan *ch_tx = &priv->chan_tx;
372 ltq_dma_init_port(DMA_PORT_ETOP);
374 ch_rx->dma.nr = XRX200_DMA_RX;
375 ch_rx->dma.dev = priv->dev;
378 ltq_dma_alloc_rx(&ch_rx->dma);
379 for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM;
381 ret = xrx200_alloc_skb(ch_rx);
386 ret = devm_request_irq(priv->dev, ch_rx->dma.irq, xrx200_dma_irq, 0,
387 "xrx200_net_rx", &priv->chan_rx);
389 dev_err(priv->dev, "failed to request RX irq %d\n",
394 ch_tx->dma.nr = XRX200_DMA_TX;
395 ch_tx->dma.dev = priv->dev;
398 ltq_dma_alloc_tx(&ch_tx->dma);
399 ret = devm_request_irq(priv->dev, ch_tx->dma.irq, xrx200_dma_irq, 0,
400 "xrx200_net_tx", &priv->chan_tx);
402 dev_err(priv->dev, "failed to request TX irq %d\n",
410 ltq_dma_free(&ch_tx->dma);
413 /* free the allocated RX ring */
414 for (i = 0; i < LTQ_DESC_NUM; i++) {
415 if (priv->chan_rx.skb[i])
416 dev_kfree_skb_any(priv->chan_rx.skb[i]);
420 ltq_dma_free(&ch_rx->dma);
424 static void xrx200_hw_cleanup(struct xrx200_priv *priv)
428 ltq_dma_free(&priv->chan_tx.dma);
429 ltq_dma_free(&priv->chan_rx.dma);
431 /* free the allocated RX ring */
432 for (i = 0; i < LTQ_DESC_NUM; i++)
433 dev_kfree_skb_any(priv->chan_rx.skb[i]);
436 static int xrx200_probe(struct platform_device *pdev)
438 struct device *dev = &pdev->dev;
439 struct device_node *np = dev->of_node;
440 struct resource *res;
441 struct xrx200_priv *priv;
442 struct net_device *net_dev;
446 /* alloc the network device */
447 net_dev = devm_alloc_etherdev(dev, sizeof(struct xrx200_priv));
451 priv = netdev_priv(net_dev);
452 priv->net_dev = net_dev;
455 net_dev->netdev_ops = &xrx200_netdev_ops;
456 SET_NETDEV_DEV(net_dev, dev);
457 net_dev->min_mtu = ETH_ZLEN;
458 net_dev->max_mtu = XRX200_DMA_DATA_LEN;
460 /* load the memory ranges */
461 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
463 dev_err(dev, "failed to get resources\n");
467 priv->pmac_reg = devm_ioremap_resource(dev, res);
468 if (IS_ERR(priv->pmac_reg)) {
469 dev_err(dev, "failed to request and remap io ranges\n");
470 return PTR_ERR(priv->pmac_reg);
473 priv->chan_rx.dma.irq = platform_get_irq_byname(pdev, "rx");
474 if (priv->chan_rx.dma.irq < 0)
476 priv->chan_tx.dma.irq = platform_get_irq_byname(pdev, "tx");
477 if (priv->chan_tx.dma.irq < 0)
481 priv->clk = devm_clk_get(dev, NULL);
482 if (IS_ERR(priv->clk)) {
483 dev_err(dev, "failed to get clock\n");
484 return PTR_ERR(priv->clk);
487 mac = of_get_mac_address(np);
489 ether_addr_copy(net_dev->dev_addr, mac);
491 eth_hw_addr_random(net_dev);
493 /* bring up the dma engine and IP core */
494 err = xrx200_dma_init(priv);
498 /* enable clock gate */
499 err = clk_prepare_enable(priv->clk);
504 xrx200_pmac_mask(priv, PMAC_RX_IPG_MASK, 0xb, PMAC_RX_IPG);
506 /* enable status header, enable CRC */
507 xrx200_pmac_mask(priv, 0,
508 PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH |
509 PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC,
513 netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32);
514 netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32);
516 platform_set_drvdata(pdev, priv);
518 err = register_netdev(net_dev);
520 goto err_unprepare_clk;
525 clk_disable_unprepare(priv->clk);
528 xrx200_hw_cleanup(priv);
533 static int xrx200_remove(struct platform_device *pdev)
535 struct xrx200_priv *priv = platform_get_drvdata(pdev);
536 struct net_device *net_dev = priv->net_dev;
538 /* free stack related instances */
539 netif_stop_queue(net_dev);
540 netif_napi_del(&priv->chan_tx.napi);
541 netif_napi_del(&priv->chan_rx.napi);
543 /* remove the actual device */
544 unregister_netdev(net_dev);
546 /* release the clock */
547 clk_disable_unprepare(priv->clk);
549 /* shut down hardware */
550 xrx200_hw_cleanup(priv);
555 static const struct of_device_id xrx200_match[] = {
556 { .compatible = "lantiq,xrx200-net" },
559 MODULE_DEVICE_TABLE(of, xrx200_match);
561 static struct platform_driver xrx200_driver = {
562 .probe = xrx200_probe,
563 .remove = xrx200_remove,
565 .name = "lantiq,xrx200-net",
566 .of_match_table = xrx200_match,
570 module_platform_driver(xrx200_driver);
572 MODULE_AUTHOR("John Crispin <john@phrozen.org>");
573 MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
574 MODULE_LICENSE("GPL");