1 /*******************************************************************************
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *******************************************************************************/
30 #include <linux/types.h>
31 #include <linux/bitops.h>
32 #include <linux/timer.h>
34 #include <linux/netdevice.h>
35 #include <linux/if_vlan.h>
36 #include <linux/u64_stats_sync.h>
40 #ifdef CONFIG_NET_RX_BUSY_POLL
41 #include <net/busy_poll.h>
42 #define BP_EXTENDED_STATS
45 #define IXGBE_MAX_TXD_PWR 14
46 #define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR)
48 /* Tx Descriptors needed, worst case */
49 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
50 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
52 /* wrapper around a pointer to a socket buffer,
53 * so a DMA handle can be stored along with the buffer
55 struct ixgbevf_tx_buffer {
56 union ixgbe_adv_tx_desc *next_to_watch;
57 unsigned long time_stamp;
59 unsigned int bytecount;
60 unsigned short gso_segs;
62 DEFINE_DMA_UNMAP_ADDR(dma);
63 DEFINE_DMA_UNMAP_LEN(len);
67 struct ixgbevf_rx_buffer {
70 unsigned int page_offset;
73 struct ixgbevf_stats {
76 #ifdef BP_EXTENDED_STATS
83 struct ixgbevf_tx_queue_stats {
89 struct ixgbevf_rx_queue_stats {
90 u64 alloc_rx_page_failed;
91 u64 alloc_rx_buff_failed;
95 enum ixgbevf_ring_state_t {
96 __IXGBEVF_TX_DETECT_HANG,
97 __IXGBEVF_HANG_CHECK_ARMED,
100 #define check_for_tx_hang(ring) \
101 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
102 #define set_check_for_tx_hang(ring) \
103 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
104 #define clear_check_for_tx_hang(ring) \
105 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
107 struct ixgbevf_ring {
108 struct ixgbevf_ring *next;
109 struct net_device *netdev;
111 void *desc; /* descriptor ring memory */
112 dma_addr_t dma; /* phys. address of descriptor ring */
113 unsigned int size; /* length in bytes */
114 u16 count; /* amount of descriptors */
120 struct ixgbevf_tx_buffer *tx_buffer_info;
121 struct ixgbevf_rx_buffer *rx_buffer_info;
124 struct ixgbevf_stats stats;
125 struct u64_stats_sync syncp;
127 struct ixgbevf_tx_queue_stats tx_stats;
128 struct ixgbevf_rx_queue_stats rx_stats;
131 u64 hw_csum_rx_error;
135 /* holds the special value that gets the hardware register offset
136 * associated with this ring, which is different for DCB and RSS modes
139 int queue_index; /* needed for multiqueue queue management */
142 /* How many Rx Buffers do we bundle into one write to the hardware ? */
143 #define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
145 #define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
146 #define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
147 #define IXGBEVF_MAX_RSS_QUEUES 2
148 #define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */
149 #define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */
150 #define IXGBEVF_RSS_HASH_KEY_SIZE 40
151 #define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */
153 #define IXGBEVF_DEFAULT_TXD 1024
154 #define IXGBEVF_DEFAULT_RXD 512
155 #define IXGBEVF_MAX_TXD 4096
156 #define IXGBEVF_MIN_TXD 64
157 #define IXGBEVF_MAX_RXD 4096
158 #define IXGBEVF_MIN_RXD 64
160 /* Supported Rx Buffer Sizes */
161 #define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
162 #define IXGBEVF_RXBUFFER_2048 2048
164 #define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
165 #define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048
167 #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
169 #define IXGBE_TX_FLAGS_CSUM BIT(0)
170 #define IXGBE_TX_FLAGS_VLAN BIT(1)
171 #define IXGBE_TX_FLAGS_TSO BIT(2)
172 #define IXGBE_TX_FLAGS_IPV4 BIT(3)
173 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
174 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
175 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
177 struct ixgbevf_ring_container {
178 struct ixgbevf_ring *ring; /* pointer to linked list of rings */
179 unsigned int total_bytes; /* total bytes processed this int */
180 unsigned int total_packets; /* total packets processed this int */
181 u8 count; /* total number of rings in vector */
182 u8 itr; /* current ITR setting for ring */
185 /* iterator for handling rings in ring container */
186 #define ixgbevf_for_each_ring(pos, head) \
187 for (pos = (head).ring; pos != NULL; pos = pos->next)
189 /* MAX_MSIX_Q_VECTORS of these are allocated,
190 * but we only use one per queue-specific vector.
192 struct ixgbevf_q_vector {
193 struct ixgbevf_adapter *adapter;
194 /* index of q_vector within array, also used for finding the bit in
195 * EICR and friends that represents the vector for this ring
198 u16 itr; /* Interrupt throttle rate written to EITR */
199 struct napi_struct napi;
200 struct ixgbevf_ring_container rx, tx;
201 char name[IFNAMSIZ + 9];
202 #ifdef CONFIG_NET_RX_BUSY_POLL
204 #define IXGBEVF_QV_STATE_IDLE 0
205 #define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
206 #define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
207 #define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
208 #define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
209 #define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
210 #define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
211 #define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
212 #define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \
213 IXGBEVF_QV_STATE_POLL_YIELD)
214 #define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \
215 IXGBEVF_QV_STATE_POLL_YIELD)
217 #endif /* CONFIG_NET_RX_BUSY_POLL */
220 #ifdef CONFIG_NET_RX_BUSY_POLL
221 static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
223 spin_lock_init(&q_vector->lock);
224 q_vector->state = IXGBEVF_QV_STATE_IDLE;
227 /* called from the device poll routine to get ownership of a q_vector */
228 static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
232 spin_lock_bh(&q_vector->lock);
233 if (q_vector->state & IXGBEVF_QV_LOCKED) {
234 WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
235 q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD;
237 #ifdef BP_EXTENDED_STATS
238 q_vector->tx.ring->stats.yields++;
241 /* we don't care if someone yielded */
242 q_vector->state = IXGBEVF_QV_STATE_NAPI;
244 spin_unlock_bh(&q_vector->lock);
248 /* returns true is someone tried to get the qv while napi had it */
249 static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
253 spin_lock_bh(&q_vector->lock);
254 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL |
255 IXGBEVF_QV_STATE_NAPI_YIELD));
257 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
259 /* reset state to idle, unless QV is disabled */
260 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
261 spin_unlock_bh(&q_vector->lock);
265 /* called from ixgbevf_low_latency_poll() */
266 static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
270 spin_lock_bh(&q_vector->lock);
271 if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
272 q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD;
274 #ifdef BP_EXTENDED_STATS
275 q_vector->rx.ring->stats.yields++;
278 /* preserve yield marks */
279 q_vector->state |= IXGBEVF_QV_STATE_POLL;
281 spin_unlock_bh(&q_vector->lock);
285 /* returns true if someone tried to get the qv while it was locked */
286 static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
290 spin_lock_bh(&q_vector->lock);
291 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));
293 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
295 /* reset state to idle, unless QV is disabled */
296 q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
297 spin_unlock_bh(&q_vector->lock);
301 /* true if a socket is polling, even if it did not get the lock */
302 static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
304 WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
305 return q_vector->state & IXGBEVF_QV_USER_PEND;
308 /* false if QV is currently owned */
309 static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
313 spin_lock_bh(&q_vector->lock);
314 if (q_vector->state & IXGBEVF_QV_OWNED)
316 q_vector->state |= IXGBEVF_QV_STATE_DISABLED;
317 spin_unlock_bh(&q_vector->lock);
321 #endif /* CONFIG_NET_RX_BUSY_POLL */
323 /* microsecond values for various ITR rates shifted by 2 to fit itr register
324 * with the first 3 bits reserved 0
326 #define IXGBE_MIN_RSC_ITR 24
327 #define IXGBE_100K_ITR 40
328 #define IXGBE_20K_ITR 200
329 #define IXGBE_12K_ITR 336
331 /* Helper macros to switch between ints/sec and what the register uses.
332 * And yes, it's the same math going both ways. The lowest value
333 * supported by all of the ixgbe hardware is 8.
335 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
336 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
337 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
339 /* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
340 static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
341 const u32 stat_err_bits)
343 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
346 static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
348 u16 ntc = ring->next_to_clean;
349 u16 ntu = ring->next_to_use;
351 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
354 static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
356 writel(value, ring->tail);
359 #define IXGBEVF_RX_DESC(R, i) \
360 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
361 #define IXGBEVF_TX_DESC(R, i) \
362 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
363 #define IXGBEVF_TX_CTXTDESC(R, i) \
364 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
366 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
368 #define OTHER_VECTOR 1
369 #define NON_Q_VECTORS (OTHER_VECTOR)
371 #define MAX_MSIX_Q_VECTORS 2
373 #define MIN_MSIX_Q_VECTORS 1
374 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
376 /* board specific private data structure */
377 struct ixgbevf_adapter {
378 /* this field must be first, see ixgbevf_process_skb_fields */
379 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
381 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
383 /* Interrupt Throttle Rate */
387 /* interrupt masks */
388 u32 eims_enable_mask;
393 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
395 u32 tx_timeout_count;
399 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
400 u64 hw_csum_rx_error;
401 u64 hw_rx_no_dma_resources;
402 int num_msix_vectors;
403 u32 alloc_rx_page_failed;
404 u32 alloc_rx_buff_failed;
406 struct msix_entry *msix_entries;
408 /* OS defined structs */
409 struct net_device *netdev;
410 struct pci_dev *pdev;
412 /* structs defined in ixgbe_vf.h */
415 /* Interrupt Throttle Rate */
418 struct ixgbevf_hw_stats stats;
422 unsigned int tx_ring_count;
423 unsigned int rx_ring_count;
425 u8 __iomem *io_addr; /* Mainly for iounmap use */
429 struct timer_list service_timer;
430 struct work_struct service_task;
433 unsigned long last_reset;
435 u32 rss_key[IXGBEVF_VFRSSRK_REGS];
436 u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
439 enum ixbgevf_state_t {
445 __IXGBEVF_SERVICE_SCHED,
446 __IXGBEVF_SERVICE_INITED,
447 __IXGBEVF_RESET_REQUESTED,
448 __IXGBEVF_QUEUE_RESET_REQUESTED,
451 enum ixgbevf_boards {
459 board_X550EM_x_vf_hv,
463 enum ixgbevf_xcast_modes {
464 IXGBEVF_XCAST_MODE_NONE = 0,
465 IXGBEVF_XCAST_MODE_MULTI,
466 IXGBEVF_XCAST_MODE_ALLMULTI,
469 extern const struct ixgbevf_info ixgbevf_82599_vf_info;
470 extern const struct ixgbevf_info ixgbevf_X540_vf_info;
471 extern const struct ixgbevf_info ixgbevf_X550_vf_info;
472 extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
473 extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
474 extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info;
476 extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info;
477 extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info;
478 extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info;
479 extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info;
480 extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops;
482 /* needed by ethtool.c */
483 extern const char ixgbevf_driver_name[];
484 extern const char ixgbevf_driver_version[];
486 int ixgbevf_open(struct net_device *netdev);
487 int ixgbevf_close(struct net_device *netdev);
488 void ixgbevf_up(struct ixgbevf_adapter *adapter);
489 void ixgbevf_down(struct ixgbevf_adapter *adapter);
490 void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
491 void ixgbevf_reset(struct ixgbevf_adapter *adapter);
492 void ixgbevf_set_ethtool_ops(struct net_device *netdev);
493 int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
494 int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
495 void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
496 void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
497 void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
498 int ethtool_ioctl(struct ifreq *ifr);
500 extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
502 void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
503 void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
505 #define ixgbevf_hw_to_netdev(hw) \
506 (((struct ixgbevf_adapter *)(hw)->back)->netdev)
508 #define hw_dbg(hw, format, arg...) \
509 netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg)
510 #endif /* _IXGBEVF_H_ */