1 /*******************************************************************************
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 1999 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
18 * Contact Information:
19 * Linux NICS <linux.nics@intel.com>
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 ******************************************************************************/
24 #include "ixgbe_x540.h"
25 #include "ixgbe_type.h"
26 #include "ixgbe_common.h"
27 #include "ixgbe_phy.h"
29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
37 struct ixgbe_mac_info *mac = &hw->mac;
38 struct ixgbe_phy_info *phy = &hw->phy;
39 struct ixgbe_link_info *link = &hw->link;
41 /* Start with X540 invariants, since so simular */
42 ixgbe_get_invariants_X540(hw);
44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
45 phy->ops.set_phy_power = NULL;
47 link->addr = IXGBE_CS4227;
52 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
54 struct ixgbe_phy_info *phy = &hw->phy;
56 /* Start with X540 invariants, since so similar */
57 ixgbe_get_invariants_X540(hw);
59 phy->ops.set_phy_power = NULL;
64 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
66 struct ixgbe_mac_info *mac = &hw->mac;
67 struct ixgbe_phy_info *phy = &hw->phy;
69 /* Start with X540 invariants, since so simular */
70 ixgbe_get_invariants_X540(hw);
72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
73 phy->ops.set_phy_power = NULL;
78 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
80 struct ixgbe_phy_info *phy = &hw->phy;
82 /* Start with X540 invariants, since so similar */
83 ixgbe_get_invariants_X540(hw);
85 phy->ops.set_phy_power = NULL;
90 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
91 * @hw: pointer to hardware structure
93 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
99 esdp |= IXGBE_ESDP_SDP1_DIR;
101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
103 IXGBE_WRITE_FLUSH(hw);
107 * ixgbe_read_cs4227 - Read CS4227 register
108 * @hw: pointer to hardware structure
109 * @reg: register number to write
110 * @value: pointer to receive value read
112 * Returns status code
114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
120 * ixgbe_write_cs4227 - Write CS4227 register
121 * @hw: pointer to hardware structure
122 * @reg: register number to write
123 * @value: value to write to register
125 * Returns status code
127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
133 * ixgbe_read_pe - Read register from port expander
134 * @hw: pointer to hardware structure
135 * @reg: register number to read
136 * @value: pointer to receive read value
138 * Returns status code
140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
146 hw_err(hw, "port expander access failed with %d\n", status);
151 * ixgbe_write_pe - Write register to port expander
152 * @hw: pointer to hardware structure
153 * @reg: register number to write
154 * @value: value to write
156 * Returns status code
158 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
165 hw_err(hw, "port expander access failed with %d\n", status);
170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
171 * @hw: pointer to hardware structure
173 * This function assumes that the caller has acquired the proper semaphore.
176 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
183 /* Trigger hard reset. */
184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
187 reg |= IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 reg &= ~IXGBE_PE_BIT1;
204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
213 reg |= IXGBE_PE_BIT1;
214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
218 /* Wait for the reset to complete. */
219 msleep(IXGBE_CS4227_RESET_DELAY);
220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
225 msleep(IXGBE_CS4227_CHECK_DELAY);
227 if (retry == IXGBE_CS4227_RETRIES) {
228 hw_err(hw, "CS4227 reset did not complete\n");
229 return IXGBE_ERR_PHY;
232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
234 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
235 return IXGBE_ERR_PHY;
242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
243 * @hw: pointer to hardware structure
245 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
247 u32 swfw_mask = hw->phy.phy_semaphore_mask;
252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
255 hw_err(hw, "semaphore failed with %d\n", status);
256 msleep(IXGBE_CS4227_CHECK_DELAY);
260 /* Get status of reset flow. */
261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
265 if (status || value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msleep(IXGBE_CS4227_CHECK_DELAY);
272 /* If still pending, assume other instance failed. */
273 if (retry == IXGBE_CS4227_RETRIES) {
274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 hw_err(hw, "semaphore failed with %d\n", status);
281 /* Reset the CS4227. */
282 status = ixgbe_reset_cs4227(hw);
284 hw_err(hw, "CS4227 reset failed: %d", status);
288 /* Reset takes so long, temporarily release semaphore in case the
289 * other driver instance is waiting for the reset indication.
291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
292 IXGBE_CS4227_RESET_PENDING);
293 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
294 usleep_range(10000, 12000);
295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
297 hw_err(hw, "semaphore failed with %d", status);
301 /* Record completion for next time. */
302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
303 IXGBE_CS4227_RESET_COMPLETE);
306 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
307 msleep(hw->eeprom.semaphore_delay);
310 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
311 * @hw: pointer to hardware structure
315 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
317 switch (hw->device_id) {
318 case IXGBE_DEV_ID_X550EM_A_SFP:
320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
323 return ixgbe_identify_module_generic(hw);
324 case IXGBE_DEV_ID_X550EM_X_SFP:
325 /* set up for CS4227 usage */
326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
327 ixgbe_setup_mux_ctl(hw);
328 ixgbe_check_cs4227(hw);
330 case IXGBE_DEV_ID_X550EM_A_SFP_N:
331 return ixgbe_identify_module_generic(hw);
332 case IXGBE_DEV_ID_X550EM_X_KX4:
333 hw->phy.type = ixgbe_phy_x550em_kx4;
335 case IXGBE_DEV_ID_X550EM_X_XFI:
336 hw->phy.type = ixgbe_phy_x550em_xfi;
338 case IXGBE_DEV_ID_X550EM_X_KR:
339 case IXGBE_DEV_ID_X550EM_A_KR:
340 case IXGBE_DEV_ID_X550EM_A_KR_L:
341 hw->phy.type = ixgbe_phy_x550em_kr;
343 case IXGBE_DEV_ID_X550EM_A_10G_T:
345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
349 case IXGBE_DEV_ID_X550EM_X_10G_T:
350 return ixgbe_identify_phy_generic(hw);
351 case IXGBE_DEV_ID_X550EM_X_1G_T:
352 hw->phy.type = ixgbe_phy_ext_1g_t;
354 case IXGBE_DEV_ID_X550EM_A_1G_T:
355 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
356 hw->phy.type = ixgbe_phy_fw;
357 hw->phy.ops.read_reg = NULL;
358 hw->phy.ops.write_reg = NULL;
360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
370 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
371 u32 device_type, u16 *phy_data)
373 return IXGBE_NOT_IMPLEMENTED;
376 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
377 u32 device_type, u16 phy_data)
379 return IXGBE_NOT_IMPLEMENTED;
383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
384 * @hw: pointer to the hardware structure
385 * @addr: I2C bus address to read from
386 * @reg: I2C device register to read from
387 * @val: pointer to location to receive read value
389 * Returns an error code on error.
391 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
399 * @hw: pointer to the hardware structure
400 * @addr: I2C bus address to read from
401 * @reg: I2C device register to read from
402 * @val: pointer to location to receive read value
404 * Returns an error code on error.
407 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
415 * @hw: pointer to the hardware structure
416 * @addr: I2C bus address to write to
417 * @reg: I2C device register to write to
418 * @val: value to write
420 * Returns an error code on error.
422 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
423 u8 addr, u16 reg, u16 val)
425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
430 * @hw: pointer to the hardware structure
431 * @addr: I2C bus address to write to
432 * @reg: I2C device register to write to
433 * @val: value to write
435 * Returns an error code on error.
438 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
439 u8 addr, u16 reg, u16 val)
441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
445 * ixgbe_fw_phy_activity - Perform an activity on a PHY
446 * @hw: pointer to hardware structure
447 * @activity: activity to perform
448 * @data: Pointer to 4 32-bit words of data
450 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
451 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
454 struct ixgbe_hic_phy_activity_req cmd;
455 struct ixgbe_hic_phy_activity_resp rsp;
457 u16 retries = FW_PHY_ACT_RETRIES;
462 memset(&hic, 0, sizeof(hic));
463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
466 hic.cmd.port_number = hw->bus.lan_id;
467 hic.cmd.activity_id = cpu_to_le16(activity);
468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
469 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
472 IXGBE_HI_COMMAND_TIMEOUT,
476 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
477 FW_CEM_RESP_STATUS_SUCCESS) {
478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
482 usleep_range(20, 30);
484 } while (retries > 0);
486 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
489 static const struct {
491 ixgbe_link_speed phy_speed;
493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
503 * @hw: pointer to hardware structure
507 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
522 hw->phy.speeds_supported = 0;
523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
525 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
534 return IXGBE_ERR_PHY_ADDR_INVALID;
536 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
538 IXGBE_LINK_SPEED_1GB_FULL;
539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
545 * @hw: pointer to hardware structure
549 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
556 hw->phy.type = ixgbe_phy_fw;
557 hw->phy.ops.read_reg = NULL;
558 hw->phy.ops.write_reg = NULL;
559 return ixgbe_get_phy_id_fw(hw);
563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
564 * @hw: pointer to hardware structure
568 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
578 * @hw: pointer to hardware structure
580 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
591 return IXGBE_ERR_INVALID_LINK_SETTINGS;
594 switch (hw->fc.requested_mode) {
596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
599 case ixgbe_fc_rx_pause:
600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
603 case ixgbe_fc_tx_pause:
604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
613 setup[0] |= ixgbe_fw_map[i].fw_speed;
615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
617 if (hw->phy.eee_speeds_advertised)
618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
624 return IXGBE_ERR_OVERTEMP;
629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
630 * @hw: pointer to hardware structure
632 * Called at init time to set up flow control.
634 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
636 if (hw->fc.requested_mode == ixgbe_fc_default)
637 hw->fc.requested_mode = ixgbe_fc_full;
639 return ixgbe_setup_fw_link(hw);
642 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
643 * @hw: pointer to hardware structure
645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
646 * ixgbe_hw struct in order to set up EEPROM access.
648 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
654 if (eeprom->type == ixgbe_eeprom_uninitialized) {
655 eeprom->semaphore_delay = 10;
656 eeprom->type = ixgbe_flash;
658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
660 IXGBE_EEC_SIZE_SHIFT);
661 eeprom->word_size = BIT(eeprom_size +
662 IXGBE_EEPROM_WORD_SIZE_SHIFT);
664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
665 eeprom->type, eeprom->word_size);
672 * ixgbe_iosf_wait - Wait for IOSF command completion
673 * @hw: pointer to hardware structure
674 * @ctrl: pointer to location to receive final IOSF control value
676 * Return: failing status on timeout
678 * Note: ctrl can be NULL if the IOSF control register value is not needed
680 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
684 /* Check every 10 usec to see if the address cycle completed.
685 * The SB IOSF BUSY bit will clear when the operation is
688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
697 hw_dbg(hw, "IOSF wait timed out\n");
698 return IXGBE_ERR_PHY;
704 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
706 * @hw: pointer to hardware structure
707 * @reg_addr: 32 bit PHY register to write
708 * @device_type: 3 bit device type
709 * @phy_data: Pointer to read data from the register
711 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
712 u32 device_type, u32 *data)
714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
722 ret = ixgbe_iosf_wait(hw, NULL);
726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
729 /* Write IOSF control register */
730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
732 ret = ixgbe_iosf_wait(hw, &command);
734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
737 hw_dbg(hw, "Failed to read, error %x\n", error);
738 return IXGBE_ERR_PHY;
742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
745 hw->mac.ops.release_swfw_sync(hw, gssr);
750 * ixgbe_get_phy_token - Get the token for shared PHY access
751 * @hw: Pointer to hardware structure
753 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
755 struct ixgbe_hic_phy_token_req token_cmd;
758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
762 token_cmd.port_number = hw->bus.lan_id;
763 token_cmd.command_type = FW_PHY_TOKEN_REQ;
765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
766 IXGBE_HI_COMMAND_TIMEOUT,
770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
773 return IXGBE_ERR_FW_RESP_INVALID;
775 return IXGBE_ERR_TOKEN_RETRY;
779 * ixgbe_put_phy_token - Put the token for shared PHY access
780 * @hw: Pointer to hardware structure
782 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
784 struct ixgbe_hic_phy_token_req token_cmd;
787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
791 token_cmd.port_number = hw->bus.lan_id;
792 token_cmd.command_type = FW_PHY_TOKEN_REL;
794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
795 IXGBE_HI_COMMAND_TIMEOUT,
799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
801 return IXGBE_ERR_FW_RESP_INVALID;
805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
806 * @hw: pointer to hardware structure
807 * @reg_addr: 32 bit PHY register to write
808 * @device_type: 3 bit device type
809 * @data: Data to write to the register
811 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
812 __always_unused u32 device_type,
815 struct ixgbe_hic_internal_phy_req write_cmd;
817 memset(&write_cmd, 0, sizeof(write_cmd));
818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
821 write_cmd.port_number = hw->bus.lan_id;
822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
823 write_cmd.address = cpu_to_be16(reg_addr);
824 write_cmd.write_data = cpu_to_be32(data);
826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
827 IXGBE_HI_COMMAND_TIMEOUT, false);
831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
832 * @hw: pointer to hardware structure
833 * @reg_addr: 32 bit PHY register to write
834 * @device_type: 3 bit device type
835 * @data: Pointer to read data from the register
837 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
838 __always_unused u32 device_type,
842 struct ixgbe_hic_internal_phy_req cmd;
843 struct ixgbe_hic_internal_phy_resp rsp;
847 memset(&hic, 0, sizeof(hic));
848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
851 hic.cmd.port_number = hw->bus.lan_id;
852 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
853 hic.cmd.address = cpu_to_be16(reg_addr);
855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
856 IXGBE_HI_COMMAND_TIMEOUT, true);
858 /* Extract the register value from the response. */
859 *data = be32_to_cpu(hic.rsp.read_data);
864 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
865 * @hw: pointer to hardware structure
866 * @offset: offset of word in the EEPROM to read
867 * @words: number of words
868 * @data: word(s) read from the EEPROM
870 * Reads a 16 bit word(s) from the EEPROM using the hostif.
872 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
873 u16 offset, u16 words, u16 *data)
875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
876 struct ixgbe_hic_read_shadow_ram buffer;
877 u32 current_word = 0;
882 /* Take semaphore for the entire operation. */
883 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
890 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
893 words_to_read = words;
895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
896 buffer.hdr.req.buf_lenh = 0;
897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
900 /* convert offset from words to bytes */
901 buffer.address = cpu_to_be32((offset + current_word) * 2);
902 buffer.length = cpu_to_be16(words_to_read * 2);
906 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
907 IXGBE_HI_COMMAND_TIMEOUT);
909 hw_dbg(hw, "Host interface command failed\n");
913 for (i = 0; i < words_to_read; i++) {
914 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
916 u32 value = IXGBE_READ_REG(hw, reg);
918 data[current_word] = (u16)(value & 0xffff);
921 if (i < words_to_read) {
923 data[current_word] = (u16)(value & 0xffff);
927 words -= words_to_read;
931 hw->mac.ops.release_swfw_sync(hw, mask);
935 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
936 * @hw: pointer to hardware structure
937 * @ptr: pointer offset in eeprom
938 * @size: size of section pointed by ptr, if 0 first word will be used as size
939 * @csum: address of checksum to update
941 * Returns error status for any failure
943 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
944 u16 size, u16 *csum, u16 *buffer,
949 u16 length, bufsz, i, start;
952 bufsz = sizeof(buf) / sizeof(buf[0]);
954 /* Read a chunk at the pointer location */
956 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
958 hw_dbg(hw, "Failed to read EEPROM image\n");
963 if (buffer_size < ptr)
964 return IXGBE_ERR_PARAM;
965 local_buffer = &buffer[ptr];
973 length = local_buffer[0];
975 /* Skip pointer section if length is invalid. */
976 if (length == 0xFFFF || length == 0 ||
977 (ptr + length) >= hw->eeprom.word_size)
981 if (buffer && ((u32)start + (u32)length > buffer_size))
982 return IXGBE_ERR_PARAM;
984 for (i = start; length; i++, length--) {
985 if (i == bufsz && !buffer) {
991 /* Read a chunk at the pointer location */
992 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
995 hw_dbg(hw, "Failed to read EEPROM image\n");
999 *csum += local_buffer[i];
1004 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
1005 * @hw: pointer to hardware structure
1006 * @buffer: pointer to buffer containing calculated checksum
1007 * @buffer_size: size of buffer
1009 * Returns a negative error code on error, or the 16-bit checksum
1011 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
1014 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1018 u16 pointer, i, size;
1020 hw->eeprom.ops.init_params(hw);
1023 /* Read pointer area */
1024 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1025 IXGBE_EEPROM_LAST_WORD + 1,
1028 hw_dbg(hw, "Failed to read EEPROM image\n");
1031 local_buffer = eeprom_ptrs;
1033 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1034 return IXGBE_ERR_PARAM;
1035 local_buffer = buffer;
1038 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1039 * checksum word itself
1041 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1042 if (i != IXGBE_EEPROM_CHECKSUM)
1043 checksum += local_buffer[i];
1045 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1046 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1048 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1049 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1052 pointer = local_buffer[i];
1054 /* Skip pointer section if the pointer is invalid. */
1055 if (pointer == 0xFFFF || pointer == 0 ||
1056 pointer >= hw->eeprom.word_size)
1060 case IXGBE_PCIE_GENERAL_PTR:
1061 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1063 case IXGBE_PCIE_CONFIG0_PTR:
1064 case IXGBE_PCIE_CONFIG1_PTR:
1065 size = IXGBE_PCIE_CONFIG_SIZE;
1072 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1073 buffer, buffer_size);
1078 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1080 return (s32)checksum;
1083 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1084 * @hw: pointer to hardware structure
1086 * Returns a negative error code on error, or the 16-bit checksum
1088 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1090 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1093 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1094 * @hw: pointer to hardware structure
1095 * @offset: offset of word in the EEPROM to read
1096 * @data: word read from the EEPROM
1098 * Reads a 16 bit word from the EEPROM using the hostif.
1100 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1102 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1103 struct ixgbe_hic_read_shadow_ram buffer;
1106 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1107 buffer.hdr.req.buf_lenh = 0;
1108 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1109 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1111 /* convert offset from words to bytes */
1112 buffer.address = cpu_to_be32(offset * 2);
1114 buffer.length = cpu_to_be16(sizeof(u16));
1116 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1120 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1121 IXGBE_HI_COMMAND_TIMEOUT);
1123 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1124 FW_NVM_DATA_OFFSET);
1127 hw->mac.ops.release_swfw_sync(hw, mask);
1131 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1132 * @hw: pointer to hardware structure
1133 * @checksum_val: calculated checksum
1135 * Performs checksum calculation and validates the EEPROM checksum. If the
1136 * caller does not need checksum_val, the value can be NULL.
1138 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1143 u16 read_checksum = 0;
1145 /* Read the first word from the EEPROM. If this times out or fails, do
1146 * not continue or we could be in for a very long wait while every
1149 status = hw->eeprom.ops.read(hw, 0, &checksum);
1151 hw_dbg(hw, "EEPROM read failed\n");
1155 status = hw->eeprom.ops.calc_checksum(hw);
1159 checksum = (u16)(status & 0xffff);
1161 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1166 /* Verify read checksum from EEPROM is the same as
1167 * calculated checksum
1169 if (read_checksum != checksum) {
1170 status = IXGBE_ERR_EEPROM_CHECKSUM;
1171 hw_dbg(hw, "Invalid EEPROM checksum");
1174 /* If the user cares, return the calculated checksum */
1176 *checksum_val = checksum;
1181 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1182 * @hw: pointer to hardware structure
1183 * @offset: offset of word in the EEPROM to write
1184 * @data: word write to the EEPROM
1186 * Write a 16 bit word to the EEPROM using the hostif.
1188 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1192 struct ixgbe_hic_write_shadow_ram buffer;
1194 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1195 buffer.hdr.req.buf_lenh = 0;
1196 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1197 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1200 buffer.length = cpu_to_be16(sizeof(u16));
1202 buffer.address = cpu_to_be32(offset * 2);
1204 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1205 IXGBE_HI_COMMAND_TIMEOUT, false);
1209 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1210 * @hw: pointer to hardware structure
1211 * @offset: offset of word in the EEPROM to write
1212 * @data: word write to the EEPROM
1214 * Write a 16 bit word to the EEPROM using the hostif.
1216 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1220 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1221 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1222 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1224 hw_dbg(hw, "write ee hostif failed to get semaphore");
1225 status = IXGBE_ERR_SWFW_SYNC;
1231 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1232 * @hw: pointer to hardware structure
1234 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1236 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1239 union ixgbe_hic_hdr2 buffer;
1241 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1242 buffer.req.buf_lenh = 0;
1243 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1244 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1246 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1247 IXGBE_HI_COMMAND_TIMEOUT, false);
1252 * ixgbe_get_bus_info_X550em - Set PCI bus info
1253 * @hw: pointer to hardware structure
1255 * Sets bus link width and speed to unknown because X550em is
1258 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1260 hw->bus.type = ixgbe_bus_type_internal;
1261 hw->bus.width = ixgbe_bus_width_unknown;
1262 hw->bus.speed = ixgbe_bus_speed_unknown;
1264 hw->mac.ops.set_lan_id(hw);
1269 /** ixgbe_disable_rx_x550 - Disable RX unit
1271 * Enables the Rx DMA unit for x550
1273 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1275 u32 rxctrl, pfdtxgswc;
1277 struct ixgbe_hic_disable_rxen fw_cmd;
1279 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1280 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1281 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1282 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1283 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1284 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1285 hw->mac.set_lben = true;
1287 hw->mac.set_lben = false;
1290 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1291 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1292 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1293 fw_cmd.port_number = hw->bus.lan_id;
1295 status = ixgbe_host_interface_command(hw, &fw_cmd,
1296 sizeof(struct ixgbe_hic_disable_rxen),
1297 IXGBE_HI_COMMAND_TIMEOUT, true);
1299 /* If we fail - disable RX using register write */
1301 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1302 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1303 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1304 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1310 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1311 * @hw: pointer to hardware structure
1313 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1314 * checksum and updates the EEPROM and instructs the hardware to update
1317 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1322 /* Read the first word from the EEPROM. If this times out or fails, do
1323 * not continue or we could be in for a very long wait while every
1326 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1328 hw_dbg(hw, "EEPROM read failed\n");
1332 status = ixgbe_calc_eeprom_checksum_X550(hw);
1336 checksum = (u16)(status & 0xffff);
1338 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1343 status = ixgbe_update_flash_X550(hw);
1348 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1349 * @hw: pointer to hardware structure
1350 * @offset: offset of word in the EEPROM to write
1351 * @words: number of words
1352 * @data: word(s) write to the EEPROM
1355 * Write a 16 bit word(s) to the EEPROM using the hostif.
1357 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1358 u16 offset, u16 words,
1364 /* Take semaphore for the entire operation. */
1365 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1367 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1371 for (i = 0; i < words; i++) {
1372 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1375 hw_dbg(hw, "Eeprom buffered write failed\n");
1380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1385 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1388 * @hw: pointer to hardware structure
1389 * @reg_addr: 32 bit PHY register to write
1390 * @device_type: 3 bit device type
1391 * @data: Data to write to the register
1393 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1394 u32 device_type, u32 data)
1396 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1400 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1404 ret = ixgbe_iosf_wait(hw, NULL);
1408 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1409 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1411 /* Write IOSF control register */
1412 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1414 /* Write IOSF data register */
1415 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1417 ret = ixgbe_iosf_wait(hw, &command);
1419 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1420 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1421 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1422 hw_dbg(hw, "Failed to write, error %x\n", error);
1423 return IXGBE_ERR_PHY;
1427 hw->mac.ops.release_swfw_sync(hw, gssr);
1432 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1433 * @hw: pointer to hardware structure
1435 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1437 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1442 /* Disable training protocol FSM. */
1443 status = ixgbe_read_iosf_sb_reg_x550(hw,
1444 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1445 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1449 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1450 status = ixgbe_write_iosf_sb_reg_x550(hw,
1451 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1452 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1456 /* Disable Flex from training TXFFE. */
1457 status = ixgbe_read_iosf_sb_reg_x550(hw,
1458 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1459 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1464 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1465 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1466 status = ixgbe_write_iosf_sb_reg_x550(hw,
1467 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1468 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1472 status = ixgbe_read_iosf_sb_reg_x550(hw,
1473 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1474 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1479 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1480 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1481 status = ixgbe_write_iosf_sb_reg_x550(hw,
1482 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1483 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1487 /* Enable override for coefficients. */
1488 status = ixgbe_read_iosf_sb_reg_x550(hw,
1489 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1490 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1496 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1497 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1498 status = ixgbe_write_iosf_sb_reg_x550(hw,
1499 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1500 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1505 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1507 * @hw: pointer to hardware structure
1509 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1514 /* Restart auto-negotiation. */
1515 status = hw->mac.ops.read_iosf_sb_reg(hw,
1516 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1517 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1520 hw_dbg(hw, "Auto-negotiation did not complete\n");
1524 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1525 status = hw->mac.ops.write_iosf_sb_reg(hw,
1526 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1527 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1529 if (hw->mac.type == ixgbe_mac_x550em_a) {
1532 /* Indicate to FW that AN restart has been asserted */
1533 status = hw->mac.ops.read_iosf_sb_reg(hw,
1534 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1535 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1538 hw_dbg(hw, "Auto-negotiation did not complete\n");
1542 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1543 status = hw->mac.ops.write_iosf_sb_reg(hw,
1544 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1545 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1551 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1552 * @hw: pointer to hardware structure
1553 * @speed: the link speed to force
1555 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1556 * internal and external PHY at a specific speed, without autonegotiation.
1558 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1560 struct ixgbe_mac_info *mac = &hw->mac;
1564 /* iXFI is only supported with X552 */
1565 if (mac->type != ixgbe_mac_X550EM_x)
1566 return IXGBE_ERR_LINK_SETUP;
1568 /* Disable AN and force speed to 10G Serial. */
1569 status = ixgbe_read_iosf_sb_reg_x550(hw,
1570 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1571 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1575 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1576 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1578 /* Select forced link speed for internal PHY. */
1580 case IXGBE_LINK_SPEED_10GB_FULL:
1581 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1583 case IXGBE_LINK_SPEED_1GB_FULL:
1584 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1587 /* Other link speeds are not supported by internal KR PHY. */
1588 return IXGBE_ERR_LINK_SETUP;
1591 status = ixgbe_write_iosf_sb_reg_x550(hw,
1592 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1593 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1597 /* Additional configuration needed for x550em_x */
1598 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1599 status = ixgbe_setup_ixfi_x550em_x(hw);
1604 /* Toggle port SW reset by AN reset. */
1605 status = ixgbe_restart_an_internal_phy_x550em(hw);
1611 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1612 * @hw: pointer to hardware structure
1613 * @linear: true if SFP module is linear
1615 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1617 switch (hw->phy.sfp_type) {
1618 case ixgbe_sfp_type_not_present:
1619 return IXGBE_ERR_SFP_NOT_PRESENT;
1620 case ixgbe_sfp_type_da_cu_core0:
1621 case ixgbe_sfp_type_da_cu_core1:
1624 case ixgbe_sfp_type_srlr_core0:
1625 case ixgbe_sfp_type_srlr_core1:
1626 case ixgbe_sfp_type_da_act_lmt_core0:
1627 case ixgbe_sfp_type_da_act_lmt_core1:
1628 case ixgbe_sfp_type_1g_sx_core0:
1629 case ixgbe_sfp_type_1g_sx_core1:
1630 case ixgbe_sfp_type_1g_lx_core0:
1631 case ixgbe_sfp_type_1g_lx_core1:
1634 case ixgbe_sfp_type_unknown:
1635 case ixgbe_sfp_type_1g_cu_core0:
1636 case ixgbe_sfp_type_1g_cu_core1:
1638 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1645 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1646 * @hw: pointer to hardware structure
1648 * Configures the extern PHY and the integrated KR PHY for SFP support.
1651 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1652 ixgbe_link_speed speed,
1653 __always_unused bool autoneg_wait_to_complete)
1656 u16 reg_slice, reg_val;
1657 bool setup_linear = false;
1659 /* Check if SFP module is supported and linear */
1660 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1662 /* If no SFP module present, then return success. Return success since
1663 * there is no reason to configure CS4227 and SFP not present error is
1664 * not accepted in the setup MAC link flow.
1666 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1672 /* Configure internal PHY for KR/KX. */
1673 ixgbe_setup_kr_speed_x550em(hw, speed);
1675 /* Configure CS4227 LINE side to proper mode. */
1676 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1678 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1680 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1682 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1689 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1690 * @hw: pointer to hardware structure
1691 * @speed: the link speed to force
1693 * Configures the integrated PHY for native SFI mode. Used to connect the
1694 * internal PHY directly to an SFP cage, without autonegotiation.
1696 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1698 struct ixgbe_mac_info *mac = &hw->mac;
1702 /* Disable all AN and force speed to 10G Serial. */
1703 status = mac->ops.read_iosf_sb_reg(hw,
1704 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1705 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1712 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1714 /* Select forced link speed for internal PHY. */
1716 case IXGBE_LINK_SPEED_10GB_FULL:
1717 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1719 case IXGBE_LINK_SPEED_1GB_FULL:
1720 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1723 /* Other link speeds are not supported by internal PHY. */
1724 return IXGBE_ERR_LINK_SETUP;
1727 status = mac->ops.write_iosf_sb_reg(hw,
1728 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1729 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1731 /* Toggle port SW reset by AN reset. */
1732 status = ixgbe_restart_an_internal_phy_x550em(hw);
1738 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1739 * @hw: pointer to hardware structure
1741 * Configure the the integrated PHY for native SFP support.
1744 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1745 __always_unused bool autoneg_wait_to_complete)
1747 bool setup_linear = false;
1751 /* Check if SFP module is supported and linear */
1752 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1754 /* If no SFP module present, then return success. Return success since
1755 * SFP not present error is not excepted in the setup MAC link flow.
1757 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1763 /* Configure internal PHY for native SFI based on module type */
1764 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1765 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1766 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1770 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1772 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1774 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1775 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1776 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1780 /* Setup SFI internal link. */
1781 return ixgbe_setup_sfi_x550a(hw, &speed);
1785 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1786 * @hw: pointer to hardware structure
1788 * Configure the the integrated PHY for SFP support.
1791 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1792 __always_unused bool autoneg_wait_to_complete)
1794 u32 reg_slice, slice_offset;
1795 bool setup_linear = false;
1799 /* Check if SFP module is supported and linear */
1800 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1802 /* If no SFP module present, then return success. Return success since
1803 * SFP not present error is not excepted in the setup MAC link flow.
1805 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1811 /* Configure internal PHY for KR/KX. */
1812 ixgbe_setup_kr_speed_x550em(hw, speed);
1814 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1815 return IXGBE_ERR_PHY_ADDR_INVALID;
1817 /* Get external PHY SKU id */
1818 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1819 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1823 /* When configuring quad port CS4223, the MAC instance is part
1824 * of the slice offset.
1826 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1827 slice_offset = (hw->bus.lan_id +
1828 (hw->bus.instance_id << 1)) << 12;
1830 slice_offset = hw->bus.lan_id << 12;
1832 /* Configure CS4227/CS4223 LINE side to proper mode. */
1833 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1835 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1836 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1840 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1841 (IXGBE_CS4227_EDC_MODE_SR << 1));
1844 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1846 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1848 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1849 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1853 /* Flush previous write with a read */
1854 return hw->phy.ops.read_reg(hw, reg_slice,
1855 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1859 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1860 * @hw: pointer to hardware structure
1861 * @speed: new link speed
1862 * @autoneg_wait_to_complete: true when waiting for completion is needed
1864 * Setup internal/external PHY link speed based on link speed, then set
1865 * external PHY auto advertised link speed.
1867 * Returns error status for any failure
1869 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1870 ixgbe_link_speed speed,
1874 ixgbe_link_speed force_speed;
1876 /* Setup internal/external PHY link speed to iXFI (10G), unless
1877 * only 1G is auto advertised then setup KX link.
1879 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1880 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1882 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1884 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1886 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1887 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1888 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1894 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1897 /** ixgbe_check_link_t_X550em - Determine link and speed status
1898 * @hw: pointer to hardware structure
1899 * @speed: pointer to link speed
1900 * @link_up: true when link is up
1901 * @link_up_wait_to_complete: bool used to wait for link up or not
1903 * Check that both the MAC and X557 external PHY have link.
1905 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1906 ixgbe_link_speed *speed,
1908 bool link_up_wait_to_complete)
1911 u16 i, autoneg_status;
1913 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1914 return IXGBE_ERR_CONFIG;
1916 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1917 link_up_wait_to_complete);
1919 /* If check link fails or MAC link is not up, then return */
1920 if (status || !(*link_up))
1923 /* MAC link is up, so check external PHY link.
1924 * Link status is latching low, and can only be used to detect link
1925 * drop, and not the current status of the link without performing
1926 * back-to-back reads.
1928 for (i = 0; i < 2; i++) {
1929 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1936 /* If external PHY link is not up, then indicate link not up */
1937 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1944 * ixgbe_setup_sgmii - Set up link for sgmii
1945 * @hw: pointer to hardware structure
1948 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1949 __always_unused bool autoneg_wait_to_complete)
1951 struct ixgbe_mac_info *mac = &hw->mac;
1952 u32 lval, sval, flx_val;
1955 rc = mac->ops.read_iosf_sb_reg(hw,
1956 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1957 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1961 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1962 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1963 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1964 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1965 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1966 rc = mac->ops.write_iosf_sb_reg(hw,
1967 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1968 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1972 rc = mac->ops.read_iosf_sb_reg(hw,
1973 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1974 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1978 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1979 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1980 rc = mac->ops.write_iosf_sb_reg(hw,
1981 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1982 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1986 rc = mac->ops.read_iosf_sb_reg(hw,
1987 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1988 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1992 rc = mac->ops.read_iosf_sb_reg(hw,
1993 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1994 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1998 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1999 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2000 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2001 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2002 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2004 rc = mac->ops.write_iosf_sb_reg(hw,
2005 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2006 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2010 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2015 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2016 * @hw: pointer to hardware structure
2018 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2021 struct ixgbe_mac_info *mac = &hw->mac;
2022 u32 lval, sval, flx_val;
2025 rc = mac->ops.read_iosf_sb_reg(hw,
2026 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2027 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2031 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2032 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2033 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2034 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2035 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2036 rc = mac->ops.write_iosf_sb_reg(hw,
2037 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2038 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2042 rc = mac->ops.read_iosf_sb_reg(hw,
2043 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2044 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2048 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2049 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2050 rc = mac->ops.write_iosf_sb_reg(hw,
2051 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2052 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2056 rc = mac->ops.write_iosf_sb_reg(hw,
2057 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2058 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2062 rc = mac->ops.read_iosf_sb_reg(hw,
2063 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2064 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2068 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2069 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2070 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2071 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2072 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2074 rc = mac->ops.write_iosf_sb_reg(hw,
2075 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2076 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2080 ixgbe_restart_an_internal_phy_x550em(hw);
2082 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2086 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2087 * @hw: pointer to hardware structure
2089 * Enable flow control according to IEEE clause 37.
2091 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2093 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2094 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2095 ixgbe_link_speed speed;
2098 /* AN should have completed when the cable was plugged in.
2099 * Look for reasons to bail out. Bail out if:
2100 * - FC autoneg is disabled, or if
2103 if (hw->fc.disable_fc_autoneg)
2106 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2110 /* Check if auto-negotiation has completed */
2111 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2112 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2113 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2117 /* Negotiate the flow control */
2118 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2119 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2120 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2121 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2122 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2126 hw->fc.fc_was_autonegged = true;
2128 hw->fc.fc_was_autonegged = false;
2129 hw->fc.current_mode = hw->fc.requested_mode;
2133 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2134 * @hw: pointer to hardware structure
2136 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2138 struct ixgbe_mac_info *mac = &hw->mac;
2140 switch (mac->ops.get_media_type(hw)) {
2141 case ixgbe_media_type_fiber:
2142 mac->ops.setup_fc = NULL;
2143 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2145 case ixgbe_media_type_copper:
2146 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2147 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2148 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2151 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2152 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2153 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2154 mac->ops.check_link = ixgbe_check_mac_link_generic;
2156 case ixgbe_media_type_backplane:
2157 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2158 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2165 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2166 * @hw: pointer to hardware structure
2168 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2170 struct ixgbe_mac_info *mac = &hw->mac;
2172 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2174 switch (mac->ops.get_media_type(hw)) {
2175 case ixgbe_media_type_fiber:
2176 /* CS4227 does not support autoneg, so disable the laser control
2177 * functions for SFP+ fiber
2179 mac->ops.disable_tx_laser = NULL;
2180 mac->ops.enable_tx_laser = NULL;
2181 mac->ops.flap_tx_laser = NULL;
2182 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2183 switch (hw->device_id) {
2184 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2185 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2187 case IXGBE_DEV_ID_X550EM_A_SFP:
2188 mac->ops.setup_mac_link =
2189 ixgbe_setup_mac_link_sfp_x550a;
2192 mac->ops.setup_mac_link =
2193 ixgbe_setup_mac_link_sfp_x550em;
2196 mac->ops.set_rate_select_speed =
2197 ixgbe_set_soft_rate_select_speed;
2199 case ixgbe_media_type_copper:
2200 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2202 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2203 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2204 mac->ops.check_link = ixgbe_check_link_t_X550em;
2206 case ixgbe_media_type_backplane:
2207 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2208 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2209 mac->ops.setup_link = ixgbe_setup_sgmii;
2215 /* Additional modification for X550em_a devices */
2216 if (hw->mac.type == ixgbe_mac_x550em_a)
2217 ixgbe_init_mac_link_ops_X550em_a(hw);
2220 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2221 * @hw: pointer to hardware structure
2223 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2228 /* Check if SFP module is supported */
2229 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2233 ixgbe_init_mac_link_ops_X550em(hw);
2234 hw->phy.ops.reset = NULL;
2239 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2240 * @hw: pointer to hardware structure
2241 * @speed: pointer to link speed
2242 * @autoneg: true when autoneg or autotry is enabled
2244 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2245 ixgbe_link_speed *speed,
2248 if (hw->phy.type == ixgbe_phy_fw) {
2250 *speed = hw->phy.speeds_supported;
2255 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2256 /* CS4227 SFP must not enable auto-negotiation */
2259 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2260 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2261 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2262 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2263 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2267 /* Link capabilities are based on SFP */
2268 if (hw->phy.multispeed_fiber)
2269 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2270 IXGBE_LINK_SPEED_1GB_FULL;
2272 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2274 switch (hw->phy.type) {
2275 case ixgbe_phy_x550em_kx4:
2276 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2277 IXGBE_LINK_SPEED_2_5GB_FULL |
2278 IXGBE_LINK_SPEED_10GB_FULL;
2280 case ixgbe_phy_x550em_xfi:
2281 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2282 IXGBE_LINK_SPEED_10GB_FULL;
2284 case ixgbe_phy_ext_1g_t:
2285 case ixgbe_phy_sgmii:
2286 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2288 case ixgbe_phy_x550em_kr:
2289 if (hw->mac.type == ixgbe_mac_x550em_a) {
2290 /* check different backplane modes */
2291 if (hw->phy.nw_mng_if_sel &
2292 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2293 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2295 } else if (hw->device_id ==
2296 IXGBE_DEV_ID_X550EM_A_KR_L) {
2297 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2303 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2304 IXGBE_LINK_SPEED_1GB_FULL;
2313 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2314 * @hw: pointer to hardware structure
2315 * @lsc: pointer to boolean flag which indicates whether external Base T
2316 * PHY interrupt is lsc
2318 * Determime if external Base T PHY interrupt cause is high temperature
2319 * failure alarm or link status change.
2321 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2322 * failure alarm, else return PHY access status.
2324 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
2331 /* Vendor alarm triggered */
2332 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2336 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2339 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2344 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2345 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2348 /* Global alarm triggered */
2349 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2356 /* If high temperature failure, then return over temp error and exit */
2357 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2358 /* power down the PHY in case the PHY FW didn't already */
2359 ixgbe_set_copper_phy_power(hw, false);
2360 return IXGBE_ERR_OVERTEMP;
2362 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2363 /* device fault alarm triggered */
2364 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2370 /* if device fault was due to high temp alarm handle and exit */
2371 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2372 /* power down the PHY in case the PHY FW didn't */
2373 ixgbe_set_copper_phy_power(hw, false);
2374 return IXGBE_ERR_OVERTEMP;
2378 /* Vendor alarm 2 triggered */
2379 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2382 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2385 /* link connect/disconnect event occurred */
2386 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2393 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2400 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2401 * @hw: pointer to hardware structure
2403 * Enable link status change and temperature failure alarm for the external
2406 * Returns PHY access status
2408 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2414 /* Clear interrupt flags */
2415 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2417 /* Enable link status change alarm */
2419 /* Enable the LASI interrupts on X552 devices to receive notifications
2420 * of the link configurations of the external PHY and correspondingly
2421 * support the configuration of the internal iXFI link, since iXFI does
2422 * not support auto-negotiation. This is not required for X553 devices
2423 * having KR support, which performs auto-negotiations and which is used
2424 * as the internal link to the external PHY. Hence adding a check here
2425 * to avoid enabling LASI interrupts for X553 devices.
2427 if (hw->mac.type != ixgbe_mac_x550em_a) {
2428 status = hw->phy.ops.read_reg(hw,
2429 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2434 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2436 status = hw->phy.ops.write_reg(hw,
2437 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2443 /* Enable high temperature failure and global fault alarms */
2444 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2450 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2451 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2453 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2459 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2460 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2466 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2467 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2469 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2475 /* Enable chip-wide vendor alarm */
2476 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2482 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2484 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2492 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2493 * @hw: pointer to hardware structure
2495 * Handle external Base T PHY interrupt. If high temperature
2496 * failure alarm then return error, else if link status change
2497 * then setup internal/external PHY link
2499 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2500 * failure alarm, else return PHY access status.
2502 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2504 struct ixgbe_phy_info *phy = &hw->phy;
2508 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2512 if (lsc && phy->ops.setup_internal_link)
2513 return phy->ops.setup_internal_link(hw);
2519 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2520 * @hw: pointer to hardware structure
2521 * @speed: link speed
2523 * Configures the integrated KR PHY.
2525 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2526 ixgbe_link_speed speed)
2531 status = hw->mac.ops.read_iosf_sb_reg(hw,
2532 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2533 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2537 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2538 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2539 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2541 /* Advertise 10G support. */
2542 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2543 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2545 /* Advertise 1G support. */
2546 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2547 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2549 status = hw->mac.ops.write_iosf_sb_reg(hw,
2550 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2551 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2553 if (hw->mac.type == ixgbe_mac_x550em_a) {
2554 /* Set lane mode to KR auto negotiation */
2555 status = hw->mac.ops.read_iosf_sb_reg(hw,
2556 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2557 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2562 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2563 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2564 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2565 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2566 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2568 status = hw->mac.ops.write_iosf_sb_reg(hw,
2569 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2570 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2573 return ixgbe_restart_an_internal_phy_x550em(hw);
2577 * ixgbe_setup_kr_x550em - Configure the KR PHY
2578 * @hw: pointer to hardware structure
2580 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2582 /* leave link alone for 2.5G */
2583 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2586 if (ixgbe_check_reset_blocked(hw))
2589 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2592 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2593 * @hw: address of hardware structure
2594 * @link_up: address of boolean to indicate link status
2596 * Returns error code if unable to get link status.
2598 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2605 /* read this twice back to back to indicate current status */
2606 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2611 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2616 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2621 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2622 * @hw: point to hardware structure
2624 * Configures the link between the integrated KR PHY and the external X557 PHY
2625 * The driver will call this function when it gets a link status change
2626 * interrupt from the X557 PHY. This function configures the link speed
2627 * between the PHYs to match the link speed of the BASE-T link.
2629 * A return of a non-zero value indicates an error, and the base driver should
2630 * not report link up.
2632 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2634 ixgbe_link_speed force_speed;
2639 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2640 return IXGBE_ERR_CONFIG;
2642 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2643 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2644 speed = IXGBE_LINK_SPEED_10GB_FULL |
2645 IXGBE_LINK_SPEED_1GB_FULL;
2646 return ixgbe_setup_kr_speed_x550em(hw, speed);
2649 /* If link is not up, then there is no setup necessary so return */
2650 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2657 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2663 /* If link is not still up, then no setup is necessary so return */
2664 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2671 /* clear everything but the speed and duplex bits */
2672 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2675 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2676 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2678 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2679 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2682 /* Internal PHY does not support anything else */
2683 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2686 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2689 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2690 * @hw: pointer to hardware structure
2692 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2696 status = ixgbe_reset_phy_generic(hw);
2701 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2702 return ixgbe_enable_lasi_ext_t_x550em(hw);
2706 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2707 * @hw: pointer to hardware structure
2708 * @led_idx: led number to turn on
2710 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2714 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2715 return IXGBE_ERR_PARAM;
2717 /* To turn on the LED, set mode to ON. */
2718 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2719 MDIO_MMD_VEND1, &phy_data);
2720 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2721 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2722 MDIO_MMD_VEND1, phy_data);
2728 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2729 * @hw: pointer to hardware structure
2730 * @led_idx: led number to turn off
2732 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2736 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2737 return IXGBE_ERR_PARAM;
2739 /* To turn on the LED, set mode to ON. */
2740 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2741 MDIO_MMD_VEND1, &phy_data);
2742 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2743 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2744 MDIO_MMD_VEND1, phy_data);
2750 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2751 * @hw: pointer to the HW structure
2752 * @maj: driver version major number
2753 * @min: driver version minor number
2754 * @build: driver version build number
2755 * @sub: driver version sub build number
2756 * @len: length of driver_ver string
2757 * @driver_ver: driver string
2759 * Sends driver version number to firmware through the manageability
2760 * block. On success return 0
2761 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
2762 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
2764 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2765 u8 build, u8 sub, u16 len,
2766 const char *driver_ver)
2768 struct ixgbe_hic_drv_info2 fw_cmd;
2772 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2773 return IXGBE_ERR_INVALID_ARGUMENT;
2775 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2776 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2777 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2778 fw_cmd.port_num = (u8)hw->bus.func;
2779 fw_cmd.ver_maj = maj;
2780 fw_cmd.ver_min = min;
2781 fw_cmd.ver_build = build;
2782 fw_cmd.ver_sub = sub;
2783 fw_cmd.hdr.checksum = 0;
2784 memcpy(fw_cmd.driver_string, driver_ver, len);
2785 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2786 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2788 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2789 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2791 IXGBE_HI_COMMAND_TIMEOUT,
2796 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2797 FW_CEM_RESP_STATUS_SUCCESS)
2798 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
2805 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2806 * @hw: pointer to hardware structure
2807 * @lcd_speed: pointer to lowest common link speed
2809 * Determine lowest common link speed with link partner.
2811 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2812 ixgbe_link_speed *lcd_speed)
2816 u16 word = hw->eeprom.ctrl_word_3;
2818 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2820 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2826 /* If link partner advertised 1G, return 1G */
2827 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2828 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2832 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2833 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2834 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2837 /* Link partner not capable of lower speeds, return 10G */
2838 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2843 * ixgbe_setup_fc_x550em - Set up flow control
2844 * @hw: pointer to hardware structure
2846 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2848 bool pause, asm_dir;
2852 /* Validate the requested mode */
2853 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2854 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2855 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2858 /* 10gig parts do not have a word in the EEPROM to determine the
2859 * default flow control setting, so we explicitly set it to full.
2861 if (hw->fc.requested_mode == ixgbe_fc_default)
2862 hw->fc.requested_mode = ixgbe_fc_full;
2864 /* Determine PAUSE and ASM_DIR bits. */
2865 switch (hw->fc.requested_mode) {
2870 case ixgbe_fc_tx_pause:
2874 case ixgbe_fc_rx_pause:
2875 /* Rx Flow control is enabled and Tx Flow control is
2876 * disabled by software override. Since there really
2877 * isn't a way to advertise that we are capable of RX
2878 * Pause ONLY, we will advertise that we support both
2879 * symmetric and asymmetric Rx PAUSE, as such we fall
2880 * through to the fc_full statement. Later, we will
2881 * disable the adapter's ability to send PAUSE frames.
2889 hw_err(hw, "Flow control param set incorrectly\n");
2890 return IXGBE_ERR_CONFIG;
2893 switch (hw->device_id) {
2894 case IXGBE_DEV_ID_X550EM_X_KR:
2895 case IXGBE_DEV_ID_X550EM_A_KR:
2896 case IXGBE_DEV_ID_X550EM_A_KR_L:
2897 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2898 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2899 IXGBE_SB_IOSF_TARGET_KR_PHY,
2904 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2905 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2907 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2909 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2910 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2911 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2912 IXGBE_SB_IOSF_TARGET_KR_PHY,
2915 /* This device does not fully support AN. */
2916 hw->fc.disable_fc_autoneg = true;
2918 case IXGBE_DEV_ID_X550EM_X_XFI:
2919 hw->fc.disable_fc_autoneg = true;
2928 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2929 * @hw: pointer to hardware structure
2931 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2933 u32 link_s1, lp_an_page_low, an_cntl_1;
2934 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2935 ixgbe_link_speed speed;
2938 /* AN should have completed when the cable was plugged in.
2939 * Look for reasons to bail out. Bail out if:
2940 * - FC autoneg is disabled, or if
2943 if (hw->fc.disable_fc_autoneg) {
2944 hw_err(hw, "Flow control autoneg is disabled");
2948 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2950 hw_err(hw, "The link is down");
2954 /* Check at auto-negotiation has completed */
2955 status = hw->mac.ops.read_iosf_sb_reg(hw,
2956 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2957 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2959 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2960 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2961 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2965 /* Read the 10g AN autoc and LP ability registers and resolve
2966 * local flow control settings accordingly
2968 status = hw->mac.ops.read_iosf_sb_reg(hw,
2969 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2970 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2973 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2977 status = hw->mac.ops.read_iosf_sb_reg(hw,
2978 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2979 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2982 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2986 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2987 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2988 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2989 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2990 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
2994 hw->fc.fc_was_autonegged = true;
2996 hw->fc.fc_was_autonegged = false;
2997 hw->fc.current_mode = hw->fc.requested_mode;
3002 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3003 * @hw: pointer to hardware structure
3005 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3007 hw->fc.fc_was_autonegged = false;
3008 hw->fc.current_mode = hw->fc.requested_mode;
3011 /** ixgbe_enter_lplu_x550em - Transition to low power states
3012 * @hw: pointer to hardware structure
3014 * Configures Low Power Link Up on transition to low power states
3015 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3016 * the X557 PHY immediately prior to entering LPLU.
3018 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3020 u16 an_10g_cntl_reg, autoneg_reg, speed;
3022 ixgbe_link_speed lcd_speed;
3026 /* If blocked by MNG FW, then don't restart AN */
3027 if (ixgbe_check_reset_blocked(hw))
3030 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3034 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3035 &hw->eeprom.ctrl_word_3);
3039 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3040 * manageability disabled, then force link down by entering
3043 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3044 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3045 return ixgbe_set_copper_phy_power(hw, false);
3048 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3052 /* If no valid LCD link speed, then force link down and exit. */
3053 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3054 return ixgbe_set_copper_phy_power(hw, false);
3056 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3062 /* If no link now, speed is invalid so take link down */
3063 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3065 return ixgbe_set_copper_phy_power(hw, false);
3067 /* clear everything but the speed bits */
3068 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3070 /* If current speed is already LCD, then exit. */
3071 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3072 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3073 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3074 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3077 /* Clear AN completed indication */
3078 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3084 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3090 status = hw->phy.ops.read_reg(hw,
3091 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3097 save_autoneg = hw->phy.autoneg_advertised;
3099 /* Setup link at least common link speed */
3100 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3102 /* restore autoneg from before setting lplu speed */
3103 hw->phy.autoneg_advertised = save_autoneg;
3109 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3110 * @hw: pointer to hardware structure
3112 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3114 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3117 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3120 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3123 memset(store, 0, sizeof(store));
3125 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3129 return ixgbe_setup_fw_link(hw);
3133 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3134 * @hw: pointer to hardware structure
3136 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3138 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3141 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3145 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3146 ixgbe_shutdown_fw_phy(hw);
3147 return IXGBE_ERR_OVERTEMP;
3153 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3154 * @hw: pointer to hardware structure
3156 * Read NW_MNG_IF_SEL register and save field values.
3158 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3160 /* Save NW management interface connected on board. This is used
3161 * to determine internal PHY mode.
3163 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3165 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3166 * PHY address. This register field was has only been used for X552.
3168 if (hw->mac.type == ixgbe_mac_x550em_a &&
3169 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3170 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
3171 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
3172 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
3176 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3177 * @hw: pointer to hardware structure
3179 * Initialize any function pointers that were not able to be
3180 * set during init_shared_code because the PHY/SFP type was
3181 * not known. Perform the SFP init if necessary.
3183 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3185 struct ixgbe_phy_info *phy = &hw->phy;
3188 hw->mac.ops.set_lan_id(hw);
3190 ixgbe_read_mng_if_sel_x550em(hw);
3192 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3193 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3194 ixgbe_setup_mux_ctl(hw);
3197 /* Identify the PHY or SFP module */
3198 ret_val = phy->ops.identify(hw);
3200 /* Setup function pointers based on detected hardware */
3201 ixgbe_init_mac_link_ops_X550em(hw);
3202 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3203 phy->ops.reset = NULL;
3205 /* Set functions pointers based on phy type */
3206 switch (hw->phy.type) {
3207 case ixgbe_phy_x550em_kx4:
3208 phy->ops.setup_link = NULL;
3209 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3210 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3212 case ixgbe_phy_x550em_kr:
3213 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3214 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3215 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3217 case ixgbe_phy_x550em_xfi:
3218 /* link is managed by HW */
3219 phy->ops.setup_link = NULL;
3220 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3221 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3223 case ixgbe_phy_x550em_ext_t:
3224 /* Save NW management interface connected on board. This is used
3225 * to determine internal PHY mode
3227 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3229 /* If internal link mode is XFI, then setup iXFI internal link,
3230 * else setup KR now.
3232 phy->ops.setup_internal_link =
3233 ixgbe_setup_internal_phy_t_x550em;
3235 /* setup SW LPLU only for first revision */
3236 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3237 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3238 IXGBE_FUSES0_REV_MASK))
3239 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3241 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3242 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3244 case ixgbe_phy_sgmii:
3245 phy->ops.setup_link = NULL;
3248 phy->ops.setup_link = ixgbe_setup_fw_link;
3249 phy->ops.reset = ixgbe_reset_phy_fw;
3251 case ixgbe_phy_ext_1g_t:
3252 phy->ops.setup_link = NULL;
3253 phy->ops.read_reg = NULL;
3254 phy->ops.write_reg = NULL;
3255 phy->ops.reset = NULL;
3264 /** ixgbe_get_media_type_X550em - Get media type
3265 * @hw: pointer to hardware structure
3267 * Returns the media type (fiber, copper, backplane)
3270 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3272 enum ixgbe_media_type media_type;
3274 /* Detect if there is a copper PHY attached. */
3275 switch (hw->device_id) {
3276 case IXGBE_DEV_ID_X550EM_A_SGMII:
3277 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3278 hw->phy.type = ixgbe_phy_sgmii;
3280 case IXGBE_DEV_ID_X550EM_X_KR:
3281 case IXGBE_DEV_ID_X550EM_X_KX4:
3282 case IXGBE_DEV_ID_X550EM_X_XFI:
3283 case IXGBE_DEV_ID_X550EM_A_KR:
3284 case IXGBE_DEV_ID_X550EM_A_KR_L:
3285 media_type = ixgbe_media_type_backplane;
3287 case IXGBE_DEV_ID_X550EM_X_SFP:
3288 case IXGBE_DEV_ID_X550EM_A_SFP:
3289 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3290 media_type = ixgbe_media_type_fiber;
3292 case IXGBE_DEV_ID_X550EM_X_1G_T:
3293 case IXGBE_DEV_ID_X550EM_X_10G_T:
3294 case IXGBE_DEV_ID_X550EM_A_10G_T:
3295 case IXGBE_DEV_ID_X550EM_A_1G_T:
3296 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3297 media_type = ixgbe_media_type_copper;
3300 media_type = ixgbe_media_type_unknown;
3306 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3307 ** @hw: pointer to hardware structure
3309 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3314 status = hw->phy.ops.read_reg(hw,
3315 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3321 /* If PHY FW reset completed bit is set then this is the first
3322 * SW instance after a power on so the PHY FW must be un-stalled.
3324 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3325 status = hw->phy.ops.read_reg(hw,
3326 IXGBE_MDIO_GLOBAL_RES_PR_10,
3332 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3334 status = hw->phy.ops.write_reg(hw,
3335 IXGBE_MDIO_GLOBAL_RES_PR_10,
3346 * ixgbe_set_mdio_speed - Set MDIO clock speed
3347 * @hw: pointer to hardware structure
3349 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3353 switch (hw->device_id) {
3354 case IXGBE_DEV_ID_X550EM_X_10G_T:
3355 case IXGBE_DEV_ID_X550EM_A_SGMII:
3356 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3357 case IXGBE_DEV_ID_X550EM_A_10G_T:
3358 case IXGBE_DEV_ID_X550EM_A_SFP:
3359 /* Config MDIO clock speed before the first MDIO PHY access */
3360 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3361 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3362 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3364 case IXGBE_DEV_ID_X550EM_A_1G_T:
3365 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3366 /* Select fast MDIO clock speed for these devices */
3367 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3368 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3369 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3376 /** ixgbe_reset_hw_X550em - Perform hardware reset
3377 ** @hw: pointer to hardware structure
3379 ** Resets the hardware by resetting the transmit and receive units, masks
3380 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3383 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3385 ixgbe_link_speed link_speed;
3389 bool link_up = false;
3390 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3392 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3393 status = hw->mac.ops.stop_adapter(hw);
3397 /* flush pending Tx transactions */
3398 ixgbe_clear_tx_pending(hw);
3400 /* set MDIO speed before talking to the PHY in case it's the 1st time */
3401 ixgbe_set_mdio_speed(hw);
3403 /* PHY ops must be identified and initialized prior to reset */
3405 /* Identify PHY and related function pointers */
3406 status = hw->phy.ops.init(hw);
3408 /* start the external PHY */
3409 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3410 status = ixgbe_init_ext_t_x550em(hw);
3415 /* Setup SFP module if there is one present. */
3416 if (hw->phy.sfp_setup_needed) {
3417 status = hw->mac.ops.setup_sfp(hw);
3418 hw->phy.sfp_setup_needed = false;
3421 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
3425 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3426 hw->phy.ops.reset(hw);
3429 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3430 * If link reset is used when link is up, it might reset the PHY when
3431 * mng is using it. If link is down or the flag to force full link
3432 * reset is set, then perform link reset.
3434 ctrl = IXGBE_CTRL_LNK_RST;
3436 if (!hw->force_full_reset) {
3437 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3439 ctrl = IXGBE_CTRL_RST;
3442 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3444 hw_dbg(hw, "semaphore failed with %d", status);
3445 return IXGBE_ERR_SWFW_SYNC;
3448 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3449 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3450 IXGBE_WRITE_FLUSH(hw);
3451 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3452 usleep_range(1000, 1200);
3454 /* Poll for reset bit to self-clear meaning reset is complete */
3455 for (i = 0; i < 10; i++) {
3456 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3457 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3462 if (ctrl & IXGBE_CTRL_RST_MASK) {
3463 status = IXGBE_ERR_RESET_FAILED;
3464 hw_dbg(hw, "Reset polling failed to complete.\n");
3469 /* Double resets are required for recovery from certain error
3470 * clear the multicast table. Also reset num_rar_entries to 128,
3471 * since we modify this value when programming the SAN MAC address.
3473 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3474 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3478 /* Store the permanent mac address */
3479 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3481 /* Store MAC address from RAR0, clear receive address registers, and
3482 * clear the multicast table. Also reset num_rar_entries to 128,
3483 * since we modify this value when programming the SAN MAC address.
3485 hw->mac.num_rar_entries = 128;
3486 hw->mac.ops.init_rx_addrs(hw);
3488 ixgbe_set_mdio_speed(hw);
3490 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3491 ixgbe_setup_mux_ctl(hw);
3496 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3498 * @hw: pointer to hardware structure
3499 * @enable: enable or disable switch for Ethertype anti-spoofing
3500 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3502 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3503 bool enable, int vf)
3505 int vf_target_reg = vf >> 3;
3506 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3509 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3511 pfvfspoof |= BIT(vf_target_shift);
3513 pfvfspoof &= ~BIT(vf_target_shift);
3515 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3518 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3519 * @hw: pointer to hardware structure
3520 * @enable: enable or disable source address pruning
3521 * @pool: Rx pool to set source address pruning for
3523 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3529 /* max rx pool is 63 */
3533 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3534 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3537 pfflp |= (1ULL << pool);
3539 pfflp &= ~(1ULL << pool);
3541 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3542 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3546 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3547 * @hw: pointer to hardware structure
3549 * Called at init time to set up flow control.
3551 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3556 /* Validate the requested mode */
3557 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3558 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3559 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3562 if (hw->fc.requested_mode == ixgbe_fc_default)
3563 hw->fc.requested_mode = ixgbe_fc_full;
3565 /* Set up the 1G and 10G flow control advertisement registers so the
3566 * HW will be able to do FC autoneg once the cable is plugged in. If
3567 * we link at 10G, the 1G advertisement is harmless and vice versa.
3569 status = hw->mac.ops.read_iosf_sb_reg(hw,
3570 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3571 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3574 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3578 /* The possible values of fc.requested_mode are:
3579 * 0: Flow control is completely disabled
3580 * 1: Rx flow control is enabled (we can receive pause frames,
3581 * but not send pause frames).
3582 * 2: Tx flow control is enabled (we can send pause frames but
3583 * we do not support receiving pause frames).
3584 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3587 switch (hw->fc.requested_mode) {
3589 /* Flow control completely disabled by software override. */
3590 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3591 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3593 case ixgbe_fc_tx_pause:
3594 /* Tx Flow control is enabled, and Rx Flow control is
3595 * disabled by software override.
3597 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3598 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3600 case ixgbe_fc_rx_pause:
3601 /* Rx Flow control is enabled and Tx Flow control is
3602 * disabled by software override. Since there really
3603 * isn't a way to advertise that we are capable of RX
3604 * Pause ONLY, we will advertise that we support both
3605 * symmetric and asymmetric Rx PAUSE, as such we fall
3606 * through to the fc_full statement. Later, we will
3607 * disable the adapter's ability to send PAUSE frames.
3610 /* Flow control (both Rx and Tx) is enabled by SW override. */
3611 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3612 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3615 hw_err(hw, "Flow control param set incorrectly\n");
3616 return IXGBE_ERR_CONFIG;
3619 status = hw->mac.ops.write_iosf_sb_reg(hw,
3620 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3621 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3623 /* Restart auto-negotiation. */
3624 status = ixgbe_restart_an_internal_phy_x550em(hw);
3630 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3631 * @hw: pointer to hardware structure
3632 * @state: set mux if 1, clear if 0
3634 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3638 if (!hw->bus.lan_id)
3640 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3642 esdp |= IXGBE_ESDP_SDP1;
3644 esdp &= ~IXGBE_ESDP_SDP1;
3645 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3646 IXGBE_WRITE_FLUSH(hw);
3650 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3651 * @hw: pointer to hardware structure
3652 * @mask: Mask to specify which semaphore to acquire
3654 * Acquires the SWFW semaphore and sets the I2C MUX
3656 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3660 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3664 if (mask & IXGBE_GSSR_I2C_MASK)
3665 ixgbe_set_mux(hw, 1);
3671 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3672 * @hw: pointer to hardware structure
3673 * @mask: Mask to specify which semaphore to release
3675 * Releases the SWFW semaphore and sets the I2C MUX
3677 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3679 if (mask & IXGBE_GSSR_I2C_MASK)
3680 ixgbe_set_mux(hw, 0);
3682 ixgbe_release_swfw_sync_X540(hw, mask);
3686 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3687 * @hw: pointer to hardware structure
3688 * @mask: Mask to specify which semaphore to acquire
3690 * Acquires the SWFW semaphore and get the shared PHY token as needed
3692 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3694 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3695 int retries = FW_PHY_TOKEN_RETRIES;
3701 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3704 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3707 status = ixgbe_get_phy_token(hw);
3711 ixgbe_release_swfw_sync_X540(hw, hmask);
3712 if (status != IXGBE_ERR_TOKEN_RETRY)
3714 msleep(FW_PHY_TOKEN_DELAY);
3721 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3722 * @hw: pointer to hardware structure
3723 * @mask: Mask to specify which semaphore to release
3725 * Release the SWFW semaphore and puts the shared PHY token as needed
3727 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3729 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3731 if (mask & IXGBE_GSSR_TOKEN_SM)
3732 ixgbe_put_phy_token(hw);
3735 ixgbe_release_swfw_sync_X540(hw, hmask);
3739 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3740 * @hw: pointer to hardware structure
3741 * @reg_addr: 32 bit address of PHY register to read
3742 * @phy_data: Pointer to read data from PHY register
3744 * Reads a value from a specified PHY register using the SWFW lock and PHY
3745 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3748 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3749 u32 device_type, u16 *phy_data)
3751 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3754 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3755 return IXGBE_ERR_SWFW_SYNC;
3757 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3759 hw->mac.ops.release_swfw_sync(hw, mask);
3765 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3766 * @hw: pointer to hardware structure
3767 * @reg_addr: 32 bit PHY register to write
3768 * @device_type: 5 bit device type
3769 * @phy_data: Data to write to the PHY register
3771 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3772 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3774 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3775 u32 device_type, u16 phy_data)
3777 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3780 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3781 return IXGBE_ERR_SWFW_SYNC;
3783 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3784 hw->mac.ops.release_swfw_sync(hw, mask);
3789 #define X550_COMMON_MAC \
3790 .init_hw = &ixgbe_init_hw_generic, \
3791 .start_hw = &ixgbe_start_hw_X540, \
3792 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3793 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3794 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3795 .get_device_caps = &ixgbe_get_device_caps_generic, \
3796 .stop_adapter = &ixgbe_stop_adapter_generic, \
3797 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3798 .read_analog_reg8 = NULL, \
3799 .write_analog_reg8 = NULL, \
3800 .set_rxpba = &ixgbe_set_rxpba_generic, \
3801 .check_link = &ixgbe_check_mac_link_generic, \
3802 .blink_led_start = &ixgbe_blink_led_start_X540, \
3803 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3804 .set_rar = &ixgbe_set_rar_generic, \
3805 .clear_rar = &ixgbe_clear_rar_generic, \
3806 .set_vmdq = &ixgbe_set_vmdq_generic, \
3807 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3808 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3809 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3810 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3811 .enable_mc = &ixgbe_enable_mc_generic, \
3812 .disable_mc = &ixgbe_disable_mc_generic, \
3813 .clear_vfta = &ixgbe_clear_vfta_generic, \
3814 .set_vfta = &ixgbe_set_vfta_generic, \
3815 .fc_enable = &ixgbe_fc_enable_generic, \
3816 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3817 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3818 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3819 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3820 .set_source_address_pruning = \
3821 &ixgbe_set_source_address_pruning_X550, \
3822 .set_ethertype_anti_spoofing = \
3823 &ixgbe_set_ethertype_anti_spoofing_X550, \
3824 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3825 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3826 .get_thermal_sensor_data = NULL, \
3827 .init_thermal_sensor_thresh = NULL, \
3828 .enable_rx = &ixgbe_enable_rx_generic, \
3829 .disable_rx = &ixgbe_disable_rx_x550, \
3831 static const struct ixgbe_mac_operations mac_ops_X550 = {
3833 .led_on = ixgbe_led_on_generic,
3834 .led_off = ixgbe_led_off_generic,
3835 .init_led_link_act = ixgbe_init_led_link_act_generic,
3836 .reset_hw = &ixgbe_reset_hw_X540,
3837 .get_media_type = &ixgbe_get_media_type_X540,
3838 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3839 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3840 .setup_link = &ixgbe_setup_mac_link_X540,
3841 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3842 .get_bus_info = &ixgbe_get_bus_info_generic,
3844 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3845 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3846 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3847 .prot_autoc_read = prot_autoc_read_generic,
3848 .prot_autoc_write = prot_autoc_write_generic,
3849 .setup_fc = ixgbe_setup_fc_generic,
3850 .fc_autoneg = ixgbe_fc_autoneg,
3853 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3855 .led_on = ixgbe_led_on_t_x550em,
3856 .led_off = ixgbe_led_off_t_x550em,
3857 .init_led_link_act = ixgbe_init_led_link_act_generic,
3858 .reset_hw = &ixgbe_reset_hw_X550em,
3859 .get_media_type = &ixgbe_get_media_type_X550em,
3860 .get_san_mac_addr = NULL,
3861 .get_wwn_prefix = NULL,
3862 .setup_link = &ixgbe_setup_mac_link_X540,
3863 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3864 .get_bus_info = &ixgbe_get_bus_info_X550em,
3865 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3866 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3867 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3868 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3869 .setup_fc = NULL, /* defined later */
3870 .fc_autoneg = ixgbe_fc_autoneg,
3871 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3872 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3875 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3879 .init_led_link_act = NULL,
3880 .reset_hw = &ixgbe_reset_hw_X550em,
3881 .get_media_type = &ixgbe_get_media_type_X550em,
3882 .get_san_mac_addr = NULL,
3883 .get_wwn_prefix = NULL,
3884 .setup_link = &ixgbe_setup_mac_link_X540,
3885 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3886 .get_bus_info = &ixgbe_get_bus_info_X550em,
3887 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3888 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3889 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3890 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3892 .fc_autoneg = ixgbe_fc_autoneg,
3893 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3894 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3897 static struct ixgbe_mac_operations mac_ops_x550em_a = {
3899 .led_on = ixgbe_led_on_t_x550em,
3900 .led_off = ixgbe_led_off_t_x550em,
3901 .init_led_link_act = ixgbe_init_led_link_act_generic,
3902 .reset_hw = ixgbe_reset_hw_X550em,
3903 .get_media_type = ixgbe_get_media_type_X550em,
3904 .get_san_mac_addr = NULL,
3905 .get_wwn_prefix = NULL,
3906 .setup_link = &ixgbe_setup_mac_link_X540,
3907 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3908 .get_bus_info = ixgbe_get_bus_info_X550em,
3909 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3910 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3911 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3912 .setup_fc = ixgbe_setup_fc_x550em,
3913 .fc_autoneg = ixgbe_fc_autoneg,
3914 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3915 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3918 static struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3920 .led_on = ixgbe_led_on_generic,
3921 .led_off = ixgbe_led_off_generic,
3922 .init_led_link_act = ixgbe_init_led_link_act_generic,
3923 .reset_hw = ixgbe_reset_hw_X550em,
3924 .get_media_type = ixgbe_get_media_type_X550em,
3925 .get_san_mac_addr = NULL,
3926 .get_wwn_prefix = NULL,
3927 .setup_link = NULL, /* defined later */
3928 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3929 .get_bus_info = ixgbe_get_bus_info_X550em,
3930 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3931 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3932 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3933 .setup_fc = ixgbe_setup_fc_x550em,
3934 .fc_autoneg = ixgbe_fc_autoneg,
3935 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3936 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3939 #define X550_COMMON_EEP \
3940 .read = &ixgbe_read_ee_hostif_X550, \
3941 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3942 .write = &ixgbe_write_ee_hostif_X550, \
3943 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3944 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3945 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3946 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3948 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3950 .init_params = &ixgbe_init_eeprom_params_X550,
3953 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3955 .init_params = &ixgbe_init_eeprom_params_X540,
3958 #define X550_COMMON_PHY \
3959 .identify_sfp = &ixgbe_identify_module_generic, \
3961 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3962 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3963 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3964 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3965 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3966 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3967 .setup_link = &ixgbe_setup_phy_link_generic, \
3968 .set_phy_power = NULL,
3970 static const struct ixgbe_phy_operations phy_ops_X550 = {
3972 .check_overtemp = &ixgbe_tn_check_overtemp,
3974 .identify = &ixgbe_identify_phy_generic,
3975 .read_reg = &ixgbe_read_phy_reg_generic,
3976 .write_reg = &ixgbe_write_phy_reg_generic,
3979 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3981 .check_overtemp = &ixgbe_tn_check_overtemp,
3982 .init = &ixgbe_init_phy_ops_X550em,
3983 .identify = &ixgbe_identify_phy_x550em,
3984 .read_reg = &ixgbe_read_phy_reg_generic,
3985 .write_reg = &ixgbe_write_phy_reg_generic,
3988 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
3990 .check_overtemp = NULL,
3991 .init = ixgbe_init_phy_ops_X550em,
3992 .identify = ixgbe_identify_phy_x550em,
3995 .read_reg_mdi = NULL,
3996 .write_reg_mdi = NULL,
3999 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4001 .check_overtemp = &ixgbe_tn_check_overtemp,
4002 .init = &ixgbe_init_phy_ops_X550em,
4003 .identify = &ixgbe_identify_phy_x550em,
4004 .read_reg = &ixgbe_read_phy_reg_x550a,
4005 .write_reg = &ixgbe_write_phy_reg_x550a,
4006 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
4007 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
4010 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4012 .check_overtemp = ixgbe_check_overtemp_fw,
4013 .init = ixgbe_init_phy_ops_X550em,
4014 .identify = ixgbe_identify_phy_fw,
4017 .read_reg_mdi = NULL,
4018 .write_reg_mdi = NULL,
4021 static const struct ixgbe_link_operations link_ops_x550em_x = {
4022 .read_link = &ixgbe_read_i2c_combined_generic,
4023 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4024 .write_link = &ixgbe_write_i2c_combined_generic,
4025 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4028 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4029 IXGBE_MVALS_INIT(X550)
4032 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4033 IXGBE_MVALS_INIT(X550EM_x)
4036 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4037 IXGBE_MVALS_INIT(X550EM_a)
4040 const struct ixgbe_info ixgbe_X550_info = {
4041 .mac = ixgbe_mac_X550,
4042 .get_invariants = &ixgbe_get_invariants_X540,
4043 .mac_ops = &mac_ops_X550,
4044 .eeprom_ops = &eeprom_ops_X550,
4045 .phy_ops = &phy_ops_X550,
4046 .mbx_ops = &mbx_ops_generic,
4047 .mvals = ixgbe_mvals_X550,
4050 const struct ixgbe_info ixgbe_X550EM_x_info = {
4051 .mac = ixgbe_mac_X550EM_x,
4052 .get_invariants = &ixgbe_get_invariants_X550_x,
4053 .mac_ops = &mac_ops_X550EM_x,
4054 .eeprom_ops = &eeprom_ops_X550EM_x,
4055 .phy_ops = &phy_ops_X550EM_x,
4056 .mbx_ops = &mbx_ops_generic,
4057 .mvals = ixgbe_mvals_X550EM_x,
4058 .link_ops = &link_ops_x550em_x,
4061 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4062 .mac = ixgbe_mac_X550EM_x,
4063 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4064 .mac_ops = &mac_ops_X550EM_x_fw,
4065 .eeprom_ops = &eeprom_ops_X550EM_x,
4066 .phy_ops = &phy_ops_x550em_x_fw,
4067 .mbx_ops = &mbx_ops_generic,
4068 .mvals = ixgbe_mvals_X550EM_x,
4071 const struct ixgbe_info ixgbe_x550em_a_info = {
4072 .mac = ixgbe_mac_x550em_a,
4073 .get_invariants = &ixgbe_get_invariants_X550_a,
4074 .mac_ops = &mac_ops_x550em_a,
4075 .eeprom_ops = &eeprom_ops_X550EM_x,
4076 .phy_ops = &phy_ops_x550em_a,
4077 .mbx_ops = &mbx_ops_generic,
4078 .mvals = ixgbe_mvals_x550em_a,
4081 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4082 .mac = ixgbe_mac_x550em_a,
4083 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4084 .mac_ops = &mac_ops_x550em_a_fw,
4085 .eeprom_ops = &eeprom_ops_X550EM_x,
4086 .phy_ops = &phy_ops_x550em_a_fw,
4087 .mbx_ops = &mbx_ops_generic,
4088 .mvals = ixgbe_mvals_x550em_a,