drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35 #include "ixgbe_x540.h"
  36
  37 #define IXGBE_X540_MAX_TX_QUEUES        128
  38 #define IXGBE_X540_MAX_RX_QUEUES        128
  39 #define IXGBE_X540_RAR_ENTRIES          128
  40 #define IXGBE_X540_MC_TBL_SIZE          128
  41 #define IXGBE_X540_VFT_TBL_SIZE         128
  42 #define IXGBE_X540_RX_PB_SIZE           384
  43
  44 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  45 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  48
  49 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
  50 {
  51         return ixgbe_media_type_copper;
  52 }
  53
  54 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
  55 {
  56         struct ixgbe_mac_info *mac = &hw->mac;
  57         struct ixgbe_phy_info *phy = &hw->phy;
  58
  59         /* set_phy_power was set by default to NULL */
  60         phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
  61
  62         mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
  63         mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
  64         mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
  65         mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
  66         mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
  67         mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
  68         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
  69
  70         return 0;
  71 }
  72
  73 /**
  74  *  ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
  75  *  @hw: pointer to hardware structure
  76  *  @speed: new link speed
  77  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  78  **/
  79 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
  80                               bool autoneg_wait_to_complete)
  81 {
  82         return hw->phy.ops.setup_link_speed(hw, speed,
  83                                             autoneg_wait_to_complete);
  84 }
  85
  86 /**
  87  *  ixgbe_reset_hw_X540 - Perform hardware reset
  88  *  @hw: pointer to hardware structure
  89  *
  90  *  Resets the hardware by resetting the transmit and receive units, masks
  91  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  92  *  reset.
  93  **/
  94 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
  95 {
  96         s32 status;
  97         u32 ctrl, i;
  98
  99         /* Call adapter stop to disable tx/rx and clear interrupts */
 100         status = hw->mac.ops.stop_adapter(hw);
 101         if (status)
 102                 return status;
 103
 104         /* flush pending Tx transactions */
 105         ixgbe_clear_tx_pending(hw);
 106
 107 mac_reset_top:
 108         ctrl = IXGBE_CTRL_RST;
 109         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 110         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 111         IXGBE_WRITE_FLUSH(hw);
 112         usleep_range(1000, 1200);
 113
 114         /* Poll for reset bit to self-clear indicating reset is complete */
 115         for (i = 0; i < 10; i++) {
 116                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 117                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 118                         break;
 119                 udelay(1);
 120         }
 121
 122         if (ctrl & IXGBE_CTRL_RST_MASK) {
 123                 status = IXGBE_ERR_RESET_FAILED;
 124                 hw_dbg(hw, "Reset polling failed to complete.\n");
 125         }
 126         msleep(100);
 127
 128         /*
 129          * Double resets are required for recovery from certain error
 130          * conditions.  Between resets, it is necessary to stall to allow time
 131          * for any pending HW events to complete.
 132          */
 133         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 134                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 135                 goto mac_reset_top;
 136         }
 137
 138         /* Set the Rx packet buffer size. */
 139         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 140
 141         /* Store the permanent mac address */
 142         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 143
 144         /*
 145          * Store MAC address from RAR0, clear receive address registers, and
 146          * clear the multicast table.  Also reset num_rar_entries to 128,
 147          * since we modify this value when programming the SAN MAC address.
 148          */
 149         hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
 150         hw->mac.ops.init_rx_addrs(hw);
 151
 152         /* Store the permanent SAN mac address */
 153         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 154
 155         /* Add the SAN MAC address to the RAR only if it's a valid address */
 156         if (is_valid_ether_addr(hw->mac.san_addr)) {
 157                 /* Save the SAN MAC RAR index */
 158                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 159
 160                 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
 161                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 162
 163                 /* clear VMDq pool/queue selection for this RAR */
 164                 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
 165                                        IXGBE_CLEAR_VMDQ_ALL);
 166
 167                 /* Reserve the last RAR for the SAN MAC address */
 168                 hw->mac.num_rar_entries--;
 169         }
 170
 171         /* Store the alternative WWNN/WWPN prefix */
 172         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 173                                    &hw->mac.wwpn_prefix);
 174
 175         return status;
 176 }
 177
 178 /**
 179  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 180  *  @hw: pointer to hardware structure
 181  *
 182  *  Starts the hardware using the generic start_hw function
 183  *  and the generation start_hw function.
 184  *  Then performs revision-specific operations, if any.
 185  **/
 186 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 187 {
 188         s32 ret_val;
 189
 190         ret_val = ixgbe_start_hw_generic(hw);
 191         if (ret_val)
 192                 return ret_val;
 193
 194         return ixgbe_start_hw_gen2(hw);
 195 }
 196
 197 /**
 198  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 199  *  @hw: pointer to hardware structure
 200  *
 201  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 202  *  ixgbe_hw struct in order to set up EEPROM access.
 203  **/
 204 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 205 {
 206         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 207         u32 eec;
 208         u16 eeprom_size;
 209
 210         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 211                 eeprom->semaphore_delay = 10;
 212                 eeprom->type = ixgbe_flash;
 213
 214                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 215                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 216                                     IXGBE_EEC_SIZE_SHIFT);
 217                 eeprom->word_size = BIT(eeprom_size +
 218                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 219
 220                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 221                        eeprom->type, eeprom->word_size);
 222         }
 223
 224         return 0;
 225 }
 226
 227 /**
 228  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 229  *  @hw: pointer to hardware structure
 230  *  @offset: offset of  word in the EEPROM to read
 231  *  @data: word read from the EEPROM
 232  *
 233  *  Reads a 16 bit word from the EEPROM using the EERD register.
 234  **/
 235 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 236 {
 237         s32 status;
 238
 239         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 240                 return IXGBE_ERR_SWFW_SYNC;
 241
 242         status = ixgbe_read_eerd_generic(hw, offset, data);
 243
 244         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 245         return status;
 246 }
 247
 248 /**
 249  *  ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
 250  *  @hw: pointer to hardware structure
 251  *  @offset: offset of  word in the EEPROM to read
 252  *  @words: number of words
 253  *  @data: word(s) read from the EEPROM
 254  *
 255  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 256  **/
 257 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 258                                        u16 offset, u16 words, u16 *data)
 259 {
 260         s32 status;
 261
 262         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 263                 return IXGBE_ERR_SWFW_SYNC;
 264
 265         status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
 266
 267         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 268         return status;
 269 }
 270
 271 /**
 272  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 273  *  @hw: pointer to hardware structure
 274  *  @offset: offset of  word in the EEPROM to write
 275  *  @data: word write to the EEPROM
 276  *
 277  *  Write a 16 bit word to the EEPROM using the EEWR register.
 278  **/
 279 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 280 {
 281         s32 status;
 282
 283         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 284                 return IXGBE_ERR_SWFW_SYNC;
 285
 286         status = ixgbe_write_eewr_generic(hw, offset, data);
 287
 288         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 289         return status;
 290 }
 291
 292 /**
 293  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 294  *  @hw: pointer to hardware structure
 295  *  @offset: offset of  word in the EEPROM to write
 296  *  @words: number of words
 297  *  @data: word(s) write to the EEPROM
 298  *
 299  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 300  **/
 301 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 302                                         u16 offset, u16 words, u16 *data)
 303 {
 304         s32 status;
 305
 306         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 307                 return IXGBE_ERR_SWFW_SYNC;
 308
 309         status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
 310
 311         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 312         return status;
 313 }
 314
 315 /**
 316  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 317  *
 318  *  This function does not use synchronization for EERD and EEWR. It can
 319  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 320  *
 321  *  @hw: pointer to hardware structure
 322  **/
 323 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 324 {
 325         u16 i;
 326         u16 j;
 327         u16 checksum = 0;
 328         u16 length = 0;
 329         u16 pointer = 0;
 330         u16 word = 0;
 331         u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
 332         u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
 333
 334         /*
 335          * Do not use hw->eeprom.ops.read because we do not want to take
 336          * the synchronization semaphores here. Instead use
 337          * ixgbe_read_eerd_generic
 338          */
 339
 340         /* Include 0x0-0x3F in the checksum */
 341         for (i = 0; i < checksum_last_word; i++) {
 342                 if (ixgbe_read_eerd_generic(hw, i, &word)) {
 343                         hw_dbg(hw, "EEPROM read failed\n");
 344                         return IXGBE_ERR_EEPROM;
 345                 }
 346                 checksum += word;
 347         }
 348
 349         /*
 350          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 351          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 352          */
 353         for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
 354                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 355                         continue;
 356
 357                 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
 358                         hw_dbg(hw, "EEPROM read failed\n");
 359                         break;
 360                 }
 361
 362                 /* Skip pointer section if the pointer is invalid. */
 363                 if (pointer == 0xFFFF || pointer == 0 ||
 364                     pointer >= hw->eeprom.word_size)
 365                         continue;
 366
 367                 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
 368                         hw_dbg(hw, "EEPROM read failed\n");
 369                         return IXGBE_ERR_EEPROM;
 370                         break;
 371                 }
 372
 373                 /* Skip pointer section if length is invalid. */
 374                 if (length == 0xFFFF || length == 0 ||
 375                     (pointer + length) >= hw->eeprom.word_size)
 376                         continue;
 377
 378                 for (j = pointer + 1; j <= pointer + length; j++) {
 379                         if (ixgbe_read_eerd_generic(hw, j, &word)) {
 380                                 hw_dbg(hw, "EEPROM read failed\n");
 381                                 return IXGBE_ERR_EEPROM;
 382                         }
 383                         checksum += word;
 384                 }
 385         }
 386
 387         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 388
 389         return (s32)checksum;
 390 }
 391
 392 /**
 393  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 394  *  @hw: pointer to hardware structure
 395  *  @checksum_val: calculated checksum
 396  *
 397  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 398  *  caller does not need checksum_val, the value can be NULL.
 399  **/
 400 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 401                                                u16 *checksum_val)
 402 {
 403         s32 status;
 404         u16 checksum;
 405         u16 read_checksum = 0;
 406
 407         /* Read the first word from the EEPROM. If this times out or fails, do
 408          * not continue or we could be in for a very long wait while every
 409          * EEPROM read fails
 410          */
 411         status = hw->eeprom.ops.read(hw, 0, &checksum);
 412         if (status) {
 413                 hw_dbg(hw, "EEPROM read failed\n");
 414                 return status;
 415         }
 416
 417         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 418                 return IXGBE_ERR_SWFW_SYNC;
 419
 420         status = hw->eeprom.ops.calc_checksum(hw);
 421         if (status < 0)
 422                 goto out;
 423
 424         checksum = (u16)(status & 0xffff);
 425
 426         /* Do not use hw->eeprom.ops.read because we do not want to take
 427          * the synchronization semaphores twice here.
 428          */
 429         status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 430                                          &read_checksum);
 431         if (status)
 432                 goto out;
 433
 434         /* Verify read checksum from EEPROM is the same as
 435          * calculated checksum
 436          */
 437         if (read_checksum != checksum) {
 438                 hw_dbg(hw, "Invalid EEPROM checksum");
 439                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 440         }
 441
 442         /* If the user cares, return the calculated checksum */
 443         if (checksum_val)
 444                 *checksum_val = checksum;
 445
 446 out:
 447         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 448
 449         return status;
 450 }
 451
 452 /**
 453  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 454  * @hw: pointer to hardware structure
 455  *
 456  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 457  * checksum and updates the EEPROM and instructs the hardware to update
 458  * the flash.
 459  **/
 460 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 461 {
 462         s32 status;
 463         u16 checksum;
 464
 465         /* Read the first word from the EEPROM. If this times out or fails, do
 466          * not continue or we could be in for a very long wait while every
 467          * EEPROM read fails
 468          */
 469         status = hw->eeprom.ops.read(hw, 0, &checksum);
 470         if (status) {
 471                 hw_dbg(hw, "EEPROM read failed\n");
 472                 return status;
 473         }
 474
 475         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 476                 return  IXGBE_ERR_SWFW_SYNC;
 477
 478         status = hw->eeprom.ops.calc_checksum(hw);
 479         if (status < 0)
 480                 goto out;
 481
 482         checksum = (u16)(status & 0xffff);
 483
 484         /* Do not use hw->eeprom.ops.write because we do not want to
 485          * take the synchronization semaphores twice here.
 486          */
 487         status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
 488         if (status)
 489                 goto out;
 490
 491         status = ixgbe_update_flash_X540(hw);
 492
 493 out:
 494         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 495         return status;
 496 }
 497
 498 /**
 499  * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 500  * @hw: pointer to hardware structure
 501  *
 502  * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 503  * EEPROM from shadow RAM to the flash device.
 504  **/
 505 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 506 {
 507         u32 flup;
 508         s32 status;
 509
 510         status = ixgbe_poll_flash_update_done_X540(hw);
 511         if (status == IXGBE_ERR_EEPROM) {
 512                 hw_dbg(hw, "Flash update time out\n");
 513                 return status;
 514         }
 515
 516         flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
 517         IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
 518
 519         status = ixgbe_poll_flash_update_done_X540(hw);
 520         if (status == 0)
 521                 hw_dbg(hw, "Flash update complete\n");
 522         else
 523                 hw_dbg(hw, "Flash update time out\n");
 524
 525         if (hw->revision_id == 0) {
 526                 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 527
 528                 if (flup & IXGBE_EEC_SEC1VAL) {
 529                         flup |= IXGBE_EEC_FLUP;
 530                         IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
 531                 }
 532
 533                 status = ixgbe_poll_flash_update_done_X540(hw);
 534                 if (status == 0)
 535                         hw_dbg(hw, "Flash update complete\n");
 536                 else
 537                         hw_dbg(hw, "Flash update time out\n");
 538         }
 539
 540         return status;
 541 }
 542
 543 /**
 544  * ixgbe_poll_flash_update_done_X540 - Poll flash update status
 545  * @hw: pointer to hardware structure
 546  *
 547  * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 548  * flash update is done.
 549  **/
 550 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 551 {
 552         u32 i;
 553         u32 reg;
 554
 555         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 556                 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 557                 if (reg & IXGBE_EEC_FLUDONE)
 558                         return 0;
 559                 udelay(5);
 560         }
 561         return IXGBE_ERR_EEPROM;
 562 }
 563
 564 /**
 565  * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 566  * @hw: pointer to hardware structure
 567  * @mask: Mask to specify which semaphore to acquire
 568  *
 569  * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 570  * the specified function (CSR, PHY0, PHY1, NVM, Flash)
 571  **/
 572 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 573 {
 574         u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
 575         u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
 576         u32 fwmask = swmask << 5;
 577         u32 timeout = 200;
 578         u32 hwmask = 0;
 579         u32 swfw_sync;
 580         u32 i;
 581
 582         if (swmask & IXGBE_GSSR_EEP_SM)
 583                 hwmask = IXGBE_GSSR_FLASH_SM;
 584
 585         /* SW only mask does not have FW bit pair */
 586         if (mask & IXGBE_GSSR_SW_MNG_SM)
 587                 swmask |= IXGBE_GSSR_SW_MNG_SM;
 588
 589         swmask |= swi2c_mask;
 590         fwmask |= swi2c_mask << 2;
 591         for (i = 0; i < timeout; i++) {
 592                 /* SW NVM semaphore bit is used for access to all
 593                  * SW_FW_SYNC bits (not just NVM)
 594                  */
 595                 if (ixgbe_get_swfw_sync_semaphore(hw))
 596                         return IXGBE_ERR_SWFW_SYNC;
 597
 598                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 599                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 600                         swfw_sync |= swmask;
 601                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
 602                         ixgbe_release_swfw_sync_semaphore(hw);
 603                         usleep_range(5000, 6000);
 604                         return 0;
 605                 }
 606                 /* Firmware currently using resource (fwmask), hardware
 607                  * currently using resource (hwmask), or other software
 608                  * thread currently using resource (swmask)
 609                  */
 610                 ixgbe_release_swfw_sync_semaphore(hw);
 611                 usleep_range(5000, 10000);
 612         }
 613
 614         /* Failed to get SW only semaphore */
 615         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 616                 hw_dbg(hw, "Failed to get SW only semaphore\n");
 617                 return IXGBE_ERR_SWFW_SYNC;
 618         }
 619
 620         /* If the resource is not released by the FW/HW the SW can assume that
 621          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 622          * of the requested resource(s) while ignoring the corresponding FW/HW
 623          * bits in the SW_FW_SYNC register.
 624          */
 625         if (ixgbe_get_swfw_sync_semaphore(hw))
 626                 return IXGBE_ERR_SWFW_SYNC;
 627         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 628         if (swfw_sync & (fwmask | hwmask)) {
 629                 swfw_sync |= swmask;
 630                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
 631                 ixgbe_release_swfw_sync_semaphore(hw);
 632                 usleep_range(5000, 6000);
 633                 return 0;
 634         }
 635         /* If the resource is not released by other SW the SW can assume that
 636          * the other SW malfunctions. In that case the SW should clear all SW
 637          * flags that it does not own and then repeat the whole process once
 638          * again.
 639          */
 640         if (swfw_sync & swmask) {
 641                 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
 642                             IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
 643
 644                 if (swi2c_mask)
 645                         rmask |= IXGBE_GSSR_I2C_MASK;
 646                 ixgbe_release_swfw_sync_X540(hw, rmask);
 647                 ixgbe_release_swfw_sync_semaphore(hw);
 648                 return IXGBE_ERR_SWFW_SYNC;
 649         }
 650         ixgbe_release_swfw_sync_semaphore(hw);
 651
 652         return IXGBE_ERR_SWFW_SYNC;
 653 }
 654
 655 /**
 656  * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 657  * @hw: pointer to hardware structure
 658  * @mask: Mask to specify which semaphore to release
 659  *
 660  * Releases the SWFW semaphore through the SW_FW_SYNC register
 661  * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 662  **/
 663 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 664 {
 665         u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
 666         u32 swfw_sync;
 667
 668         if (mask & IXGBE_GSSR_I2C_MASK)
 669                 swmask |= mask & IXGBE_GSSR_I2C_MASK;
 670         ixgbe_get_swfw_sync_semaphore(hw);
 671
 672         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 673         swfw_sync &= ~swmask;
 674         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
 675
 676         ixgbe_release_swfw_sync_semaphore(hw);
 677         usleep_range(5000, 6000);
 678 }
 679
 680 /**
 681  * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
 682  * @hw: pointer to hardware structure
 683  *
 684  * Sets the hardware semaphores so SW/FW can gain control of shared resources
 685  */
 686 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 687 {
 688         u32 timeout = 2000;
 689         u32 i;
 690         u32 swsm;
 691
 692         /* Get SMBI software semaphore between device drivers first */
 693         for (i = 0; i < timeout; i++) {
 694                 /* If the SMBI bit is 0 when we read it, then the bit will be
 695                  * set and we have the semaphore
 696                  */
 697                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
 698                 if (!(swsm & IXGBE_SWSM_SMBI))
 699                         break;
 700                 usleep_range(50, 100);
 701         }
 702
 703         if (i == timeout) {
 704                 hw_dbg(hw,
 705                        "Software semaphore SMBI between device drivers not granted.\n");
 706                 return IXGBE_ERR_EEPROM;
 707         }
 708
 709         /* Now get the semaphore between SW/FW through the REGSMP bit */
 710         for (i = 0; i < timeout; i++) {
 711                 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 712                 if (!(swsm & IXGBE_SWFW_REGSMP))
 713                         return 0;
 714
 715                 usleep_range(50, 100);
 716         }
 717
 718         /* Release semaphores and return error if SW NVM semaphore
 719          * was not granted because we do not have access to the EEPROM
 720          */
 721         hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
 722         ixgbe_release_swfw_sync_semaphore(hw);
 723         return IXGBE_ERR_EEPROM;
 724 }
 725
 726 /**
 727  * ixgbe_release_nvm_semaphore - Release hardware semaphore
 728  * @hw: pointer to hardware structure
 729  *
 730  * This function clears hardware semaphore bits.
 731  **/
 732 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 733 {
 734          u32 swsm;
 735
 736         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 737
 738         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 739         swsm &= ~IXGBE_SWFW_REGSMP;
 740         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
 741
 742         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
 743         swsm &= ~IXGBE_SWSM_SMBI;
 744         IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
 745
 746         IXGBE_WRITE_FLUSH(hw);
 747 }
 748
 749 /**
 750  *  ixgbe_init_swfw_sync_X540 - Release hardware semaphore
 751  *  @hw: pointer to hardware structure
 752  *
 753  *  This function reset hardware semaphore bits for a semaphore that may
 754  *  have be left locked due to a catastrophic failure.
 755  **/
 756 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
 757 {
 758         /* First try to grab the semaphore but we don't need to bother
 759          * looking to see whether we got the lock or not since we do
 760          * the same thing regardless of whether we got the lock or not.
 761          * We got the lock - we release it.
 762          * We timeout trying to get the lock - we force its release.
 763          */
 764         ixgbe_get_swfw_sync_semaphore(hw);
 765         ixgbe_release_swfw_sync_semaphore(hw);
 766 }
 767
 768 /**
 769  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 770  * @hw: pointer to hardware structure
 771  * @index: led number to blink
 772  *
 773  * Devices that implement the version 2 interface:
 774  *   X540
 775  **/
 776 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 777 {
 778         u32 macc_reg;
 779         u32 ledctl_reg;
 780         ixgbe_link_speed speed;
 781         bool link_up;
 782
 783         /*
 784          * Link should be up in order for the blink bit in the LED control
 785          * register to work. Force link and speed in the MAC if link is down.
 786          * This will be reversed when we stop the blinking.
 787          */
 788         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 789         if (!link_up) {
 790                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 791                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 792                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 793         }
 794         /* Set the LED to LINK_UP + BLINK. */
 795         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 796         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 797         ledctl_reg |= IXGBE_LED_BLINK(index);
 798         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 799         IXGBE_WRITE_FLUSH(hw);
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 806  * @hw: pointer to hardware structure
 807  * @index: led number to stop blinking
 808  *
 809  * Devices that implement the version 2 interface:
 810  *   X540
 811  **/
 812 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 813 {
 814         u32 macc_reg;
 815         u32 ledctl_reg;
 816
 817         /* Restore the LED to its default value. */
 818         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 819         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 820         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 821         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 822         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 823
 824         /* Unforce link and speed in the MAC. */
 825         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 826         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 827         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 828         IXGBE_WRITE_FLUSH(hw);
 829
 830         return 0;
 831 }
 832 static const struct ixgbe_mac_operations mac_ops_X540 = {
 833         .init_hw                = &ixgbe_init_hw_generic,
 834         .reset_hw               = &ixgbe_reset_hw_X540,
 835         .start_hw               = &ixgbe_start_hw_X540,
 836         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
 837         .get_media_type         = &ixgbe_get_media_type_X540,
 838         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
 839         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
 840         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
 841         .get_device_caps        = &ixgbe_get_device_caps_generic,
 842         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
 843         .stop_adapter           = &ixgbe_stop_adapter_generic,
 844         .get_bus_info           = &ixgbe_get_bus_info_generic,
 845         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
 846         .read_analog_reg8       = NULL,
 847         .write_analog_reg8      = NULL,
 848         .setup_link             = &ixgbe_setup_mac_link_X540,
 849         .set_rxpba              = &ixgbe_set_rxpba_generic,
 850         .check_link             = &ixgbe_check_mac_link_generic,
 851         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
 852         .led_on                 = &ixgbe_led_on_generic,
 853         .led_off                = &ixgbe_led_off_generic,
 854         .blink_led_start        = &ixgbe_blink_led_start_X540,
 855         .blink_led_stop         = &ixgbe_blink_led_stop_X540,
 856         .set_rar                = &ixgbe_set_rar_generic,
 857         .clear_rar              = &ixgbe_clear_rar_generic,
 858         .set_vmdq               = &ixgbe_set_vmdq_generic,
 859         .set_vmdq_san_mac       = &ixgbe_set_vmdq_san_mac_generic,
 860         .clear_vmdq             = &ixgbe_clear_vmdq_generic,
 861         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
 862         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
 863         .enable_mc              = &ixgbe_enable_mc_generic,
 864         .disable_mc             = &ixgbe_disable_mc_generic,
 865         .clear_vfta             = &ixgbe_clear_vfta_generic,
 866         .set_vfta               = &ixgbe_set_vfta_generic,
 867         .fc_enable              = &ixgbe_fc_enable_generic,
 868         .setup_fc               = ixgbe_setup_fc_generic,
 869         .set_fw_drv_ver         = &ixgbe_set_fw_drv_ver_generic,
 870         .init_uta_tables        = &ixgbe_init_uta_tables_generic,
 871         .setup_sfp              = NULL,
 872         .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
 873         .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
 874         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
 875         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
 876         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
 877         .disable_rx_buff        = &ixgbe_disable_rx_buff_generic,
 878         .enable_rx_buff         = &ixgbe_enable_rx_buff_generic,
 879         .get_thermal_sensor_data = NULL,
 880         .init_thermal_sensor_thresh = NULL,
 881         .prot_autoc_read        = &prot_autoc_read_generic,
 882         .prot_autoc_write       = &prot_autoc_write_generic,
 883         .enable_rx              = &ixgbe_enable_rx_generic,
 884         .disable_rx             = &ixgbe_disable_rx_generic,
 885 };
 886
 887 static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
 888         .init_params            = &ixgbe_init_eeprom_params_X540,
 889         .read                   = &ixgbe_read_eerd_X540,
 890         .read_buffer            = &ixgbe_read_eerd_buffer_X540,
 891         .write                  = &ixgbe_write_eewr_X540,
 892         .write_buffer           = &ixgbe_write_eewr_buffer_X540,
 893         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X540,
 894         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X540,
 895         .update_checksum        = &ixgbe_update_eeprom_checksum_X540,
 896 };
 897
 898 static const struct ixgbe_phy_operations phy_ops_X540 = {
 899         .identify               = &ixgbe_identify_phy_generic,
 900         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
 901         .init                   = NULL,
 902         .reset                  = NULL,
 903         .read_reg               = &ixgbe_read_phy_reg_generic,
 904         .write_reg              = &ixgbe_write_phy_reg_generic,
 905         .setup_link             = &ixgbe_setup_phy_link_generic,
 906         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
 907         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
 908         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
 909         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic,
 910         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
 911         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
 912         .check_overtemp         = &ixgbe_tn_check_overtemp,
 913         .set_phy_power          = &ixgbe_set_copper_phy_power,
 914         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
 915 };
 916
 917 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
 918         IXGBE_MVALS_INIT(X540)
 919 };
 920
 921 const struct ixgbe_info ixgbe_X540_info = {
 922         .mac                    = ixgbe_mac_X540,
 923         .get_invariants         = &ixgbe_get_invariants_X540,
 924         .mac_ops                = &mac_ops_X540,
 925         .eeprom_ops             = &eeprom_ops_X540,
 926         .phy_ops                = &phy_ops_X540,
 927         .mbx_ops                = &mbx_ops_generic,
 928         .mvals                  = ixgbe_mvals_X540,
 929 };