1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/ptp_classify.h>
30 #include <linux/clocksource.h>
33 * The 82599 and the X540 do not have true 64bit nanosecond scale
34 * counter registers. Instead, SYSTIME is defined by a fixed point
35 * system which allows the user to define the scale counter increment
36 * value at every level change of the oscillator driving the SYSTIME
37 * value. For both devices the TIMINCA:IV field defines this
38 * increment. On the X540 device, 31 bits are provided. However on the
39 * 82599 only provides 24 bits. The time unit is determined by the
40 * clock frequency of the oscillator in combination with the TIMINCA
41 * register. When these devices link at 10Gb the oscillator has a
42 * period of 6.4ns. In order to convert the scale counter into
43 * nanoseconds the cyclecounter and timecounter structures are
44 * used. The SYSTIME registers need to be converted to ns values by use
45 * of only a right shift (division by power of 2). The following math
46 * determines the largest incvalue that will fit into the available
47 * bits in the TIMINCA register.
49 * PeriodWidth: Number of bits to store the clock period
50 * MaxWidth: The maximum width value of the TIMINCA register
51 * Period: The clock period for the oscillator
52 * round(): discard the fractional portion of the calculation
54 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
56 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
57 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
59 * The period also changes based on the link speed:
60 * At 10Gb link or no link, the period remains the same.
61 * At 1Gb link, the period is multiplied by 10. (64ns)
62 * At 100Mb link, the period is multiplied by 100. (640ns)
64 * The calculated value allows us to right shift the SYSTIME register
65 * value in order to quickly convert it into a nanosecond clock,
66 * while allowing for the maximum possible adjustment value.
68 * These diagrams are only for the 10Gb link period
71 * +--------------+ +--------------+
72 * X540 | 32 | | 1 | 3 | 28 |
73 * *--------------+ +--------------+
74 * \________ 36 bits ______/ fract
76 * +--------------+ +--------------+
77 * 82599 | 32 | | 8 | 3 | 21 |
78 * *--------------+ +--------------+
79 * \________ 43 bits ______/ fract
81 * The 36 bit X540 SYSTIME overflows every
82 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
84 * The 43 bit 82599 SYSTIME overflows every
85 * 2^43 * 10^-9 / 3600 = 2.4 hours
87 #define IXGBE_INCVAL_10GB 0x66666666
88 #define IXGBE_INCVAL_1GB 0x40000000
89 #define IXGBE_INCVAL_100 0x50000000
91 #define IXGBE_INCVAL_SHIFT_10GB 28
92 #define IXGBE_INCVAL_SHIFT_1GB 24
93 #define IXGBE_INCVAL_SHIFT_100 21
95 #define IXGBE_INCVAL_SHIFT_82599 7
96 #define IXGBE_INCPER_SHIFT_82599 24
98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
101 /* half of a one second clock period, for use with PPS signal. We have to use
102 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in
103 * order to force at least 64bits of precision for shifting
105 #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
107 /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
108 * which contain measurements of seconds and nanoseconds respectively. This
109 * matches the standard linux representation of time in the kernel. In addition,
110 * the X550 also has a SYSTIMER register which represents residue, or
111 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
112 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
113 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
114 * high bit representing whether the adjustent is positive or negative. Every
115 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
116 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
117 * X550's clock for purposes of SYSTIME generation is constant and not dependent
120 * SYSTIMEH SYSTIMEL SYSTIMER
121 * +--------------+ +--------------+ +-------------+
122 * X550 | 32 | | 32 | | 32 |
123 * *--------------+ +--------------+ +-------------+
124 * \____seconds___/ \_nanoseconds_/ \__2^-32 ns__/
126 * This results in a full 96 bits to represent the clock, with 32 bits for
127 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
128 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
129 * underflow of adjustments.
131 * The 32 bits of seconds for the X550 overflows every
132 * 2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
134 * In order to adjust the clock frequency for the X550, the TIMINCA register is
135 * provided. This register represents a + or minus nearly 0.5 ns adjustment to
136 * the base frequency. It is measured in 2^-32 ns units, with the high bit being
137 * the sign bit. This register enables software to calculate frequency
138 * adjustments and apply them directly to the clock rate.
140 * The math for converting ppb into TIMINCA values is fairly straightforward.
141 * TIMINCA value = ( Base_Frequency * ppb ) / 1000000000ULL
143 * This assumes that ppb is never high enough to create a value bigger than
144 * TIMINCA's 31 bits can store. This is ensured by the stack. Calculating this
145 * value is also simple.
146 * Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
148 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
149 * 12.5 nanoseconds. This means that the Max ppb is 39999999
150 * Note: We subtract one in order to ensure no overflow, because the TIMINCA
151 * register can only hold slightly under 0.5 nanoseconds.
153 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
154 * into 2^-32 units, which is
156 * 12.5 * 2^32 = C80000000
158 * Some revisions of hardware have a faster base frequency than the registers
159 * were defined for. To fix this, we use a timecounter structure with the
160 * proper mult and shift to convert the cycles into nanoseconds of time.
162 #define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
163 #define INCVALUE_MASK 0x7FFFFFFF
164 #define ISGN 0x80000000
165 #define MAX_TIMADJ 0x7FFFFFFF
168 * ixgbe_ptp_setup_sdp_x540
169 * @hw: the hardware private structure
171 * this function enables or disables the clock out feature on SDP0 for
172 * the X540 device. It will create a 1second periodic output that can
173 * be used as the PPS (via an interrupt).
175 * It calculates when the systime will be on an exact second, and then
176 * aligns the start of the PPS signal to that value. The shift is
177 * necessary because it can change based on the link speed.
179 static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter)
181 struct ixgbe_hw *hw = &adapter->hw;
182 int shift = adapter->hw_cc.shift;
183 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
184 u64 ns = 0, clock_edge = 0;
186 /* disable the pin first */
187 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
188 IXGBE_WRITE_FLUSH(hw);
190 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
193 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
195 /* enable the SDP0 pin as output, and connected to the
196 * native function for Timesync (ClockOut)
198 esdp |= IXGBE_ESDP_SDP0_DIR |
199 IXGBE_ESDP_SDP0_NATIVE;
201 /* enable the Clock Out feature on SDP0, and allow
202 * interrupts to occur when the pin changes
204 tsauxc = IXGBE_TSAUXC_EN_CLK |
205 IXGBE_TSAUXC_SYNCLK |
206 IXGBE_TSAUXC_SDP0_INT;
208 /* clock period (or pulse length) */
209 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
210 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
212 /* Account for the cyclecounter wrap-around value by
213 * using the converted ns value of the current time to
214 * check for when the next aligned second would occur.
216 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
217 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
218 ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge);
220 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
221 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
223 /* specify the initial clock start time */
224 trgttiml = (u32)clock_edge;
225 trgttimh = (u32)(clock_edge >> 32);
227 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
228 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
229 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
230 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
232 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
233 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
235 IXGBE_WRITE_FLUSH(hw);
239 * ixgbe_ptp_read_X550 - read cycle counter value
240 * @hw_cc: cyclecounter structure
242 * This function reads SYSTIME registers. It is called by the cyclecounter
243 * structure to convert from internal representation into nanoseconds. We need
244 * this for X550 since some skews do not have expected clock frequency and
245 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
246 * "cycles", rather than seconds and nanoseconds.
248 static cycle_t ixgbe_ptp_read_X550(const struct cyclecounter *hw_cc)
250 struct ixgbe_adapter *adapter =
251 container_of(hw_cc, struct ixgbe_adapter, hw_cc);
252 struct ixgbe_hw *hw = &adapter->hw;
253 struct timespec64 ts;
255 /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
256 * Some revisions of hardware run at a higher frequency and so the
257 * cycles are not guaranteed to be nanoseconds. The timespec64 created
258 * here is used for its math/conversions but does not necessarily
259 * represent nominal time.
261 * It should be noted that this cyclecounter will overflow at a
262 * non-bitmask field since we have to convert our billions of cycles
263 * into an actual cycles count. This results in some possible weird
264 * situations at high cycle counter stamps. However given that 32 bits
265 * of "seconds" is ~138 years this isn't a problem. Even at the
266 * increased frequency of some revisions, this is still ~103 years.
267 * Since the SYSTIME values start at 0 and we never write them, it is
268 * highly unlikely for the cyclecounter to overflow in practice.
270 IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
271 ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
272 ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
274 return (u64)timespec64_to_ns(&ts);
278 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
279 * @cc: the cyclecounter structure
281 * this function reads the cyclecounter registers and is called by the
282 * cyclecounter structure used to construct a ns counter from the
283 * arbitrary fixed point registers
285 static cycle_t ixgbe_ptp_read_82599(const struct cyclecounter *cc)
287 struct ixgbe_adapter *adapter =
288 container_of(cc, struct ixgbe_adapter, hw_cc);
289 struct ixgbe_hw *hw = &adapter->hw;
292 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
293 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
299 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
300 * @adapter: private adapter structure
301 * @hwtstamp: stack timestamp structure
302 * @systim: unsigned 64bit system time value
304 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
305 * which can be used by the stack's ptp functions.
307 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
308 * registers. However, it does not need to protect against the Rx or Tx
309 * timestamp registers, as there can't be a new timestamp until the old one is
310 * unlatched by reading.
312 * In addition to the timestamp in hardware, some controllers need a software
313 * overflow cyclecounter, and this function takes this into account as well.
315 static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
316 struct skb_shared_hwtstamps *hwtstamp,
320 struct timespec64 systime;
323 memset(hwtstamp, 0, sizeof(*hwtstamp));
325 switch (adapter->hw.mac.type) {
326 /* X550 and later hardware supposedly represent time using a seconds
327 * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
328 * to convert the timestamp into cycles before it can be fed to the
329 * cyclecounter. We need an actual cyclecounter because some revisions
330 * of hardware run at a higher frequency and thus the counter does
331 * not represent seconds/nanoseconds. Instead it can be thought of as
332 * cycles and billions of cycles.
335 case ixgbe_mac_X550EM_x:
336 case ixgbe_mac_x550em_a:
337 /* Upper 32 bits represent billions of cycles, lower 32 bits
338 * represent cycles. However, we use timespec64_to_ns for the
339 * correct math even though the units haven't been corrected
342 systime.tv_sec = timestamp >> 32;
343 systime.tv_nsec = timestamp & 0xFFFFFFFF;
345 timestamp = timespec64_to_ns(&systime);
351 spin_lock_irqsave(&adapter->tmreg_lock, flags);
352 ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
353 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
355 hwtstamp->hwtstamp = ns_to_ktime(ns);
359 * ixgbe_ptp_adjfreq_82599
360 * @ptp: the ptp clock structure
361 * @ppb: parts per billion adjustment from base
363 * adjust the frequency of the ptp cycle counter by the
364 * indicated ppb from the base frequency.
366 static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb)
368 struct ixgbe_adapter *adapter =
369 container_of(ptp, struct ixgbe_adapter, ptp_caps);
370 struct ixgbe_hw *hw = &adapter->hw;
381 incval = ACCESS_ONCE(adapter->base_incval);
385 diff = div_u64(freq, 1000000000ULL);
387 incval = neg_adj ? (incval - diff) : (incval + diff);
389 switch (hw->mac.type) {
391 if (incval > 0xFFFFFFFFULL)
392 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
393 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
395 case ixgbe_mac_82599EB:
396 if (incval > 0x00FFFFFFULL)
397 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
398 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
399 BIT(IXGBE_INCPER_SHIFT_82599) |
400 ((u32)incval & 0x00FFFFFFUL));
410 * ixgbe_ptp_adjfreq_X550
411 * @ptp: the ptp clock structure
412 * @ppb: parts per billion adjustment from base
414 * adjust the frequency of the SYSTIME registers by the indicated ppb from base
417 static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb)
419 struct ixgbe_adapter *adapter =
420 container_of(ptp, struct ixgbe_adapter, ptp_caps);
421 struct ixgbe_hw *hw = &adapter->hw;
423 u64 rate = IXGBE_X550_BASE_PERIOD;
431 rate = div_u64(rate, 1000000000ULL);
433 /* warn if rate is too large */
434 if (rate >= INCVALUE_MASK)
435 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
437 inca = rate & INCVALUE_MASK;
441 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
448 * @ptp: the ptp clock structure
449 * @delta: offset to adjust the cycle counter by
451 * adjust the timer by resetting the timecounter structure.
453 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
455 struct ixgbe_adapter *adapter =
456 container_of(ptp, struct ixgbe_adapter, ptp_caps);
459 spin_lock_irqsave(&adapter->tmreg_lock, flags);
460 timecounter_adjtime(&adapter->hw_tc, delta);
461 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
463 if (adapter->ptp_setup_sdp)
464 adapter->ptp_setup_sdp(adapter);
471 * @ptp: the ptp clock structure
472 * @ts: timespec structure to hold the current time value
474 * read the timecounter and return the correct value on ns,
475 * after converting it into a struct timespec.
477 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
479 struct ixgbe_adapter *adapter =
480 container_of(ptp, struct ixgbe_adapter, ptp_caps);
484 spin_lock_irqsave(&adapter->tmreg_lock, flags);
485 ns = timecounter_read(&adapter->hw_tc);
486 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
488 *ts = ns_to_timespec64(ns);
495 * @ptp: the ptp clock structure
496 * @ts: the timespec containing the new time for the cycle counter
498 * reset the timecounter to use a new base value instead of the kernel
501 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
502 const struct timespec64 *ts)
504 struct ixgbe_adapter *adapter =
505 container_of(ptp, struct ixgbe_adapter, ptp_caps);
507 u64 ns = timespec64_to_ns(ts);
509 /* reset the timecounter */
510 spin_lock_irqsave(&adapter->tmreg_lock, flags);
511 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
512 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
514 if (adapter->ptp_setup_sdp)
515 adapter->ptp_setup_sdp(adapter);
520 * ixgbe_ptp_feature_enable
521 * @ptp: the ptp clock structure
522 * @rq: the requested feature to change
523 * @on: whether to enable or disable the feature
525 * enable (or disable) ancillary features of the phc subsystem.
526 * our driver only supports the PPS feature on the X540
528 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
529 struct ptp_clock_request *rq, int on)
531 struct ixgbe_adapter *adapter =
532 container_of(ptp, struct ixgbe_adapter, ptp_caps);
535 * When PPS is enabled, unmask the interrupt for the ClockOut
536 * feature, so that the interrupt handler can send the PPS
537 * event when the clock SDP triggers. Clear mask when PPS is
540 if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
544 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
546 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
548 adapter->ptp_setup_sdp(adapter);
553 * ixgbe_ptp_check_pps_event
554 * @adapter: the private adapter structure
556 * This function is called by the interrupt routine when checking for
557 * interrupts. It will check and handle a pps event.
559 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
561 struct ixgbe_hw *hw = &adapter->hw;
562 struct ptp_clock_event event;
564 event.type = PTP_CLOCK_PPS;
566 /* this check is necessary in case the interrupt was enabled via some
567 * alternative means (ex. debug_fs). Better to check here than
568 * everywhere that calls this function.
570 if (!adapter->ptp_clock)
573 switch (hw->mac.type) {
575 ptp_clock_event(adapter->ptp_clock, &event);
583 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
584 * @adapter: private adapter struct
586 * this watchdog task periodically reads the timecounter
587 * in order to prevent missing when the system time registers wrap
588 * around. This needs to be run approximately twice a minute.
590 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
592 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
593 IXGBE_OVERFLOW_PERIOD);
594 struct timespec64 ts;
597 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
598 adapter->last_overflow_check = jiffies;
603 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
604 * @adapter: private network adapter structure
606 * this watchdog task is scheduled to detect error case where hardware has
607 * dropped an Rx packet that was timestamped when the ring is full. The
608 * particular error is rare but leaves the device in a state unable to timestamp
609 * any future packets.
611 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
613 struct ixgbe_hw *hw = &adapter->hw;
614 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
615 struct ixgbe_ring *rx_ring;
616 unsigned long rx_event;
619 /* if we don't have a valid timestamp in the registers, just update the
620 * timeout counter and exit
622 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
623 adapter->last_rx_ptp_check = jiffies;
627 /* determine the most recent watchdog or rx_timestamp event */
628 rx_event = adapter->last_rx_ptp_check;
629 for (n = 0; n < adapter->num_rx_queues; n++) {
630 rx_ring = adapter->rx_ring[n];
631 if (time_after(rx_ring->last_rx_timestamp, rx_event))
632 rx_event = rx_ring->last_rx_timestamp;
635 /* only need to read the high RXSTMP register to clear the lock */
636 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
637 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
638 adapter->last_rx_ptp_check = jiffies;
640 adapter->rx_hwtstamp_cleared++;
641 e_warn(drv, "clearing RX Timestamp hang\n");
646 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
647 * @adapter: the private adapter structure
649 * This function should be called whenever the state related to a Tx timestamp
650 * needs to be cleared. This helps ensure that all related bits are reset for
651 * the next Tx timestamp event.
653 static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
655 struct ixgbe_hw *hw = &adapter->hw;
657 IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
658 if (adapter->ptp_tx_skb) {
659 dev_kfree_skb_any(adapter->ptp_tx_skb);
660 adapter->ptp_tx_skb = NULL;
662 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
666 * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
667 * @adapter: private network adapter structure
669 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
671 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
672 IXGBE_PTP_TX_TIMEOUT);
674 if (!adapter->ptp_tx_skb)
677 if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
680 /* If we haven't received a timestamp within the timeout, it is
681 * reasonable to assume that it will never occur, so we can unlock the
682 * timestamp bit when this occurs.
685 cancel_work_sync(&adapter->ptp_tx_work);
686 ixgbe_ptp_clear_tx_timestamp(adapter);
687 adapter->tx_hwtstamp_timeouts++;
688 e_warn(drv, "clearing Tx timestamp hang\n");
693 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
694 * @adapter: the private adapter struct
696 * if the timestamp is valid, we convert it into the timecounter ns
697 * value, then store that result into the shhwtstamps structure which
698 * is passed up the network stack
700 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
702 struct ixgbe_hw *hw = &adapter->hw;
703 struct skb_shared_hwtstamps shhwtstamps;
706 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
707 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
709 ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
710 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
712 ixgbe_ptp_clear_tx_timestamp(adapter);
716 * ixgbe_ptp_tx_hwtstamp_work
717 * @work: pointer to the work struct
719 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
720 * timestamp has been taken for the current skb. It is necessary, because the
721 * descriptor's "done" bit does not correlate with the timestamp event.
723 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
725 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
727 struct ixgbe_hw *hw = &adapter->hw;
728 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
729 IXGBE_PTP_TX_TIMEOUT);
732 /* we have to have a valid skb to poll for a timestamp */
733 if (!adapter->ptp_tx_skb) {
734 ixgbe_ptp_clear_tx_timestamp(adapter);
738 /* stop polling once we have a valid timestamp */
739 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
740 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
741 ixgbe_ptp_tx_hwtstamp(adapter);
746 ixgbe_ptp_clear_tx_timestamp(adapter);
747 adapter->tx_hwtstamp_timeouts++;
748 e_warn(drv, "clearing Tx Timestamp hang\n");
750 /* reschedule to keep checking if it's not available yet */
751 schedule_work(&adapter->ptp_tx_work);
756 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
757 * @q_vector: structure containing interrupt and ring information
760 * This function will be called by the Rx routine of the timestamp for this
761 * packet is stored in the buffer. The value is stored in little endian format
762 * starting at the end of the packet data.
764 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
769 /* copy the bits out of the skb, and then trim the skb length */
770 skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val,
772 __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
774 /* The timestamp is recorded in little endian format, and is stored at
775 * the end of the packet.
777 * DWORD: N N + 1 N + 2
778 * Field: End of Packet SYSTIMH SYSTIML
780 ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
781 le64_to_cpu(regval));
785 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
786 * @q_vector: structure containing interrupt and ring information
787 * @skb: particular skb to send timestamp with
789 * if the timestamp is valid, we convert it into the timecounter ns
790 * value, then store that result into the shhwtstamps structure which
791 * is passed up the network stack
793 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
796 struct ixgbe_adapter *adapter;
801 /* we cannot process timestamps on a ring without a q_vector */
802 if (!q_vector || !q_vector->adapter)
805 adapter = q_vector->adapter;
808 /* Read the tsyncrxctl register afterwards in order to prevent taking an
809 * I/O hit on every packet.
812 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
813 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
816 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
817 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
819 ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
822 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
824 struct hwtstamp_config *config = &adapter->tstamp_config;
826 return copy_to_user(ifr->ifr_data, config,
827 sizeof(*config)) ? -EFAULT : 0;
831 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
832 * @adapter: the private ixgbe adapter structure
833 * @config: the hwtstamp configuration requested
835 * Outgoing time stamping can be enabled and disabled. Play nice and
836 * disable it when requested, although it shouldn't cause any overhead
837 * when no packet needs it. At most one packet in the queue may be
838 * marked for time stamping, otherwise it would be impossible to tell
839 * for sure to which packet the hardware time stamp belongs.
841 * Incoming time stamping has to be configured via the hardware
842 * filters. Not all combinations are supported, in particular event
843 * type has to be specified. Matching the kind of event packet is
844 * not supported, with the exception of "all V2 events regardless of
847 * Since hardware always timestamps Path delay packets when timestamping V2
848 * packets, regardless of the type specified in the register, only use V2
849 * Event mode. This more accurately tells the user what the hardware is going
852 * Note: this may modify the hwtstamp configuration towards a more general
853 * mode, if required to support the specifically requested mode.
855 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
856 struct hwtstamp_config *config)
858 struct ixgbe_hw *hw = &adapter->hw;
859 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
860 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
861 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
865 /* reserved for future extensions */
869 switch (config->tx_type) {
870 case HWTSTAMP_TX_OFF:
878 switch (config->rx_filter) {
879 case HWTSTAMP_FILTER_NONE:
882 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
883 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
885 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
886 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
887 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
888 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
889 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
891 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
892 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
893 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
894 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
895 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
897 case HWTSTAMP_FILTER_PTP_V2_EVENT:
898 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
899 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
900 case HWTSTAMP_FILTER_PTP_V2_SYNC:
901 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
902 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
903 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
904 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
905 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
906 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
908 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
909 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
910 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
912 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
913 case HWTSTAMP_FILTER_ALL:
914 /* The X550 controller is capable of timestamping all packets,
915 * which allows it to accept any filter.
917 if (hw->mac.type >= ixgbe_mac_X550) {
918 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
919 config->rx_filter = HWTSTAMP_FILTER_ALL;
920 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
926 * register RXMTRL must be set in order to do V1 packets,
927 * therefore it is not possible to time stamp both V1 Sync and
928 * Delay_Req messages and hardware does not support
929 * timestamping all packets => return error
931 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
932 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
933 config->rx_filter = HWTSTAMP_FILTER_NONE;
937 if (hw->mac.type == ixgbe_mac_82598EB) {
938 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
939 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
940 if (tsync_rx_ctl | tsync_tx_ctl)
945 /* Per-packet timestamping only works if the filter is set to all
946 * packets. Since this is desired, always timestamp all packets as long
947 * as any Rx filter was configured.
949 switch (hw->mac.type) {
951 case ixgbe_mac_X550EM_x:
952 case ixgbe_mac_x550em_a:
953 /* enable timestamping all packets only if at least some
954 * packets were requested. Otherwise, play nice and disable
957 if (config->rx_filter == HWTSTAMP_FILTER_NONE)
960 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
961 IXGBE_TSYNCRXCTL_TYPE_ALL |
962 IXGBE_TSYNCRXCTL_TSIP_UT_EN;
963 config->rx_filter = HWTSTAMP_FILTER_ALL;
964 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
965 adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
972 /* define ethertype filter for timestamping L2 packets */
974 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
975 (IXGBE_ETQF_FILTER_EN | /* enable filter */
976 IXGBE_ETQF_1588 | /* enable timestamping */
977 ETH_P_1588)); /* 1588 eth protocol type */
979 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
981 /* enable/disable TX */
982 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
983 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
984 regval |= tsync_tx_ctl;
985 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
987 /* enable/disable RX */
988 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
989 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
990 regval |= tsync_rx_ctl;
991 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
993 /* define which PTP packets are time stamped */
994 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
996 IXGBE_WRITE_FLUSH(hw);
998 /* clear TX/RX time stamp registers, just to be sure */
999 ixgbe_ptp_clear_tx_timestamp(adapter);
1000 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
1006 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
1007 * @adapter: pointer to adapter struct
1008 * @ifreq: ioctl data
1010 * Set hardware to requested mode. If unsupported, return an error with no
1011 * changes. Otherwise, store the mode for future reference.
1013 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1015 struct hwtstamp_config config;
1018 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1021 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1025 /* save these settings for future reference */
1026 memcpy(&adapter->tstamp_config, &config,
1027 sizeof(adapter->tstamp_config));
1029 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1033 static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1034 u32 *shift, u32 *incval)
1037 * Scale the NIC cycle counter by a large factor so that
1038 * relatively small corrections to the frequency can be added
1039 * or subtracted. The drawbacks of a large factor include
1040 * (a) the clock register overflows more quickly, (b) the cycle
1041 * counter structure must be able to convert the systime value
1042 * to nanoseconds using only a multiplier and a right-shift,
1043 * and (c) the value must fit within the timinca register space
1044 * => math based on internal DMA clock rate and available bits
1046 * Note that when there is no link, internal DMA clock is same as when
1047 * link speed is 10Gb. Set the registers correctly even when link is
1048 * down to preserve the clock setting
1050 switch (adapter->link_speed) {
1051 case IXGBE_LINK_SPEED_100_FULL:
1052 *shift = IXGBE_INCVAL_SHIFT_100;
1053 *incval = IXGBE_INCVAL_100;
1055 case IXGBE_LINK_SPEED_1GB_FULL:
1056 *shift = IXGBE_INCVAL_SHIFT_1GB;
1057 *incval = IXGBE_INCVAL_1GB;
1059 case IXGBE_LINK_SPEED_10GB_FULL:
1061 *shift = IXGBE_INCVAL_SHIFT_10GB;
1062 *incval = IXGBE_INCVAL_10GB;
1068 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1069 * @adapter: pointer to the adapter structure
1071 * This function should be called to set the proper values for the TIMINCA
1072 * register and tell the cyclecounter structure what the tick rate of SYSTIME
1073 * is. It does not directly modify SYSTIME registers or the timecounter
1074 * structure. It should be called whenever a new TIMINCA value is necessary,
1075 * such as during initialization or when the link speed changes.
1077 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1079 struct ixgbe_hw *hw = &adapter->hw;
1080 struct cyclecounter cc;
1081 unsigned long flags;
1086 /* For some of the boards below this mask is technically incorrect.
1087 * The timestamp mask overflows at approximately 61bits. However the
1088 * particular hardware does not overflow on an even bitmask value.
1089 * Instead, it overflows due to conversion of upper 32bits billions of
1090 * cycles. Timecounters are not really intended for this purpose so
1091 * they do not properly function if the overflow point isn't 2^N-1.
1092 * However, the actual SYSTIME values in question take ~138 years to
1093 * overflow. In practice this means they won't actually overflow. A
1094 * proper fix to this problem would require modification of the
1095 * timecounter delta calculations.
1097 cc.mask = CLOCKSOURCE_MASK(64);
1101 switch (hw->mac.type) {
1102 case ixgbe_mac_X550EM_x:
1103 /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1104 * designed to represent seconds and nanoseconds when this is
1105 * the case. However, some revisions of hardware have a 400Mhz
1106 * clock and we have to compensate for this frequency
1107 * variation using corrected mult and shift values.
1109 fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1110 if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1115 case ixgbe_mac_x550em_a:
1116 case ixgbe_mac_X550:
1117 cc.read = ixgbe_ptp_read_X550;
1119 /* enable SYSTIME counter */
1120 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1121 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1122 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1123 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1124 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1125 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1126 IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1127 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1129 IXGBE_WRITE_FLUSH(hw);
1131 case ixgbe_mac_X540:
1132 cc.read = ixgbe_ptp_read_82599;
1134 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1135 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1137 case ixgbe_mac_82599EB:
1138 cc.read = ixgbe_ptp_read_82599;
1140 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1141 incval >>= IXGBE_INCVAL_SHIFT_82599;
1142 cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1143 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1144 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1147 /* other devices aren't supported */
1151 /* update the base incval used to calculate frequency adjustment */
1152 ACCESS_ONCE(adapter->base_incval) = incval;
1155 /* need lock to prevent incorrect read while modifying cyclecounter */
1156 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1157 memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1158 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1163 * @adapter: the ixgbe private board structure
1165 * When the MAC resets, all the hardware bits for timesync are reset. This
1166 * function is used to re-enable the device for PTP based on current settings.
1167 * We do lose the current clock time, so just reset the cyclecounter to the
1168 * system real clock time.
1170 * This function will maintain hwtstamp_config settings, and resets the SDP
1171 * output if it was enabled.
1173 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1175 struct ixgbe_hw *hw = &adapter->hw;
1176 unsigned long flags;
1178 /* reset the hardware timestamping mode */
1179 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1181 /* 82598 does not support PTP */
1182 if (hw->mac.type == ixgbe_mac_82598EB)
1185 ixgbe_ptp_start_cyclecounter(adapter);
1187 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1188 timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1189 ktime_to_ns(ktime_get_real()));
1190 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1192 adapter->last_overflow_check = jiffies;
1194 /* Now that the shift has been calculated and the systime
1195 * registers reset, (re-)enable the Clock out feature
1197 if (adapter->ptp_setup_sdp)
1198 adapter->ptp_setup_sdp(adapter);
1202 * ixgbe_ptp_create_clock
1203 * @adapter: the ixgbe private adapter structure
1205 * This function performs setup of the user entry point function table and
1206 * initializes the PTP clock device, which is used to access the clock-like
1207 * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1208 * reuse a previously initialized clock (such as during a suspend/resume
1211 static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1213 struct net_device *netdev = adapter->netdev;
1216 /* do nothing if we already have a clock device */
1217 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1220 switch (adapter->hw.mac.type) {
1221 case ixgbe_mac_X540:
1222 snprintf(adapter->ptp_caps.name,
1223 sizeof(adapter->ptp_caps.name),
1224 "%s", netdev->name);
1225 adapter->ptp_caps.owner = THIS_MODULE;
1226 adapter->ptp_caps.max_adj = 250000000;
1227 adapter->ptp_caps.n_alarm = 0;
1228 adapter->ptp_caps.n_ext_ts = 0;
1229 adapter->ptp_caps.n_per_out = 0;
1230 adapter->ptp_caps.pps = 1;
1231 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1232 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1233 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1234 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1235 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1236 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540;
1238 case ixgbe_mac_82599EB:
1239 snprintf(adapter->ptp_caps.name,
1240 sizeof(adapter->ptp_caps.name),
1241 "%s", netdev->name);
1242 adapter->ptp_caps.owner = THIS_MODULE;
1243 adapter->ptp_caps.max_adj = 250000000;
1244 adapter->ptp_caps.n_alarm = 0;
1245 adapter->ptp_caps.n_ext_ts = 0;
1246 adapter->ptp_caps.n_per_out = 0;
1247 adapter->ptp_caps.pps = 0;
1248 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1249 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1250 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1251 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1252 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1254 case ixgbe_mac_X550:
1255 case ixgbe_mac_X550EM_x:
1256 case ixgbe_mac_x550em_a:
1257 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1258 adapter->ptp_caps.owner = THIS_MODULE;
1259 adapter->ptp_caps.max_adj = 30000000;
1260 adapter->ptp_caps.n_alarm = 0;
1261 adapter->ptp_caps.n_ext_ts = 0;
1262 adapter->ptp_caps.n_per_out = 0;
1263 adapter->ptp_caps.pps = 0;
1264 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550;
1265 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1266 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime;
1267 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1268 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1269 adapter->ptp_setup_sdp = NULL;
1272 adapter->ptp_clock = NULL;
1273 adapter->ptp_setup_sdp = NULL;
1277 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1278 &adapter->pdev->dev);
1279 if (IS_ERR(adapter->ptp_clock)) {
1280 err = PTR_ERR(adapter->ptp_clock);
1281 adapter->ptp_clock = NULL;
1282 e_dev_err("ptp_clock_register failed\n");
1284 } else if (adapter->ptp_clock)
1285 e_dev_info("registered PHC device on %s\n", netdev->name);
1287 /* set default timestamp mode to disabled here. We do this in
1288 * create_clock instead of init, because we don't want to override the
1289 * previous settings during a resume cycle.
1291 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1292 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1299 * @adapter: the ixgbe private adapter structure
1301 * This function performs the required steps for enabling PTP
1302 * support. If PTP support has already been loaded it simply calls the
1303 * cyclecounter init routine and exits.
1305 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1307 /* initialize the spin lock first since we can't control when a user
1308 * will call the entry functions once we have initialized the clock
1311 spin_lock_init(&adapter->tmreg_lock);
1313 /* obtain a PTP device, or re-use an existing device */
1314 if (ixgbe_ptp_create_clock(adapter))
1317 /* we have a clock so we can initialize work now */
1318 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1320 /* reset the PTP related hardware bits */
1321 ixgbe_ptp_reset(adapter);
1323 /* enter the IXGBE_PTP_RUNNING state */
1324 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1330 * ixgbe_ptp_suspend - stop PTP work items
1331 * @ adapter: pointer to adapter struct
1333 * this function suspends PTP activity, and prevents more PTP work from being
1334 * generated, but does not destroy the PTP clock device.
1336 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1338 /* Leave the IXGBE_PTP_RUNNING state. */
1339 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1342 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1343 if (adapter->ptp_setup_sdp)
1344 adapter->ptp_setup_sdp(adapter);
1346 /* ensure that we cancel any pending PTP Tx work item in progress */
1347 cancel_work_sync(&adapter->ptp_tx_work);
1348 ixgbe_ptp_clear_tx_timestamp(adapter);
1352 * ixgbe_ptp_stop - close the PTP device
1353 * @adapter: pointer to adapter struct
1355 * completely destroy the PTP device, should only be called when the device is
1356 * being fully closed.
1358 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1360 /* first, suspend PTP activity */
1361 ixgbe_ptp_suspend(adapter);
1363 /* disable the PTP clock device */
1364 if (adapter->ptp_clock) {
1365 ptp_clock_unregister(adapter->ptp_clock);
1366 adapter->ptp_clock = NULL;
1367 e_dev_info("removed PHC on %s\n",
1368 adapter->netdev->name);