1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 #include <linux/delay.h>
6 #include <linux/iopoll.h>
7 #include <linux/sched.h>
10 #include "ixgbe_phy.h"
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
33 * Returns an error code on error.
35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
42 return ixgbe_get_i2c_ack(hw);
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
50 * Returns an error code on error.
52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
60 return ixgbe_clock_out_i2c_bit(hw, false);
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
68 * Returns one's complement 8-bit sum.
70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
72 u16 sum = add1 + add2;
74 sum = (sum & 0xFF) + (sum >> 8);
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
86 * Returns an error code on error.
88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
119 /* Re-start condition */
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
134 if (ixgbe_clock_out_i2c_bit(hw, false))
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
143 ixgbe_i2c_bus_clear(hw);
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
164 * Returns an error code on error.
166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
208 ixgbe_i2c_bus_clear(hw);
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
226 * Returns true if PHY found
228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
236 if (ixgbe_get_phy_id(hw))
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
251 hw->phy.type = ixgbe_phy_generic;
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
261 * Determines the physical layer module found on the current adapter.
263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
265 u32 status = -EFAULT;
268 if (!hw->phy.phy_semaphore_mask) {
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
275 if (hw->phy.type != ixgbe_phy_unknown)
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = (hw->phy.nw_mng_if_sel &
280 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 if (ixgbe_probe_phy(hw, phy_addr))
288 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 if (ixgbe_probe_phy(hw, phy_addr)) {
295 /* Certain media types do not have a phy so an address will not
296 * be found and the code will take this path. Caller has to
297 * decide if it is an error or not.
300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307 * @hw: pointer to the hardware structure
309 * This function checks the MMNGC.MNG_VETO bit to see if there are
310 * any constraints on link from manageability. For MAC's that don't
311 * have this bit just return false since the link can not be blocked
314 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
318 /* If we don't have this bit, it can't be blocking */
319 if (hw->mac.type == ixgbe_mac_82598EB)
322 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 hw_dbg(hw, "MNG_VETO bit detected.\n");
332 * ixgbe_get_phy_id - Get the phy type
333 * @hw: pointer to hardware structure
336 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
342 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
346 hw->phy.id = (u32)(phy_id_high << 16);
347 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
349 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
356 * ixgbe_get_phy_type_from_id - Get the phy type
357 * @phy_id: hardware phy id
360 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
362 enum ixgbe_phy_type phy_type;
366 phy_type = ixgbe_phy_tn;
371 phy_type = ixgbe_phy_aq;
374 phy_type = ixgbe_phy_qt;
377 phy_type = ixgbe_phy_nl;
381 phy_type = ixgbe_phy_x550em_ext_t;
384 phy_type = ixgbe_phy_unknown;
392 * ixgbe_reset_phy_generic - Performs a PHY reset
393 * @hw: pointer to hardware structure
395 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
401 if (hw->phy.type == ixgbe_phy_unknown)
402 status = ixgbe_identify_phy_generic(hw);
404 if (status != 0 || hw->phy.type == ixgbe_phy_none)
407 /* Don't reset PHY if it's shut down due to overtemp. */
408 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
411 /* Blocked by MNG FW so bail */
412 if (ixgbe_check_reset_blocked(hw))
416 * Perform soft PHY reset to the PHY_XS.
417 * This will cause a soft reset to the PHY
419 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
424 * Poll for reset bit to self-clear indicating reset is complete.
425 * Some PHYs could take up to 3 seconds to complete and need about
426 * 1.7 usec delay after the reset is complete.
428 for (i = 0; i < 30; i++) {
430 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
431 status = hw->phy.ops.read_reg(hw,
432 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
433 MDIO_MMD_PMAPMD, &ctrl);
437 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
442 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
443 MDIO_MMD_PHYXS, &ctrl);
447 if (!(ctrl & MDIO_CTRL1_RESET)) {
454 if (ctrl & MDIO_CTRL1_RESET) {
455 hw_dbg(hw, "PHY reset polling failed to complete.\n");
463 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
465 * @hw: pointer to hardware structure
466 * @reg_addr: 32 bit address of PHY register to read
467 * @device_type: 5 bit device type
468 * @phy_data: Pointer to read data from PHY register
470 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
473 u32 i, data, command;
475 /* Setup and write the address cycle command */
476 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
477 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
478 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
479 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
481 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
483 /* Check every 10 usec to see if the address cycle completed.
484 * The MDI Command bit will clear when the operation is
487 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
490 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
491 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
496 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
497 hw_dbg(hw, "PHY address command did not complete.\n");
501 /* Address cycle complete, setup and write the read
504 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
505 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
506 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
507 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
509 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
511 /* Check every 10 usec to see if the address cycle
512 * completed. The MDI Command bit will clear when the
513 * operation is complete
515 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
518 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
519 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
523 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
524 hw_dbg(hw, "PHY read command didn't complete\n");
528 /* Read operation is complete. Get the data
531 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
532 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
533 *phy_data = (u16)(data);
539 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
540 * using the SWFW lock - this function is needed in most cases
541 * @hw: pointer to hardware structure
542 * @reg_addr: 32 bit address of PHY register to read
543 * @device_type: 5 bit device type
544 * @phy_data: Pointer to read data from PHY register
546 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
547 u32 device_type, u16 *phy_data)
550 u32 gssr = hw->phy.phy_semaphore_mask;
552 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
553 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
555 hw->mac.ops.release_swfw_sync(hw, gssr);
564 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
566 * @hw: pointer to hardware structure
567 * @reg_addr: 32 bit PHY register to write
568 * @device_type: 5 bit device type
569 * @phy_data: Data to write to the PHY register
571 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
572 u32 device_type, u16 phy_data)
576 /* Put the data in the MDI single read and write data register*/
577 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
579 /* Setup and write the address cycle command */
580 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
581 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
582 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
583 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
585 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
588 * Check every 10 usec to see if the address cycle completed.
589 * The MDI Command bit will clear when the operation is
592 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
595 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
596 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
600 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
601 hw_dbg(hw, "PHY address cmd didn't complete\n");
606 * Address cycle complete, setup and write the write
609 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
610 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
611 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
612 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
614 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
616 /* Check every 10 usec to see if the address cycle
617 * completed. The MDI Command bit will clear when the
618 * operation is complete
620 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
623 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
624 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
628 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
629 hw_dbg(hw, "PHY write cmd didn't complete\n");
637 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
638 * using SWFW lock- this function is needed in most cases
639 * @hw: pointer to hardware structure
640 * @reg_addr: 32 bit PHY register to write
641 * @device_type: 5 bit device type
642 * @phy_data: Data to write to the PHY register
644 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
645 u32 device_type, u16 phy_data)
648 u32 gssr = hw->phy.phy_semaphore_mask;
650 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
651 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
653 hw->mac.ops.release_swfw_sync(hw, gssr);
661 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
664 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
665 * @hw: pointer to hardware structure
666 * @cmd: command register value to write
668 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
670 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
672 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
673 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
674 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
678 * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
679 * @hw: pointer to hardware structure
681 * @regnum: register number
682 * @gssr: semaphore flags to acquire
684 static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
685 int regnum, u32 gssr)
690 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
693 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
694 if (regnum & MII_ADDR_C45) {
695 hwaddr |= regnum & GENMASK(21, 0);
696 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
698 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
699 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
700 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
703 data = ixgbe_msca_cmd(hw, cmd);
705 goto mii_bus_read_done;
707 /* For a clause 45 access the address cycle just completed, we still
708 * need to do the read command, otherwise just get the data
710 if (!(regnum & MII_ADDR_C45))
711 goto do_mii_bus_read;
713 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
714 data = ixgbe_msca_cmd(hw, cmd);
716 goto mii_bus_read_done;
719 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
720 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
723 hw->mac.ops.release_swfw_sync(hw, gssr);
728 * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
729 * @hw: pointer to hardware structure
731 * @regnum: register number
732 * @val: value to write
733 * @gssr: semaphore flags to acquire
735 static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
736 int regnum, u16 val, u32 gssr)
741 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
744 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
746 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
747 if (regnum & MII_ADDR_C45) {
748 hwaddr |= regnum & GENMASK(21, 0);
749 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
751 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
752 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
753 IXGBE_MSCA_MDI_COMMAND;
756 /* For clause 45 this is an address cycle, for clause 22 this is the
759 err = ixgbe_msca_cmd(hw, cmd);
760 if (err < 0 || !(regnum & MII_ADDR_C45))
761 goto mii_bus_write_done;
763 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
764 err = ixgbe_msca_cmd(hw, cmd);
767 hw->mac.ops.release_swfw_sync(hw, gssr);
772 * ixgbe_mii_bus_read - Read a clause 22/45 register
773 * @bus: pointer to mii_bus structure which points to our driver private
775 * @regnum: register number
777 static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
779 struct ixgbe_adapter *adapter = bus->priv;
780 struct ixgbe_hw *hw = &adapter->hw;
781 u32 gssr = hw->phy.phy_semaphore_mask;
783 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
787 * ixgbe_mii_bus_write - Write a clause 22/45 register
788 * @bus: pointer to mii_bus structure which points to our driver private
790 * @regnum: register number
791 * @val: value to write
793 static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
796 struct ixgbe_adapter *adapter = bus->priv;
797 struct ixgbe_hw *hw = &adapter->hw;
798 u32 gssr = hw->phy.phy_semaphore_mask;
800 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
804 * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
805 * @bus: pointer to mii_bus structure which points to our driver private
807 * @regnum: register number
809 static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
812 struct ixgbe_adapter *adapter = bus->priv;
813 struct ixgbe_hw *hw = &adapter->hw;
814 u32 gssr = hw->phy.phy_semaphore_mask;
816 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
817 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
821 * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
822 * @bus: pointer to mii_bus structure which points to our driver private
824 * @regnum: register number
825 * @val: value to write
827 static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
830 struct ixgbe_adapter *adapter = bus->priv;
831 struct ixgbe_hw *hw = &adapter->hw;
832 u32 gssr = hw->phy.phy_semaphore_mask;
834 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
835 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
839 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
840 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
842 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
843 * on domain 0, bus 0, devfn = 'devfn'
845 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
847 struct pci_dev *rp_pdev;
850 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
851 if (rp_pdev && rp_pdev->subordinate) {
852 bus = rp_pdev->subordinate->number;
853 pci_dev_put(rp_pdev);
854 return pci_get_domain_bus_and_slot(0, bus, 0);
857 pci_dev_put(rp_pdev);
862 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
863 * @hw: pointer to hardware structure
865 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
866 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
867 * but we only want to register one MDIO bus.
869 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
871 struct ixgbe_adapter *adapter = hw->back;
872 struct pci_dev *pdev = adapter->pdev;
873 struct pci_dev *func0_pdev;
874 bool has_mii = false;
876 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
877 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
878 * It's not valid for function 0 to be disabled and function 1 is up,
879 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
880 * of those two root ports
882 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
884 if (func0_pdev == pdev)
888 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
889 if (func0_pdev == pdev)
893 pci_dev_put(func0_pdev);
898 * ixgbe_mii_bus_init - mii_bus structure setup
899 * @hw: pointer to hardware structure
901 * Returns 0 on success, negative on failure
903 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
905 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
907 s32 (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
908 s32 (*read)(struct mii_bus *bus, int addr, int regnum);
909 struct ixgbe_adapter *adapter = hw->back;
910 struct pci_dev *pdev = adapter->pdev;
911 struct device *dev = &adapter->netdev->dev;
914 switch (hw->device_id) {
916 case IXGBE_DEV_ID_X550EM_A_KR:
917 case IXGBE_DEV_ID_X550EM_A_KR_L:
918 case IXGBE_DEV_ID_X550EM_A_SFP_N:
919 case IXGBE_DEV_ID_X550EM_A_SGMII:
920 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
921 case IXGBE_DEV_ID_X550EM_A_10G_T:
922 case IXGBE_DEV_ID_X550EM_A_SFP:
923 case IXGBE_DEV_ID_X550EM_A_1G_T:
924 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
925 if (!ixgbe_x550em_a_has_mii(hw))
927 read = &ixgbe_x550em_a_mii_bus_read;
928 write = &ixgbe_x550em_a_mii_bus_write;
931 read = &ixgbe_mii_bus_read;
932 write = &ixgbe_mii_bus_write;
936 bus = devm_mdiobus_alloc(dev);
943 /* Use the position of the device in the PCI hierarchy as the id */
944 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
947 bus->name = "ixgbe-mdio";
950 bus->phy_mask = GENMASK(31, 0);
952 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
953 * unfortunately that causes some clause 22 frames to be sent with
954 * clause 45 addressing. We don't want that.
956 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
958 adapter->mii_bus = bus;
959 return mdiobus_register(bus);
963 * ixgbe_setup_phy_link_generic - Set and restart autoneg
964 * @hw: pointer to hardware structure
966 * Restart autonegotiation and PHY and waits for completion.
968 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
971 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
972 bool autoneg = false;
973 ixgbe_link_speed speed;
975 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
977 /* Set or unset auto-negotiation 10G advertisement */
978 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
980 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
981 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
982 (speed & IXGBE_LINK_SPEED_10GB_FULL))
983 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
985 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
987 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
988 MDIO_MMD_AN, &autoneg_reg);
990 if (hw->mac.type == ixgbe_mac_X550) {
991 /* Set or unset auto-negotiation 5G advertisement */
992 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
993 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
994 (speed & IXGBE_LINK_SPEED_5GB_FULL))
995 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
997 /* Set or unset auto-negotiation 2.5G advertisement */
998 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
999 if ((hw->phy.autoneg_advertised &
1000 IXGBE_LINK_SPEED_2_5GB_FULL) &&
1001 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1002 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1005 /* Set or unset auto-negotiation 1G advertisement */
1006 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1007 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1008 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1009 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1011 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1012 MDIO_MMD_AN, autoneg_reg);
1014 /* Set or unset auto-negotiation 100M advertisement */
1015 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1017 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1018 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1019 (speed & IXGBE_LINK_SPEED_100_FULL))
1020 autoneg_reg |= ADVERTISE_100FULL;
1022 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1024 /* Blocked by MNG FW so don't reset PHY */
1025 if (ixgbe_check_reset_blocked(hw))
1028 /* Restart PHY autonegotiation and wait for completion */
1029 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1030 MDIO_MMD_AN, &autoneg_reg);
1032 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1034 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1035 MDIO_MMD_AN, autoneg_reg);
1041 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1042 * @hw: pointer to hardware structure
1043 * @speed: new link speed
1044 * @autoneg_wait_to_complete: unused
1046 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1047 ixgbe_link_speed speed,
1048 bool autoneg_wait_to_complete)
1050 /* Clear autoneg_advertised and set new values based on input link
1053 hw->phy.autoneg_advertised = 0;
1055 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1056 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1058 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1059 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1061 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1062 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1064 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1065 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1067 if (speed & IXGBE_LINK_SPEED_100_FULL)
1068 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1070 if (speed & IXGBE_LINK_SPEED_10_FULL)
1071 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1073 /* Setup link based on the new speed settings */
1074 if (hw->phy.ops.setup_link)
1075 hw->phy.ops.setup_link(hw);
1081 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1082 * @hw: pointer to hardware structure
1084 * Determines the supported link capabilities by reading the PHY auto
1085 * negotiation register.
1087 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1092 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1097 if (speed_ability & MDIO_SPEED_10G)
1098 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1099 if (speed_ability & MDIO_PMA_SPEED_1000)
1100 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1101 if (speed_ability & MDIO_PMA_SPEED_100)
1102 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1104 switch (hw->mac.type) {
1105 case ixgbe_mac_X550:
1106 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1107 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1109 case ixgbe_mac_X550EM_x:
1110 case ixgbe_mac_x550em_a:
1111 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1121 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1122 * @hw: pointer to hardware structure
1123 * @speed: pointer to link speed
1124 * @autoneg: boolean auto-negotiation value
1126 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1127 ixgbe_link_speed *speed,
1133 if (!hw->phy.speeds_supported)
1134 status = ixgbe_get_copper_speeds_supported(hw);
1136 *speed = hw->phy.speeds_supported;
1141 * ixgbe_check_phy_link_tnx - Determine link and speed status
1142 * @hw: pointer to hardware structure
1143 * @speed: link speed
1144 * @link_up: status of link
1146 * Reads the VS1 register to determine if link is up and the current speed for
1149 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1154 u32 max_time_out = 10;
1159 /* Initialize speed and link to default case */
1161 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1164 * Check current speed and link status of the PHY register.
1165 * This is a vendor specific register and may have to
1166 * be changed for other copper PHYs.
1168 for (time_out = 0; time_out < max_time_out; time_out++) {
1170 status = hw->phy.ops.read_reg(hw,
1174 phy_link = phy_data &
1175 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1176 phy_speed = phy_data &
1177 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1178 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1181 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1182 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1191 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1192 * @hw: pointer to hardware structure
1194 * Restart autonegotiation and PHY and waits for completion.
1195 * This function always returns success, this is nessary since
1196 * it is called via a function pointer that could call other
1197 * functions that could return an error.
1199 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1201 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1202 bool autoneg = false;
1203 ixgbe_link_speed speed;
1205 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1207 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1208 /* Set or unset auto-negotiation 10G advertisement */
1209 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1213 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1214 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1215 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1217 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1222 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1223 /* Set or unset auto-negotiation 1G advertisement */
1224 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1228 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1229 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1230 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1232 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1237 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1238 /* Set or unset auto-negotiation 100M advertisement */
1239 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1243 autoneg_reg &= ~(ADVERTISE_100FULL |
1245 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1246 autoneg_reg |= ADVERTISE_100FULL;
1248 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1253 /* Blocked by MNG FW so don't reset PHY */
1254 if (ixgbe_check_reset_blocked(hw))
1257 /* Restart PHY autonegotiation and wait for completion */
1258 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1259 MDIO_MMD_AN, &autoneg_reg);
1261 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1263 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1264 MDIO_MMD_AN, autoneg_reg);
1269 * ixgbe_reset_phy_nl - Performs a PHY reset
1270 * @hw: pointer to hardware structure
1272 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1274 u16 phy_offset, control, eword, edata, block_crc;
1275 bool end_data = false;
1276 u16 list_offset, data_offset;
1281 /* Blocked by MNG FW so bail */
1282 if (ixgbe_check_reset_blocked(hw))
1285 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1287 /* reset the PHY and poll for completion */
1288 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1289 (phy_data | MDIO_CTRL1_RESET));
1291 for (i = 0; i < 100; i++) {
1292 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1294 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1296 usleep_range(10000, 20000);
1299 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1300 hw_dbg(hw, "PHY reset did not complete.\n");
1304 /* Get init offsets */
1305 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1310 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1314 * Read control word from PHY init contents offset
1316 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1319 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1320 IXGBE_CONTROL_SHIFT_NL;
1321 edata = eword & IXGBE_DATA_MASK_NL;
1323 case IXGBE_DELAY_NL:
1325 hw_dbg(hw, "DELAY: %d MS\n", edata);
1326 usleep_range(edata * 1000, edata * 2000);
1329 hw_dbg(hw, "DATA:\n");
1331 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1335 for (i = 0; i < edata; i++) {
1336 ret_val = hw->eeprom.ops.read(hw, data_offset,
1340 hw->phy.ops.write_reg(hw, phy_offset,
1341 MDIO_MMD_PMAPMD, eword);
1342 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1348 case IXGBE_CONTROL_NL:
1350 hw_dbg(hw, "CONTROL:\n");
1351 if (edata == IXGBE_CONTROL_EOL_NL) {
1352 hw_dbg(hw, "EOL\n");
1354 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1355 hw_dbg(hw, "SOL\n");
1357 hw_dbg(hw, "Bad control value\n");
1362 hw_dbg(hw, "Bad control type\n");
1370 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1375 * ixgbe_identify_module_generic - Identifies module type
1376 * @hw: pointer to hardware structure
1378 * Determines HW type and calls appropriate function.
1380 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1382 switch (hw->mac.ops.get_media_type(hw)) {
1383 case ixgbe_media_type_fiber:
1384 return ixgbe_identify_sfp_module_generic(hw);
1385 case ixgbe_media_type_fiber_qsfp:
1386 return ixgbe_identify_qsfp_module_generic(hw);
1388 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1396 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1397 * @hw: pointer to hardware structure
1399 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1401 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1403 struct ixgbe_adapter *adapter = hw->back;
1406 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1408 u8 comp_codes_1g = 0;
1409 u8 comp_codes_10g = 0;
1410 u8 oui_bytes[3] = {0, 0, 0};
1413 u16 enforce_sfp = 0;
1415 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1416 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1420 /* LAN ID is needed for sfp_type determination */
1421 hw->mac.ops.set_lan_id(hw);
1423 status = hw->phy.ops.read_i2c_eeprom(hw,
1424 IXGBE_SFF_IDENTIFIER,
1428 goto err_read_i2c_eeprom;
1430 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1431 hw->phy.type = ixgbe_phy_sfp_unsupported;
1434 status = hw->phy.ops.read_i2c_eeprom(hw,
1435 IXGBE_SFF_1GBE_COMP_CODES,
1439 goto err_read_i2c_eeprom;
1441 status = hw->phy.ops.read_i2c_eeprom(hw,
1442 IXGBE_SFF_10GBE_COMP_CODES,
1446 goto err_read_i2c_eeprom;
1447 status = hw->phy.ops.read_i2c_eeprom(hw,
1448 IXGBE_SFF_CABLE_TECHNOLOGY,
1452 goto err_read_i2c_eeprom;
1459 * 3 SFP_DA_CORE0 - 82599-specific
1460 * 4 SFP_DA_CORE1 - 82599-specific
1461 * 5 SFP_SR/LR_CORE0 - 82599-specific
1462 * 6 SFP_SR/LR_CORE1 - 82599-specific
1463 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1464 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1465 * 9 SFP_1g_cu_CORE0 - 82599-specific
1466 * 10 SFP_1g_cu_CORE1 - 82599-specific
1467 * 11 SFP_1g_sx_CORE0 - 82599-specific
1468 * 12 SFP_1g_sx_CORE1 - 82599-specific
1470 if (hw->mac.type == ixgbe_mac_82598EB) {
1471 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1472 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1473 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1474 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1475 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1476 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1478 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1480 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1481 if (hw->bus.lan_id == 0)
1483 ixgbe_sfp_type_da_cu_core0;
1486 ixgbe_sfp_type_da_cu_core1;
1487 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1488 hw->phy.ops.read_i2c_eeprom(
1489 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1492 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1493 if (hw->bus.lan_id == 0)
1495 ixgbe_sfp_type_da_act_lmt_core0;
1498 ixgbe_sfp_type_da_act_lmt_core1;
1501 ixgbe_sfp_type_unknown;
1503 } else if (comp_codes_10g &
1504 (IXGBE_SFF_10GBASESR_CAPABLE |
1505 IXGBE_SFF_10GBASELR_CAPABLE)) {
1506 if (hw->bus.lan_id == 0)
1508 ixgbe_sfp_type_srlr_core0;
1511 ixgbe_sfp_type_srlr_core1;
1512 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1513 if (hw->bus.lan_id == 0)
1515 ixgbe_sfp_type_1g_cu_core0;
1518 ixgbe_sfp_type_1g_cu_core1;
1519 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1520 if (hw->bus.lan_id == 0)
1522 ixgbe_sfp_type_1g_sx_core0;
1525 ixgbe_sfp_type_1g_sx_core1;
1526 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1527 if (hw->bus.lan_id == 0)
1529 ixgbe_sfp_type_1g_lx_core0;
1532 ixgbe_sfp_type_1g_lx_core1;
1534 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1538 if (hw->phy.sfp_type != stored_sfp_type)
1539 hw->phy.sfp_setup_needed = true;
1541 /* Determine if the SFP+ PHY is dual speed or not. */
1542 hw->phy.multispeed_fiber = false;
1543 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1544 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1545 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1546 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1547 hw->phy.multispeed_fiber = true;
1549 /* Determine PHY vendor */
1550 if (hw->phy.type != ixgbe_phy_nl) {
1551 hw->phy.id = identifier;
1552 status = hw->phy.ops.read_i2c_eeprom(hw,
1553 IXGBE_SFF_VENDOR_OUI_BYTE0,
1557 goto err_read_i2c_eeprom;
1559 status = hw->phy.ops.read_i2c_eeprom(hw,
1560 IXGBE_SFF_VENDOR_OUI_BYTE1,
1564 goto err_read_i2c_eeprom;
1566 status = hw->phy.ops.read_i2c_eeprom(hw,
1567 IXGBE_SFF_VENDOR_OUI_BYTE2,
1571 goto err_read_i2c_eeprom;
1574 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1575 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1576 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1578 switch (vendor_oui) {
1579 case IXGBE_SFF_VENDOR_OUI_TYCO:
1580 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1582 ixgbe_phy_sfp_passive_tyco;
1584 case IXGBE_SFF_VENDOR_OUI_FTL:
1585 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1586 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1588 hw->phy.type = ixgbe_phy_sfp_ftl;
1590 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1591 hw->phy.type = ixgbe_phy_sfp_avago;
1593 case IXGBE_SFF_VENDOR_OUI_INTEL:
1594 hw->phy.type = ixgbe_phy_sfp_intel;
1597 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1599 ixgbe_phy_sfp_passive_unknown;
1600 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1602 ixgbe_phy_sfp_active_unknown;
1604 hw->phy.type = ixgbe_phy_sfp_unknown;
1609 /* Allow any DA cable vendor */
1610 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1611 IXGBE_SFF_DA_ACTIVE_CABLE))
1614 /* Verify supported 1G SFP modules */
1615 if (comp_codes_10g == 0 &&
1616 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1617 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1618 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1619 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1620 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1621 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1622 hw->phy.type = ixgbe_phy_sfp_unsupported;
1626 /* Anything else 82598-based is supported */
1627 if (hw->mac.type == ixgbe_mac_82598EB)
1630 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1631 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1632 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1633 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1634 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1635 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1636 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1637 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1638 /* Make sure we're a supported PHY type */
1639 if (hw->phy.type == ixgbe_phy_sfp_intel)
1641 if (hw->allow_unsupported_sfp) {
1642 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1645 hw_dbg(hw, "SFP+ module not supported\n");
1646 hw->phy.type = ixgbe_phy_sfp_unsupported;
1651 err_read_i2c_eeprom:
1652 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1653 if (hw->phy.type != ixgbe_phy_nl) {
1655 hw->phy.type = ixgbe_phy_unknown;
1661 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1662 * @hw: pointer to hardware structure
1664 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1666 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1668 struct ixgbe_adapter *adapter = hw->back;
1671 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1673 u8 comp_codes_1g = 0;
1674 u8 comp_codes_10g = 0;
1675 u8 oui_bytes[3] = {0, 0, 0};
1676 u16 enforce_sfp = 0;
1678 u8 cable_length = 0;
1680 bool active_cable = false;
1682 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1683 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1687 /* LAN ID is needed for sfp_type determination */
1688 hw->mac.ops.set_lan_id(hw);
1690 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1694 goto err_read_i2c_eeprom;
1696 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1697 hw->phy.type = ixgbe_phy_sfp_unsupported;
1701 hw->phy.id = identifier;
1703 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1707 goto err_read_i2c_eeprom;
1709 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1713 goto err_read_i2c_eeprom;
1715 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1716 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1717 if (hw->bus.lan_id == 0)
1718 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1720 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1721 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1722 IXGBE_SFF_10GBASELR_CAPABLE)) {
1723 if (hw->bus.lan_id == 0)
1724 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1726 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1728 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1729 active_cable = true;
1731 if (!active_cable) {
1732 /* check for active DA cables that pre-date
1735 hw->phy.ops.read_i2c_eeprom(hw,
1736 IXGBE_SFF_QSFP_CONNECTOR,
1739 hw->phy.ops.read_i2c_eeprom(hw,
1740 IXGBE_SFF_QSFP_CABLE_LENGTH,
1743 hw->phy.ops.read_i2c_eeprom(hw,
1744 IXGBE_SFF_QSFP_DEVICE_TECH,
1748 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1749 (cable_length > 0) &&
1750 ((device_tech >> 4) ==
1751 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1752 active_cable = true;
1756 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1757 if (hw->bus.lan_id == 0)
1759 ixgbe_sfp_type_da_act_lmt_core0;
1762 ixgbe_sfp_type_da_act_lmt_core1;
1764 /* unsupported module type */
1765 hw->phy.type = ixgbe_phy_sfp_unsupported;
1770 if (hw->phy.sfp_type != stored_sfp_type)
1771 hw->phy.sfp_setup_needed = true;
1773 /* Determine if the QSFP+ PHY is dual speed or not. */
1774 hw->phy.multispeed_fiber = false;
1775 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1776 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1777 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1778 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1779 hw->phy.multispeed_fiber = true;
1781 /* Determine PHY vendor for optical modules */
1782 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1783 IXGBE_SFF_10GBASELR_CAPABLE)) {
1784 status = hw->phy.ops.read_i2c_eeprom(hw,
1785 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1789 goto err_read_i2c_eeprom;
1791 status = hw->phy.ops.read_i2c_eeprom(hw,
1792 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1796 goto err_read_i2c_eeprom;
1798 status = hw->phy.ops.read_i2c_eeprom(hw,
1799 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1803 goto err_read_i2c_eeprom;
1806 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1807 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1808 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1810 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1811 hw->phy.type = ixgbe_phy_qsfp_intel;
1813 hw->phy.type = ixgbe_phy_qsfp_unknown;
1815 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1816 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1817 /* Make sure we're a supported PHY type */
1818 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1820 if (hw->allow_unsupported_sfp) {
1821 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1824 hw_dbg(hw, "QSFP module not supported\n");
1825 hw->phy.type = ixgbe_phy_sfp_unsupported;
1832 err_read_i2c_eeprom:
1833 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1835 hw->phy.type = ixgbe_phy_unknown;
1841 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1842 * @hw: pointer to hardware structure
1843 * @list_offset: offset to the SFP ID list
1844 * @data_offset: offset to the SFP data block
1846 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1847 * so it returns the offsets to the phy init sequence block.
1849 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1854 u16 sfp_type = hw->phy.sfp_type;
1856 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1859 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1862 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1863 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1867 * Limiting active cables and 1G Phys must be initialized as
1870 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1871 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1872 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1873 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1874 sfp_type = ixgbe_sfp_type_srlr_core0;
1875 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1876 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1877 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1878 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1879 sfp_type = ixgbe_sfp_type_srlr_core1;
1881 /* Read offset to PHY init contents */
1882 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1883 hw_err(hw, "eeprom read at %d failed\n",
1884 IXGBE_PHY_INIT_OFFSET_NL);
1888 if ((!*list_offset) || (*list_offset == 0xFFFF))
1891 /* Shift offset to first ID word */
1895 * Find the matching SFP ID in the EEPROM
1896 * and program the init sequence
1898 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1901 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1902 if (sfp_id == sfp_type) {
1904 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1906 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1907 hw_dbg(hw, "SFP+ module not supported\n");
1913 (*list_offset) += 2;
1914 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1919 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1920 hw_dbg(hw, "No matching SFP+ module found\n");
1927 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1932 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1933 * @hw: pointer to hardware structure
1934 * @byte_offset: EEPROM byte offset to read
1935 * @eeprom_data: value read
1937 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1939 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1942 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1943 IXGBE_I2C_EEPROM_DEV_ADDR,
1948 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1949 * @hw: pointer to hardware structure
1950 * @byte_offset: byte offset at address 0xA2
1951 * @sff8472_data: value read
1953 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1955 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1958 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1959 IXGBE_I2C_EEPROM_DEV_ADDR2,
1964 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1965 * @hw: pointer to hardware structure
1966 * @byte_offset: EEPROM byte offset to write
1967 * @eeprom_data: value to write
1969 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1971 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1974 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1975 IXGBE_I2C_EEPROM_DEV_ADDR,
1980 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1981 * @hw: pointer to hardware structure
1982 * @offset: eeprom offset to be read
1983 * @addr: I2C address to be read
1985 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1987 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1988 offset == IXGBE_SFF_IDENTIFIER &&
1989 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1995 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1996 * @hw: pointer to hardware structure
1997 * @byte_offset: byte offset to read
1998 * @dev_addr: device address
2000 * @lock: true if to take and release semaphore
2002 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2003 * a specified device address.
2005 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2006 u8 dev_addr, u8 *data, bool lock)
2011 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2014 if (hw->mac.type >= ixgbe_mac_X550)
2016 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2017 max_retry = IXGBE_SFP_DETECT_RETRIES;
2022 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2025 ixgbe_i2c_start(hw);
2027 /* Device Address and write indication */
2028 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2032 status = ixgbe_get_i2c_ack(hw);
2036 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2040 status = ixgbe_get_i2c_ack(hw);
2044 ixgbe_i2c_start(hw);
2046 /* Device Address and read indication */
2047 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2051 status = ixgbe_get_i2c_ack(hw);
2055 status = ixgbe_clock_in_i2c_byte(hw, data);
2059 status = ixgbe_clock_out_i2c_bit(hw, nack);
2065 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2069 ixgbe_i2c_bus_clear(hw);
2071 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2075 if (retry < max_retry)
2076 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2078 hw_dbg(hw, "I2C byte read error.\n");
2080 } while (retry < max_retry);
2086 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2087 * @hw: pointer to hardware structure
2088 * @byte_offset: byte offset to read
2089 * @dev_addr: device address
2092 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2093 * a specified device address.
2095 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2096 u8 dev_addr, u8 *data)
2098 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2103 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2104 * @hw: pointer to hardware structure
2105 * @byte_offset: byte offset to read
2106 * @dev_addr: device address
2109 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2110 * a specified device address.
2112 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2113 u8 dev_addr, u8 *data)
2115 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2120 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2121 * @hw: pointer to hardware structure
2122 * @byte_offset: byte offset to write
2123 * @dev_addr: device address
2124 * @data: value to write
2125 * @lock: true if to take and release semaphore
2127 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2128 * a specified device address.
2130 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2131 u8 dev_addr, u8 data, bool lock)
2136 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2138 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2142 ixgbe_i2c_start(hw);
2144 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2148 status = ixgbe_get_i2c_ack(hw);
2152 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2156 status = ixgbe_get_i2c_ack(hw);
2160 status = ixgbe_clock_out_i2c_byte(hw, data);
2164 status = ixgbe_get_i2c_ack(hw);
2170 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2174 ixgbe_i2c_bus_clear(hw);
2176 if (retry < max_retry)
2177 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2179 hw_dbg(hw, "I2C byte write error.\n");
2180 } while (retry < max_retry);
2183 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2189 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2190 * @hw: pointer to hardware structure
2191 * @byte_offset: byte offset to write
2192 * @dev_addr: device address
2193 * @data: value to write
2195 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2196 * a specified device address.
2198 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2199 u8 dev_addr, u8 data)
2201 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2206 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2207 * @hw: pointer to hardware structure
2208 * @byte_offset: byte offset to write
2209 * @dev_addr: device address
2210 * @data: value to write
2212 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2213 * a specified device address.
2215 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2216 u8 dev_addr, u8 data)
2218 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2223 * ixgbe_i2c_start - Sets I2C start condition
2224 * @hw: pointer to hardware structure
2226 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2227 * Set bit-bang mode on X550 hardware.
2229 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2231 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2233 i2cctl |= IXGBE_I2C_BB_EN(hw);
2235 /* Start condition must begin with data and clock high */
2236 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2237 ixgbe_raise_i2c_clk(hw, &i2cctl);
2239 /* Setup time for start condition (4.7us) */
2240 udelay(IXGBE_I2C_T_SU_STA);
2242 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2244 /* Hold time for start condition (4us) */
2245 udelay(IXGBE_I2C_T_HD_STA);
2247 ixgbe_lower_i2c_clk(hw, &i2cctl);
2249 /* Minimum low period of clock is 4.7 us */
2250 udelay(IXGBE_I2C_T_LOW);
2255 * ixgbe_i2c_stop - Sets I2C stop condition
2256 * @hw: pointer to hardware structure
2258 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2259 * Disables bit-bang mode and negates data output enable on X550
2262 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2264 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2265 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2266 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2267 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2269 /* Stop condition must begin with data low and clock high */
2270 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2271 ixgbe_raise_i2c_clk(hw, &i2cctl);
2273 /* Setup time for stop condition (4us) */
2274 udelay(IXGBE_I2C_T_SU_STO);
2276 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2278 /* bus free time between stop and start (4.7us)*/
2279 udelay(IXGBE_I2C_T_BUF);
2281 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2282 i2cctl &= ~bb_en_bit;
2283 i2cctl |= data_oe_bit | clk_oe_bit;
2284 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2285 IXGBE_WRITE_FLUSH(hw);
2290 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2291 * @hw: pointer to hardware structure
2292 * @data: data byte to clock in
2294 * Clocks in one byte data via I2C data/clock
2296 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2302 for (i = 7; i >= 0; i--) {
2303 ixgbe_clock_in_i2c_bit(hw, &bit);
2311 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2312 * @hw: pointer to hardware structure
2313 * @data: data byte clocked out
2315 * Clocks out one byte data via I2C data/clock
2317 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2324 for (i = 7; i >= 0; i--) {
2325 bit = (data >> i) & 0x1;
2326 status = ixgbe_clock_out_i2c_bit(hw, bit);
2332 /* Release SDA line (set high) */
2333 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2334 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2335 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2336 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2337 IXGBE_WRITE_FLUSH(hw);
2343 * ixgbe_get_i2c_ack - Polls for I2C ACK
2344 * @hw: pointer to hardware structure
2346 * Clocks in/out one bit via I2C data/clock
2348 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2350 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2353 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2358 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2359 i2cctl |= data_oe_bit;
2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2361 IXGBE_WRITE_FLUSH(hw);
2363 ixgbe_raise_i2c_clk(hw, &i2cctl);
2365 /* Minimum high period of clock is 4us */
2366 udelay(IXGBE_I2C_T_HIGH);
2368 /* Poll for ACK. Note that ACK in I2C spec is
2369 * transition from 1 to 0 */
2370 for (i = 0; i < timeout; i++) {
2371 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2372 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2380 hw_dbg(hw, "I2C ack was not received.\n");
2384 ixgbe_lower_i2c_clk(hw, &i2cctl);
2386 /* Minimum low period of clock is 4.7 us */
2387 udelay(IXGBE_I2C_T_LOW);
2393 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2394 * @hw: pointer to hardware structure
2395 * @data: read data value
2397 * Clocks in one bit via I2C data/clock
2399 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2401 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2402 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2405 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2406 i2cctl |= data_oe_bit;
2407 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2408 IXGBE_WRITE_FLUSH(hw);
2410 ixgbe_raise_i2c_clk(hw, &i2cctl);
2412 /* Minimum high period of clock is 4us */
2413 udelay(IXGBE_I2C_T_HIGH);
2415 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2416 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2418 ixgbe_lower_i2c_clk(hw, &i2cctl);
2420 /* Minimum low period of clock is 4.7 us */
2421 udelay(IXGBE_I2C_T_LOW);
2427 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2428 * @hw: pointer to hardware structure
2429 * @data: data value to write
2431 * Clocks out one bit via I2C data/clock
2433 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2436 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2438 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2440 ixgbe_raise_i2c_clk(hw, &i2cctl);
2442 /* Minimum high period of clock is 4us */
2443 udelay(IXGBE_I2C_T_HIGH);
2445 ixgbe_lower_i2c_clk(hw, &i2cctl);
2447 /* Minimum low period of clock is 4.7 us.
2448 * This also takes care of the data hold time.
2450 udelay(IXGBE_I2C_T_LOW);
2452 hw_dbg(hw, "I2C data was not set to %X\n", data);
2459 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2460 * @hw: pointer to hardware structure
2461 * @i2cctl: Current value of I2CCTL register
2463 * Raises the I2C clock line '0'->'1'
2464 * Negates the I2C clock output enable on X550 hardware.
2466 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2468 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2470 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2474 *i2cctl |= clk_oe_bit;
2475 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2478 for (i = 0; i < timeout; i++) {
2479 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2480 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2481 IXGBE_WRITE_FLUSH(hw);
2482 /* SCL rise time (1000ns) */
2483 udelay(IXGBE_I2C_T_RISE);
2485 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2486 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2492 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2493 * @hw: pointer to hardware structure
2494 * @i2cctl: Current value of I2CCTL register
2496 * Lowers the I2C clock line '1'->'0'
2497 * Asserts the I2C clock output enable on X550 hardware.
2499 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2502 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2503 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2505 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2506 IXGBE_WRITE_FLUSH(hw);
2508 /* SCL fall time (300ns) */
2509 udelay(IXGBE_I2C_T_FALL);
2513 * ixgbe_set_i2c_data - Sets the I2C data bit
2514 * @hw: pointer to hardware structure
2515 * @i2cctl: Current value of I2CCTL register
2516 * @data: I2C data value (0 or 1) to set
2518 * Sets the I2C data bit
2519 * Asserts the I2C data output enable on X550 hardware.
2521 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2523 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2526 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2528 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2529 *i2cctl &= ~data_oe_bit;
2531 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2532 IXGBE_WRITE_FLUSH(hw);
2534 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2535 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2537 if (!data) /* Can't verify data in this case */
2540 *i2cctl |= data_oe_bit;
2541 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2542 IXGBE_WRITE_FLUSH(hw);
2545 /* Verify data was set correctly */
2546 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2547 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2548 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2556 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2557 * @hw: pointer to hardware structure
2558 * @i2cctl: Current value of I2CCTL register
2560 * Returns the I2C data bit value
2561 * Negates the I2C data output enable on X550 hardware.
2563 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2565 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2568 *i2cctl |= data_oe_bit;
2569 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2570 IXGBE_WRITE_FLUSH(hw);
2571 udelay(IXGBE_I2C_T_FALL);
2574 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2580 * ixgbe_i2c_bus_clear - Clears the I2C bus
2581 * @hw: pointer to hardware structure
2583 * Clears the I2C bus by sending nine clock pulses.
2584 * Used when data line is stuck low.
2586 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2591 ixgbe_i2c_start(hw);
2592 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2594 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2596 for (i = 0; i < 9; i++) {
2597 ixgbe_raise_i2c_clk(hw, &i2cctl);
2599 /* Min high period of clock is 4us */
2600 udelay(IXGBE_I2C_T_HIGH);
2602 ixgbe_lower_i2c_clk(hw, &i2cctl);
2604 /* Min low period of clock is 4.7us*/
2605 udelay(IXGBE_I2C_T_LOW);
2608 ixgbe_i2c_start(hw);
2610 /* Put the i2c bus back to default state */
2615 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2616 * @hw: pointer to hardware structure
2618 * Checks if the LASI temp alarm status was triggered due to overtemp
2620 * Return true when an overtemp event detected, otherwise false.
2622 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2627 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2630 /* Check that the LASI temp alarm status was triggered */
2631 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2632 MDIO_MMD_PMAPMD, &phy_data);
2636 return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM);
2639 /** ixgbe_set_copper_phy_power - Control power for copper phy
2640 * @hw: pointer to hardware structure
2641 * @on: true for on, false for off
2643 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2648 /* Bail if we don't have copper phy */
2649 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2652 if (!on && ixgbe_mng_present(hw))
2655 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2660 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2662 if (ixgbe_check_reset_blocked(hw))
2664 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2667 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);