1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 #include "ixgbe_sriov.h"
32 #ifdef CONFIG_IXGBE_DCB
34 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
35 * @adapter: board private structure to initialize
37 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
38 * will also try to cache the proper offsets if RSS/FCoE are enabled along
42 static bool ixgbe_cache_ring_dcb_sriov(struct ixgbe_adapter *adapter)
45 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE];
46 #endif /* IXGBE_FCOE */
47 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
50 u8 tcs = netdev_get_num_tc(adapter->netdev);
52 /* verify we have DCB queueing enabled before proceeding */
56 /* verify we have VMDq enabled before proceeding */
57 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
60 /* start at VMDq register offset for SR-IOV enabled setups */
61 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
62 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) {
63 /* If we are greater than indices move to next pool */
64 if ((reg_idx & ~vmdq->mask) >= tcs)
65 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
66 adapter->rx_ring[i]->reg_idx = reg_idx;
69 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
70 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) {
71 /* If we are greater than indices move to next pool */
72 if ((reg_idx & ~vmdq->mask) >= tcs)
73 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
74 adapter->tx_ring[i]->reg_idx = reg_idx;
78 /* nothing to do if FCoE is disabled */
79 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
82 /* The work is already done if the FCoE ring is shared */
83 if (fcoe->offset < tcs)
86 /* The FCoE rings exist separately, we need to move their reg_idx */
88 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
89 u8 fcoe_tc = ixgbe_fcoe_get_tc(adapter);
91 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool;
92 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) {
93 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc;
94 adapter->rx_ring[i]->reg_idx = reg_idx;
98 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool;
99 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) {
100 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc;
101 adapter->tx_ring[i]->reg_idx = reg_idx;
106 #endif /* IXGBE_FCOE */
110 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
111 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
112 unsigned int *tx, unsigned int *rx)
114 struct net_device *dev = adapter->netdev;
115 struct ixgbe_hw *hw = &adapter->hw;
116 u8 num_tcs = netdev_get_num_tc(dev);
121 switch (hw->mac.type) {
122 case ixgbe_mac_82598EB:
123 /* TxQs/TC: 4 RxQs/TC: 8 */
124 *tx = tc << 2; /* 0, 4, 8, 12, 16, 20, 24, 28 */
125 *rx = tc << 3; /* 0, 8, 16, 24, 32, 40, 48, 56 */
127 case ixgbe_mac_82599EB:
130 case ixgbe_mac_X550EM_x:
133 * TCs : TC0/1 TC2/3 TC4-7
139 *tx = tc << 5; /* 0, 32, 64 */
141 *tx = (tc + 2) << 4; /* 80, 96 */
143 *tx = (tc + 8) << 3; /* 104, 112, 120 */
146 * TCs : TC0 TC1 TC2/3
152 *tx = tc << 6; /* 0, 64 */
154 *tx = (tc + 4) << 4; /* 96, 112 */
162 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
163 * @adapter: board private structure to initialize
165 * Cache the descriptor ring offsets for DCB to the assigned rings.
168 static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
170 struct net_device *dev = adapter->netdev;
171 unsigned int tx_idx, rx_idx;
172 int tc, offset, rss_i, i;
173 u8 num_tcs = netdev_get_num_tc(dev);
175 /* verify we have DCB queueing enabled before proceeding */
179 rss_i = adapter->ring_feature[RING_F_RSS].indices;
181 for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) {
182 ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx);
183 for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) {
184 adapter->tx_ring[offset + i]->reg_idx = tx_idx;
185 adapter->rx_ring[offset + i]->reg_idx = rx_idx;
186 adapter->tx_ring[offset + i]->dcb_tc = tc;
187 adapter->rx_ring[offset + i]->dcb_tc = tc;
196 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
197 * @adapter: board private structure to initialize
199 * SR-IOV doesn't use any descriptor rings but changes the default if
200 * no other mapping is used.
203 static bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
206 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE];
207 #endif /* IXGBE_FCOE */
208 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
209 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS];
213 /* only proceed if VMDq is enabled */
214 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED))
217 /* start at VMDq register offset for SR-IOV enabled setups */
218 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
219 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) {
221 /* Allow first FCoE queue to be mapped as RSS */
222 if (fcoe->offset && (i > fcoe->offset))
225 /* If we are greater than indices move to next pool */
226 if ((reg_idx & ~vmdq->mask) >= rss->indices)
227 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
228 adapter->rx_ring[i]->reg_idx = reg_idx;
232 /* FCoE uses a linear block of queues so just assigning 1:1 */
233 for (; i < adapter->num_rx_queues; i++, reg_idx++)
234 adapter->rx_ring[i]->reg_idx = reg_idx;
237 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
238 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) {
240 /* Allow first FCoE queue to be mapped as RSS */
241 if (fcoe->offset && (i > fcoe->offset))
244 /* If we are greater than indices move to next pool */
245 if ((reg_idx & rss->mask) >= rss->indices)
246 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
247 adapter->tx_ring[i]->reg_idx = reg_idx;
251 /* FCoE uses a linear block of queues so just assigning 1:1 */
252 for (; i < adapter->num_tx_queues; i++, reg_idx++)
253 adapter->tx_ring[i]->reg_idx = reg_idx;
261 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
262 * @adapter: board private structure to initialize
264 * Cache the descriptor ring offsets for RSS to the assigned rings.
267 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
271 for (i = 0; i < adapter->num_rx_queues; i++)
272 adapter->rx_ring[i]->reg_idx = i;
273 for (i = 0; i < adapter->num_tx_queues; i++)
274 adapter->tx_ring[i]->reg_idx = i;
280 * ixgbe_cache_ring_register - Descriptor ring to register mapping
281 * @adapter: board private structure to initialize
283 * Once we know the feature-set enabled for the device, we'll cache
284 * the register offset the descriptor ring is assigned to.
286 * Note, the order the various feature calls is important. It must start with
287 * the "most" features enabled at the same time, then trickle down to the
288 * least amount of features turned on at once.
290 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
292 /* start with default case */
293 adapter->rx_ring[0]->reg_idx = 0;
294 adapter->tx_ring[0]->reg_idx = 0;
296 #ifdef CONFIG_IXGBE_DCB
297 if (ixgbe_cache_ring_dcb_sriov(adapter))
300 if (ixgbe_cache_ring_dcb(adapter))
304 if (ixgbe_cache_ring_sriov(adapter))
307 ixgbe_cache_ring_rss(adapter);
310 #define IXGBE_RSS_64Q_MASK 0x3F
311 #define IXGBE_RSS_16Q_MASK 0xF
312 #define IXGBE_RSS_8Q_MASK 0x7
313 #define IXGBE_RSS_4Q_MASK 0x3
314 #define IXGBE_RSS_2Q_MASK 0x1
315 #define IXGBE_RSS_DISABLED_MASK 0x0
317 #ifdef CONFIG_IXGBE_DCB
319 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB
320 * @adapter: board private structure to initialize
322 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
323 * and VM pools where appropriate. Also assign queues based on DCB
324 * priorities and map accordingly..
327 static bool ixgbe_set_dcb_sriov_queues(struct ixgbe_adapter *adapter)
330 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit;
335 u8 tcs = netdev_get_num_tc(adapter->netdev);
337 /* verify we have DCB queueing enabled before proceeding */
341 /* verify we have VMDq enabled before proceeding */
342 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
345 /* Add starting offset to total pool count */
346 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset;
348 /* 16 pools w/ 8 TC per pool */
350 vmdq_i = min_t(u16, vmdq_i, 16);
351 vmdq_m = IXGBE_82599_VMDQ_8Q_MASK;
352 /* 32 pools w/ 4 TC per pool */
354 vmdq_i = min_t(u16, vmdq_i, 32);
355 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK;
359 /* queues in the remaining pools are available for FCoE */
360 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i;
363 /* remove the starting offset from the pool count */
364 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset;
366 /* save features for later use */
367 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i;
368 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m;
371 * We do not support DCB, VMDq, and RSS all simultaneously
372 * so we will disable RSS since it is the lowest priority
374 adapter->ring_feature[RING_F_RSS].indices = 1;
375 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK;
377 /* disable ATR as it is not supported when VMDq is enabled */
378 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
380 adapter->num_rx_pools = vmdq_i;
381 adapter->num_rx_queues_per_pool = tcs;
383 adapter->num_tx_queues = vmdq_i * tcs;
384 adapter->num_rx_queues = vmdq_i * tcs;
387 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
388 struct ixgbe_ring_feature *fcoe;
390 fcoe = &adapter->ring_feature[RING_F_FCOE];
392 /* limit ourselves based on feature limits */
393 fcoe_i = min_t(u16, fcoe_i, fcoe->limit);
396 /* alloc queues for FCoE separately */
397 fcoe->indices = fcoe_i;
398 fcoe->offset = vmdq_i * tcs;
400 /* add queues to adapter */
401 adapter->num_tx_queues += fcoe_i;
402 adapter->num_rx_queues += fcoe_i;
403 } else if (tcs > 1) {
404 /* use queue belonging to FcoE TC */
406 fcoe->offset = ixgbe_fcoe_get_tc(adapter);
408 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
415 #endif /* IXGBE_FCOE */
416 /* configure TC to queue mapping */
417 for (i = 0; i < tcs; i++)
418 netdev_set_tc_queue(adapter->netdev, i, 1, i);
423 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
425 struct net_device *dev = adapter->netdev;
426 struct ixgbe_ring_feature *f;
430 /* Map queue offset and counts onto allocated tx queues */
431 tcs = netdev_get_num_tc(dev);
433 /* verify we have DCB queueing enabled before proceeding */
437 /* determine the upper limit for our current DCB mode */
438 rss_i = dev->num_tx_queues / tcs;
439 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
440 /* 8 TC w/ 4 queues per TC */
441 rss_i = min_t(u16, rss_i, 4);
442 rss_m = IXGBE_RSS_4Q_MASK;
443 } else if (tcs > 4) {
444 /* 8 TC w/ 8 queues per TC */
445 rss_i = min_t(u16, rss_i, 8);
446 rss_m = IXGBE_RSS_8Q_MASK;
448 /* 4 TC w/ 16 queues per TC */
449 rss_i = min_t(u16, rss_i, 16);
450 rss_m = IXGBE_RSS_16Q_MASK;
453 /* set RSS mask and indices */
454 f = &adapter->ring_feature[RING_F_RSS];
455 rss_i = min_t(int, rss_i, f->limit);
459 /* disable ATR as it is not supported when multiple TCs are enabled */
460 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
463 /* FCoE enabled queues require special configuration indexed
464 * by feature specific indices and offset. Here we map FCoE
465 * indices onto the DCB queue pairs allowing FCoE to own
466 * configuration later.
468 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
469 u8 tc = ixgbe_fcoe_get_tc(adapter);
471 f = &adapter->ring_feature[RING_F_FCOE];
472 f->indices = min_t(u16, rss_i, f->limit);
473 f->offset = rss_i * tc;
476 #endif /* IXGBE_FCOE */
477 for (i = 0; i < tcs; i++)
478 netdev_set_tc_queue(dev, i, rss_i, rss_i * i);
480 adapter->num_tx_queues = rss_i * tcs;
481 adapter->num_rx_queues = rss_i * tcs;
488 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices
489 * @adapter: board private structure to initialize
491 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
492 * and VM pools where appropriate. If RSS is available, then also try and
493 * enable RSS and map accordingly.
496 static bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
498 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit;
500 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit;
501 u16 rss_m = IXGBE_RSS_DISABLED_MASK;
505 bool pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
507 /* only proceed if SR-IOV is enabled */
508 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
511 /* Add starting offset to total pool count */
512 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset;
514 /* double check we are limited to maximum pools */
515 vmdq_i = min_t(u16, IXGBE_MAX_VMDQ_INDICES, vmdq_i);
517 /* 64 pool mode with 2 queues per pool */
518 if ((vmdq_i > 32) || (rss_i < 4) || (vmdq_i > 16 && pools)) {
519 vmdq_m = IXGBE_82599_VMDQ_2Q_MASK;
520 rss_m = IXGBE_RSS_2Q_MASK;
521 rss_i = min_t(u16, rss_i, 2);
522 /* 32 pool mode with 4 queues per pool */
524 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK;
525 rss_m = IXGBE_RSS_4Q_MASK;
530 /* queues in the remaining pools are available for FCoE */
531 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m));
534 /* remove the starting offset from the pool count */
535 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset;
537 /* save features for later use */
538 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i;
539 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m;
541 /* limit RSS based on user input and save for later use */
542 adapter->ring_feature[RING_F_RSS].indices = rss_i;
543 adapter->ring_feature[RING_F_RSS].mask = rss_m;
545 adapter->num_rx_pools = vmdq_i;
546 adapter->num_rx_queues_per_pool = rss_i;
548 adapter->num_rx_queues = vmdq_i * rss_i;
549 adapter->num_tx_queues = vmdq_i * rss_i;
551 /* disable ATR as it is not supported when VMDq is enabled */
552 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
556 * FCoE can use rings from adjacent buffers to allow RSS
557 * like behavior. To account for this we need to add the
558 * FCoE indices to the total ring count.
560 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
561 struct ixgbe_ring_feature *fcoe;
563 fcoe = &adapter->ring_feature[RING_F_FCOE];
565 /* limit ourselves based on feature limits */
566 fcoe_i = min_t(u16, fcoe_i, fcoe->limit);
568 if (vmdq_i > 1 && fcoe_i) {
569 /* alloc queues for FCoE separately */
570 fcoe->indices = fcoe_i;
571 fcoe->offset = vmdq_i * rss_i;
573 /* merge FCoE queues with RSS queues */
574 fcoe_i = min_t(u16, fcoe_i + rss_i, num_online_cpus());
576 /* limit indices to rss_i if MSI-X is disabled */
577 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
580 /* attempt to reserve some queues for just FCoE */
581 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit);
582 fcoe->offset = fcoe_i - fcoe->indices;
587 /* add queues to adapter */
588 adapter->num_tx_queues += fcoe_i;
589 adapter->num_rx_queues += fcoe_i;
597 * ixgbe_set_rss_queues - Allocate queues for RSS
598 * @adapter: board private structure to initialize
600 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
601 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
604 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
606 struct ixgbe_hw *hw = &adapter->hw;
607 struct ixgbe_ring_feature *f;
610 /* set mask for 16 queue limit of RSS */
611 f = &adapter->ring_feature[RING_F_RSS];
616 if (hw->mac.type < ixgbe_mac_X550)
617 f->mask = IXGBE_RSS_16Q_MASK;
619 f->mask = IXGBE_RSS_64Q_MASK;
621 /* disable ATR by default, it will be configured below */
622 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
625 * Use Flow Director in addition to RSS to ensure the best
626 * distribution of flows across cores, even when an FDIR flow
629 if (rss_i > 1 && adapter->atr_sample_rate) {
630 f = &adapter->ring_feature[RING_F_FDIR];
632 rss_i = f->indices = f->limit;
634 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
635 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
640 * FCoE can exist on the same rings as standard network traffic
641 * however it is preferred to avoid that if possible. In order
642 * to get the best performance we allocate as many FCoE queues
643 * as we can and we place them at the end of the ring array to
644 * avoid sharing queues with standard RSS on systems with 24 or
647 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
648 struct net_device *dev = adapter->netdev;
651 f = &adapter->ring_feature[RING_F_FCOE];
653 /* merge FCoE queues with RSS queues */
654 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus());
655 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues);
657 /* limit indices to rss_i if MSI-X is disabled */
658 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
661 /* attempt to reserve some queues for just FCoE */
662 f->indices = min_t(u16, fcoe_i, f->limit);
663 f->offset = fcoe_i - f->indices;
664 rss_i = max_t(u16, fcoe_i, rss_i);
667 #endif /* IXGBE_FCOE */
668 adapter->num_rx_queues = rss_i;
669 adapter->num_tx_queues = rss_i;
675 * ixgbe_set_num_queues - Allocate queues for device, feature dependent
676 * @adapter: board private structure to initialize
678 * This is the top level queue allocation routine. The order here is very
679 * important, starting with the "most" number of features turned on at once,
680 * and ending with the smallest set of features. This way large combinations
681 * can be allocated if they're turned on, and smaller combinations are the
682 * fallthrough conditions.
685 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
687 /* Start with base case */
688 adapter->num_rx_queues = 1;
689 adapter->num_tx_queues = 1;
690 adapter->num_rx_pools = adapter->num_rx_queues;
691 adapter->num_rx_queues_per_pool = 1;
693 #ifdef CONFIG_IXGBE_DCB
694 if (ixgbe_set_dcb_sriov_queues(adapter))
697 if (ixgbe_set_dcb_queues(adapter))
701 if (ixgbe_set_sriov_queues(adapter))
704 ixgbe_set_rss_queues(adapter);
708 * ixgbe_acquire_msix_vectors - acquire MSI-X vectors
709 * @adapter: board private structure
711 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
712 * return a negative error code if unable to acquire MSI-X vectors for any
715 static int ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter)
717 struct ixgbe_hw *hw = &adapter->hw;
718 int i, vectors, vector_threshold;
720 /* We start by asking for one vector per queue pair */
721 vectors = max(adapter->num_rx_queues, adapter->num_tx_queues);
723 /* It is easy to be greedy for MSI-X vectors. However, it really
724 * doesn't do much good if we have a lot more vectors than CPUs. We'll
725 * be somewhat conservative and only ask for (roughly) the same number
726 * of vectors as there are CPUs.
728 vectors = min_t(int, vectors, num_online_cpus());
730 /* Some vectors are necessary for non-queue interrupts */
731 vectors += NON_Q_VECTORS;
733 /* Hardware can only support a maximum of hw.mac->max_msix_vectors.
734 * With features such as RSS and VMDq, we can easily surpass the
735 * number of Rx and Tx descriptor queues supported by our device.
736 * Thus, we cap the maximum in the rare cases where the CPU count also
737 * exceeds our vector limit
739 vectors = min_t(int, vectors, hw->mac.max_msix_vectors);
741 /* We want a minimum of two MSI-X vectors for (1) a TxQ[0] + RxQ[0]
742 * handler, and (2) an Other (Link Status Change, etc.) handler.
744 vector_threshold = MIN_MSIX_COUNT;
746 adapter->msix_entries = kcalloc(vectors,
747 sizeof(struct msix_entry),
749 if (!adapter->msix_entries)
752 for (i = 0; i < vectors; i++)
753 adapter->msix_entries[i].entry = i;
755 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries,
756 vector_threshold, vectors);
759 /* A negative count of allocated vectors indicates an error in
760 * acquiring within the specified range of MSI-X vectors
762 e_dev_warn("Failed to allocate MSI-X interrupts. Err: %d\n",
765 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
766 kfree(adapter->msix_entries);
767 adapter->msix_entries = NULL;
772 /* we successfully allocated some number of vectors within our
775 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED;
777 /* Adjust for only the vectors we'll use, which is minimum
778 * of max_q_vectors, or the number of vectors we were allocated.
780 vectors -= NON_Q_VECTORS;
781 adapter->num_q_vectors = min_t(int, vectors, adapter->max_q_vectors);
786 static void ixgbe_add_ring(struct ixgbe_ring *ring,
787 struct ixgbe_ring_container *head)
789 ring->next = head->ring;
795 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
796 * @adapter: board private structure to initialize
797 * @v_count: q_vectors allocated on adapter, used for ring interleaving
798 * @v_idx: index of vector in adapter struct
799 * @txr_count: total number of Tx rings to allocate
800 * @txr_idx: index of first Tx ring to allocate
801 * @rxr_count: total number of Rx rings to allocate
802 * @rxr_idx: index of first Rx ring to allocate
804 * We allocate one q_vector. If allocation fails we return -ENOMEM.
806 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter,
807 int v_count, int v_idx,
808 int txr_count, int txr_idx,
809 int rxr_count, int rxr_idx)
811 struct ixgbe_q_vector *q_vector;
812 struct ixgbe_ring *ring;
813 int node = NUMA_NO_NODE;
815 int ring_count, size;
816 u8 tcs = netdev_get_num_tc(adapter->netdev);
818 ring_count = txr_count + rxr_count;
819 size = sizeof(struct ixgbe_q_vector) +
820 (sizeof(struct ixgbe_ring) * ring_count);
822 /* customize cpu for Flow Director mapping */
823 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
824 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
825 if (rss_i > 1 && adapter->atr_sample_rate) {
826 if (cpu_online(v_idx)) {
828 node = cpu_to_node(cpu);
833 /* allocate q_vector and rings */
834 q_vector = kzalloc_node(size, GFP_KERNEL, node);
836 q_vector = kzalloc(size, GFP_KERNEL);
840 /* setup affinity mask and node */
842 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
843 q_vector->numa_node = node;
845 #ifdef CONFIG_IXGBE_DCA
846 /* initialize CPU for DCA */
850 /* initialize NAPI */
851 netif_napi_add(adapter->netdev, &q_vector->napi,
853 napi_hash_add(&q_vector->napi);
855 #ifdef CONFIG_NET_RX_BUSY_POLL
856 /* initialize busy poll */
857 atomic_set(&q_vector->state, IXGBE_QV_STATE_DISABLE);
860 /* tie q_vector and adapter together */
861 adapter->q_vector[v_idx] = q_vector;
862 q_vector->adapter = adapter;
863 q_vector->v_idx = v_idx;
865 /* initialize work limits */
866 q_vector->tx.work_limit = adapter->tx_work_limit;
868 /* initialize pointer to rings */
869 ring = q_vector->ring;
872 if (txr_count && !rxr_count) {
874 if (adapter->tx_itr_setting == 1)
875 q_vector->itr = IXGBE_12K_ITR;
877 q_vector->itr = adapter->tx_itr_setting;
879 /* rx or rx/tx vector */
880 if (adapter->rx_itr_setting == 1)
881 q_vector->itr = IXGBE_20K_ITR;
883 q_vector->itr = adapter->rx_itr_setting;
887 /* assign generic ring traits */
888 ring->dev = &adapter->pdev->dev;
889 ring->netdev = adapter->netdev;
891 /* configure backlink on ring */
892 ring->q_vector = q_vector;
894 /* update q_vector Tx values */
895 ixgbe_add_ring(ring, &q_vector->tx);
897 /* apply Tx specific ring traits */
898 ring->count = adapter->tx_ring_count;
899 if (adapter->num_rx_pools > 1)
901 txr_idx % adapter->num_rx_queues_per_pool;
903 ring->queue_index = txr_idx;
905 /* assign ring to adapter */
906 adapter->tx_ring[txr_idx] = ring;
908 /* update count and index */
912 /* push pointer to next ring */
917 /* assign generic ring traits */
918 ring->dev = &adapter->pdev->dev;
919 ring->netdev = adapter->netdev;
921 /* configure backlink on ring */
922 ring->q_vector = q_vector;
924 /* update q_vector Rx values */
925 ixgbe_add_ring(ring, &q_vector->rx);
928 * 82599 errata, UDP frames with a 0 checksum
929 * can be marked as checksum errors.
931 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
932 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
935 if (adapter->netdev->features & NETIF_F_FCOE_MTU) {
936 struct ixgbe_ring_feature *f;
937 f = &adapter->ring_feature[RING_F_FCOE];
938 if ((rxr_idx >= f->offset) &&
939 (rxr_idx < f->offset + f->indices))
940 set_bit(__IXGBE_RX_FCOE, &ring->state);
943 #endif /* IXGBE_FCOE */
944 /* apply Rx specific ring traits */
945 ring->count = adapter->rx_ring_count;
946 if (adapter->num_rx_pools > 1)
948 rxr_idx % adapter->num_rx_queues_per_pool;
950 ring->queue_index = rxr_idx;
952 /* assign ring to adapter */
953 adapter->rx_ring[rxr_idx] = ring;
955 /* update count and index */
959 /* push pointer to next ring */
967 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
968 * @adapter: board private structure to initialize
969 * @v_idx: Index of vector to be freed
971 * This function frees the memory allocated to the q_vector. In addition if
972 * NAPI is enabled it will delete any references to the NAPI struct prior
973 * to freeing the q_vector.
975 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
977 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
978 struct ixgbe_ring *ring;
980 ixgbe_for_each_ring(ring, q_vector->tx)
981 adapter->tx_ring[ring->queue_index] = NULL;
983 ixgbe_for_each_ring(ring, q_vector->rx)
984 adapter->rx_ring[ring->queue_index] = NULL;
986 adapter->q_vector[v_idx] = NULL;
987 napi_hash_del(&q_vector->napi);
988 netif_napi_del(&q_vector->napi);
991 * ixgbe_get_stats64() might access the rings on this vector,
992 * we must wait a grace period before freeing it.
994 kfree_rcu(q_vector, rcu);
998 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
999 * @adapter: board private structure to initialize
1001 * We allocate one q_vector per queue interrupt. If allocation fails we
1004 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
1006 int q_vectors = adapter->num_q_vectors;
1007 int rxr_remaining = adapter->num_rx_queues;
1008 int txr_remaining = adapter->num_tx_queues;
1009 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1012 /* only one q_vector if MSI-X is disabled. */
1013 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1016 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1017 for (; rxr_remaining; v_idx++) {
1018 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx,
1024 /* update counts and index */
1030 for (; v_idx < q_vectors; v_idx++) {
1031 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1032 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1033 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx,
1040 /* update counts and index */
1041 rxr_remaining -= rqpv;
1042 txr_remaining -= tqpv;
1050 adapter->num_tx_queues = 0;
1051 adapter->num_rx_queues = 0;
1052 adapter->num_q_vectors = 0;
1055 ixgbe_free_q_vector(adapter, v_idx);
1061 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
1068 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
1070 int v_idx = adapter->num_q_vectors;
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
1074 adapter->num_q_vectors = 0;
1077 ixgbe_free_q_vector(adapter, v_idx);
1080 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
1082 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1083 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1084 pci_disable_msix(adapter->pdev);
1085 kfree(adapter->msix_entries);
1086 adapter->msix_entries = NULL;
1087 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1088 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
1089 pci_disable_msi(adapter->pdev);
1094 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
1095 * @adapter: board private structure to initialize
1097 * Attempt to configure the interrupts using the best available
1098 * capabilities of the hardware and the kernel.
1100 static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
1104 /* We will try to get MSI-X interrupts first */
1105 if (!ixgbe_acquire_msix_vectors(adapter))
1108 /* At this point, we do not have MSI-X capabilities. We need to
1109 * reconfigure or disable various features which require MSI-X
1113 /* Disable DCB unless we only have a single traffic class */
1114 if (netdev_get_num_tc(adapter->netdev) > 1) {
1115 e_dev_warn("Number of DCB TCs exceeds number of available queues. Disabling DCB support.\n");
1116 netdev_reset_tc(adapter->netdev);
1118 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1119 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
1121 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1122 adapter->temp_dcb_cfg.pfc_mode_enable = false;
1123 adapter->dcb_cfg.pfc_mode_enable = false;
1126 adapter->dcb_cfg.num_tcs.pg_tcs = 1;
1127 adapter->dcb_cfg.num_tcs.pfc_tcs = 1;
1129 /* Disable SR-IOV support */
1130 e_dev_warn("Disabling SR-IOV support\n");
1131 ixgbe_disable_sriov(adapter);
1134 e_dev_warn("Disabling RSS support\n");
1135 adapter->ring_feature[RING_F_RSS].limit = 1;
1137 /* recalculate number of queues now that many features have been
1138 * changed or disabled.
1140 ixgbe_set_num_queues(adapter);
1141 adapter->num_q_vectors = 1;
1143 err = pci_enable_msi(adapter->pdev);
1145 e_dev_warn("Failed to allocate MSI interrupt, falling back to legacy. Error: %d\n",
1148 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
1152 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
1153 * @adapter: board private structure to initialize
1155 * We determine which interrupt scheme to use based on...
1156 * - Kernel support (MSI, MSI-X)
1157 * - which can be user-defined (via MODULE_PARAM)
1158 * - Hardware queue count (num_*_queues)
1159 * - defined by miscellaneous hardware support/features (RSS, etc.)
1161 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
1165 /* Number of supported queues */
1166 ixgbe_set_num_queues(adapter);
1168 /* Set interrupt mode */
1169 ixgbe_set_interrupt_capability(adapter);
1171 err = ixgbe_alloc_q_vectors(adapter);
1173 e_dev_err("Unable to allocate memory for queue vectors\n");
1174 goto err_alloc_q_vectors;
1177 ixgbe_cache_ring_register(adapter);
1179 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
1180 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
1181 adapter->num_rx_queues, adapter->num_tx_queues);
1183 set_bit(__IXGBE_DOWN, &adapter->state);
1187 err_alloc_q_vectors:
1188 ixgbe_reset_interrupt_capability(adapter);
1193 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
1194 * @adapter: board private structure to clear interrupt scheme on
1196 * We go through and clear interrupt specific resources and reset the structure
1197 * to pre-load conditions
1199 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
1201 adapter->num_tx_queues = 0;
1202 adapter->num_rx_queues = 0;
1204 ixgbe_free_q_vectors(adapter);
1205 ixgbe_reset_interrupt_capability(adapter);
1208 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
1209 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1211 struct ixgbe_adv_tx_context_desc *context_desc;
1212 u16 i = tx_ring->next_to_use;
1214 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
1217 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1219 /* set bits to identify this as an advanced context descriptor */
1220 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
1222 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1223 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
1224 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1225 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);