1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 #include "ixgbe_sriov.h"
32 #ifdef CONFIG_IXGBE_DCB
34 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
35 * @adapter: board private structure to initialize
37 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
38 * will also try to cache the proper offsets if RSS/FCoE are enabled along
42 static bool ixgbe_cache_ring_dcb_sriov(struct ixgbe_adapter *adapter)
45 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE];
46 #endif /* IXGBE_FCOE */
47 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
50 u8 tcs = netdev_get_num_tc(adapter->netdev);
52 /* verify we have DCB queueing enabled before proceeding */
56 /* verify we have VMDq enabled before proceeding */
57 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
60 /* start at VMDq register offset for SR-IOV enabled setups */
61 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
62 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) {
63 /* If we are greater than indices move to next pool */
64 if ((reg_idx & ~vmdq->mask) >= tcs)
65 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
66 adapter->rx_ring[i]->reg_idx = reg_idx;
69 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
70 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) {
71 /* If we are greater than indices move to next pool */
72 if ((reg_idx & ~vmdq->mask) >= tcs)
73 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
74 adapter->tx_ring[i]->reg_idx = reg_idx;
78 /* nothing to do if FCoE is disabled */
79 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
82 /* The work is already done if the FCoE ring is shared */
83 if (fcoe->offset < tcs)
86 /* The FCoE rings exist separately, we need to move their reg_idx */
88 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
89 u8 fcoe_tc = ixgbe_fcoe_get_tc(adapter);
91 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool;
92 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) {
93 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc;
94 adapter->rx_ring[i]->reg_idx = reg_idx;
98 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool;
99 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) {
100 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc;
101 adapter->tx_ring[i]->reg_idx = reg_idx;
106 #endif /* IXGBE_FCOE */
110 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
111 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
112 unsigned int *tx, unsigned int *rx)
114 struct net_device *dev = adapter->netdev;
115 struct ixgbe_hw *hw = &adapter->hw;
116 u8 num_tcs = netdev_get_num_tc(dev);
121 switch (hw->mac.type) {
122 case ixgbe_mac_82598EB:
123 /* TxQs/TC: 4 RxQs/TC: 8 */
124 *tx = tc << 2; /* 0, 4, 8, 12, 16, 20, 24, 28 */
125 *rx = tc << 3; /* 0, 8, 16, 24, 32, 40, 48, 56 */
127 case ixgbe_mac_82599EB:
130 case ixgbe_mac_X550EM_x:
131 case ixgbe_mac_x550em_a:
134 * TCs : TC0/1 TC2/3 TC4-7
140 *tx = tc << 5; /* 0, 32, 64 */
142 *tx = (tc + 2) << 4; /* 80, 96 */
144 *tx = (tc + 8) << 3; /* 104, 112, 120 */
147 * TCs : TC0 TC1 TC2/3
153 *tx = tc << 6; /* 0, 64 */
155 *tx = (tc + 4) << 4; /* 96, 112 */
163 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
164 * @adapter: board private structure to initialize
166 * Cache the descriptor ring offsets for DCB to the assigned rings.
169 static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
171 struct net_device *dev = adapter->netdev;
172 unsigned int tx_idx, rx_idx;
173 int tc, offset, rss_i, i;
174 u8 num_tcs = netdev_get_num_tc(dev);
176 /* verify we have DCB queueing enabled before proceeding */
180 rss_i = adapter->ring_feature[RING_F_RSS].indices;
182 for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) {
183 ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx);
184 for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) {
185 adapter->tx_ring[offset + i]->reg_idx = tx_idx;
186 adapter->rx_ring[offset + i]->reg_idx = rx_idx;
187 adapter->tx_ring[offset + i]->dcb_tc = tc;
188 adapter->rx_ring[offset + i]->dcb_tc = tc;
197 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
198 * @adapter: board private structure to initialize
200 * SR-IOV doesn't use any descriptor rings but changes the default if
201 * no other mapping is used.
204 static bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
207 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE];
208 #endif /* IXGBE_FCOE */
209 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
210 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS];
214 /* only proceed if VMDq is enabled */
215 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED))
218 /* start at VMDq register offset for SR-IOV enabled setups */
219 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
220 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) {
222 /* Allow first FCoE queue to be mapped as RSS */
223 if (fcoe->offset && (i > fcoe->offset))
226 /* If we are greater than indices move to next pool */
227 if ((reg_idx & ~vmdq->mask) >= rss->indices)
228 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
229 adapter->rx_ring[i]->reg_idx = reg_idx;
233 /* FCoE uses a linear block of queues so just assigning 1:1 */
234 for (; i < adapter->num_rx_queues; i++, reg_idx++)
235 adapter->rx_ring[i]->reg_idx = reg_idx;
238 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask);
239 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) {
241 /* Allow first FCoE queue to be mapped as RSS */
242 if (fcoe->offset && (i > fcoe->offset))
245 /* If we are greater than indices move to next pool */
246 if ((reg_idx & rss->mask) >= rss->indices)
247 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask);
248 adapter->tx_ring[i]->reg_idx = reg_idx;
252 /* FCoE uses a linear block of queues so just assigning 1:1 */
253 for (; i < adapter->num_tx_queues; i++, reg_idx++)
254 adapter->tx_ring[i]->reg_idx = reg_idx;
262 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
263 * @adapter: board private structure to initialize
265 * Cache the descriptor ring offsets for RSS to the assigned rings.
268 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
272 for (i = 0; i < adapter->num_rx_queues; i++)
273 adapter->rx_ring[i]->reg_idx = i;
274 for (i = 0; i < adapter->num_tx_queues; i++)
275 adapter->tx_ring[i]->reg_idx = i;
281 * ixgbe_cache_ring_register - Descriptor ring to register mapping
282 * @adapter: board private structure to initialize
284 * Once we know the feature-set enabled for the device, we'll cache
285 * the register offset the descriptor ring is assigned to.
287 * Note, the order the various feature calls is important. It must start with
288 * the "most" features enabled at the same time, then trickle down to the
289 * least amount of features turned on at once.
291 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
293 /* start with default case */
294 adapter->rx_ring[0]->reg_idx = 0;
295 adapter->tx_ring[0]->reg_idx = 0;
297 #ifdef CONFIG_IXGBE_DCB
298 if (ixgbe_cache_ring_dcb_sriov(adapter))
301 if (ixgbe_cache_ring_dcb(adapter))
305 if (ixgbe_cache_ring_sriov(adapter))
308 ixgbe_cache_ring_rss(adapter);
311 #define IXGBE_RSS_64Q_MASK 0x3F
312 #define IXGBE_RSS_16Q_MASK 0xF
313 #define IXGBE_RSS_8Q_MASK 0x7
314 #define IXGBE_RSS_4Q_MASK 0x3
315 #define IXGBE_RSS_2Q_MASK 0x1
316 #define IXGBE_RSS_DISABLED_MASK 0x0
318 #ifdef CONFIG_IXGBE_DCB
320 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB
321 * @adapter: board private structure to initialize
323 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
324 * and VM pools where appropriate. Also assign queues based on DCB
325 * priorities and map accordingly..
328 static bool ixgbe_set_dcb_sriov_queues(struct ixgbe_adapter *adapter)
331 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit;
336 u8 tcs = netdev_get_num_tc(adapter->netdev);
338 /* verify we have DCB queueing enabled before proceeding */
342 /* verify we have VMDq enabled before proceeding */
343 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
346 /* Add starting offset to total pool count */
347 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset;
349 /* 16 pools w/ 8 TC per pool */
351 vmdq_i = min_t(u16, vmdq_i, 16);
352 vmdq_m = IXGBE_82599_VMDQ_8Q_MASK;
353 /* 32 pools w/ 4 TC per pool */
355 vmdq_i = min_t(u16, vmdq_i, 32);
356 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK;
360 /* queues in the remaining pools are available for FCoE */
361 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i;
364 /* remove the starting offset from the pool count */
365 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset;
367 /* save features for later use */
368 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i;
369 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m;
372 * We do not support DCB, VMDq, and RSS all simultaneously
373 * so we will disable RSS since it is the lowest priority
375 adapter->ring_feature[RING_F_RSS].indices = 1;
376 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK;
378 /* disable ATR as it is not supported when VMDq is enabled */
379 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
381 adapter->num_rx_pools = vmdq_i;
382 adapter->num_rx_queues_per_pool = tcs;
384 adapter->num_tx_queues = vmdq_i * tcs;
385 adapter->num_rx_queues = vmdq_i * tcs;
388 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
389 struct ixgbe_ring_feature *fcoe;
391 fcoe = &adapter->ring_feature[RING_F_FCOE];
393 /* limit ourselves based on feature limits */
394 fcoe_i = min_t(u16, fcoe_i, fcoe->limit);
397 /* alloc queues for FCoE separately */
398 fcoe->indices = fcoe_i;
399 fcoe->offset = vmdq_i * tcs;
401 /* add queues to adapter */
402 adapter->num_tx_queues += fcoe_i;
403 adapter->num_rx_queues += fcoe_i;
404 } else if (tcs > 1) {
405 /* use queue belonging to FcoE TC */
407 fcoe->offset = ixgbe_fcoe_get_tc(adapter);
409 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
416 #endif /* IXGBE_FCOE */
417 /* configure TC to queue mapping */
418 for (i = 0; i < tcs; i++)
419 netdev_set_tc_queue(adapter->netdev, i, 1, i);
424 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
426 struct net_device *dev = adapter->netdev;
427 struct ixgbe_ring_feature *f;
431 /* Map queue offset and counts onto allocated tx queues */
432 tcs = netdev_get_num_tc(dev);
434 /* verify we have DCB queueing enabled before proceeding */
438 /* determine the upper limit for our current DCB mode */
439 rss_i = dev->num_tx_queues / tcs;
440 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
441 /* 8 TC w/ 4 queues per TC */
442 rss_i = min_t(u16, rss_i, 4);
443 rss_m = IXGBE_RSS_4Q_MASK;
444 } else if (tcs > 4) {
445 /* 8 TC w/ 8 queues per TC */
446 rss_i = min_t(u16, rss_i, 8);
447 rss_m = IXGBE_RSS_8Q_MASK;
449 /* 4 TC w/ 16 queues per TC */
450 rss_i = min_t(u16, rss_i, 16);
451 rss_m = IXGBE_RSS_16Q_MASK;
454 /* set RSS mask and indices */
455 f = &adapter->ring_feature[RING_F_RSS];
456 rss_i = min_t(int, rss_i, f->limit);
460 /* disable ATR as it is not supported when multiple TCs are enabled */
461 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
464 /* FCoE enabled queues require special configuration indexed
465 * by feature specific indices and offset. Here we map FCoE
466 * indices onto the DCB queue pairs allowing FCoE to own
467 * configuration later.
469 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
470 u8 tc = ixgbe_fcoe_get_tc(adapter);
472 f = &adapter->ring_feature[RING_F_FCOE];
473 f->indices = min_t(u16, rss_i, f->limit);
474 f->offset = rss_i * tc;
477 #endif /* IXGBE_FCOE */
478 for (i = 0; i < tcs; i++)
479 netdev_set_tc_queue(dev, i, rss_i, rss_i * i);
481 adapter->num_tx_queues = rss_i * tcs;
482 adapter->num_rx_queues = rss_i * tcs;
489 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices
490 * @adapter: board private structure to initialize
492 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
493 * and VM pools where appropriate. If RSS is available, then also try and
494 * enable RSS and map accordingly.
497 static bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
499 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit;
501 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit;
502 u16 rss_m = IXGBE_RSS_DISABLED_MASK;
506 bool pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
508 /* only proceed if SR-IOV is enabled */
509 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
512 /* Add starting offset to total pool count */
513 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset;
515 /* double check we are limited to maximum pools */
516 vmdq_i = min_t(u16, IXGBE_MAX_VMDQ_INDICES, vmdq_i);
518 /* 64 pool mode with 2 queues per pool */
519 if ((vmdq_i > 32) || (vmdq_i > 16 && pools)) {
520 vmdq_m = IXGBE_82599_VMDQ_2Q_MASK;
521 rss_m = IXGBE_RSS_2Q_MASK;
522 rss_i = min_t(u16, rss_i, 2);
523 /* 32 pool mode with up to 4 queues per pool */
525 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK;
526 rss_m = IXGBE_RSS_4Q_MASK;
527 /* We can support 4, 2, or 1 queues */
528 rss_i = (rss_i > 3) ? 4 : (rss_i > 1) ? 2 : 1;
532 /* queues in the remaining pools are available for FCoE */
533 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m));
536 /* remove the starting offset from the pool count */
537 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset;
539 /* save features for later use */
540 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i;
541 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m;
543 /* limit RSS based on user input and save for later use */
544 adapter->ring_feature[RING_F_RSS].indices = rss_i;
545 adapter->ring_feature[RING_F_RSS].mask = rss_m;
547 adapter->num_rx_pools = vmdq_i;
548 adapter->num_rx_queues_per_pool = rss_i;
550 adapter->num_rx_queues = vmdq_i * rss_i;
551 adapter->num_tx_queues = vmdq_i * rss_i;
553 /* disable ATR as it is not supported when VMDq is enabled */
554 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
558 * FCoE can use rings from adjacent buffers to allow RSS
559 * like behavior. To account for this we need to add the
560 * FCoE indices to the total ring count.
562 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
563 struct ixgbe_ring_feature *fcoe;
565 fcoe = &adapter->ring_feature[RING_F_FCOE];
567 /* limit ourselves based on feature limits */
568 fcoe_i = min_t(u16, fcoe_i, fcoe->limit);
570 if (vmdq_i > 1 && fcoe_i) {
571 /* alloc queues for FCoE separately */
572 fcoe->indices = fcoe_i;
573 fcoe->offset = vmdq_i * rss_i;
575 /* merge FCoE queues with RSS queues */
576 fcoe_i = min_t(u16, fcoe_i + rss_i, num_online_cpus());
578 /* limit indices to rss_i if MSI-X is disabled */
579 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
582 /* attempt to reserve some queues for just FCoE */
583 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit);
584 fcoe->offset = fcoe_i - fcoe->indices;
589 /* add queues to adapter */
590 adapter->num_tx_queues += fcoe_i;
591 adapter->num_rx_queues += fcoe_i;
599 * ixgbe_set_rss_queues - Allocate queues for RSS
600 * @adapter: board private structure to initialize
602 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
603 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
606 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
608 struct ixgbe_hw *hw = &adapter->hw;
609 struct ixgbe_ring_feature *f;
612 /* set mask for 16 queue limit of RSS */
613 f = &adapter->ring_feature[RING_F_RSS];
618 if (hw->mac.type < ixgbe_mac_X550)
619 f->mask = IXGBE_RSS_16Q_MASK;
621 f->mask = IXGBE_RSS_64Q_MASK;
623 /* disable ATR by default, it will be configured below */
624 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
627 * Use Flow Director in addition to RSS to ensure the best
628 * distribution of flows across cores, even when an FDIR flow
631 if (rss_i > 1 && adapter->atr_sample_rate) {
632 f = &adapter->ring_feature[RING_F_FDIR];
634 rss_i = f->indices = f->limit;
636 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
637 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
642 * FCoE can exist on the same rings as standard network traffic
643 * however it is preferred to avoid that if possible. In order
644 * to get the best performance we allocate as many FCoE queues
645 * as we can and we place them at the end of the ring array to
646 * avoid sharing queues with standard RSS on systems with 24 or
649 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
650 struct net_device *dev = adapter->netdev;
653 f = &adapter->ring_feature[RING_F_FCOE];
655 /* merge FCoE queues with RSS queues */
656 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus());
657 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues);
659 /* limit indices to rss_i if MSI-X is disabled */
660 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
663 /* attempt to reserve some queues for just FCoE */
664 f->indices = min_t(u16, fcoe_i, f->limit);
665 f->offset = fcoe_i - f->indices;
666 rss_i = max_t(u16, fcoe_i, rss_i);
669 #endif /* IXGBE_FCOE */
670 adapter->num_rx_queues = rss_i;
671 adapter->num_tx_queues = rss_i;
677 * ixgbe_set_num_queues - Allocate queues for device, feature dependent
678 * @adapter: board private structure to initialize
680 * This is the top level queue allocation routine. The order here is very
681 * important, starting with the "most" number of features turned on at once,
682 * and ending with the smallest set of features. This way large combinations
683 * can be allocated if they're turned on, and smaller combinations are the
684 * fallthrough conditions.
687 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
689 /* Start with base case */
690 adapter->num_rx_queues = 1;
691 adapter->num_tx_queues = 1;
692 adapter->num_rx_pools = adapter->num_rx_queues;
693 adapter->num_rx_queues_per_pool = 1;
695 #ifdef CONFIG_IXGBE_DCB
696 if (ixgbe_set_dcb_sriov_queues(adapter))
699 if (ixgbe_set_dcb_queues(adapter))
703 if (ixgbe_set_sriov_queues(adapter))
706 ixgbe_set_rss_queues(adapter);
710 * ixgbe_acquire_msix_vectors - acquire MSI-X vectors
711 * @adapter: board private structure
713 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
714 * return a negative error code if unable to acquire MSI-X vectors for any
717 static int ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter)
719 struct ixgbe_hw *hw = &adapter->hw;
720 int i, vectors, vector_threshold;
722 /* We start by asking for one vector per queue pair */
723 vectors = max(adapter->num_rx_queues, adapter->num_tx_queues);
725 /* It is easy to be greedy for MSI-X vectors. However, it really
726 * doesn't do much good if we have a lot more vectors than CPUs. We'll
727 * be somewhat conservative and only ask for (roughly) the same number
728 * of vectors as there are CPUs.
730 vectors = min_t(int, vectors, num_online_cpus());
732 /* Some vectors are necessary for non-queue interrupts */
733 vectors += NON_Q_VECTORS;
735 /* Hardware can only support a maximum of hw.mac->max_msix_vectors.
736 * With features such as RSS and VMDq, we can easily surpass the
737 * number of Rx and Tx descriptor queues supported by our device.
738 * Thus, we cap the maximum in the rare cases where the CPU count also
739 * exceeds our vector limit
741 vectors = min_t(int, vectors, hw->mac.max_msix_vectors);
743 /* We want a minimum of two MSI-X vectors for (1) a TxQ[0] + RxQ[0]
744 * handler, and (2) an Other (Link Status Change, etc.) handler.
746 vector_threshold = MIN_MSIX_COUNT;
748 adapter->msix_entries = kcalloc(vectors,
749 sizeof(struct msix_entry),
751 if (!adapter->msix_entries)
754 for (i = 0; i < vectors; i++)
755 adapter->msix_entries[i].entry = i;
757 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries,
758 vector_threshold, vectors);
761 /* A negative count of allocated vectors indicates an error in
762 * acquiring within the specified range of MSI-X vectors
764 e_dev_warn("Failed to allocate MSI-X interrupts. Err: %d\n",
767 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
768 kfree(adapter->msix_entries);
769 adapter->msix_entries = NULL;
774 /* we successfully allocated some number of vectors within our
777 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED;
779 /* Adjust for only the vectors we'll use, which is minimum
780 * of max_q_vectors, or the number of vectors we were allocated.
782 vectors -= NON_Q_VECTORS;
783 adapter->num_q_vectors = min_t(int, vectors, adapter->max_q_vectors);
788 static void ixgbe_add_ring(struct ixgbe_ring *ring,
789 struct ixgbe_ring_container *head)
791 ring->next = head->ring;
797 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
798 * @adapter: board private structure to initialize
799 * @v_count: q_vectors allocated on adapter, used for ring interleaving
800 * @v_idx: index of vector in adapter struct
801 * @txr_count: total number of Tx rings to allocate
802 * @txr_idx: index of first Tx ring to allocate
803 * @rxr_count: total number of Rx rings to allocate
804 * @rxr_idx: index of first Rx ring to allocate
806 * We allocate one q_vector. If allocation fails we return -ENOMEM.
808 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter,
809 int v_count, int v_idx,
810 int txr_count, int txr_idx,
811 int rxr_count, int rxr_idx)
813 struct ixgbe_q_vector *q_vector;
814 struct ixgbe_ring *ring;
815 int node = NUMA_NO_NODE;
817 int ring_count, size;
818 u8 tcs = netdev_get_num_tc(adapter->netdev);
820 ring_count = txr_count + rxr_count;
821 size = sizeof(struct ixgbe_q_vector) +
822 (sizeof(struct ixgbe_ring) * ring_count);
824 /* customize cpu for Flow Director mapping */
825 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
826 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
827 if (rss_i > 1 && adapter->atr_sample_rate) {
828 if (cpu_online(v_idx)) {
830 node = cpu_to_node(cpu);
835 /* allocate q_vector and rings */
836 q_vector = kzalloc_node(size, GFP_KERNEL, node);
838 q_vector = kzalloc(size, GFP_KERNEL);
842 /* setup affinity mask and node */
844 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
845 q_vector->numa_node = node;
847 #ifdef CONFIG_IXGBE_DCA
848 /* initialize CPU for DCA */
852 /* initialize NAPI */
853 netif_napi_add(adapter->netdev, &q_vector->napi,
856 #ifdef CONFIG_NET_RX_BUSY_POLL
857 /* initialize busy poll */
858 atomic_set(&q_vector->state, IXGBE_QV_STATE_DISABLE);
861 /* tie q_vector and adapter together */
862 adapter->q_vector[v_idx] = q_vector;
863 q_vector->adapter = adapter;
864 q_vector->v_idx = v_idx;
866 /* initialize work limits */
867 q_vector->tx.work_limit = adapter->tx_work_limit;
869 /* initialize pointer to rings */
870 ring = q_vector->ring;
873 if (txr_count && !rxr_count) {
875 if (adapter->tx_itr_setting == 1)
876 q_vector->itr = IXGBE_12K_ITR;
878 q_vector->itr = adapter->tx_itr_setting;
880 /* rx or rx/tx vector */
881 if (adapter->rx_itr_setting == 1)
882 q_vector->itr = IXGBE_20K_ITR;
884 q_vector->itr = adapter->rx_itr_setting;
888 /* assign generic ring traits */
889 ring->dev = &adapter->pdev->dev;
890 ring->netdev = adapter->netdev;
892 /* configure backlink on ring */
893 ring->q_vector = q_vector;
895 /* update q_vector Tx values */
896 ixgbe_add_ring(ring, &q_vector->tx);
898 /* apply Tx specific ring traits */
899 ring->count = adapter->tx_ring_count;
900 if (adapter->num_rx_pools > 1)
902 txr_idx % adapter->num_rx_queues_per_pool;
904 ring->queue_index = txr_idx;
906 /* assign ring to adapter */
907 adapter->tx_ring[txr_idx] = ring;
909 /* update count and index */
913 /* push pointer to next ring */
918 /* assign generic ring traits */
919 ring->dev = &adapter->pdev->dev;
920 ring->netdev = adapter->netdev;
922 /* configure backlink on ring */
923 ring->q_vector = q_vector;
925 /* update q_vector Rx values */
926 ixgbe_add_ring(ring, &q_vector->rx);
929 * 82599 errata, UDP frames with a 0 checksum
930 * can be marked as checksum errors.
932 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
933 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
936 if (adapter->netdev->features & NETIF_F_FCOE_MTU) {
937 struct ixgbe_ring_feature *f;
938 f = &adapter->ring_feature[RING_F_FCOE];
939 if ((rxr_idx >= f->offset) &&
940 (rxr_idx < f->offset + f->indices))
941 set_bit(__IXGBE_RX_FCOE, &ring->state);
944 #endif /* IXGBE_FCOE */
945 /* apply Rx specific ring traits */
946 ring->count = adapter->rx_ring_count;
947 if (adapter->num_rx_pools > 1)
949 rxr_idx % adapter->num_rx_queues_per_pool;
951 ring->queue_index = rxr_idx;
953 /* assign ring to adapter */
954 adapter->rx_ring[rxr_idx] = ring;
956 /* update count and index */
960 /* push pointer to next ring */
968 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
969 * @adapter: board private structure to initialize
970 * @v_idx: Index of vector to be freed
972 * This function frees the memory allocated to the q_vector. In addition if
973 * NAPI is enabled it will delete any references to the NAPI struct prior
974 * to freeing the q_vector.
976 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
978 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
979 struct ixgbe_ring *ring;
981 ixgbe_for_each_ring(ring, q_vector->tx)
982 adapter->tx_ring[ring->queue_index] = NULL;
984 ixgbe_for_each_ring(ring, q_vector->rx)
985 adapter->rx_ring[ring->queue_index] = NULL;
987 adapter->q_vector[v_idx] = NULL;
988 napi_hash_del(&q_vector->napi);
989 netif_napi_del(&q_vector->napi);
992 * ixgbe_get_stats64() might access the rings on this vector,
993 * we must wait a grace period before freeing it.
995 kfree_rcu(q_vector, rcu);
999 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
1000 * @adapter: board private structure to initialize
1002 * We allocate one q_vector per queue interrupt. If allocation fails we
1005 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
1007 int q_vectors = adapter->num_q_vectors;
1008 int rxr_remaining = adapter->num_rx_queues;
1009 int txr_remaining = adapter->num_tx_queues;
1010 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1013 /* only one q_vector if MSI-X is disabled. */
1014 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1017 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1018 for (; rxr_remaining; v_idx++) {
1019 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx,
1025 /* update counts and index */
1031 for (; v_idx < q_vectors; v_idx++) {
1032 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1033 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1034 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx,
1041 /* update counts and index */
1042 rxr_remaining -= rqpv;
1043 txr_remaining -= tqpv;
1051 adapter->num_tx_queues = 0;
1052 adapter->num_rx_queues = 0;
1053 adapter->num_q_vectors = 0;
1056 ixgbe_free_q_vector(adapter, v_idx);
1062 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
1063 * @adapter: board private structure to initialize
1065 * This function frees the memory allocated to the q_vectors. In addition if
1066 * NAPI is enabled it will delete any references to the NAPI struct prior
1067 * to freeing the q_vector.
1069 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
1071 int v_idx = adapter->num_q_vectors;
1073 adapter->num_tx_queues = 0;
1074 adapter->num_rx_queues = 0;
1075 adapter->num_q_vectors = 0;
1078 ixgbe_free_q_vector(adapter, v_idx);
1081 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
1083 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1084 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1085 pci_disable_msix(adapter->pdev);
1086 kfree(adapter->msix_entries);
1087 adapter->msix_entries = NULL;
1088 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1089 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
1090 pci_disable_msi(adapter->pdev);
1095 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
1096 * @adapter: board private structure to initialize
1098 * Attempt to configure the interrupts using the best available
1099 * capabilities of the hardware and the kernel.
1101 static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
1105 /* We will try to get MSI-X interrupts first */
1106 if (!ixgbe_acquire_msix_vectors(adapter))
1109 /* At this point, we do not have MSI-X capabilities. We need to
1110 * reconfigure or disable various features which require MSI-X
1114 /* Disable DCB unless we only have a single traffic class */
1115 if (netdev_get_num_tc(adapter->netdev) > 1) {
1116 e_dev_warn("Number of DCB TCs exceeds number of available queues. Disabling DCB support.\n");
1117 netdev_reset_tc(adapter->netdev);
1119 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1120 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
1122 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1123 adapter->temp_dcb_cfg.pfc_mode_enable = false;
1124 adapter->dcb_cfg.pfc_mode_enable = false;
1127 adapter->dcb_cfg.num_tcs.pg_tcs = 1;
1128 adapter->dcb_cfg.num_tcs.pfc_tcs = 1;
1130 /* Disable SR-IOV support */
1131 e_dev_warn("Disabling SR-IOV support\n");
1132 ixgbe_disable_sriov(adapter);
1135 e_dev_warn("Disabling RSS support\n");
1136 adapter->ring_feature[RING_F_RSS].limit = 1;
1138 /* recalculate number of queues now that many features have been
1139 * changed or disabled.
1141 ixgbe_set_num_queues(adapter);
1142 adapter->num_q_vectors = 1;
1144 err = pci_enable_msi(adapter->pdev);
1146 e_dev_warn("Failed to allocate MSI interrupt, falling back to legacy. Error: %d\n",
1149 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
1153 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
1154 * @adapter: board private structure to initialize
1156 * We determine which interrupt scheme to use based on...
1157 * - Kernel support (MSI, MSI-X)
1158 * - which can be user-defined (via MODULE_PARAM)
1159 * - Hardware queue count (num_*_queues)
1160 * - defined by miscellaneous hardware support/features (RSS, etc.)
1162 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
1166 /* Number of supported queues */
1167 ixgbe_set_num_queues(adapter);
1169 /* Set interrupt mode */
1170 ixgbe_set_interrupt_capability(adapter);
1172 err = ixgbe_alloc_q_vectors(adapter);
1174 e_dev_err("Unable to allocate memory for queue vectors\n");
1175 goto err_alloc_q_vectors;
1178 ixgbe_cache_ring_register(adapter);
1180 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
1181 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
1182 adapter->num_rx_queues, adapter->num_tx_queues);
1184 set_bit(__IXGBE_DOWN, &adapter->state);
1188 err_alloc_q_vectors:
1189 ixgbe_reset_interrupt_capability(adapter);
1194 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
1195 * @adapter: board private structure to clear interrupt scheme on
1197 * We go through and clear interrupt specific resources and reset the structure
1198 * to pre-load conditions
1200 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
1202 adapter->num_tx_queues = 0;
1203 adapter->num_rx_queues = 0;
1205 ixgbe_free_q_vectors(adapter);
1206 ixgbe_reset_interrupt_capability(adapter);
1209 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
1210 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1212 struct ixgbe_adv_tx_context_desc *context_desc;
1213 u16 i = tx_ring->next_to_use;
1215 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
1218 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1220 /* set bits to identify this as an advanced context descriptor */
1221 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
1223 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1224 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
1225 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1226 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);