1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/netdevice.h>
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
60 /* Base table for registers values that change by MAC */
61 const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
62 IXGBE_MVALS_INIT(8259X)
66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
68 * @hw: pointer to hardware structure
70 * There are several phys that do not support autoneg flow control. This
71 * function check the device id to see if the associated phy supports
72 * autoneg flow control.
74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
76 bool supported = false;
77 ixgbe_link_speed speed;
80 switch (hw->phy.media_type) {
81 case ixgbe_media_type_fiber:
82 hw->mac.ops.check_link(hw, &speed, &link_up, false);
83 /* if link is down, assume supported */
85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
90 case ixgbe_media_type_backplane:
93 case ixgbe_media_type_copper:
94 /* only some copper devices support flow control autoneg */
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82599_T3_LOM:
97 case IXGBE_DEV_ID_X540T:
98 case IXGBE_DEV_ID_X540T1:
99 case IXGBE_DEV_ID_X550T:
100 case IXGBE_DEV_ID_X550T1:
101 case IXGBE_DEV_ID_X550EM_X_10G_T:
102 case IXGBE_DEV_ID_X550EM_A_10G_T:
116 * ixgbe_setup_fc_generic - Set up flow control
117 * @hw: pointer to hardware structure
119 * Called at init time to set up flow control.
121 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
124 u32 reg = 0, reg_bp = 0;
129 * Validate the requested mode. Strict IEEE mode does not allow
130 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
132 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
133 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
134 return IXGBE_ERR_INVALID_LINK_SETTINGS;
138 * 10gig parts do not have a word in the EEPROM to determine the
139 * default flow control setting, so we explicitly set it to full.
141 if (hw->fc.requested_mode == ixgbe_fc_default)
142 hw->fc.requested_mode = ixgbe_fc_full;
145 * Set up the 1G and 10G flow control advertisement registers so the
146 * HW will be able to do fc autoneg once the cable is plugged in. If
147 * we link at 10G, the 1G advertisement is harmless and vice versa.
149 switch (hw->phy.media_type) {
150 case ixgbe_media_type_backplane:
151 /* some MAC's need RMW protection on AUTOC */
152 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
156 /* only backplane uses autoc so fall though */
157 case ixgbe_media_type_fiber:
158 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
161 case ixgbe_media_type_copper:
162 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
163 MDIO_MMD_AN, ®_cu);
170 * The possible values of fc.requested_mode are:
171 * 0: Flow control is completely disabled
172 * 1: Rx flow control is enabled (we can receive pause frames,
173 * but not send pause frames).
174 * 2: Tx flow control is enabled (we can send pause frames but
175 * we do not support receiving pause frames).
176 * 3: Both Rx and Tx flow control (symmetric) are enabled.
179 switch (hw->fc.requested_mode) {
181 /* Flow control completely disabled by software override. */
182 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
183 if (hw->phy.media_type == ixgbe_media_type_backplane)
184 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
185 IXGBE_AUTOC_ASM_PAUSE);
186 else if (hw->phy.media_type == ixgbe_media_type_copper)
187 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
189 case ixgbe_fc_tx_pause:
191 * Tx Flow control is enabled, and Rx Flow control is
192 * disabled by software override.
194 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
195 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
196 if (hw->phy.media_type == ixgbe_media_type_backplane) {
197 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
198 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
199 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
200 reg_cu |= IXGBE_TAF_ASM_PAUSE;
201 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
204 case ixgbe_fc_rx_pause:
206 * Rx Flow control is enabled and Tx Flow control is
207 * disabled by software override. Since there really
208 * isn't a way to advertise that we are capable of RX
209 * Pause ONLY, we will advertise that we support both
210 * symmetric and asymmetric Rx PAUSE, as such we fall
211 * through to the fc_full statement. Later, we will
212 * disable the adapter's ability to send PAUSE frames.
215 /* Flow control (both Rx and Tx) is enabled by SW override. */
216 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
217 if (hw->phy.media_type == ixgbe_media_type_backplane)
218 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
219 IXGBE_AUTOC_ASM_PAUSE;
220 else if (hw->phy.media_type == ixgbe_media_type_copper)
221 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
224 hw_dbg(hw, "Flow control param set incorrectly\n");
225 return IXGBE_ERR_CONFIG;
228 if (hw->mac.type != ixgbe_mac_X540) {
230 * Enable auto-negotiation between the MAC & PHY;
231 * the MAC will advertise clause 37 flow control.
233 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
234 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
236 /* Disable AN timeout */
237 if (hw->fc.strict_ieee)
238 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
240 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
241 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
245 * AUTOC restart handles negotiation of 1G and 10G on backplane
246 * and copper. There is no need to set the PCS1GCTL register.
249 if (hw->phy.media_type == ixgbe_media_type_backplane) {
250 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
251 * LESM is on, likewise reset_pipeline requries the lock as
252 * it also writes AUTOC.
254 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
258 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
259 ixgbe_device_supports_autoneg_fc(hw)) {
260 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
261 MDIO_MMD_AN, reg_cu);
264 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
269 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
270 * @hw: pointer to hardware structure
272 * Starts the hardware by filling the bus info structure and media type, clears
273 * all on chip counters, initializes receive address registers, multicast
274 * table, VLAN filter table, calls routine to set up link and flow control
275 * settings, and leaves transmit and receive units disabled and uninitialized
277 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
283 /* Set the media type */
284 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
286 /* Identify the PHY */
287 hw->phy.ops.identify(hw);
289 /* Clear the VLAN filter table */
290 hw->mac.ops.clear_vfta(hw);
292 /* Clear statistics registers */
293 hw->mac.ops.clear_hw_cntrs(hw);
295 /* Set No Snoop Disable */
296 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
297 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
298 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
299 IXGBE_WRITE_FLUSH(hw);
301 /* Setup flow control */
302 ret_val = hw->mac.ops.setup_fc(hw);
306 /* Cashe bit indicating need for crosstalk fix */
307 switch (hw->mac.type) {
308 case ixgbe_mac_82599EB:
309 case ixgbe_mac_X550EM_x:
310 case ixgbe_mac_x550em_a:
311 hw->mac.ops.get_device_caps(hw, &device_caps);
312 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
313 hw->need_crosstalk_fix = false;
315 hw->need_crosstalk_fix = true;
318 hw->need_crosstalk_fix = false;
322 /* Clear adapter stopped flag */
323 hw->adapter_stopped = false;
329 * ixgbe_start_hw_gen2 - Init sequence for common device family
330 * @hw: pointer to hw structure
332 * Performs the init sequence common to the second generation
334 * Devices in the second generation:
338 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
342 /* Clear the rate limiters */
343 for (i = 0; i < hw->mac.max_tx_queues; i++) {
344 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
345 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
347 IXGBE_WRITE_FLUSH(hw);
350 /* Disable relaxed ordering */
351 for (i = 0; i < hw->mac.max_tx_queues; i++) {
354 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
355 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
356 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
359 for (i = 0; i < hw->mac.max_rx_queues; i++) {
362 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
363 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
364 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
365 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
372 * ixgbe_init_hw_generic - Generic hardware initialization
373 * @hw: pointer to hardware structure
375 * Initialize the hardware by resetting the hardware, filling the bus info
376 * structure and media type, clears all on chip counters, initializes receive
377 * address registers, multicast table, VLAN filter table, calls routine to set
378 * up link and flow control settings, and leaves transmit and receive units
379 * disabled and uninitialized
381 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
385 /* Reset the hardware */
386 status = hw->mac.ops.reset_hw(hw);
390 status = hw->mac.ops.start_hw(hw);
397 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
398 * @hw: pointer to hardware structure
400 * Clears all hardware statistics counters by reading them from the hardware
401 * Statistics counters are clear on read.
403 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
407 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
408 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
409 IXGBE_READ_REG(hw, IXGBE_ERRBC);
410 IXGBE_READ_REG(hw, IXGBE_MSPDC);
411 for (i = 0; i < 8; i++)
412 IXGBE_READ_REG(hw, IXGBE_MPC(i));
414 IXGBE_READ_REG(hw, IXGBE_MLFC);
415 IXGBE_READ_REG(hw, IXGBE_MRFC);
416 IXGBE_READ_REG(hw, IXGBE_RLEC);
417 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
418 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
419 if (hw->mac.type >= ixgbe_mac_82599EB) {
420 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
421 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
423 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
424 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
427 for (i = 0; i < 8; i++) {
428 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
429 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
430 if (hw->mac.type >= ixgbe_mac_82599EB) {
431 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
432 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
434 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
435 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
438 if (hw->mac.type >= ixgbe_mac_82599EB)
439 for (i = 0; i < 8; i++)
440 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
441 IXGBE_READ_REG(hw, IXGBE_PRC64);
442 IXGBE_READ_REG(hw, IXGBE_PRC127);
443 IXGBE_READ_REG(hw, IXGBE_PRC255);
444 IXGBE_READ_REG(hw, IXGBE_PRC511);
445 IXGBE_READ_REG(hw, IXGBE_PRC1023);
446 IXGBE_READ_REG(hw, IXGBE_PRC1522);
447 IXGBE_READ_REG(hw, IXGBE_GPRC);
448 IXGBE_READ_REG(hw, IXGBE_BPRC);
449 IXGBE_READ_REG(hw, IXGBE_MPRC);
450 IXGBE_READ_REG(hw, IXGBE_GPTC);
451 IXGBE_READ_REG(hw, IXGBE_GORCL);
452 IXGBE_READ_REG(hw, IXGBE_GORCH);
453 IXGBE_READ_REG(hw, IXGBE_GOTCL);
454 IXGBE_READ_REG(hw, IXGBE_GOTCH);
455 if (hw->mac.type == ixgbe_mac_82598EB)
456 for (i = 0; i < 8; i++)
457 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
458 IXGBE_READ_REG(hw, IXGBE_RUC);
459 IXGBE_READ_REG(hw, IXGBE_RFC);
460 IXGBE_READ_REG(hw, IXGBE_ROC);
461 IXGBE_READ_REG(hw, IXGBE_RJC);
462 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
463 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
464 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
465 IXGBE_READ_REG(hw, IXGBE_TORL);
466 IXGBE_READ_REG(hw, IXGBE_TORH);
467 IXGBE_READ_REG(hw, IXGBE_TPR);
468 IXGBE_READ_REG(hw, IXGBE_TPT);
469 IXGBE_READ_REG(hw, IXGBE_PTC64);
470 IXGBE_READ_REG(hw, IXGBE_PTC127);
471 IXGBE_READ_REG(hw, IXGBE_PTC255);
472 IXGBE_READ_REG(hw, IXGBE_PTC511);
473 IXGBE_READ_REG(hw, IXGBE_PTC1023);
474 IXGBE_READ_REG(hw, IXGBE_PTC1522);
475 IXGBE_READ_REG(hw, IXGBE_MPTC);
476 IXGBE_READ_REG(hw, IXGBE_BPTC);
477 for (i = 0; i < 16; i++) {
478 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
479 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
480 if (hw->mac.type >= ixgbe_mac_82599EB) {
481 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
482 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
483 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
484 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
485 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
487 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
488 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
492 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
494 hw->phy.ops.identify(hw);
495 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
496 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
497 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
498 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
505 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
506 * @hw: pointer to hardware structure
507 * @pba_num: stores the part number string from the EEPROM
508 * @pba_num_size: part number string buffer length
510 * Reads the part number string from the EEPROM.
512 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
521 if (pba_num == NULL) {
522 hw_dbg(hw, "PBA string buffer was null\n");
523 return IXGBE_ERR_INVALID_ARGUMENT;
526 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
528 hw_dbg(hw, "NVM Read Error\n");
532 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
534 hw_dbg(hw, "NVM Read Error\n");
539 * if data is not ptr guard the PBA must be in legacy format which
540 * means pba_ptr is actually our second data word for the PBA number
541 * and we can decode it into an ascii string
543 if (data != IXGBE_PBANUM_PTR_GUARD) {
544 hw_dbg(hw, "NVM PBA number is not stored as string\n");
546 /* we will need 11 characters to store the PBA */
547 if (pba_num_size < 11) {
548 hw_dbg(hw, "PBA string buffer too small\n");
549 return IXGBE_ERR_NO_SPACE;
552 /* extract hex string from data and pba_ptr */
553 pba_num[0] = (data >> 12) & 0xF;
554 pba_num[1] = (data >> 8) & 0xF;
555 pba_num[2] = (data >> 4) & 0xF;
556 pba_num[3] = data & 0xF;
557 pba_num[4] = (pba_ptr >> 12) & 0xF;
558 pba_num[5] = (pba_ptr >> 8) & 0xF;
561 pba_num[8] = (pba_ptr >> 4) & 0xF;
562 pba_num[9] = pba_ptr & 0xF;
564 /* put a null character on the end of our string */
567 /* switch all the data but the '-' to hex char */
568 for (offset = 0; offset < 10; offset++) {
569 if (pba_num[offset] < 0xA)
570 pba_num[offset] += '0';
571 else if (pba_num[offset] < 0x10)
572 pba_num[offset] += 'A' - 0xA;
578 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
580 hw_dbg(hw, "NVM Read Error\n");
584 if (length == 0xFFFF || length == 0) {
585 hw_dbg(hw, "NVM PBA number section invalid length\n");
586 return IXGBE_ERR_PBA_SECTION;
589 /* check if pba_num buffer is big enough */
590 if (pba_num_size < (((u32)length * 2) - 1)) {
591 hw_dbg(hw, "PBA string buffer too small\n");
592 return IXGBE_ERR_NO_SPACE;
595 /* trim pba length from start of string */
599 for (offset = 0; offset < length; offset++) {
600 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
602 hw_dbg(hw, "NVM Read Error\n");
605 pba_num[offset * 2] = (u8)(data >> 8);
606 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
608 pba_num[offset * 2] = '\0';
614 * ixgbe_get_mac_addr_generic - Generic get MAC address
615 * @hw: pointer to hardware structure
616 * @mac_addr: Adapter MAC address
618 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
619 * A reset of the adapter must be performed prior to calling this function
620 * in order for the MAC address to have been loaded from the EEPROM into RAR0
622 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
628 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
629 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
631 for (i = 0; i < 4; i++)
632 mac_addr[i] = (u8)(rar_low >> (i*8));
634 for (i = 0; i < 2; i++)
635 mac_addr[i+4] = (u8)(rar_high >> (i*8));
640 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
642 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
643 case IXGBE_PCI_LINK_WIDTH_1:
644 return ixgbe_bus_width_pcie_x1;
645 case IXGBE_PCI_LINK_WIDTH_2:
646 return ixgbe_bus_width_pcie_x2;
647 case IXGBE_PCI_LINK_WIDTH_4:
648 return ixgbe_bus_width_pcie_x4;
649 case IXGBE_PCI_LINK_WIDTH_8:
650 return ixgbe_bus_width_pcie_x8;
652 return ixgbe_bus_width_unknown;
656 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
658 switch (link_status & IXGBE_PCI_LINK_SPEED) {
659 case IXGBE_PCI_LINK_SPEED_2500:
660 return ixgbe_bus_speed_2500;
661 case IXGBE_PCI_LINK_SPEED_5000:
662 return ixgbe_bus_speed_5000;
663 case IXGBE_PCI_LINK_SPEED_8000:
664 return ixgbe_bus_speed_8000;
666 return ixgbe_bus_speed_unknown;
671 * ixgbe_get_bus_info_generic - Generic set PCI bus info
672 * @hw: pointer to hardware structure
674 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
676 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
680 hw->bus.type = ixgbe_bus_type_pci_express;
682 /* Get the negotiated link width and speed from PCI config space */
683 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
685 hw->bus.width = ixgbe_convert_bus_width(link_status);
686 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
688 hw->mac.ops.set_lan_id(hw);
694 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
695 * @hw: pointer to the HW structure
697 * Determines the LAN function id by reading memory-mapped registers
698 * and swaps the port value if requested.
700 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
702 struct ixgbe_bus_info *bus = &hw->bus;
706 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
707 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
708 bus->lan_id = bus->func;
710 /* check for a port swap */
711 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
712 if (reg & IXGBE_FACTPS_LFS)
715 /* Get MAC instance from EEPROM for configuring CS4227 */
716 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
717 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
718 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
719 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
724 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
725 * @hw: pointer to hardware structure
727 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
728 * disables transmit and receive units. The adapter_stopped flag is used by
729 * the shared code and drivers to determine if the adapter is in a stopped
730 * state and should not touch the hardware.
732 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
738 * Set the adapter_stopped flag so other driver functions stop touching
741 hw->adapter_stopped = true;
743 /* Disable the receive unit */
744 hw->mac.ops.disable_rx(hw);
746 /* Clear interrupt mask to stop interrupts from being generated */
747 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
749 /* Clear any pending interrupts, flush previous writes */
750 IXGBE_READ_REG(hw, IXGBE_EICR);
752 /* Disable the transmit unit. Each queue must be disabled. */
753 for (i = 0; i < hw->mac.max_tx_queues; i++)
754 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
756 /* Disable the receive unit by stopping each queue */
757 for (i = 0; i < hw->mac.max_rx_queues; i++) {
758 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
759 reg_val &= ~IXGBE_RXDCTL_ENABLE;
760 reg_val |= IXGBE_RXDCTL_SWFLSH;
761 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
764 /* flush all queues disables */
765 IXGBE_WRITE_FLUSH(hw);
766 usleep_range(1000, 2000);
769 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
770 * access and verify no pending requests
772 return ixgbe_disable_pcie_master(hw);
776 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
777 * @hw: pointer to hardware structure
778 * @index: led number to turn on
780 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
782 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
785 return IXGBE_ERR_PARAM;
787 /* To turn on the LED, set mode to ON. */
788 led_reg &= ~IXGBE_LED_MODE_MASK(index);
789 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
790 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
791 IXGBE_WRITE_FLUSH(hw);
797 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
798 * @hw: pointer to hardware structure
799 * @index: led number to turn off
801 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
803 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
806 return IXGBE_ERR_PARAM;
808 /* To turn off the LED, set mode to OFF. */
809 led_reg &= ~IXGBE_LED_MODE_MASK(index);
810 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
811 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
812 IXGBE_WRITE_FLUSH(hw);
818 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
819 * @hw: pointer to hardware structure
821 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
822 * ixgbe_hw struct in order to set up EEPROM access.
824 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
826 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
830 if (eeprom->type == ixgbe_eeprom_uninitialized) {
831 eeprom->type = ixgbe_eeprom_none;
832 /* Set default semaphore delay to 10ms which is a well
834 eeprom->semaphore_delay = 10;
835 /* Clear EEPROM page size, it will be initialized as needed */
836 eeprom->word_page_size = 0;
839 * Check for EEPROM present first.
840 * If not present leave as none
842 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
843 if (eec & IXGBE_EEC_PRES) {
844 eeprom->type = ixgbe_eeprom_spi;
847 * SPI EEPROM is assumed here. This code would need to
848 * change if a future EEPROM is not SPI.
850 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
851 IXGBE_EEC_SIZE_SHIFT);
852 eeprom->word_size = BIT(eeprom_size +
853 IXGBE_EEPROM_WORD_SIZE_SHIFT);
856 if (eec & IXGBE_EEC_ADDR_SIZE)
857 eeprom->address_bits = 16;
859 eeprom->address_bits = 8;
860 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
861 eeprom->type, eeprom->word_size, eeprom->address_bits);
868 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
869 * @hw: pointer to hardware structure
870 * @offset: offset within the EEPROM to write
871 * @words: number of words
872 * @data: 16 bit word(s) to write to EEPROM
874 * Reads 16 bit word(s) from EEPROM through bit-bang method
876 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
877 u16 words, u16 *data)
882 hw->eeprom.ops.init_params(hw);
885 return IXGBE_ERR_INVALID_ARGUMENT;
887 if (offset + words > hw->eeprom.word_size)
888 return IXGBE_ERR_EEPROM;
891 * The EEPROM page size cannot be queried from the chip. We do lazy
892 * initialization. It is worth to do that when we write large buffer.
894 if ((hw->eeprom.word_page_size == 0) &&
895 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
896 ixgbe_detect_eeprom_page_size_generic(hw, offset);
899 * We cannot hold synchronization semaphores for too long
900 * to avoid other entity starvation. However it is more efficient
901 * to read in bursts than synchronizing access for each word.
903 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
904 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
905 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
906 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
917 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
918 * @hw: pointer to hardware structure
919 * @offset: offset within the EEPROM to be written to
920 * @words: number of word(s)
921 * @data: 16 bit word(s) to be written to the EEPROM
923 * If ixgbe_eeprom_update_checksum is not called after this function, the
924 * EEPROM will most likely contain an invalid checksum.
926 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
927 u16 words, u16 *data)
933 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
935 /* Prepare the EEPROM for writing */
936 status = ixgbe_acquire_eeprom(hw);
940 if (ixgbe_ready_eeprom(hw) != 0) {
941 ixgbe_release_eeprom(hw);
942 return IXGBE_ERR_EEPROM;
945 for (i = 0; i < words; i++) {
946 ixgbe_standby_eeprom(hw);
948 /* Send the WRITE ENABLE command (8 bit opcode) */
949 ixgbe_shift_out_eeprom_bits(hw,
950 IXGBE_EEPROM_WREN_OPCODE_SPI,
951 IXGBE_EEPROM_OPCODE_BITS);
953 ixgbe_standby_eeprom(hw);
955 /* Some SPI eeproms use the 8th address bit embedded
958 if ((hw->eeprom.address_bits == 8) &&
959 ((offset + i) >= 128))
960 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
962 /* Send the Write command (8-bit opcode + addr) */
963 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
964 IXGBE_EEPROM_OPCODE_BITS);
965 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
966 hw->eeprom.address_bits);
968 page_size = hw->eeprom.word_page_size;
970 /* Send the data in burst via SPI */
973 word = (word >> 8) | (word << 8);
974 ixgbe_shift_out_eeprom_bits(hw, word, 16);
979 /* do not wrap around page */
980 if (((offset + i) & (page_size - 1)) ==
983 } while (++i < words);
985 ixgbe_standby_eeprom(hw);
986 usleep_range(10000, 20000);
988 /* Done with writing - release the EEPROM */
989 ixgbe_release_eeprom(hw);
995 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
996 * @hw: pointer to hardware structure
997 * @offset: offset within the EEPROM to be written to
998 * @data: 16 bit word to be written to the EEPROM
1000 * If ixgbe_eeprom_update_checksum is not called after this function, the
1001 * EEPROM will most likely contain an invalid checksum.
1003 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1005 hw->eeprom.ops.init_params(hw);
1007 if (offset >= hw->eeprom.word_size)
1008 return IXGBE_ERR_EEPROM;
1010 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1014 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1015 * @hw: pointer to hardware structure
1016 * @offset: offset within the EEPROM to be read
1017 * @words: number of word(s)
1018 * @data: read 16 bit words(s) from EEPROM
1020 * Reads 16 bit word(s) from EEPROM through bit-bang method
1022 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1023 u16 words, u16 *data)
1028 hw->eeprom.ops.init_params(hw);
1031 return IXGBE_ERR_INVALID_ARGUMENT;
1033 if (offset + words > hw->eeprom.word_size)
1034 return IXGBE_ERR_EEPROM;
1037 * We cannot hold synchronization semaphores for too long
1038 * to avoid other entity starvation. However it is more efficient
1039 * to read in bursts than synchronizing access for each word.
1041 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1042 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1043 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1045 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1056 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1057 * @hw: pointer to hardware structure
1058 * @offset: offset within the EEPROM to be read
1059 * @words: number of word(s)
1060 * @data: read 16 bit word(s) from EEPROM
1062 * Reads 16 bit word(s) from EEPROM through bit-bang method
1064 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1065 u16 words, u16 *data)
1069 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1072 /* Prepare the EEPROM for reading */
1073 status = ixgbe_acquire_eeprom(hw);
1077 if (ixgbe_ready_eeprom(hw) != 0) {
1078 ixgbe_release_eeprom(hw);
1079 return IXGBE_ERR_EEPROM;
1082 for (i = 0; i < words; i++) {
1083 ixgbe_standby_eeprom(hw);
1084 /* Some SPI eeproms use the 8th address bit embedded
1087 if ((hw->eeprom.address_bits == 8) &&
1088 ((offset + i) >= 128))
1089 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1091 /* Send the READ command (opcode + addr) */
1092 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1093 IXGBE_EEPROM_OPCODE_BITS);
1094 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1095 hw->eeprom.address_bits);
1097 /* Read the data. */
1098 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1099 data[i] = (word_in >> 8) | (word_in << 8);
1102 /* End this read operation */
1103 ixgbe_release_eeprom(hw);
1109 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1110 * @hw: pointer to hardware structure
1111 * @offset: offset within the EEPROM to be read
1112 * @data: read 16 bit value from EEPROM
1114 * Reads 16 bit value from EEPROM through bit-bang method
1116 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1119 hw->eeprom.ops.init_params(hw);
1121 if (offset >= hw->eeprom.word_size)
1122 return IXGBE_ERR_EEPROM;
1124 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1128 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1129 * @hw: pointer to hardware structure
1130 * @offset: offset of word in the EEPROM to read
1131 * @words: number of word(s)
1132 * @data: 16 bit word(s) from the EEPROM
1134 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1136 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1137 u16 words, u16 *data)
1143 hw->eeprom.ops.init_params(hw);
1146 return IXGBE_ERR_INVALID_ARGUMENT;
1148 if (offset >= hw->eeprom.word_size)
1149 return IXGBE_ERR_EEPROM;
1151 for (i = 0; i < words; i++) {
1152 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1153 IXGBE_EEPROM_RW_REG_START;
1155 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1156 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1159 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1160 IXGBE_EEPROM_RW_REG_DATA);
1162 hw_dbg(hw, "Eeprom read timed out\n");
1171 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1172 * @hw: pointer to hardware structure
1173 * @offset: offset within the EEPROM to be used as a scratch pad
1175 * Discover EEPROM page size by writing marching data at given offset.
1176 * This function is called only when we are writing a new large buffer
1177 * at given offset so the data would be overwritten anyway.
1179 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1182 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1186 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1189 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1190 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1191 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1192 hw->eeprom.word_page_size = 0;
1196 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1201 * When writing in burst more than the actual page size
1202 * EEPROM address wraps around current page.
1204 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1206 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
1207 hw->eeprom.word_page_size);
1212 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1213 * @hw: pointer to hardware structure
1214 * @offset: offset of word in the EEPROM to read
1215 * @data: word read from the EEPROM
1217 * Reads a 16 bit word from the EEPROM using the EERD register.
1219 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1221 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1225 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1226 * @hw: pointer to hardware structure
1227 * @offset: offset of word in the EEPROM to write
1228 * @words: number of words
1229 * @data: word(s) write to the EEPROM
1231 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1233 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1234 u16 words, u16 *data)
1240 hw->eeprom.ops.init_params(hw);
1243 return IXGBE_ERR_INVALID_ARGUMENT;
1245 if (offset >= hw->eeprom.word_size)
1246 return IXGBE_ERR_EEPROM;
1248 for (i = 0; i < words; i++) {
1249 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1250 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1251 IXGBE_EEPROM_RW_REG_START;
1253 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1255 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1259 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1261 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1263 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1272 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1273 * @hw: pointer to hardware structure
1274 * @offset: offset of word in the EEPROM to write
1275 * @data: word write to the EEPROM
1277 * Write a 16 bit word to the EEPROM using the EEWR register.
1279 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1281 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1285 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1286 * @hw: pointer to hardware structure
1287 * @ee_reg: EEPROM flag for polling
1289 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1290 * read or write is done respectively.
1292 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1297 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1298 if (ee_reg == IXGBE_NVM_POLL_READ)
1299 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1301 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1303 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1308 return IXGBE_ERR_EEPROM;
1312 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1313 * @hw: pointer to hardware structure
1315 * Prepares EEPROM for access using bit-bang method. This function should
1316 * be called before issuing a command to the EEPROM.
1318 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1323 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1324 return IXGBE_ERR_SWFW_SYNC;
1326 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1328 /* Request EEPROM Access */
1329 eec |= IXGBE_EEC_REQ;
1330 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1332 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1333 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1334 if (eec & IXGBE_EEC_GNT)
1339 /* Release if grant not acquired */
1340 if (!(eec & IXGBE_EEC_GNT)) {
1341 eec &= ~IXGBE_EEC_REQ;
1342 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1343 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1345 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1346 return IXGBE_ERR_EEPROM;
1349 /* Setup EEPROM for Read/Write */
1350 /* Clear CS and SK */
1351 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1352 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1353 IXGBE_WRITE_FLUSH(hw);
1359 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1360 * @hw: pointer to hardware structure
1362 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1364 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1370 /* Get SMBI software semaphore between device drivers first */
1371 for (i = 0; i < timeout; i++) {
1373 * If the SMBI bit is 0 when we read it, then the bit will be
1374 * set and we have the semaphore
1376 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1377 if (!(swsm & IXGBE_SWSM_SMBI))
1379 usleep_range(50, 100);
1383 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
1384 /* this release is particularly important because our attempts
1385 * above to get the semaphore may have succeeded, and if there
1386 * was a timeout, we should unconditionally clear the semaphore
1387 * bits to free the driver to make progress
1389 ixgbe_release_eeprom_semaphore(hw);
1391 usleep_range(50, 100);
1393 * If the SMBI bit is 0 when we read it, then the bit will be
1394 * set and we have the semaphore
1396 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1397 if (swsm & IXGBE_SWSM_SMBI) {
1398 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1399 return IXGBE_ERR_EEPROM;
1403 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1404 for (i = 0; i < timeout; i++) {
1405 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1407 /* Set the SW EEPROM semaphore bit to request access */
1408 swsm |= IXGBE_SWSM_SWESMBI;
1409 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
1411 /* If we set the bit successfully then we got the
1414 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1415 if (swsm & IXGBE_SWSM_SWESMBI)
1418 usleep_range(50, 100);
1421 /* Release semaphores and return error if SW EEPROM semaphore
1422 * was not granted because we don't have access to the EEPROM
1425 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1426 ixgbe_release_eeprom_semaphore(hw);
1427 return IXGBE_ERR_EEPROM;
1434 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1435 * @hw: pointer to hardware structure
1437 * This function clears hardware semaphore bits.
1439 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1443 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1445 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1446 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1447 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
1448 IXGBE_WRITE_FLUSH(hw);
1452 * ixgbe_ready_eeprom - Polls for EEPROM ready
1453 * @hw: pointer to hardware structure
1455 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1461 * Read "Status Register" repeatedly until the LSB is cleared. The
1462 * EEPROM will signal that the command has been completed by clearing
1463 * bit 0 of the internal status register. If it's not cleared within
1464 * 5 milliseconds, then error out.
1466 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1467 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1468 IXGBE_EEPROM_OPCODE_BITS);
1469 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1470 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1474 ixgbe_standby_eeprom(hw);
1478 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1479 * devices (and only 0-5mSec on 5V devices)
1481 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1482 hw_dbg(hw, "SPI EEPROM Status error\n");
1483 return IXGBE_ERR_EEPROM;
1490 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1491 * @hw: pointer to hardware structure
1493 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1497 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1499 /* Toggle CS to flush commands */
1500 eec |= IXGBE_EEC_CS;
1501 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1502 IXGBE_WRITE_FLUSH(hw);
1504 eec &= ~IXGBE_EEC_CS;
1505 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1506 IXGBE_WRITE_FLUSH(hw);
1511 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1512 * @hw: pointer to hardware structure
1513 * @data: data to send to the EEPROM
1514 * @count: number of bits to shift out
1516 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1523 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1526 * Mask is used to shift "count" bits of "data" out to the EEPROM
1527 * one bit at a time. Determine the starting bit based on count
1529 mask = BIT(count - 1);
1531 for (i = 0; i < count; i++) {
1533 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1534 * "1", and then raising and then lowering the clock (the SK
1535 * bit controls the clock input to the EEPROM). A "0" is
1536 * shifted out to the EEPROM by setting "DI" to "0" and then
1537 * raising and then lowering the clock.
1540 eec |= IXGBE_EEC_DI;
1542 eec &= ~IXGBE_EEC_DI;
1544 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1545 IXGBE_WRITE_FLUSH(hw);
1549 ixgbe_raise_eeprom_clk(hw, &eec);
1550 ixgbe_lower_eeprom_clk(hw, &eec);
1553 * Shift mask to signify next bit of data to shift in to the
1559 /* We leave the "DI" bit set to "0" when we leave this routine. */
1560 eec &= ~IXGBE_EEC_DI;
1561 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1562 IXGBE_WRITE_FLUSH(hw);
1566 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1567 * @hw: pointer to hardware structure
1569 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1576 * In order to read a register from the EEPROM, we need to shift
1577 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1578 * the clock input to the EEPROM (setting the SK bit), and then reading
1579 * the value of the "DO" bit. During this "shifting in" process the
1580 * "DI" bit should always be clear.
1582 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1584 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1586 for (i = 0; i < count; i++) {
1588 ixgbe_raise_eeprom_clk(hw, &eec);
1590 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1592 eec &= ~(IXGBE_EEC_DI);
1593 if (eec & IXGBE_EEC_DO)
1596 ixgbe_lower_eeprom_clk(hw, &eec);
1603 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1604 * @hw: pointer to hardware structure
1605 * @eec: EEC register's current value
1607 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1610 * Raise the clock input to the EEPROM
1611 * (setting the SK bit), then delay
1613 *eec = *eec | IXGBE_EEC_SK;
1614 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
1615 IXGBE_WRITE_FLUSH(hw);
1620 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1621 * @hw: pointer to hardware structure
1622 * @eecd: EECD's current value
1624 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1627 * Lower the clock input to the EEPROM (clearing the SK bit), then
1630 *eec = *eec & ~IXGBE_EEC_SK;
1631 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
1632 IXGBE_WRITE_FLUSH(hw);
1637 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1638 * @hw: pointer to hardware structure
1640 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1644 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1646 eec |= IXGBE_EEC_CS; /* Pull CS high */
1647 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1649 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1650 IXGBE_WRITE_FLUSH(hw);
1654 /* Stop requesting EEPROM access */
1655 eec &= ~IXGBE_EEC_REQ;
1656 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1658 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1661 * Delay before attempt to obtain semaphore again to allow FW
1662 * access. semaphore_delay is in ms we need us for usleep_range
1664 usleep_range(hw->eeprom.semaphore_delay * 1000,
1665 hw->eeprom.semaphore_delay * 2000);
1669 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1670 * @hw: pointer to hardware structure
1672 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1681 /* Include 0x0-0x3F in the checksum */
1682 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1683 if (hw->eeprom.ops.read(hw, i, &word)) {
1684 hw_dbg(hw, "EEPROM read failed\n");
1690 /* Include all data from pointers except for the fw pointer */
1691 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1692 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1693 hw_dbg(hw, "EEPROM read failed\n");
1694 return IXGBE_ERR_EEPROM;
1697 /* If the pointer seems invalid */
1698 if (pointer == 0xFFFF || pointer == 0)
1701 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1702 hw_dbg(hw, "EEPROM read failed\n");
1703 return IXGBE_ERR_EEPROM;
1706 if (length == 0xFFFF || length == 0)
1709 for (j = pointer + 1; j <= pointer + length; j++) {
1710 if (hw->eeprom.ops.read(hw, j, &word)) {
1711 hw_dbg(hw, "EEPROM read failed\n");
1712 return IXGBE_ERR_EEPROM;
1718 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1720 return (s32)checksum;
1724 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1725 * @hw: pointer to hardware structure
1726 * @checksum_val: calculated checksum
1728 * Performs checksum calculation and validates the EEPROM checksum. If the
1729 * caller does not need checksum_val, the value can be NULL.
1731 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1736 u16 read_checksum = 0;
1739 * Read the first word from the EEPROM. If this times out or fails, do
1740 * not continue or we could be in for a very long wait while every
1743 status = hw->eeprom.ops.read(hw, 0, &checksum);
1745 hw_dbg(hw, "EEPROM read failed\n");
1749 status = hw->eeprom.ops.calc_checksum(hw);
1753 checksum = (u16)(status & 0xffff);
1755 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1757 hw_dbg(hw, "EEPROM read failed\n");
1761 /* Verify read checksum from EEPROM is the same as
1762 * calculated checksum
1764 if (read_checksum != checksum)
1765 status = IXGBE_ERR_EEPROM_CHECKSUM;
1767 /* If the user cares, return the calculated checksum */
1769 *checksum_val = checksum;
1775 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1776 * @hw: pointer to hardware structure
1778 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1784 * Read the first word from the EEPROM. If this times out or fails, do
1785 * not continue or we could be in for a very long wait while every
1788 status = hw->eeprom.ops.read(hw, 0, &checksum);
1790 hw_dbg(hw, "EEPROM read failed\n");
1794 status = hw->eeprom.ops.calc_checksum(hw);
1798 checksum = (u16)(status & 0xffff);
1800 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1806 * ixgbe_set_rar_generic - Set Rx address register
1807 * @hw: pointer to hardware structure
1808 * @index: Receive address register to write
1809 * @addr: Address to put into receive address register
1810 * @vmdq: VMDq "set" or "pool" index
1811 * @enable_addr: set flag that address is active
1813 * Puts an ethernet address into a receive address register.
1815 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1818 u32 rar_low, rar_high;
1819 u32 rar_entries = hw->mac.num_rar_entries;
1821 /* Make sure we are using a valid rar index range */
1822 if (index >= rar_entries) {
1823 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1824 return IXGBE_ERR_INVALID_ARGUMENT;
1827 /* setup VMDq pool selection before this RAR gets enabled */
1828 hw->mac.ops.set_vmdq(hw, index, vmdq);
1831 * HW expects these in little endian so we reverse the byte
1832 * order from network order (big endian) to little endian
1834 rar_low = ((u32)addr[0] |
1835 ((u32)addr[1] << 8) |
1836 ((u32)addr[2] << 16) |
1837 ((u32)addr[3] << 24));
1839 * Some parts put the VMDq setting in the extra RAH bits,
1840 * so save everything except the lower 16 bits that hold part
1841 * of the address and the address valid bit.
1843 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1844 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1845 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1847 if (enable_addr != 0)
1848 rar_high |= IXGBE_RAH_AV;
1850 /* Record lower 32 bits of MAC address and then make
1851 * sure that write is flushed to hardware before writing
1852 * the upper 16 bits and setting the valid bit.
1854 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1855 IXGBE_WRITE_FLUSH(hw);
1856 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1862 * ixgbe_clear_rar_generic - Remove Rx address register
1863 * @hw: pointer to hardware structure
1864 * @index: Receive address register to write
1866 * Clears an ethernet address from a receive address register.
1868 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1871 u32 rar_entries = hw->mac.num_rar_entries;
1873 /* Make sure we are using a valid rar index range */
1874 if (index >= rar_entries) {
1875 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1876 return IXGBE_ERR_INVALID_ARGUMENT;
1880 * Some parts put the VMDq setting in the extra RAH bits,
1881 * so save everything except the lower 16 bits that hold part
1882 * of the address and the address valid bit.
1884 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1885 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1887 /* Clear the address valid bit and upper 16 bits of the address
1888 * before clearing the lower bits. This way we aren't updating
1891 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1892 IXGBE_WRITE_FLUSH(hw);
1893 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1895 /* clear VMDq pool/queue selection for this RAR */
1896 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1902 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1903 * @hw: pointer to hardware structure
1905 * Places the MAC address in receive address register 0 and clears the rest
1906 * of the receive address registers. Clears the multicast table. Assumes
1907 * the receiver is in reset when the routine is called.
1909 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1912 u32 rar_entries = hw->mac.num_rar_entries;
1915 * If the current mac address is valid, assume it is a software override
1916 * to the permanent address.
1917 * Otherwise, use the permanent address from the eeprom.
1919 if (!is_valid_ether_addr(hw->mac.addr)) {
1920 /* Get the MAC address from the RAR0 for later reference */
1921 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1923 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1925 /* Setup the receive address. */
1926 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1927 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1929 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1932 /* clear VMDq pool/queue selection for RAR 0 */
1933 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1935 hw->addr_ctrl.overflow_promisc = 0;
1937 hw->addr_ctrl.rar_used_count = 1;
1939 /* Zero out the other receive addresses. */
1940 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1941 for (i = 1; i < rar_entries; i++) {
1942 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1943 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1947 hw->addr_ctrl.mta_in_use = 0;
1948 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1950 hw_dbg(hw, " Clearing MTA\n");
1951 for (i = 0; i < hw->mac.mcft_size; i++)
1952 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1954 if (hw->mac.ops.init_uta_tables)
1955 hw->mac.ops.init_uta_tables(hw);
1961 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1962 * @hw: pointer to hardware structure
1963 * @mc_addr: the multicast address
1965 * Extracts the 12 bits, from a multicast address, to determine which
1966 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1967 * incoming rx multicast addresses, to determine the bit-vector to check in
1968 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1969 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1970 * to mc_filter_type.
1972 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1976 switch (hw->mac.mc_filter_type) {
1977 case 0: /* use bits [47:36] of the address */
1978 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1980 case 1: /* use bits [46:35] of the address */
1981 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1983 case 2: /* use bits [45:34] of the address */
1984 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1986 case 3: /* use bits [43:32] of the address */
1987 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1989 default: /* Invalid mc_filter_type */
1990 hw_dbg(hw, "MC filter type param set incorrectly\n");
1994 /* vector can only be 12-bits or boundary will be exceeded */
2000 * ixgbe_set_mta - Set bit-vector in multicast table
2001 * @hw: pointer to hardware structure
2002 * @hash_value: Multicast address hash value
2004 * Sets the bit-vector in the multicast table.
2006 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2012 hw->addr_ctrl.mta_in_use++;
2014 vector = ixgbe_mta_vector(hw, mc_addr);
2015 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2018 * The MTA is a register array of 128 32-bit registers. It is treated
2019 * like an array of 4096 bits. We want to set bit
2020 * BitArray[vector_value]. So we figure out what register the bit is
2021 * in, read it, OR in the new bit, then write back the new value. The
2022 * register is determined by the upper 7 bits of the vector value and
2023 * the bit within that register are determined by the lower 5 bits of
2026 vector_reg = (vector >> 5) & 0x7F;
2027 vector_bit = vector & 0x1F;
2028 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);
2032 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2033 * @hw: pointer to hardware structure
2034 * @netdev: pointer to net device structure
2036 * The given list replaces any existing list. Clears the MC addrs from receive
2037 * address registers and the multicast table. Uses unused receive address
2038 * registers for the first multicast addresses, and hashes the rest into the
2041 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2042 struct net_device *netdev)
2044 struct netdev_hw_addr *ha;
2048 * Set the new number of MC addresses that we are being requested to
2051 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
2052 hw->addr_ctrl.mta_in_use = 0;
2054 /* Clear mta_shadow */
2055 hw_dbg(hw, " Clearing MTA\n");
2056 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2058 /* Update mta shadow */
2059 netdev_for_each_mc_addr(ha, netdev) {
2060 hw_dbg(hw, " Adding the multicast addresses:\n");
2061 ixgbe_set_mta(hw, ha->addr);
2065 for (i = 0; i < hw->mac.mcft_size; i++)
2066 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2067 hw->mac.mta_shadow[i]);
2069 if (hw->addr_ctrl.mta_in_use > 0)
2070 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2071 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2073 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2078 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2079 * @hw: pointer to hardware structure
2081 * Enables multicast address in RAR and the use of the multicast hash table.
2083 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2085 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2087 if (a->mta_in_use > 0)
2088 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2089 hw->mac.mc_filter_type);
2095 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2096 * @hw: pointer to hardware structure
2098 * Disables multicast address in RAR and the use of the multicast hash table.
2100 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2102 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2104 if (a->mta_in_use > 0)
2105 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2111 * ixgbe_fc_enable_generic - Enable flow control
2112 * @hw: pointer to hardware structure
2114 * Enable flow control according to the current settings.
2116 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2118 u32 mflcn_reg, fccfg_reg;
2123 /* Validate the water mark configuration. */
2124 if (!hw->fc.pause_time)
2125 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2127 /* Low water mark of zero causes XOFF floods */
2128 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2129 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2130 hw->fc.high_water[i]) {
2131 if (!hw->fc.low_water[i] ||
2132 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2133 hw_dbg(hw, "Invalid water mark configuration\n");
2134 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2139 /* Negotiate the fc mode to use */
2140 ixgbe_fc_autoneg(hw);
2142 /* Disable any previous flow control settings */
2143 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2144 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2146 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2147 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2150 * The possible values of fc.current_mode are:
2151 * 0: Flow control is completely disabled
2152 * 1: Rx flow control is enabled (we can receive pause frames,
2153 * but not send pause frames).
2154 * 2: Tx flow control is enabled (we can send pause frames but
2155 * we do not support receiving pause frames).
2156 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2159 switch (hw->fc.current_mode) {
2162 * Flow control is disabled by software override or autoneg.
2163 * The code below will actually disable it in the HW.
2166 case ixgbe_fc_rx_pause:
2168 * Rx Flow control is enabled and Tx Flow control is
2169 * disabled by software override. Since there really
2170 * isn't a way to advertise that we are capable of RX
2171 * Pause ONLY, we will advertise that we support both
2172 * symmetric and asymmetric Rx PAUSE. Later, we will
2173 * disable the adapter's ability to send PAUSE frames.
2175 mflcn_reg |= IXGBE_MFLCN_RFCE;
2177 case ixgbe_fc_tx_pause:
2179 * Tx Flow control is enabled, and Rx Flow control is
2180 * disabled by software override.
2182 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2185 /* Flow control (both Rx and Tx) is enabled by SW override. */
2186 mflcn_reg |= IXGBE_MFLCN_RFCE;
2187 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2190 hw_dbg(hw, "Flow control param set incorrectly\n");
2191 return IXGBE_ERR_CONFIG;
2194 /* Set 802.3x based flow control settings. */
2195 mflcn_reg |= IXGBE_MFLCN_DPF;
2196 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2197 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2199 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2200 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2201 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2202 hw->fc.high_water[i]) {
2203 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2204 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2205 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2207 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2209 * In order to prevent Tx hangs when the internal Tx
2210 * switch is enabled we must set the high water mark
2211 * to the Rx packet buffer size - 24KB. This allows
2212 * the Tx switch to function even under heavy Rx
2215 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2218 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2221 /* Configure pause time (2 TCs per register) */
2222 reg = hw->fc.pause_time * 0x00010001U;
2223 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2224 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2226 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2232 * ixgbe_negotiate_fc - Negotiate flow control
2233 * @hw: pointer to hardware structure
2234 * @adv_reg: flow control advertised settings
2235 * @lp_reg: link partner's flow control settings
2236 * @adv_sym: symmetric pause bit in advertisement
2237 * @adv_asm: asymmetric pause bit in advertisement
2238 * @lp_sym: symmetric pause bit in link partner advertisement
2239 * @lp_asm: asymmetric pause bit in link partner advertisement
2241 * Find the intersection between advertised settings and link partner's
2242 * advertised settings
2244 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2245 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2247 if ((!(adv_reg)) || (!(lp_reg)))
2248 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2250 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2252 * Now we need to check if the user selected Rx ONLY
2253 * of pause frames. In this case, we had to advertise
2254 * FULL flow control because we could not advertise RX
2255 * ONLY. Hence, we must now check to see if we need to
2256 * turn OFF the TRANSMISSION of PAUSE frames.
2258 if (hw->fc.requested_mode == ixgbe_fc_full) {
2259 hw->fc.current_mode = ixgbe_fc_full;
2260 hw_dbg(hw, "Flow Control = FULL.\n");
2262 hw->fc.current_mode = ixgbe_fc_rx_pause;
2263 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2265 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2266 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2267 hw->fc.current_mode = ixgbe_fc_tx_pause;
2268 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2269 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2270 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2271 hw->fc.current_mode = ixgbe_fc_rx_pause;
2272 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2274 hw->fc.current_mode = ixgbe_fc_none;
2275 hw_dbg(hw, "Flow Control = NONE.\n");
2281 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2282 * @hw: pointer to hardware structure
2284 * Enable flow control according on 1 gig fiber.
2286 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2288 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2292 * On multispeed fiber at 1g, bail out if
2293 * - link is up but AN did not complete, or if
2294 * - link is up and AN completed but timed out
2297 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2298 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2299 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2300 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2302 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2303 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2305 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2306 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2307 IXGBE_PCS1GANA_ASM_PAUSE,
2308 IXGBE_PCS1GANA_SYM_PAUSE,
2309 IXGBE_PCS1GANA_ASM_PAUSE);
2315 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2316 * @hw: pointer to hardware structure
2318 * Enable flow control according to IEEE clause 37.
2320 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2322 u32 links2, anlp1_reg, autoc_reg, links;
2326 * On backplane, bail out if
2327 * - backplane autoneg was not completed, or if
2328 * - we are 82599 and link partner is not AN enabled
2330 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2331 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2332 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2334 if (hw->mac.type == ixgbe_mac_82599EB) {
2335 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2336 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2337 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2340 * Read the 10g AN autoc and LP ability registers and resolve
2341 * local flow control settings accordingly
2343 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2344 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2346 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2347 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2348 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2354 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2355 * @hw: pointer to hardware structure
2357 * Enable flow control according to IEEE clause 37.
2359 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2361 u16 technology_ability_reg = 0;
2362 u16 lp_technology_ability_reg = 0;
2364 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2366 &technology_ability_reg);
2367 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2369 &lp_technology_ability_reg);
2371 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2372 (u32)lp_technology_ability_reg,
2373 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2374 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2378 * ixgbe_fc_autoneg - Configure flow control
2379 * @hw: pointer to hardware structure
2381 * Compares our advertised flow control capabilities to those advertised by
2382 * our link partner, and determines the proper flow control mode to use.
2384 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2386 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2387 ixgbe_link_speed speed;
2391 * AN should have completed when the cable was plugged in.
2392 * Look for reasons to bail out. Bail out if:
2393 * - FC autoneg is disabled, or if
2396 * Since we're being called from an LSC, link is already known to be up.
2397 * So use link_up_wait_to_complete=false.
2399 if (hw->fc.disable_fc_autoneg)
2402 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2406 switch (hw->phy.media_type) {
2407 /* Autoneg flow control on fiber adapters */
2408 case ixgbe_media_type_fiber:
2409 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2410 ret_val = ixgbe_fc_autoneg_fiber(hw);
2413 /* Autoneg flow control on backplane adapters */
2414 case ixgbe_media_type_backplane:
2415 ret_val = ixgbe_fc_autoneg_backplane(hw);
2418 /* Autoneg flow control on copper adapters */
2419 case ixgbe_media_type_copper:
2420 if (ixgbe_device_supports_autoneg_fc(hw))
2421 ret_val = ixgbe_fc_autoneg_copper(hw);
2430 hw->fc.fc_was_autonegged = true;
2432 hw->fc.fc_was_autonegged = false;
2433 hw->fc.current_mode = hw->fc.requested_mode;
2438 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2439 * @hw: pointer to hardware structure
2441 * System-wide timeout range is encoded in PCIe Device Control2 register.
2443 * Add 10% to specified maximum and return the number of times to poll for
2444 * completion timeout, in units of 100 microsec. Never return less than
2445 * 800 = 80 millisec.
2447 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2452 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
2453 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2456 case IXGBE_PCIDEVCTRL2_65_130ms:
2457 pollcnt = 1300; /* 130 millisec */
2459 case IXGBE_PCIDEVCTRL2_260_520ms:
2460 pollcnt = 5200; /* 520 millisec */
2462 case IXGBE_PCIDEVCTRL2_1_2s:
2463 pollcnt = 20000; /* 2 sec */
2465 case IXGBE_PCIDEVCTRL2_4_8s:
2466 pollcnt = 80000; /* 8 sec */
2468 case IXGBE_PCIDEVCTRL2_17_34s:
2469 pollcnt = 34000; /* 34 sec */
2471 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2472 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2473 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2474 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2476 pollcnt = 800; /* 80 millisec minimum */
2480 /* add 10% to spec maximum */
2481 return (pollcnt * 11) / 10;
2485 * ixgbe_disable_pcie_master - Disable PCI-express master access
2486 * @hw: pointer to hardware structure
2488 * Disables PCI-Express master access and verifies there are no pending
2489 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2490 * bit hasn't caused the master requests to be disabled, else 0
2491 * is returned signifying master requests disabled.
2493 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2498 /* Always set this bit to ensure any future transactions are blocked */
2499 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2501 /* Poll for bit to read as set */
2502 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2503 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
2505 usleep_range(100, 120);
2507 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) {
2508 hw_dbg(hw, "GIO disable did not set - requesting resets\n");
2509 goto gio_disable_fail;
2512 /* Exit if master requests are blocked */
2513 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2514 ixgbe_removed(hw->hw_addr))
2517 /* Poll for master request bit to clear */
2518 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2520 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2525 * Two consecutive resets are required via CTRL.RST per datasheet
2526 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2527 * of this need. The first reset prevents new master requests from
2528 * being issued by our device. We then must wait 1usec or more for any
2529 * remaining completions from the PCIe bus to trickle in, and then reset
2530 * again to clear out any effects they may have had on our device.
2532 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2534 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2536 if (hw->mac.type >= ixgbe_mac_X550)
2540 * Before proceeding, make sure that the PCIe block does not have
2541 * transactions pending.
2543 poll = ixgbe_pcie_timeout_poll(hw);
2544 for (i = 0; i < poll; i++) {
2546 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2547 if (ixgbe_removed(hw->hw_addr))
2549 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2553 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2554 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
2558 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2559 * @hw: pointer to hardware structure
2560 * @mask: Mask to specify which semaphore to acquire
2562 * Acquires the SWFW semaphore through the GSSR register for the specified
2563 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2565 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2569 u32 fwmask = mask << 5;
2573 for (i = 0; i < timeout; i++) {
2575 * SW NVM semaphore bit is used for access to all
2576 * SW_FW_SYNC bits (not just NVM)
2578 if (ixgbe_get_eeprom_semaphore(hw))
2579 return IXGBE_ERR_SWFW_SYNC;
2581 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2582 if (!(gssr & (fwmask | swmask))) {
2584 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2585 ixgbe_release_eeprom_semaphore(hw);
2588 /* Resource is currently in use by FW or SW */
2589 ixgbe_release_eeprom_semaphore(hw);
2590 usleep_range(5000, 10000);
2594 /* If time expired clear the bits holding the lock and retry */
2595 if (gssr & (fwmask | swmask))
2596 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2598 usleep_range(5000, 10000);
2599 return IXGBE_ERR_SWFW_SYNC;
2603 * ixgbe_release_swfw_sync - Release SWFW semaphore
2604 * @hw: pointer to hardware structure
2605 * @mask: Mask to specify which semaphore to release
2607 * Releases the SWFW semaphore through the GSSR register for the specified
2608 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2610 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2615 ixgbe_get_eeprom_semaphore(hw);
2617 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2619 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2621 ixgbe_release_eeprom_semaphore(hw);
2625 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2626 * @hw: pointer to hardware structure
2627 * @reg_val: Value we read from AUTOC
2628 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2629 * true in this the generic case.
2631 * The default case requires no protection so just to the register read.
2633 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2636 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2641 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2642 * @hw: pointer to hardware structure
2643 * @reg_val: value to write to AUTOC
2644 * @locked: bool to indicate whether the SW/FW lock was already taken by
2647 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2649 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2654 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2655 * @hw: pointer to hardware structure
2657 * Stops the receive data path and waits for the HW to internally
2658 * empty the Rx security block.
2660 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2662 #define IXGBE_MAX_SECRX_POLL 40
2666 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2667 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2668 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2669 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2670 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2671 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2674 /* Use interrupt-safe sleep just in case */
2678 /* For informational purposes only */
2679 if (i >= IXGBE_MAX_SECRX_POLL)
2680 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
2687 * ixgbe_enable_rx_buff - Enables the receive data path
2688 * @hw: pointer to hardware structure
2690 * Enables the receive data path
2692 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2696 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2697 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2698 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2699 IXGBE_WRITE_FLUSH(hw);
2705 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2706 * @hw: pointer to hardware structure
2707 * @regval: register value to write to RXCTRL
2709 * Enables the Rx DMA unit
2711 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2713 if (regval & IXGBE_RXCTRL_RXEN)
2714 hw->mac.ops.enable_rx(hw);
2716 hw->mac.ops.disable_rx(hw);
2722 * ixgbe_blink_led_start_generic - Blink LED based on index.
2723 * @hw: pointer to hardware structure
2724 * @index: led number to blink
2726 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2728 ixgbe_link_speed speed = 0;
2729 bool link_up = false;
2730 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2731 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2732 bool locked = false;
2736 return IXGBE_ERR_PARAM;
2739 * Link must be up to auto-blink the LEDs;
2740 * Force it if link is down.
2742 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2745 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2749 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2750 autoc_reg |= IXGBE_AUTOC_FLU;
2752 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2756 IXGBE_WRITE_FLUSH(hw);
2758 usleep_range(10000, 20000);
2761 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2762 led_reg |= IXGBE_LED_BLINK(index);
2763 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2764 IXGBE_WRITE_FLUSH(hw);
2770 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2771 * @hw: pointer to hardware structure
2772 * @index: led number to stop blinking
2774 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2777 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2778 bool locked = false;
2782 return IXGBE_ERR_PARAM;
2784 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2788 autoc_reg &= ~IXGBE_AUTOC_FLU;
2789 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2791 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2795 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2796 led_reg &= ~IXGBE_LED_BLINK(index);
2797 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2798 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2799 IXGBE_WRITE_FLUSH(hw);
2805 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2806 * @hw: pointer to hardware structure
2807 * @san_mac_offset: SAN MAC address offset
2809 * This function will read the EEPROM location for the SAN MAC address
2810 * pointer, and returns the value at that location. This is used in both
2811 * get and set mac_addr routines.
2813 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2814 u16 *san_mac_offset)
2819 * First read the EEPROM pointer to see if the MAC addresses are
2822 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2825 hw_err(hw, "eeprom read at offset %d failed\n",
2826 IXGBE_SAN_MAC_ADDR_PTR);
2832 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2833 * @hw: pointer to hardware structure
2834 * @san_mac_addr: SAN MAC address
2836 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2837 * per-port, so set_lan_id() must be called before reading the addresses.
2838 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2839 * upon for non-SFP connections, so we must call it here.
2841 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2843 u16 san_mac_data, san_mac_offset;
2848 * First read the EEPROM pointer to see if the MAC addresses are
2849 * available. If they're not, no point in calling set_lan_id() here.
2851 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2852 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
2854 goto san_mac_addr_clr;
2856 /* make sure we know which port we need to program */
2857 hw->mac.ops.set_lan_id(hw);
2858 /* apply the port offset to the address offset */
2859 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2860 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2861 for (i = 0; i < 3; i++) {
2862 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2865 hw_err(hw, "eeprom read at offset %d failed\n",
2867 goto san_mac_addr_clr;
2869 san_mac_addr[i * 2] = (u8)(san_mac_data);
2870 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2876 /* No addresses available in this EEPROM. It's not necessarily an
2877 * error though, so just wipe the local address and return.
2879 for (i = 0; i < 6; i++)
2880 san_mac_addr[i] = 0xFF;
2885 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2886 * @hw: pointer to hardware structure
2888 * Read PCIe configuration space, and get the MSI-X vector count from
2889 * the capabilities table.
2891 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2897 switch (hw->mac.type) {
2898 case ixgbe_mac_82598EB:
2899 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2900 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2902 case ixgbe_mac_82599EB:
2903 case ixgbe_mac_X540:
2904 case ixgbe_mac_X550:
2905 case ixgbe_mac_X550EM_x:
2906 case ixgbe_mac_x550em_a:
2907 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2908 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2914 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2915 if (ixgbe_removed(hw->hw_addr))
2917 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2919 /* MSI-X count is zero-based in HW */
2922 if (msix_count > max_msix_count)
2923 msix_count = max_msix_count;
2929 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2930 * @hw: pointer to hardware struct
2931 * @rar: receive address register index to disassociate
2932 * @vmdq: VMDq pool index to remove from the rar
2934 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2936 u32 mpsar_lo, mpsar_hi;
2937 u32 rar_entries = hw->mac.num_rar_entries;
2939 /* Make sure we are using a valid rar index range */
2940 if (rar >= rar_entries) {
2941 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2942 return IXGBE_ERR_INVALID_ARGUMENT;
2945 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2946 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2948 if (ixgbe_removed(hw->hw_addr))
2951 if (!mpsar_lo && !mpsar_hi)
2954 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2956 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2960 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2963 } else if (vmdq < 32) {
2964 mpsar_lo &= ~BIT(vmdq);
2965 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2967 mpsar_hi &= ~BIT(vmdq - 32);
2968 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2971 /* was that the last pool using this rar? */
2972 if (mpsar_lo == 0 && mpsar_hi == 0 &&
2973 rar != 0 && rar != hw->mac.san_mac_rar_index)
2974 hw->mac.ops.clear_rar(hw, rar);
2980 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2981 * @hw: pointer to hardware struct
2982 * @rar: receive address register index to associate with a VMDq index
2983 * @vmdq: VMDq pool index
2985 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2988 u32 rar_entries = hw->mac.num_rar_entries;
2990 /* Make sure we are using a valid rar index range */
2991 if (rar >= rar_entries) {
2992 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2993 return IXGBE_ERR_INVALID_ARGUMENT;
2997 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2999 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3001 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3002 mpsar |= BIT(vmdq - 32);
3003 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3009 * This function should only be involved in the IOV mode.
3010 * In IOV mode, Default pool is next pool after the number of
3011 * VFs advertized and not 0.
3012 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3014 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3015 * @hw: pointer to hardware struct
3016 * @vmdq: VMDq pool index
3018 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3020 u32 rar = hw->mac.san_mac_rar_index;
3023 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));
3024 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3026 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3027 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));
3034 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3035 * @hw: pointer to hardware structure
3037 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3041 for (i = 0; i < 128; i++)
3042 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3048 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3049 * @hw: pointer to hardware structure
3050 * @vlan: VLAN id to write to VLAN filter
3052 * return the VLVF index where this VLAN id should be placed
3055 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3057 s32 regindex, first_empty_slot;
3060 /* short cut the special case */
3064 /* if vlvf_bypass is set we don't want to use an empty slot, we
3065 * will simply bypass the VLVF if there are no entries present in the
3066 * VLVF that contain our VLAN
3068 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3070 /* add VLAN enable bit for comparison */
3071 vlan |= IXGBE_VLVF_VIEN;
3073 /* Search for the vlan id in the VLVF entries. Save off the first empty
3074 * slot found along the way.
3076 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3078 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3079 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3082 if (!first_empty_slot && !bits)
3083 first_empty_slot = regindex;
3086 /* If we are here then we didn't find the VLAN. Return first empty
3087 * slot we found during our search, else error.
3089 if (!first_empty_slot)
3090 hw_dbg(hw, "No space in VLVF.\n");
3092 return first_empty_slot ? : IXGBE_ERR_NO_SPACE;
3096 * ixgbe_set_vfta_generic - Set VLAN filter table
3097 * @hw: pointer to hardware structure
3098 * @vlan: VLAN id to write to VLAN filter
3099 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3100 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3101 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3103 * Turn on/off specified VLAN in the VLAN filter table.
3105 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3106 bool vlan_on, bool vlvf_bypass)
3108 u32 regidx, vfta_delta, vfta, bits;
3111 if ((vlan > 4095) || (vind > 63))
3112 return IXGBE_ERR_PARAM;
3115 * this is a 2 part operation - first the VFTA, then the
3116 * VLVF and VLVFB if VT Mode is set
3117 * We don't write the VFTA until we know the VLVF part succeeded.
3121 * The VFTA is a bitstring made up of 128 32-bit registers
3122 * that enable the particular VLAN id, much like the MTA:
3123 * bits[11-5]: which register
3124 * bits[4-0]: which bit in the register
3127 vfta_delta = BIT(vlan % 32);
3128 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3130 /* vfta_delta represents the difference between the current value
3131 * of vfta and the value we want in the register. Since the diff
3132 * is an XOR mask we can just update vfta using an XOR.
3134 vfta_delta &= vlan_on ? ~vfta : vfta;
3140 * make sure the vlan is in VLVF
3141 * set the vind bit in the matching VLVFB
3143 * clear the pool bit and possibly the vind
3145 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3148 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3149 if (vlvf_index < 0) {
3155 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3157 /* set the pool bit */
3158 bits |= BIT(vind % 32);
3162 /* clear the pool bit */
3163 bits ^= BIT(vind % 32);
3166 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3167 /* Clear VFTA first, then disable VLVF. Otherwise
3168 * we run the risk of stray packets leaking into
3169 * the PF via the default pool
3172 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3174 /* disable VLVF and clear remaining bit from pool */
3175 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3176 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
3181 /* If there are still bits set in the VLVFB registers
3182 * for the VLAN ID indicated we need to see if the
3183 * caller is requesting that we clear the VFTA entry bit.
3184 * If the caller has requested that we clear the VFTA
3185 * entry bit but there are still pools/VFs using this VLAN
3186 * ID entry then ignore the request. We're not worried
3187 * about the case where we're turning the VFTA VLAN ID
3188 * entry bit on, only when requested to turn it off as
3189 * there may be multiple pools and/or VFs using the
3190 * VLAN ID entry. In that case we cannot clear the
3191 * VFTA bit until all pools/VFs using that VLAN ID have also
3192 * been cleared. This will be indicated by "bits" being
3198 /* record pool change and enable VLAN ID if not already enabled */
3199 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
3200 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
3203 /* Update VFTA now that we are ready for traffic */
3205 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3211 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3212 * @hw: pointer to hardware structure
3214 * Clears the VLAN filer table, and the VMDq index associated with the filter
3216 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3220 for (offset = 0; offset < hw->mac.vft_size; offset++)
3221 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3223 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3224 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3225 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3226 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
3233 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
3234 * @hw: pointer to hardware structure
3236 * Contains the logic to identify if we need to verify link for the
3239 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
3241 /* Does FW say we need the fix */
3242 if (!hw->need_crosstalk_fix)
3245 /* Only consider SFP+ PHYs i.e. media type fiber */
3246 switch (hw->mac.ops.get_media_type(hw)) {
3247 case ixgbe_media_type_fiber:
3248 case ixgbe_media_type_fiber_qsfp:
3258 * ixgbe_check_mac_link_generic - Determine link and speed status
3259 * @hw: pointer to hardware structure
3260 * @speed: pointer to link speed
3261 * @link_up: true when link is up
3262 * @link_up_wait_to_complete: bool used to wait for link up or not
3264 * Reads the links register to determine if link is up and the current speed
3266 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3267 bool *link_up, bool link_up_wait_to_complete)
3269 u32 links_reg, links_orig;
3272 /* If Crosstalk fix enabled do the sanity check of making sure
3273 * the SFP+ cage is full.
3275 if (ixgbe_need_crosstalk_fix(hw)) {
3278 switch (hw->mac.type) {
3279 case ixgbe_mac_82599EB:
3280 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3283 case ixgbe_mac_X550EM_x:
3284 case ixgbe_mac_x550em_a:
3285 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3289 /* sanity check - No SFP+ devices here */
3290 sfp_cage_full = false;
3294 if (!sfp_cage_full) {
3296 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3301 /* clear the old state */
3302 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3304 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3306 if (links_orig != links_reg) {
3307 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3308 links_orig, links_reg);
3311 if (link_up_wait_to_complete) {
3312 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3313 if (links_reg & IXGBE_LINKS_UP) {
3320 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3323 if (links_reg & IXGBE_LINKS_UP)
3329 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3330 case IXGBE_LINKS_SPEED_10G_82599:
3331 if ((hw->mac.type >= ixgbe_mac_X550) &&
3332 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3333 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3335 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3337 case IXGBE_LINKS_SPEED_1G_82599:
3338 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3340 case IXGBE_LINKS_SPEED_100_82599:
3341 if ((hw->mac.type >= ixgbe_mac_X550) &&
3342 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3343 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3345 *speed = IXGBE_LINK_SPEED_100_FULL;
3348 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3355 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3357 * @hw: pointer to hardware structure
3358 * @wwnn_prefix: the alternative WWNN prefix
3359 * @wwpn_prefix: the alternative WWPN prefix
3361 * This function will read the EEPROM from the alternative SAN MAC address
3362 * block to check the support for the alternative WWNN/WWPN prefix support.
3364 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3368 u16 alt_san_mac_blk_offset;
3370 /* clear output first */
3371 *wwnn_prefix = 0xFFFF;
3372 *wwpn_prefix = 0xFFFF;
3374 /* check if alternative SAN MAC is supported */
3375 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3376 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3377 goto wwn_prefix_err;
3379 if ((alt_san_mac_blk_offset == 0) ||
3380 (alt_san_mac_blk_offset == 0xFFFF))
3383 /* check capability in alternative san mac address block */
3384 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3385 if (hw->eeprom.ops.read(hw, offset, &caps))
3386 goto wwn_prefix_err;
3387 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3390 /* get the corresponding prefix for WWNN/WWPN */
3391 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3392 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3393 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3395 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3396 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3397 goto wwn_prefix_err;
3402 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3407 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3408 * @hw: pointer to hardware structure
3409 * @enable: enable or disable switch for MAC anti-spoofing
3410 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
3413 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3415 int vf_target_reg = vf >> 3;
3416 int vf_target_shift = vf % 8;
3419 if (hw->mac.type == ixgbe_mac_82598EB)
3422 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3424 pfvfspoof |= BIT(vf_target_shift);
3426 pfvfspoof &= ~BIT(vf_target_shift);
3427 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3431 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3432 * @hw: pointer to hardware structure
3433 * @enable: enable or disable switch for VLAN anti-spoofing
3434 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3437 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3439 int vf_target_reg = vf >> 3;
3440 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3443 if (hw->mac.type == ixgbe_mac_82598EB)
3446 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3448 pfvfspoof |= BIT(vf_target_shift);
3450 pfvfspoof &= ~BIT(vf_target_shift);
3451 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3455 * ixgbe_get_device_caps_generic - Get additional device capabilities
3456 * @hw: pointer to hardware structure
3457 * @device_caps: the EEPROM word with the extra device capabilities
3459 * This function will read the EEPROM location for the device capabilities,
3460 * and return the word through device_caps.
3462 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3464 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3470 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3471 * @hw: pointer to hardware structure
3472 * @num_pb: number of packet buffers to allocate
3473 * @headroom: reserve n KB of headroom
3474 * @strategy: packet buffer allocation strategy
3476 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3481 u32 pbsize = hw->mac.rx_pb_size;
3483 u32 rxpktsize, txpktsize, txpbthresh;
3485 /* Reserve headroom */
3491 /* Divide remaining packet buffer space amongst the number
3492 * of packet buffers requested using supplied strategy.
3495 case (PBA_STRATEGY_WEIGHTED):
3496 /* pba_80_48 strategy weight first half of packet buffer with
3497 * 5/8 of the packet buffer space.
3499 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3500 pbsize -= rxpktsize * (num_pb / 2);
3501 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3502 for (; i < (num_pb / 2); i++)
3503 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3504 /* Fall through to configure remaining packet buffers */
3505 case (PBA_STRATEGY_EQUAL):
3506 /* Divide the remaining Rx packet buffer evenly among the TCs */
3507 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3508 for (; i < num_pb; i++)
3509 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3516 * Setup Tx packet buffer and threshold equally for all TCs
3517 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3518 * 10 since the largest packet we support is just over 9K.
3520 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3521 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3522 for (i = 0; i < num_pb; i++) {
3523 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3524 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3527 /* Clear unused TCs, if any, to zero buffer size*/
3528 for (; i < IXGBE_MAX_PB; i++) {
3529 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3530 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3531 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3536 * ixgbe_calculate_checksum - Calculate checksum for buffer
3537 * @buffer: pointer to EEPROM
3538 * @length: size of EEPROM to calculate a checksum for
3540 * Calculates the checksum for some buffer on a specified length. The
3541 * checksum calculated is returned.
3543 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3551 for (i = 0; i < length; i++)
3554 return (u8) (0 - sum);
3558 * ixgbe_host_interface_command - Issue command to manageability block
3559 * @hw: pointer to the HW structure
3560 * @buffer: contains the command to write and where the return status will
3562 * @length: length of buffer, must be multiple of 4 bytes
3563 * @timeout: time in ms to wait for command completion
3564 * @return_data: read and return data from the buffer (true) or not (false)
3565 * Needed because FW structures are big endian and decoding of
3566 * these fields can be 8 bit or 16 bit based on command. Decoding
3567 * is not easily understood without making a table of commands.
3568 * So we will leave this up to the caller to read back the data
3571 * Communicates with the manageability block. On success return 0
3572 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3574 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,
3575 u32 length, u32 timeout,
3578 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3579 u32 hicr, i, bi, fwsts;
3580 u16 buf_len, dword_len;
3582 struct ixgbe_hic_hdr hdr;
3587 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3588 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
3589 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3591 /* Take management host interface semaphore */
3592 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3596 /* Set bit 9 of FWSTS clearing FW reset indication */
3597 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3598 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3600 /* Check that the host interface is enabled. */
3601 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3602 if (!(hicr & IXGBE_HICR_EN)) {
3603 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3604 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3608 /* Calculate length in DWORDs. We must be DWORD aligned */
3609 if (length % sizeof(u32)) {
3610 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3611 status = IXGBE_ERR_INVALID_ARGUMENT;
3615 dword_len = length >> 2;
3617 /* The device driver writes the relevant command block
3618 * into the ram area.
3620 for (i = 0; i < dword_len; i++)
3621 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3622 i, cpu_to_le32(bp->u32arr[i]));
3624 /* Setting this bit tells the ARC that a new command is pending. */
3625 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3627 for (i = 0; i < timeout; i++) {
3628 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3629 if (!(hicr & IXGBE_HICR_C))
3631 usleep_range(1000, 2000);
3634 /* Check command successful completion. */
3635 if ((timeout && i == timeout) ||
3636 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
3637 hw_dbg(hw, "Command has failed with no status valid.\n");
3638 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3645 /* Calculate length in DWORDs */
3646 dword_len = hdr_size >> 2;
3648 /* first pull in the header so we know the buffer length */
3649 for (bi = 0; bi < dword_len; bi++) {
3650 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3651 le32_to_cpus(&bp->u32arr[bi]);
3654 /* If there is any thing in data position pull it in */
3655 buf_len = bp->hdr.buf_len;
3659 if (length < round_up(buf_len, 4) + hdr_size) {
3660 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3661 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3665 /* Calculate length in DWORDs, add 3 for odd lengths */
3666 dword_len = (buf_len + 3) >> 2;
3668 /* Pull in the rest of the buffer (bi is where we left off) */
3669 for (; bi <= dword_len; bi++) {
3670 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3671 le32_to_cpus(&bp->u32arr[bi]);
3675 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3681 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3682 * @hw: pointer to the HW structure
3683 * @maj: driver version major number
3684 * @min: driver version minor number
3685 * @build: driver version build number
3686 * @sub: driver version sub build number
3688 * Sends driver version number to firmware through the manageability
3689 * block. On success return 0
3690 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3691 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3693 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3696 struct ixgbe_hic_drv_info fw_cmd;
3700 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3701 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3702 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3703 fw_cmd.port_num = hw->bus.func;
3704 fw_cmd.ver_maj = maj;
3705 fw_cmd.ver_min = min;
3706 fw_cmd.ver_build = build;
3707 fw_cmd.ver_sub = sub;
3708 fw_cmd.hdr.checksum = 0;
3711 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3712 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3714 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3715 ret_val = ixgbe_host_interface_command(hw, &fw_cmd,
3717 IXGBE_HI_COMMAND_TIMEOUT,
3722 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3723 FW_CEM_RESP_STATUS_SUCCESS)
3726 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3735 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3736 * @hw: pointer to the hardware structure
3738 * The 82599 and x540 MACs can experience issues if TX work is still pending
3739 * when a reset occurs. This function prevents this by flushing the PCIe
3740 * buffers on the system.
3742 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3744 u32 gcr_ext, hlreg0, i, poll;
3748 * If double reset is not requested then all transactions should
3749 * already be clear and as such there is no work to do
3751 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3755 * Set loopback enable to prevent any transmits from being sent
3756 * should the link come up. This assumes that the RXCTRL.RXEN bit
3757 * has already been cleared.
3759 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3760 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3762 /* wait for a last completion before clearing buffers */
3763 IXGBE_WRITE_FLUSH(hw);
3764 usleep_range(3000, 6000);
3766 /* Before proceeding, make sure that the PCIe block does not have
3767 * transactions pending.
3769 poll = ixgbe_pcie_timeout_poll(hw);
3770 for (i = 0; i < poll; i++) {
3771 usleep_range(100, 200);
3772 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3773 if (ixgbe_removed(hw->hw_addr))
3775 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3779 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3780 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3781 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3782 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3784 /* Flush all writes and allow 20usec for all transactions to clear */
3785 IXGBE_WRITE_FLUSH(hw);
3788 /* restore previous register values */
3789 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3790 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3793 static const u8 ixgbe_emc_temp_data[4] = {
3794 IXGBE_EMC_INTERNAL_DATA,
3795 IXGBE_EMC_DIODE1_DATA,
3796 IXGBE_EMC_DIODE2_DATA,
3797 IXGBE_EMC_DIODE3_DATA
3799 static const u8 ixgbe_emc_therm_limit[4] = {
3800 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3801 IXGBE_EMC_DIODE1_THERM_LIMIT,
3802 IXGBE_EMC_DIODE2_THERM_LIMIT,
3803 IXGBE_EMC_DIODE3_THERM_LIMIT
3807 * ixgbe_get_ets_data - Extracts the ETS bit data
3808 * @hw: pointer to hardware structure
3809 * @ets_cfg: extected ETS data
3810 * @ets_offset: offset of ETS data
3812 * Returns error code.
3814 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3819 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3823 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3824 return IXGBE_NOT_IMPLEMENTED;
3826 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3830 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3831 return IXGBE_NOT_IMPLEMENTED;
3837 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3838 * @hw: pointer to hardware structure
3840 * Returns the thermal sensor data structure
3842 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3850 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3852 /* Only support thermal sensors attached to physical port 0 */
3853 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3854 return IXGBE_NOT_IMPLEMENTED;
3856 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3860 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3861 if (num_sensors > IXGBE_MAX_SENSORS)
3862 num_sensors = IXGBE_MAX_SENSORS;
3864 for (i = 0; i < num_sensors; i++) {
3868 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3873 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3874 IXGBE_ETS_DATA_INDEX_SHIFT);
3875 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3876 IXGBE_ETS_DATA_LOC_SHIFT);
3878 if (sensor_location != 0) {
3879 status = hw->phy.ops.read_i2c_byte(hw,
3880 ixgbe_emc_temp_data[sensor_index],
3881 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3882 &data->sensor[i].temp);
3892 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3893 * @hw: pointer to hardware structure
3895 * Inits the thermal sensor thresholds according to the NVM map
3896 * and save off the threshold and location values into mac.thermal_sensor_data
3898 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3904 u8 low_thresh_delta;
3908 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3910 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3912 /* Only support thermal sensors attached to physical port 0 */
3913 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3914 return IXGBE_NOT_IMPLEMENTED;
3916 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3920 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3921 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3922 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3923 if (num_sensors > IXGBE_MAX_SENSORS)
3924 num_sensors = IXGBE_MAX_SENSORS;
3926 for (i = 0; i < num_sensors; i++) {
3930 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3931 hw_err(hw, "eeprom read at offset %d failed\n",
3932 ets_offset + 1 + i);
3935 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3936 IXGBE_ETS_DATA_INDEX_SHIFT);
3937 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3938 IXGBE_ETS_DATA_LOC_SHIFT);
3939 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3941 hw->phy.ops.write_i2c_byte(hw,
3942 ixgbe_emc_therm_limit[sensor_index],
3943 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3945 if (sensor_location == 0)
3948 data->sensor[i].location = sensor_location;
3949 data->sensor[i].caution_thresh = therm_limit;
3950 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3956 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
3960 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3961 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3962 if (hw->mac.type != ixgbe_mac_82598EB) {
3965 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3966 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3967 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3968 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3969 hw->mac.set_lben = true;
3971 hw->mac.set_lben = false;
3974 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3975 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3979 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
3983 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3984 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
3986 if (hw->mac.type != ixgbe_mac_82598EB) {
3987 if (hw->mac.set_lben) {
3990 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3991 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
3992 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3993 hw->mac.set_lben = false;
3998 /** ixgbe_mng_present - returns true when management capability is present
3999 * @hw: pointer to hardware structure
4001 bool ixgbe_mng_present(struct ixgbe_hw *hw)
4005 if (hw->mac.type < ixgbe_mac_82599EB)
4008 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
4009 fwsm &= IXGBE_FWSM_MODE_MASK;
4010 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4014 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4015 * @hw: pointer to hardware structure
4016 * @speed: new link speed
4017 * @autoneg_wait_to_complete: true when waiting for completion is needed
4019 * Set the link speed in the MAC and/or PHY register and restarts link.
4021 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4022 ixgbe_link_speed speed,
4023 bool autoneg_wait_to_complete)
4025 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4026 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4030 bool autoneg, link_up = false;
4032 /* Mask off requested but non-supported speeds */
4033 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
4037 speed &= link_speed;
4039 /* Try each speed one by one, highest priority first. We do this in
4040 * software because 10Gb fiber doesn't support speed autonegotiation.
4042 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4044 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4046 /* If we already have link at this speed, just jump out */
4047 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4052 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up)
4055 /* Set the module link speed */
4056 switch (hw->phy.media_type) {
4057 case ixgbe_media_type_fiber:
4058 hw->mac.ops.set_rate_select_speed(hw,
4059 IXGBE_LINK_SPEED_10GB_FULL);
4061 case ixgbe_media_type_fiber_qsfp:
4062 /* QSFP module automatically detects MAC link speed */
4065 hw_dbg(hw, "Unexpected media type\n");
4069 /* Allow module to change analog characteristics (1G->10G) */
4072 status = hw->mac.ops.setup_mac_link(hw,
4073 IXGBE_LINK_SPEED_10GB_FULL,
4074 autoneg_wait_to_complete);
4078 /* Flap the Tx laser if it has not already been done */
4079 if (hw->mac.ops.flap_tx_laser)
4080 hw->mac.ops.flap_tx_laser(hw);
4082 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4083 * Section 73.10.2, we may have to wait up to 500ms if KR is
4084 * attempted. 82599 uses the same timing for 10g SFI.
4086 for (i = 0; i < 5; i++) {
4087 /* Wait for the link partner to also set speed */
4090 /* If we have link, just jump out */
4091 status = hw->mac.ops.check_link(hw, &link_speed,
4101 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4103 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4104 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4106 /* If we already have link at this speed, just jump out */
4107 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4112 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up)
4115 /* Set the module link speed */
4116 switch (hw->phy.media_type) {
4117 case ixgbe_media_type_fiber:
4118 hw->mac.ops.set_rate_select_speed(hw,
4119 IXGBE_LINK_SPEED_1GB_FULL);
4121 case ixgbe_media_type_fiber_qsfp:
4122 /* QSFP module automatically detects link speed */
4125 hw_dbg(hw, "Unexpected media type\n");
4129 /* Allow module to change analog characteristics (10G->1G) */
4132 status = hw->mac.ops.setup_mac_link(hw,
4133 IXGBE_LINK_SPEED_1GB_FULL,
4134 autoneg_wait_to_complete);
4138 /* Flap the Tx laser if it has not already been done */
4139 if (hw->mac.ops.flap_tx_laser)
4140 hw->mac.ops.flap_tx_laser(hw);
4142 /* Wait for the link partner to also set speed */
4145 /* If we have link, just jump out */
4146 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4155 /* We didn't get link. Configure back to the highest speed we tried,
4156 * (if there was more than one). We call ourselves back with just the
4157 * single highest speed that the user requested.
4160 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4162 autoneg_wait_to_complete);
4165 /* Set autoneg_advertised value based on input link speed */
4166 hw->phy.autoneg_advertised = 0;
4168 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4169 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4171 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4172 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4178 * ixgbe_set_soft_rate_select_speed - Set module link speed
4179 * @hw: pointer to hardware structure
4180 * @speed: link speed to set
4182 * Set module link speed via the soft rate select.
4184 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4185 ixgbe_link_speed speed)
4191 case IXGBE_LINK_SPEED_10GB_FULL:
4192 /* one bit mask same as setting on */
4193 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4195 case IXGBE_LINK_SPEED_1GB_FULL:
4196 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4199 hw_dbg(hw, "Invalid fixed module speed\n");
4204 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4205 IXGBE_I2C_EEPROM_DEV_ADDR2,
4208 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
4212 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4214 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4215 IXGBE_I2C_EEPROM_DEV_ADDR2,
4218 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");