1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
34 #include "ixgbe_phy.h"
35 #include "ixgbe_mbx.h"
37 #define IXGBE_82599_MAX_TX_QUEUES 128
38 #define IXGBE_82599_MAX_RX_QUEUES 128
39 #define IXGBE_82599_RAR_ENTRIES 128
40 #define IXGBE_82599_MC_TBL_SIZE 128
41 #define IXGBE_82599_VFT_TBL_SIZE 128
42 #define IXGBE_82599_RX_PB_SIZE 512
44 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
48 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
60 bool autoneg_wait_to_complete);
61 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
62 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
63 u8 dev_addr, u8 *data);
64 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
65 u8 dev_addr, u8 data);
66 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
67 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
69 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
71 u32 fwsm, manc, factps;
73 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
74 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
77 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
78 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
81 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
82 if (factps & IXGBE_FACTPS_MNGCG)
88 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
90 struct ixgbe_mac_info *mac = &hw->mac;
92 /* enable the laser control functions for SFP+ fiber
95 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
96 !ixgbe_mng_enabled(hw)) {
97 mac->ops.disable_tx_laser =
98 &ixgbe_disable_tx_laser_multispeed_fiber;
99 mac->ops.enable_tx_laser =
100 &ixgbe_enable_tx_laser_multispeed_fiber;
101 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
103 mac->ops.disable_tx_laser = NULL;
104 mac->ops.enable_tx_laser = NULL;
105 mac->ops.flap_tx_laser = NULL;
108 if (hw->phy.multispeed_fiber) {
109 /* Set up dual speed SFP+ support */
110 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
111 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
112 mac->ops.set_rate_select_speed =
113 ixgbe_set_hard_rate_select_speed;
115 if ((mac->ops.get_media_type(hw) ==
116 ixgbe_media_type_backplane) &&
117 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
118 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
119 !ixgbe_verify_lesm_fw_enabled_82599(hw))
120 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
122 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
126 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
129 u16 list_offset, data_offset, data_value;
131 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
132 ixgbe_init_mac_link_ops_82599(hw);
134 hw->phy.ops.reset = NULL;
136 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
141 /* PHY config will finish before releasing the semaphore */
142 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
143 IXGBE_GSSR_MAC_CSR_SM);
145 return IXGBE_ERR_SWFW_SYNC;
147 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
149 while (data_value != 0xffff) {
150 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
151 IXGBE_WRITE_FLUSH(hw);
152 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
156 /* Release the semaphore */
157 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
159 * Delay obtaining semaphore again to allow FW access,
160 * semaphore_delay is in ms usleep_range needs us.
162 usleep_range(hw->eeprom.semaphore_delay * 1000,
163 hw->eeprom.semaphore_delay * 2000);
165 /* Restart DSP and set SFI mode */
166 ret_val = hw->mac.ops.prot_autoc_write(hw,
167 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
171 hw_dbg(hw, " sfp module setup not complete\n");
172 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
179 /* Release the semaphore */
180 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
181 /* Delay obtaining semaphore again to allow FW access,
182 * semaphore_delay is in ms usleep_range needs us.
184 usleep_range(hw->eeprom.semaphore_delay * 1000,
185 hw->eeprom.semaphore_delay * 2000);
186 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
187 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
191 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
192 * @hw: pointer to hardware structure
193 * @locked: Return the if we locked for this read.
194 * @reg_val: Value we read from AUTOC
196 * For this part (82599) we need to wrap read-modify-writes with a possible
197 * FW/SW lock. It is assumed this lock will be freed with the next
198 * prot_autoc_write_82599(). Note, that locked can only be true in cases
199 * where this function doesn't return an error.
201 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,
207 /* If LESM is on then we need to hold the SW/FW semaphore. */
208 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
209 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
210 IXGBE_GSSR_MAC_CSR_SM);
212 return IXGBE_ERR_SWFW_SYNC;
217 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
222 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
223 * @hw: pointer to hardware structure
224 * @reg_val: value to write to AUTOC
225 * @locked: bool to indicate whether the SW/FW lock was already taken by
226 * previous proc_autoc_read_82599.
228 * This part (82599) may need to hold a the SW/FW lock around all writes to
229 * AUTOC. Likewise after a write we need to do a pipeline reset.
231 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
235 /* Blocked by MNG FW so bail */
236 if (ixgbe_check_reset_blocked(hw))
239 /* We only need to get the lock if:
240 * - We didn't do it already (in the read part of a read-modify-write)
243 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
244 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
245 IXGBE_GSSR_MAC_CSR_SM);
247 return IXGBE_ERR_SWFW_SYNC;
252 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
253 ret_val = ixgbe_reset_pipeline_82599(hw);
256 /* Free the SW/FW semaphore as we either grabbed it here or
257 * already had it when this function was called.
260 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
265 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
267 struct ixgbe_mac_info *mac = &hw->mac;
269 ixgbe_init_mac_link_ops_82599(hw);
271 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
272 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
273 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
274 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
275 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
276 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
277 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
283 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
284 * @hw: pointer to hardware structure
286 * Initialize any function pointers that were not able to be
287 * set during get_invariants because the PHY/SFP type was
288 * not known. Perform the SFP init if necessary.
291 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
293 struct ixgbe_mac_info *mac = &hw->mac;
294 struct ixgbe_phy_info *phy = &hw->phy;
298 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
299 /* Store flag indicating I2C bus access control unit. */
300 hw->phy.qsfp_shared_i2c_bus = true;
302 /* Initialize access to QSFP+ I2C bus */
303 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
304 esdp |= IXGBE_ESDP_SDP0_DIR;
305 esdp &= ~IXGBE_ESDP_SDP1_DIR;
306 esdp &= ~IXGBE_ESDP_SDP0;
307 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
308 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
309 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
310 IXGBE_WRITE_FLUSH(hw);
312 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
313 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
316 /* Identify the PHY or SFP module */
317 ret_val = phy->ops.identify(hw);
319 /* Setup function pointers based on detected SFP module and speeds */
320 ixgbe_init_mac_link_ops_82599(hw);
322 /* If copper media, overwrite with copper function pointers */
323 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
324 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
325 mac->ops.get_link_capabilities =
326 &ixgbe_get_copper_link_capabilities_generic;
329 /* Set necessary function pointers based on phy type */
330 switch (hw->phy.type) {
332 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
333 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
334 phy->ops.get_firmware_version =
335 &ixgbe_get_phy_firmware_version_tnx;
345 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
346 * @hw: pointer to hardware structure
347 * @speed: pointer to link speed
348 * @autoneg: true when autoneg or autotry is enabled
350 * Determines the link capabilities by reading the AUTOC register.
352 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
353 ixgbe_link_speed *speed,
358 /* Determine 1G link capabilities off of SFP+ type */
359 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
360 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
361 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
362 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
363 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
364 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
365 *speed = IXGBE_LINK_SPEED_1GB_FULL;
371 * Determine link capabilities based on the stored value of AUTOC,
372 * which represents EEPROM defaults. If AUTOC value has not been
373 * stored, use the current register value.
375 if (hw->mac.orig_link_settings_stored)
376 autoc = hw->mac.orig_autoc;
378 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
380 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
381 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
382 *speed = IXGBE_LINK_SPEED_1GB_FULL;
386 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
387 *speed = IXGBE_LINK_SPEED_10GB_FULL;
391 case IXGBE_AUTOC_LMS_1G_AN:
392 *speed = IXGBE_LINK_SPEED_1GB_FULL;
396 case IXGBE_AUTOC_LMS_10G_SERIAL:
397 *speed = IXGBE_LINK_SPEED_10GB_FULL;
401 case IXGBE_AUTOC_LMS_KX4_KX_KR:
402 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
403 *speed = IXGBE_LINK_SPEED_UNKNOWN;
404 if (autoc & IXGBE_AUTOC_KR_SUPP)
405 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
406 if (autoc & IXGBE_AUTOC_KX4_SUPP)
407 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
408 if (autoc & IXGBE_AUTOC_KX_SUPP)
409 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
413 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
414 *speed = IXGBE_LINK_SPEED_100_FULL;
415 if (autoc & IXGBE_AUTOC_KR_SUPP)
416 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
417 if (autoc & IXGBE_AUTOC_KX4_SUPP)
418 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
419 if (autoc & IXGBE_AUTOC_KX_SUPP)
420 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
424 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
425 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
430 return IXGBE_ERR_LINK_SETUP;
433 if (hw->phy.multispeed_fiber) {
434 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
435 IXGBE_LINK_SPEED_1GB_FULL;
437 /* QSFP must not enable auto-negotiation */
438 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
448 * ixgbe_get_media_type_82599 - Get media type
449 * @hw: pointer to hardware structure
451 * Returns the media type (fiber, copper, backplane)
453 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
455 /* Detect if there is a copper PHY attached. */
456 switch (hw->phy.type) {
457 case ixgbe_phy_cu_unknown:
459 return ixgbe_media_type_copper;
465 switch (hw->device_id) {
466 case IXGBE_DEV_ID_82599_KX4:
467 case IXGBE_DEV_ID_82599_KX4_MEZZ:
468 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
469 case IXGBE_DEV_ID_82599_KR:
470 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
471 case IXGBE_DEV_ID_82599_XAUI_LOM:
472 /* Default device ID is mezzanine card KX/KX4 */
473 return ixgbe_media_type_backplane;
475 case IXGBE_DEV_ID_82599_SFP:
476 case IXGBE_DEV_ID_82599_SFP_FCOE:
477 case IXGBE_DEV_ID_82599_SFP_EM:
478 case IXGBE_DEV_ID_82599_SFP_SF2:
479 case IXGBE_DEV_ID_82599_SFP_SF_QP:
480 case IXGBE_DEV_ID_82599EN_SFP:
481 return ixgbe_media_type_fiber;
483 case IXGBE_DEV_ID_82599_CX4:
484 return ixgbe_media_type_cx4;
486 case IXGBE_DEV_ID_82599_T3_LOM:
487 return ixgbe_media_type_copper;
489 case IXGBE_DEV_ID_82599_LS:
490 return ixgbe_media_type_fiber_lco;
492 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
493 return ixgbe_media_type_fiber_qsfp;
496 return ixgbe_media_type_unknown;
501 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
502 * @hw: pointer to hardware structure
504 * Disables link, should be called during D3 power down sequence.
507 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
512 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
514 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
515 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
516 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
517 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
518 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
523 * ixgbe_start_mac_link_82599 - Setup MAC link settings
524 * @hw: pointer to hardware structure
525 * @autoneg_wait_to_complete: true when waiting for completion is needed
527 * Configures link settings based on values in the ixgbe_hw struct.
528 * Restarts the link. Performs autonegotiation if needed.
530 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
531 bool autoneg_wait_to_complete)
537 bool got_lock = false;
539 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
540 status = hw->mac.ops.acquire_swfw_sync(hw,
541 IXGBE_GSSR_MAC_CSR_SM);
549 ixgbe_reset_pipeline_82599(hw);
552 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
554 /* Only poll for autoneg to complete if specified to do so */
555 if (autoneg_wait_to_complete) {
556 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
557 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
558 IXGBE_AUTOC_LMS_KX4_KX_KR ||
559 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
560 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
561 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
562 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
563 links_reg = 0; /* Just in case Autoneg time = 0 */
564 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
565 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
566 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
570 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
571 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
572 hw_dbg(hw, "Autoneg did not complete.\n");
577 /* Add delay to filter out noises during initial link setup */
584 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
585 * @hw: pointer to hardware structure
587 * The base drivers may require better control over SFP+ module
588 * PHY states. This includes selectively shutting down the Tx
589 * laser on the PHY, effectively halting physical link.
591 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
593 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
595 /* Blocked by MNG FW so bail */
596 if (ixgbe_check_reset_blocked(hw))
599 /* Disable tx laser; allow 100us to go dark per spec */
600 esdp_reg |= IXGBE_ESDP_SDP3;
601 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
602 IXGBE_WRITE_FLUSH(hw);
607 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
608 * @hw: pointer to hardware structure
610 * The base drivers may require better control over SFP+ module
611 * PHY states. This includes selectively turning on the Tx
612 * laser on the PHY, effectively starting physical link.
614 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
616 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
618 /* Enable tx laser; allow 100ms to light up */
619 esdp_reg &= ~IXGBE_ESDP_SDP3;
620 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
621 IXGBE_WRITE_FLUSH(hw);
626 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
627 * @hw: pointer to hardware structure
629 * When the driver changes the link speeds that it can support,
630 * it sets autotry_restart to true to indicate that we need to
631 * initiate a new autotry session with the link partner. To do
632 * so, we set the speed then disable and re-enable the tx laser, to
633 * alert the link partner that it also needs to restart autotry on its
634 * end. This is consistent with true clause 37 autoneg, which also
635 * involves a loss of signal.
637 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
639 /* Blocked by MNG FW so bail */
640 if (ixgbe_check_reset_blocked(hw))
643 if (hw->mac.autotry_restart) {
644 ixgbe_disable_tx_laser_multispeed_fiber(hw);
645 ixgbe_enable_tx_laser_multispeed_fiber(hw);
646 hw->mac.autotry_restart = false;
651 * ixgbe_set_hard_rate_select_speed - Set module link speed
652 * @hw: pointer to hardware structure
653 * @speed: link speed to set
655 * Set module link speed via RS0/RS1 rate select pins.
658 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
660 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
663 case IXGBE_LINK_SPEED_10GB_FULL:
664 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
666 case IXGBE_LINK_SPEED_1GB_FULL:
667 esdp_reg &= ~IXGBE_ESDP_SDP5;
668 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
671 hw_dbg(hw, "Invalid fixed module speed\n");
675 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
676 IXGBE_WRITE_FLUSH(hw);
680 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
681 * @hw: pointer to hardware structure
682 * @speed: new link speed
683 * @autoneg_wait_to_complete: true when waiting for completion is needed
685 * Implements the Intel SmartSpeed algorithm.
687 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
688 ixgbe_link_speed speed,
689 bool autoneg_wait_to_complete)
692 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
694 bool link_up = false;
695 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
697 /* Set autoneg_advertised value based on input link speed */
698 hw->phy.autoneg_advertised = 0;
700 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
701 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
703 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
704 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
706 if (speed & IXGBE_LINK_SPEED_100_FULL)
707 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
710 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
711 * autoneg advertisement if link is unable to be established at the
712 * highest negotiated rate. This can sometimes happen due to integrity
713 * issues with the physical media connection.
716 /* First, try to get link with full advertisement */
717 hw->phy.smart_speed_active = false;
718 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
719 status = ixgbe_setup_mac_link_82599(hw, speed,
720 autoneg_wait_to_complete);
725 * Wait for the controller to acquire link. Per IEEE 802.3ap,
726 * Section 73.10.2, we may have to wait up to 500ms if KR is
727 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
728 * Table 9 in the AN MAS.
730 for (i = 0; i < 5; i++) {
733 /* If we have link, just jump out */
734 status = hw->mac.ops.check_link(hw, &link_speed,
745 * We didn't get link. If we advertised KR plus one of KX4/KX
746 * (or BX4/BX), then disable KR and try again.
748 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
749 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
752 /* Turn SmartSpeed on to disable KR support */
753 hw->phy.smart_speed_active = true;
754 status = ixgbe_setup_mac_link_82599(hw, speed,
755 autoneg_wait_to_complete);
760 * Wait for the controller to acquire link. 600ms will allow for
761 * the AN link_fail_inhibit_timer as well for multiple cycles of
762 * parallel detect, both 10g and 1g. This allows for the maximum
763 * connect attempts as defined in the AN MAS table 73-7.
765 for (i = 0; i < 6; i++) {
768 /* If we have link, just jump out */
769 status = hw->mac.ops.check_link(hw, &link_speed,
778 /* We didn't get link. Turn SmartSpeed back off. */
779 hw->phy.smart_speed_active = false;
780 status = ixgbe_setup_mac_link_82599(hw, speed,
781 autoneg_wait_to_complete);
784 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
785 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n");
790 * ixgbe_setup_mac_link_82599 - Set MAC link speed
791 * @hw: pointer to hardware structure
792 * @speed: new link speed
793 * @autoneg_wait_to_complete: true when waiting for completion is needed
795 * Set the link speed in the AUTOC register and restarts link.
797 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
798 ixgbe_link_speed speed,
799 bool autoneg_wait_to_complete)
801 bool autoneg = false;
803 u32 pma_pmd_1g, link_mode, links_reg, i;
804 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
805 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
806 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
808 /* holds the value of AUTOC register at this current point in time */
809 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
810 /* holds the cached value of AUTOC register */
812 /* temporary variable used for comparison purposes */
813 u32 autoc = current_autoc;
815 /* Check to see if speed passed in is supported. */
816 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
821 speed &= link_capabilities;
823 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
824 return IXGBE_ERR_LINK_SETUP;
826 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
827 if (hw->mac.orig_link_settings_stored)
828 orig_autoc = hw->mac.orig_autoc;
832 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
833 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
835 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
836 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
837 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
838 /* Set KX4/KX/KR support according to speed requested */
839 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
840 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
841 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
842 autoc |= IXGBE_AUTOC_KX4_SUPP;
843 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
844 (hw->phy.smart_speed_active == false))
845 autoc |= IXGBE_AUTOC_KR_SUPP;
847 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
848 autoc |= IXGBE_AUTOC_KX_SUPP;
849 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
850 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
851 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
852 /* Switch from 1G SFI to 10G SFI if requested */
853 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
854 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
855 autoc &= ~IXGBE_AUTOC_LMS_MASK;
856 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
858 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
859 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
860 /* Switch from 10G SFI to 1G SFI if requested */
861 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
862 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
863 autoc &= ~IXGBE_AUTOC_LMS_MASK;
865 autoc |= IXGBE_AUTOC_LMS_1G_AN;
867 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
871 if (autoc != current_autoc) {
873 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
877 /* Only poll for autoneg to complete if specified to do so */
878 if (autoneg_wait_to_complete) {
879 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
880 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
881 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
882 links_reg = 0; /*Just in case Autoneg time=0*/
883 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
885 IXGBE_READ_REG(hw, IXGBE_LINKS);
886 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
890 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
892 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
893 hw_dbg(hw, "Autoneg did not complete.\n");
898 /* Add delay to filter out noises during initial link setup */
906 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
907 * @hw: pointer to hardware structure
908 * @speed: new link speed
909 * @autoneg_wait_to_complete: true if waiting is needed to complete
911 * Restarts link on PHY and MAC based on settings passed in.
913 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
914 ixgbe_link_speed speed,
915 bool autoneg_wait_to_complete)
919 /* Setup the PHY according to input speed */
920 status = hw->phy.ops.setup_link_speed(hw, speed,
921 autoneg_wait_to_complete);
923 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
929 * ixgbe_reset_hw_82599 - Perform hardware reset
930 * @hw: pointer to hardware structure
932 * Resets the hardware by resetting the transmit and receive units, masks
933 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
936 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
938 ixgbe_link_speed link_speed;
940 u32 ctrl, i, autoc, autoc2;
942 bool link_up = false;
944 /* Call adapter stop to disable tx/rx and clear interrupts */
945 status = hw->mac.ops.stop_adapter(hw);
949 /* flush pending Tx transactions */
950 ixgbe_clear_tx_pending(hw);
952 /* PHY ops must be identified and initialized prior to reset */
954 /* Identify PHY and related function pointers */
955 status = hw->phy.ops.init(hw);
957 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
960 /* Setup SFP module if there is one present. */
961 if (hw->phy.sfp_setup_needed) {
962 status = hw->mac.ops.setup_sfp(hw);
963 hw->phy.sfp_setup_needed = false;
966 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
970 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
971 hw->phy.ops.reset(hw);
973 /* remember AUTOC from before we reset */
974 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
978 * Issue global reset to the MAC. Needs to be SW reset if link is up.
979 * If link reset is used when link is up, it might reset the PHY when
980 * mng is using it. If link is down or the flag to force full link
981 * reset is set, then perform link reset.
983 ctrl = IXGBE_CTRL_LNK_RST;
984 if (!hw->force_full_reset) {
985 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
987 ctrl = IXGBE_CTRL_RST;
990 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
991 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
992 IXGBE_WRITE_FLUSH(hw);
994 /* Poll for reset bit to self-clear indicating reset is complete */
995 for (i = 0; i < 10; i++) {
997 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
998 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1002 if (ctrl & IXGBE_CTRL_RST_MASK) {
1003 status = IXGBE_ERR_RESET_FAILED;
1004 hw_dbg(hw, "Reset polling failed to complete.\n");
1010 * Double resets are required for recovery from certain error
1011 * conditions. Between resets, it is necessary to stall to allow time
1012 * for any pending HW events to complete.
1014 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1015 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1020 * Store the original AUTOC/AUTOC2 values if they have not been
1021 * stored off yet. Otherwise restore the stored original
1022 * values since the reset operation sets back to defaults.
1024 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1025 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1027 /* Enable link if disabled in NVM */
1028 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1029 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1030 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1031 IXGBE_WRITE_FLUSH(hw);
1034 if (hw->mac.orig_link_settings_stored == false) {
1035 hw->mac.orig_autoc = autoc;
1036 hw->mac.orig_autoc2 = autoc2;
1037 hw->mac.orig_link_settings_stored = true;
1040 /* If MNG FW is running on a multi-speed device that
1041 * doesn't autoneg with out driver support we need to
1042 * leave LMS in the state it was before we MAC reset.
1043 * Likewise if we support WoL we don't want change the
1046 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1048 hw->mac.orig_autoc =
1049 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1052 if (autoc != hw->mac.orig_autoc) {
1053 status = hw->mac.ops.prot_autoc_write(hw,
1060 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1061 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1062 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1063 autoc2 |= (hw->mac.orig_autoc2 &
1064 IXGBE_AUTOC2_UPPER_MASK);
1065 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1069 /* Store the permanent mac address */
1070 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1073 * Store MAC address from RAR0, clear receive address registers, and
1074 * clear the multicast table. Also reset num_rar_entries to 128,
1075 * since we modify this value when programming the SAN MAC address.
1077 hw->mac.num_rar_entries = 128;
1078 hw->mac.ops.init_rx_addrs(hw);
1080 /* Store the permanent SAN mac address */
1081 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1083 /* Add the SAN MAC address to the RAR only if it's a valid address */
1084 if (is_valid_ether_addr(hw->mac.san_addr)) {
1085 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1086 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1088 /* Save the SAN MAC RAR index */
1089 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1091 /* Reserve the last RAR for the SAN MAC address */
1092 hw->mac.num_rar_entries--;
1095 /* Store the alternative WWNN/WWPN prefix */
1096 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1097 &hw->mac.wwpn_prefix);
1103 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1104 * @hw: pointer to hardware structure
1105 * @fdircmd: current value of FDIRCMD register
1107 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1111 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1112 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1113 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1118 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1122 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1123 * @hw: pointer to hardware structure
1125 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1128 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1132 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1135 * Before starting reinitialization process,
1136 * FDIRCMD.CMD must be zero.
1138 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1140 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n");
1144 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1145 IXGBE_WRITE_FLUSH(hw);
1147 * 82599 adapters flow director init flow cannot be restarted,
1148 * Workaround 82599 silicon errata by performing the following steps
1149 * before re-writing the FDIRCTRL control register with the same value.
1150 * - write 1 to bit 8 of FDIRCMD register &
1151 * - write 0 to bit 8 of FDIRCMD register
1153 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1154 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1155 IXGBE_FDIRCMD_CLEARHT));
1156 IXGBE_WRITE_FLUSH(hw);
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1158 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1159 ~IXGBE_FDIRCMD_CLEARHT));
1160 IXGBE_WRITE_FLUSH(hw);
1162 * Clear FDIR Hash register to clear any leftover hashes
1163 * waiting to be programmed.
1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1166 IXGBE_WRITE_FLUSH(hw);
1168 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1169 IXGBE_WRITE_FLUSH(hw);
1171 /* Poll init-done after we write FDIRCTRL register */
1172 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1173 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1174 IXGBE_FDIRCTRL_INIT_DONE)
1176 usleep_range(1000, 2000);
1178 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1179 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1180 return IXGBE_ERR_FDIR_REINIT_FAILED;
1183 /* Clear FDIR statistics registers (read to clear) */
1184 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1185 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1186 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1187 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1188 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1194 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1195 * @hw: pointer to hardware structure
1196 * @fdirctrl: value to write to flow director control register
1198 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1202 /* Prime the keys for hashing */
1203 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1204 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1207 * Poll init-done after we write the register. Estimated times:
1208 * 10G: PBALLOC = 11b, timing is 60us
1209 * 1G: PBALLOC = 11b, timing is 600us
1210 * 100M: PBALLOC = 11b, timing is 6ms
1212 * Multiple these timings by 4 if under full Rx load
1214 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1215 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1216 * this might not finish in our poll time, but we can live with that
1219 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1220 IXGBE_WRITE_FLUSH(hw);
1221 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1222 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1223 IXGBE_FDIRCTRL_INIT_DONE)
1225 usleep_range(1000, 2000);
1228 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1229 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1233 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1234 * @hw: pointer to hardware structure
1235 * @fdirctrl: value to write to flow director control register, initially
1236 * contains just the value of the Rx packet buffer allocation
1238 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1241 * Continue setup of fdirctrl register bits:
1242 * Move the flexible bytes to use the ethertype - shift 6 words
1243 * Set the maximum length per hash bucket to 0xA filters
1244 * Send interrupt when 64 filters are left
1246 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1247 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1248 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1250 /* write hashes and fdirctrl register, poll for completion */
1251 ixgbe_fdir_enable_82599(hw, fdirctrl);
1257 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1258 * @hw: pointer to hardware structure
1259 * @fdirctrl: value to write to flow director control register, initially
1260 * contains just the value of the Rx packet buffer allocation
1262 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1265 * Continue setup of fdirctrl register bits:
1266 * Turn perfect match filtering on
1267 * Initialize the drop queue
1268 * Move the flexible bytes to use the ethertype - shift 6 words
1269 * Set the maximum length per hash bucket to 0xA filters
1270 * Send interrupt when 64 (0x4 * 16) filters are left
1272 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1273 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1274 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1275 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1276 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1278 /* write hashes and fdirctrl register, poll for completion */
1279 ixgbe_fdir_enable_82599(hw, fdirctrl);
1285 * These defines allow us to quickly generate all of the necessary instructions
1286 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1287 * for values 0 through 15
1289 #define IXGBE_ATR_COMMON_HASH_KEY \
1290 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1291 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1294 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1295 common_hash ^= lo_hash_dword >> n; \
1296 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1297 bucket_hash ^= lo_hash_dword >> n; \
1298 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1299 sig_hash ^= lo_hash_dword << (16 - n); \
1300 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1301 common_hash ^= hi_hash_dword >> n; \
1302 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1303 bucket_hash ^= hi_hash_dword >> n; \
1304 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1305 sig_hash ^= hi_hash_dword << (16 - n); \
1309 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1310 * @stream: input bitstream to compute the hash on
1312 * This function is almost identical to the function above but contains
1313 * several optomizations such as unwinding all of the loops, letting the
1314 * compiler work out all of the conditional ifs since the keys are static
1315 * defines, and computing two keys at once since the hashed dword stream
1316 * will be the same for both keys.
1318 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1319 union ixgbe_atr_hash_dword common)
1321 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1322 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1324 /* record the flow_vm_vlan bits as they are a key part to the hash */
1325 flow_vm_vlan = ntohl(input.dword);
1327 /* generate common hash dword */
1328 hi_hash_dword = ntohl(common.dword);
1330 /* low dword is word swapped version of common */
1331 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1333 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1334 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1336 /* Process bits 0 and 16 */
1337 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1340 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1341 * delay this because bit 0 of the stream should not be processed
1342 * so we do not add the vlan until after bit 0 was processed
1344 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1346 /* Process remaining 30 bit of the key */
1347 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1348 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1349 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1350 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1351 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1363 /* combine common_hash result with signature and bucket hashes */
1364 bucket_hash ^= common_hash;
1365 bucket_hash &= IXGBE_ATR_HASH_MASK;
1367 sig_hash ^= common_hash << 16;
1368 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1370 /* return completed signature hash */
1371 return sig_hash ^ bucket_hash;
1375 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1376 * @hw: pointer to hardware structure
1377 * @input: unique input dword
1378 * @common: compressed common input dword
1379 * @queue: queue index to direct traffic to
1381 * Note that the tunnel bit in input must not be set when the hardware
1382 * tunneling support does not exist.
1384 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1385 union ixgbe_atr_hash_dword input,
1386 union ixgbe_atr_hash_dword common,
1395 * Get the flow_type in order to program FDIRCMD properly
1396 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1398 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1399 flow_type = input.formatted.flow_type &
1400 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1401 switch (flow_type) {
1402 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1403 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1404 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1405 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1406 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1407 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1410 hw_dbg(hw, " Error on flow type input\n");
1411 return IXGBE_ERR_CONFIG;
1414 /* configure FDIRCMD register */
1415 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1416 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1417 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1418 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1420 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1423 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1424 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1426 fdirhashcmd = (u64)fdircmd << 32;
1427 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1428 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1430 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1435 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1438 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1439 bucket_hash ^= lo_hash_dword >> n; \
1440 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1441 bucket_hash ^= hi_hash_dword >> n; \
1445 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1446 * @atr_input: input bitstream to compute the hash on
1447 * @input_mask: mask for the input bitstream
1449 * This function serves two main purposes. First it applys the input_mask
1450 * to the atr_input resulting in a cleaned up atr_input data stream.
1451 * Secondly it computes the hash and stores it in the bkt_hash field at
1452 * the end of the input byte stream. This way it will be available for
1453 * future use without needing to recompute the hash.
1455 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1456 union ixgbe_atr_input *input_mask)
1459 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1460 u32 bucket_hash = 0, hi_dword = 0;
1463 /* Apply masks to input data */
1464 for (i = 0; i <= 10; i++)
1465 input->dword_stream[i] &= input_mask->dword_stream[i];
1467 /* record the flow_vm_vlan bits as they are a key part to the hash */
1468 flow_vm_vlan = ntohl(input->dword_stream[0]);
1470 /* generate common hash dword */
1471 for (i = 1; i <= 10; i++)
1472 hi_dword ^= input->dword_stream[i];
1473 hi_hash_dword = ntohl(hi_dword);
1475 /* low dword is word swapped version of common */
1476 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1478 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1479 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1481 /* Process bits 0 and 16 */
1482 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1485 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1486 * delay this because bit 0 of the stream should not be processed
1487 * so we do not add the vlan until after bit 0 was processed
1489 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1491 /* Process remaining 30 bit of the key */
1492 for (i = 1; i <= 15; i++)
1493 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1496 * Limit hash to 13 bits since max bucket count is 8K.
1497 * Store result at the end of the input stream.
1499 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1503 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1504 * @input_mask: mask to be bit swapped
1506 * The source and destination port masks for flow director are bit swapped
1507 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1508 * generate a correctly swapped value we need to bit swap the mask and that
1509 * is what is accomplished by this function.
1511 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1513 u32 mask = ntohs(input_mask->formatted.dst_port);
1515 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1516 mask |= ntohs(input_mask->formatted.src_port);
1517 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1518 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1519 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1520 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1524 * These two macros are meant to address the fact that we have registers
1525 * that are either all or in part big-endian. As a result on big-endian
1526 * systems we will end up byte swapping the value to little-endian before
1527 * it is byte swapped again and written to the hardware in the original
1528 * big-endian format.
1530 #define IXGBE_STORE_AS_BE32(_value) \
1531 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1532 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1534 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1535 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1537 #define IXGBE_STORE_AS_BE16(_value) \
1538 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1540 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1541 union ixgbe_atr_input *input_mask)
1543 /* mask IPv6 since it is currently not supported */
1544 u32 fdirm = IXGBE_FDIRM_DIPv6;
1548 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1549 * are zero, then assume a full mask for that field. Also assume that
1550 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1551 * cannot be masked out in this implementation.
1553 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1557 /* verify bucket hash is cleared on hash generation */
1558 if (input_mask->formatted.bkt_hash)
1559 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1561 /* Program FDIRM and verify partial masks */
1562 switch (input_mask->formatted.vm_pool & 0x7F) {
1564 fdirm |= IXGBE_FDIRM_POOL;
1568 hw_dbg(hw, " Error on vm pool mask\n");
1569 return IXGBE_ERR_CONFIG;
1572 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1574 fdirm |= IXGBE_FDIRM_L4P;
1575 if (input_mask->formatted.dst_port ||
1576 input_mask->formatted.src_port) {
1577 hw_dbg(hw, " Error on src/dst port mask\n");
1578 return IXGBE_ERR_CONFIG;
1580 case IXGBE_ATR_L4TYPE_MASK:
1583 hw_dbg(hw, " Error on flow type mask\n");
1584 return IXGBE_ERR_CONFIG;
1587 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1589 /* mask VLAN ID, fall through to mask VLAN priority */
1590 fdirm |= IXGBE_FDIRM_VLANID;
1592 /* mask VLAN priority */
1593 fdirm |= IXGBE_FDIRM_VLANP;
1596 /* mask VLAN ID only, fall through */
1597 fdirm |= IXGBE_FDIRM_VLANID;
1599 /* no VLAN fields masked */
1602 hw_dbg(hw, " Error on VLAN mask\n");
1603 return IXGBE_ERR_CONFIG;
1606 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1608 /* Mask Flex Bytes, fall through */
1609 fdirm |= IXGBE_FDIRM_FLEX;
1613 hw_dbg(hw, " Error on flexible byte mask\n");
1614 return IXGBE_ERR_CONFIG;
1617 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1618 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1620 /* store the TCP/UDP port masks, bit reversed from port layout */
1621 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1623 /* write both the same so that UDP and TCP use the same mask */
1624 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1625 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1627 /* also use it for SCTP */
1628 switch (hw->mac.type) {
1629 case ixgbe_mac_X550:
1630 case ixgbe_mac_X550EM_x:
1631 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1637 /* store source and destination IP masks (big-enian) */
1638 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1639 ~input_mask->formatted.src_ip[0]);
1640 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1641 ~input_mask->formatted.dst_ip[0]);
1646 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1647 union ixgbe_atr_input *input,
1648 u16 soft_id, u8 queue)
1650 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1653 /* currently IPv6 is not supported, must be programmed with 0 */
1654 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1655 input->formatted.src_ip[0]);
1656 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1657 input->formatted.src_ip[1]);
1658 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1659 input->formatted.src_ip[2]);
1661 /* record the source address (big-endian) */
1662 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1664 /* record the first 32 bits of the destination address (big-endian) */
1665 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1667 /* record source and destination port (little-endian)*/
1668 fdirport = ntohs(input->formatted.dst_port);
1669 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1670 fdirport |= ntohs(input->formatted.src_port);
1671 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1673 /* record vlan (little-endian) and flex_bytes(big-endian) */
1674 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1675 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1676 fdirvlan |= ntohs(input->formatted.vlan_id);
1677 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1679 /* configure FDIRHASH register */
1680 fdirhash = input->formatted.bkt_hash;
1681 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1682 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1685 * flush all previous writes to make certain registers are
1686 * programmed prior to issuing the command
1688 IXGBE_WRITE_FLUSH(hw);
1690 /* configure FDIRCMD register */
1691 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1692 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1693 if (queue == IXGBE_FDIR_DROP_QUEUE)
1694 fdircmd |= IXGBE_FDIRCMD_DROP;
1695 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1696 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1697 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1699 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1700 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1702 hw_dbg(hw, "Flow Director command did not complete!\n");
1709 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1710 union ixgbe_atr_input *input,
1717 /* configure FDIRHASH register */
1718 fdirhash = input->formatted.bkt_hash;
1719 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1722 /* flush hash to HW */
1723 IXGBE_WRITE_FLUSH(hw);
1725 /* Query if filter is present */
1726 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1728 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1730 hw_dbg(hw, "Flow Director command did not complete!\n");
1734 /* if filter exists in hardware then remove it */
1735 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1736 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1737 IXGBE_WRITE_FLUSH(hw);
1738 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1739 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1746 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1747 * @hw: pointer to hardware structure
1748 * @reg: analog register to read
1751 * Performs read operation to Omer analog register specified.
1753 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1757 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1759 IXGBE_WRITE_FLUSH(hw);
1761 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1762 *val = (u8)core_ctl;
1768 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1769 * @hw: pointer to hardware structure
1770 * @reg: atlas register to write
1771 * @val: value to write
1773 * Performs write operation to Omer analog register specified.
1775 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1779 core_ctl = (reg << 8) | val;
1780 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1781 IXGBE_WRITE_FLUSH(hw);
1788 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1789 * @hw: pointer to hardware structure
1791 * Starts the hardware using the generic start_hw function
1792 * and the generation start_hw function.
1793 * Then performs revision-specific operations, if any.
1795 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1799 ret_val = ixgbe_start_hw_generic(hw);
1803 ret_val = ixgbe_start_hw_gen2(hw);
1807 /* We need to run link autotry after the driver loads */
1808 hw->mac.autotry_restart = true;
1813 return ixgbe_verify_fw_version_82599(hw);
1817 * ixgbe_identify_phy_82599 - Get physical layer module
1818 * @hw: pointer to hardware structure
1820 * Determines the physical layer module found on the current adapter.
1821 * If PHY already detected, maintains current PHY type in hw struct,
1822 * otherwise executes the PHY detection routine.
1824 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1828 /* Detect PHY if not unknown - returns success if already detected. */
1829 status = ixgbe_identify_phy_generic(hw);
1831 /* 82599 10GBASE-T requires an external PHY */
1832 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1834 status = ixgbe_identify_module_generic(hw);
1837 /* Set PHY type none if no PHY detected */
1838 if (hw->phy.type == ixgbe_phy_unknown) {
1839 hw->phy.type = ixgbe_phy_none;
1843 /* Return error if SFP module has been detected but is not supported */
1844 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1845 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1851 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1852 * @hw: pointer to hardware structure
1853 * @regval: register value to write to RXCTRL
1855 * Enables the Rx DMA unit for 82599
1857 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1860 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1861 * If traffic is incoming before we enable the Rx unit, it could hang
1862 * the Rx DMA unit. Therefore, make sure the security engine is
1863 * completely disabled prior to enabling the Rx unit.
1865 hw->mac.ops.disable_rx_buff(hw);
1867 if (regval & IXGBE_RXCTRL_RXEN)
1868 hw->mac.ops.enable_rx(hw);
1870 hw->mac.ops.disable_rx(hw);
1872 hw->mac.ops.enable_rx_buff(hw);
1878 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1879 * @hw: pointer to hardware structure
1881 * Verifies that installed the firmware version is 0.6 or higher
1882 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1884 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1885 * if the FW version is not supported.
1887 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1889 s32 status = IXGBE_ERR_EEPROM_VERSION;
1890 u16 fw_offset, fw_ptp_cfg_offset;
1894 /* firmware check is only necessary for SFI devices */
1895 if (hw->phy.media_type != ixgbe_media_type_fiber)
1898 /* get the offset to the Firmware Module block */
1899 offset = IXGBE_FW_PTR;
1900 if (hw->eeprom.ops.read(hw, offset, &fw_offset))
1901 goto fw_version_err;
1903 if (fw_offset == 0 || fw_offset == 0xFFFF)
1904 return IXGBE_ERR_EEPROM_VERSION;
1906 /* get the offset to the Pass Through Patch Configuration block */
1907 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
1908 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
1909 goto fw_version_err;
1911 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF)
1912 return IXGBE_ERR_EEPROM_VERSION;
1914 /* get the firmware version */
1915 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
1916 if (hw->eeprom.ops.read(hw, offset, &fw_version))
1917 goto fw_version_err;
1919 if (fw_version > 0x5)
1925 hw_err(hw, "eeprom read at offset %d failed\n", offset);
1926 return IXGBE_ERR_EEPROM_VERSION;
1930 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1931 * @hw: pointer to hardware structure
1933 * Returns true if the LESM FW module is present and enabled. Otherwise
1934 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1936 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
1938 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
1941 /* get the offset to the Firmware Module block */
1942 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1944 if (status || fw_offset == 0 || fw_offset == 0xFFFF)
1947 /* get the offset to the LESM Parameters block */
1948 status = hw->eeprom.ops.read(hw, (fw_offset +
1949 IXGBE_FW_LESM_PARAMETERS_PTR),
1950 &fw_lesm_param_offset);
1953 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
1956 /* get the lesm state word */
1957 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
1958 IXGBE_FW_LESM_STATE_1),
1961 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
1968 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
1969 * fastest available method
1971 * @hw: pointer to hardware structure
1972 * @offset: offset of word in EEPROM to read
1973 * @words: number of words
1974 * @data: word(s) read from the EEPROM
1976 * Retrieves 16 bit word(s) read from EEPROM
1978 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
1979 u16 words, u16 *data)
1981 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1983 /* If EEPROM is detected and can be addressed using 14 bits,
1984 * use EERD otherwise use bit bang
1986 if (eeprom->type == ixgbe_eeprom_spi &&
1987 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)
1988 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
1990 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words,
1995 * ixgbe_read_eeprom_82599 - Read EEPROM word using
1996 * fastest available method
1998 * @hw: pointer to hardware structure
1999 * @offset: offset of word in the EEPROM to read
2000 * @data: word read from the EEPROM
2002 * Reads a 16 bit word from the EEPROM
2004 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2005 u16 offset, u16 *data)
2007 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2010 * If EEPROM is detected and can be addressed using 14 bits,
2011 * use EERD otherwise use bit bang
2013 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR)
2014 return ixgbe_read_eerd_generic(hw, offset, data);
2016 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2020 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2022 * @hw: pointer to hardware structure
2024 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2025 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2026 * to AUTOC, so this function assumes the semaphore is held.
2028 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2032 u32 i, autoc_reg, autoc2_reg;
2034 /* Enable link if disabled in NVM */
2035 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2036 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2037 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2038 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2039 IXGBE_WRITE_FLUSH(hw);
2042 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2043 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2045 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2046 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2047 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2049 /* Wait for AN to leave state 0 */
2050 for (i = 0; i < 10; i++) {
2051 usleep_range(4000, 8000);
2052 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2053 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2057 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2058 hw_dbg(hw, "auto negotiation not completed\n");
2059 ret_val = IXGBE_ERR_RESET_FAILED;
2060 goto reset_pipeline_out;
2066 /* Write AUTOC register with original LMS field and Restart_AN */
2067 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2068 IXGBE_WRITE_FLUSH(hw);
2074 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2075 * @hw: pointer to hardware structure
2076 * @byte_offset: byte offset to read
2079 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2080 * a specified device address.
2082 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2083 u8 dev_addr, u8 *data)
2089 if (hw->phy.qsfp_shared_i2c_bus == true) {
2090 /* Acquire I2C bus ownership. */
2091 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2092 esdp |= IXGBE_ESDP_SDP0;
2093 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2094 IXGBE_WRITE_FLUSH(hw);
2097 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2098 if (esdp & IXGBE_ESDP_SDP1)
2101 usleep_range(5000, 10000);
2106 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2107 status = IXGBE_ERR_I2C;
2108 goto release_i2c_access;
2112 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2115 if (hw->phy.qsfp_shared_i2c_bus == true) {
2116 /* Release I2C bus ownership. */
2117 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2118 esdp &= ~IXGBE_ESDP_SDP0;
2119 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2120 IXGBE_WRITE_FLUSH(hw);
2127 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2128 * @hw: pointer to hardware structure
2129 * @byte_offset: byte offset to write
2130 * @data: value to write
2132 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2133 * a specified device address.
2135 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2136 u8 dev_addr, u8 data)
2142 if (hw->phy.qsfp_shared_i2c_bus == true) {
2143 /* Acquire I2C bus ownership. */
2144 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2145 esdp |= IXGBE_ESDP_SDP0;
2146 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2147 IXGBE_WRITE_FLUSH(hw);
2150 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2151 if (esdp & IXGBE_ESDP_SDP1)
2154 usleep_range(5000, 10000);
2159 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2160 status = IXGBE_ERR_I2C;
2161 goto release_i2c_access;
2165 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2168 if (hw->phy.qsfp_shared_i2c_bus == true) {
2169 /* Release I2C bus ownership. */
2170 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2171 esdp &= ~IXGBE_ESDP_SDP0;
2172 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2173 IXGBE_WRITE_FLUSH(hw);
2179 static struct ixgbe_mac_operations mac_ops_82599 = {
2180 .init_hw = &ixgbe_init_hw_generic,
2181 .reset_hw = &ixgbe_reset_hw_82599,
2182 .start_hw = &ixgbe_start_hw_82599,
2183 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2184 .get_media_type = &ixgbe_get_media_type_82599,
2185 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2186 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2187 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2188 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2189 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2190 .get_device_caps = &ixgbe_get_device_caps_generic,
2191 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2192 .stop_adapter = &ixgbe_stop_adapter_generic,
2193 .get_bus_info = &ixgbe_get_bus_info_generic,
2194 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2195 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2196 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2197 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
2198 .setup_link = &ixgbe_setup_mac_link_82599,
2199 .set_rxpba = &ixgbe_set_rxpba_generic,
2200 .check_link = &ixgbe_check_mac_link_generic,
2201 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2202 .led_on = &ixgbe_led_on_generic,
2203 .led_off = &ixgbe_led_off_generic,
2204 .blink_led_start = &ixgbe_blink_led_start_generic,
2205 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2206 .set_rar = &ixgbe_set_rar_generic,
2207 .clear_rar = &ixgbe_clear_rar_generic,
2208 .set_vmdq = &ixgbe_set_vmdq_generic,
2209 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2210 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2211 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2212 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2213 .enable_mc = &ixgbe_enable_mc_generic,
2214 .disable_mc = &ixgbe_disable_mc_generic,
2215 .clear_vfta = &ixgbe_clear_vfta_generic,
2216 .set_vfta = &ixgbe_set_vfta_generic,
2217 .fc_enable = &ixgbe_fc_enable_generic,
2218 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2219 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2220 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2221 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2222 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2223 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2224 .release_swfw_sync = &ixgbe_release_swfw_sync,
2225 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2226 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2227 .prot_autoc_read = &prot_autoc_read_82599,
2228 .prot_autoc_write = &prot_autoc_write_82599,
2229 .enable_rx = &ixgbe_enable_rx_generic,
2230 .disable_rx = &ixgbe_disable_rx_generic,
2233 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2234 .init_params = &ixgbe_init_eeprom_params_generic,
2235 .read = &ixgbe_read_eeprom_82599,
2236 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2237 .write = &ixgbe_write_eeprom_generic,
2238 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2239 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2240 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2241 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2244 static struct ixgbe_phy_operations phy_ops_82599 = {
2245 .identify = &ixgbe_identify_phy_82599,
2246 .identify_sfp = &ixgbe_identify_module_generic,
2247 .init = &ixgbe_init_phy_ops_82599,
2248 .reset = &ixgbe_reset_phy_generic,
2249 .read_reg = &ixgbe_read_phy_reg_generic,
2250 .write_reg = &ixgbe_write_phy_reg_generic,
2251 .setup_link = &ixgbe_setup_phy_link_generic,
2252 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2253 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2254 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2255 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2256 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2257 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2258 .check_overtemp = &ixgbe_tn_check_overtemp,
2261 struct ixgbe_info ixgbe_82599_info = {
2262 .mac = ixgbe_mac_82599EB,
2263 .get_invariants = &ixgbe_get_invariants_82599,
2264 .mac_ops = &mac_ops_82599,
2265 .eeprom_ops = &eeprom_ops_82599,
2266 .phy_ops = &phy_ops_82599,
2267 .mbx_ops = &mbx_ops_generic,
2268 .mvals = ixgbe_mvals_8259X,