1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
34 #include "ixgbe_phy.h"
36 #define IXGBE_82598_MAX_TX_QUEUES 32
37 #define IXGBE_82598_MAX_RX_QUEUES 64
38 #define IXGBE_82598_RAR_ENTRIES 16
39 #define IXGBE_82598_MC_TBL_SIZE 128
40 #define IXGBE_82598_VFT_TBL_SIZE 128
41 #define IXGBE_82598_RX_PB_SIZE 512
43 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
44 ixgbe_link_speed speed,
45 bool autoneg_wait_to_complete);
46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
51 * @hw: pointer to the HW structure
53 * The defaults for 82598 should be in the range of 50us to 50ms,
54 * however the hardware default for these parts is 500us to 1ms which is less
55 * than the 10ms recommended by the pci-e spec. To address this we need to
56 * increase the value to either 10ms to 250ms for capability version 1 config,
57 * or 16ms to 55ms for version 2.
59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
61 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
64 if (ixgbe_removed(hw->hw_addr))
67 /* only take action if timeout value is defaulted to 0 */
68 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
72 * if capababilities version is type 1 we can write the
73 * timeout of 10ms to 250ms through the GCR register
75 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
76 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
81 * for version 2 capabilities we need to write the config space
82 * directly in order to set the completion timeout value for
85 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
86 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
87 ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
89 /* disable completion timeout resend */
90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
94 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
96 struct ixgbe_mac_info *mac = &hw->mac;
98 /* Call PHY identify routine to get the phy type */
99 ixgbe_identify_phy_generic(hw);
101 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
102 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
103 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
104 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
105 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
106 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
107 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
113 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
114 * @hw: pointer to hardware structure
116 * Initialize any function pointers that were not able to be
117 * set during get_invariants because the PHY/SFP type was
118 * not known. Perform the SFP init if necessary.
121 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
123 struct ixgbe_mac_info *mac = &hw->mac;
124 struct ixgbe_phy_info *phy = &hw->phy;
126 u16 list_offset, data_offset;
128 /* Identify the PHY */
129 phy->ops.identify(hw);
131 /* Overwrite the link function pointers if copper PHY */
132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
133 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
134 mac->ops.get_link_capabilities =
135 &ixgbe_get_copper_link_capabilities_generic;
138 switch (hw->phy.type) {
140 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
141 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
144 phy->ops.reset = &ixgbe_reset_phy_nl;
146 /* Call SFP+ identify routine to get the SFP+ module type */
147 ret_val = phy->ops.identify_sfp(hw);
150 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
151 return IXGBE_ERR_SFP_NOT_SUPPORTED;
153 /* Check to see if SFP+ module is supported */
154 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
158 return IXGBE_ERR_SFP_NOT_SUPPORTED;
168 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
169 * @hw: pointer to hardware structure
171 * Starts the hardware using the generic start_hw function.
172 * Disables relaxed ordering for archs other than SPARC
173 * Then set pcie completion timeout
176 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
180 ret_val = ixgbe_start_hw_generic(hw);
184 /* set the completion timeout for interface */
185 ixgbe_set_pcie_completion_timeout(hw);
191 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
192 * @hw: pointer to hardware structure
193 * @speed: pointer to link speed
194 * @autoneg: boolean auto-negotiation value
196 * Determines the link capabilities by reading the AUTOC register.
198 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
199 ixgbe_link_speed *speed,
205 * Determine link capabilities based on the stored value of AUTOC,
206 * which represents EEPROM defaults. If AUTOC value has not been
207 * stored, use the current register value.
209 if (hw->mac.orig_link_settings_stored)
210 autoc = hw->mac.orig_autoc;
212 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
214 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
215 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
216 *speed = IXGBE_LINK_SPEED_1GB_FULL;
220 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
221 *speed = IXGBE_LINK_SPEED_10GB_FULL;
225 case IXGBE_AUTOC_LMS_1G_AN:
226 *speed = IXGBE_LINK_SPEED_1GB_FULL;
230 case IXGBE_AUTOC_LMS_KX4_AN:
231 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
232 *speed = IXGBE_LINK_SPEED_UNKNOWN;
233 if (autoc & IXGBE_AUTOC_KX4_SUPP)
234 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
235 if (autoc & IXGBE_AUTOC_KX_SUPP)
236 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
241 return IXGBE_ERR_LINK_SETUP;
248 * ixgbe_get_media_type_82598 - Determines media type
249 * @hw: pointer to hardware structure
251 * Returns the media type (fiber, copper, backplane)
253 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
255 /* Detect if there is a copper PHY attached. */
256 switch (hw->phy.type) {
257 case ixgbe_phy_cu_unknown:
259 return ixgbe_media_type_copper;
265 /* Media type for I82598 is based on device ID */
266 switch (hw->device_id) {
267 case IXGBE_DEV_ID_82598:
268 case IXGBE_DEV_ID_82598_BX:
269 /* Default device ID is mezzanine card KX/KX4 */
270 return ixgbe_media_type_backplane;
272 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
273 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
274 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
275 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
276 case IXGBE_DEV_ID_82598EB_XF_LR:
277 case IXGBE_DEV_ID_82598EB_SFP_LOM:
278 return ixgbe_media_type_fiber;
280 case IXGBE_DEV_ID_82598EB_CX4:
281 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
282 return ixgbe_media_type_cx4;
284 case IXGBE_DEV_ID_82598AT:
285 case IXGBE_DEV_ID_82598AT2:
286 return ixgbe_media_type_copper;
289 return ixgbe_media_type_unknown;
294 * ixgbe_fc_enable_82598 - Enable flow control
295 * @hw: pointer to hardware structure
297 * Enable flow control according to the current settings.
299 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
309 /* Validate the water mark configuration */
310 if (!hw->fc.pause_time)
311 return IXGBE_ERR_INVALID_LINK_SETTINGS;
313 /* Low water mark of zero causes XOFF floods */
314 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
315 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
316 hw->fc.high_water[i]) {
317 if (!hw->fc.low_water[i] ||
318 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
319 hw_dbg(hw, "Invalid water mark configuration\n");
320 return IXGBE_ERR_INVALID_LINK_SETTINGS;
326 * On 82598 having Rx FC on causes resets while doing 1G
327 * so if it's on turn it off once we know link_speed. For
328 * more details see 82598 Specification update.
330 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
331 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
332 switch (hw->fc.requested_mode) {
334 hw->fc.requested_mode = ixgbe_fc_tx_pause;
336 case ixgbe_fc_rx_pause:
337 hw->fc.requested_mode = ixgbe_fc_none;
345 /* Negotiate the fc mode to use */
346 hw->mac.ops.fc_autoneg(hw);
348 /* Disable any previous flow control settings */
349 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
350 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
352 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
353 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
356 * The possible values of fc.current_mode are:
357 * 0: Flow control is completely disabled
358 * 1: Rx flow control is enabled (we can receive pause frames,
359 * but not send pause frames).
360 * 2: Tx flow control is enabled (we can send pause frames but
361 * we do not support receiving pause frames).
362 * 3: Both Rx and Tx flow control (symmetric) are enabled.
365 switch (hw->fc.current_mode) {
368 * Flow control is disabled by software override or autoneg.
369 * The code below will actually disable it in the HW.
372 case ixgbe_fc_rx_pause:
374 * Rx Flow control is enabled and Tx Flow control is
375 * disabled by software override. Since there really
376 * isn't a way to advertise that we are capable of RX
377 * Pause ONLY, we will advertise that we support both
378 * symmetric and asymmetric Rx PAUSE. Later, we will
379 * disable the adapter's ability to send PAUSE frames.
381 fctrl_reg |= IXGBE_FCTRL_RFCE;
383 case ixgbe_fc_tx_pause:
385 * Tx Flow control is enabled, and Rx Flow control is
386 * disabled by software override.
388 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
391 /* Flow control (both Rx and Tx) is enabled by SW override. */
392 fctrl_reg |= IXGBE_FCTRL_RFCE;
393 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
396 hw_dbg(hw, "Flow control param set incorrectly\n");
397 return IXGBE_ERR_CONFIG;
400 /* Set 802.3x based flow control settings. */
401 fctrl_reg |= IXGBE_FCTRL_DPF;
402 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
403 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
405 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
406 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
407 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
408 hw->fc.high_water[i]) {
409 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
410 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
411 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
412 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
414 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
415 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
420 /* Configure pause time (2 TCs per register) */
421 reg = hw->fc.pause_time * 0x00010001;
422 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
423 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
425 /* Configure flow control refresh threshold value */
426 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
432 * ixgbe_start_mac_link_82598 - Configures MAC link settings
433 * @hw: pointer to hardware structure
435 * Configures link settings based on values in the ixgbe_hw struct.
436 * Restarts the link. Performs autonegotiation if needed.
438 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
439 bool autoneg_wait_to_complete)
447 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
448 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
449 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
451 /* Only poll for autoneg to complete if specified to do so */
452 if (autoneg_wait_to_complete) {
453 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
454 IXGBE_AUTOC_LMS_KX4_AN ||
455 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
456 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
457 links_reg = 0; /* Just in case Autoneg time = 0 */
458 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
459 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
460 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
464 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
465 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
466 hw_dbg(hw, "Autonegotiation did not complete.\n");
471 /* Add delay to filter out noises during initial link setup */
478 * ixgbe_validate_link_ready - Function looks for phy link
479 * @hw: pointer to hardware structure
481 * Function indicates success when phy link is available. If phy is not ready
482 * within 5 seconds of MAC indicating link, the function returns error.
484 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
489 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
493 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
494 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
496 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
497 (an_reg & MDIO_STAT1_LSTATUS))
503 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
504 hw_dbg(hw, "Link was indicated but link is down\n");
505 return IXGBE_ERR_LINK_SETUP;
512 * ixgbe_check_mac_link_82598 - Get link/speed status
513 * @hw: pointer to hardware structure
514 * @speed: pointer to link speed
515 * @link_up: true is link is up, false otherwise
516 * @link_up_wait_to_complete: bool used to wait for link up or not
518 * Reads the links register to determine if link is up and the current speed
520 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
521 ixgbe_link_speed *speed, bool *link_up,
522 bool link_up_wait_to_complete)
526 u16 link_reg, adapt_comp_reg;
529 * SERDES PHY requires us to read link status from register 0xC79F.
530 * Bit 0 set indicates link is up/ready; clear indicates link down.
531 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
532 * clear indicates active; set indicates inactive.
534 if (hw->phy.type == ixgbe_phy_nl) {
535 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
536 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
537 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
539 if (link_up_wait_to_complete) {
540 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
541 if ((link_reg & 1) &&
542 ((adapt_comp_reg & 1) == 0)) {
549 hw->phy.ops.read_reg(hw, 0xC79F,
552 hw->phy.ops.read_reg(hw, 0xC00C,
557 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
567 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
568 if (link_up_wait_to_complete) {
569 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
570 if (links_reg & IXGBE_LINKS_UP) {
577 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
580 if (links_reg & IXGBE_LINKS_UP)
586 if (links_reg & IXGBE_LINKS_SPEED)
587 *speed = IXGBE_LINK_SPEED_10GB_FULL;
589 *speed = IXGBE_LINK_SPEED_1GB_FULL;
591 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
592 (ixgbe_validate_link_ready(hw) != 0))
599 * ixgbe_setup_mac_link_82598 - Set MAC link speed
600 * @hw: pointer to hardware structure
601 * @speed: new link speed
602 * @autoneg_wait_to_complete: true when waiting for completion is needed
604 * Set the link speed in the AUTOC register and restarts link.
606 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
607 ixgbe_link_speed speed,
608 bool autoneg_wait_to_complete)
610 bool autoneg = false;
611 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
612 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
613 u32 autoc = curr_autoc;
614 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
616 /* Check to see if speed passed in is supported. */
617 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
618 speed &= link_capabilities;
620 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
621 return IXGBE_ERR_LINK_SETUP;
623 /* Set KX4/KX support according to speed requested */
624 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
625 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
626 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
627 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
628 autoc |= IXGBE_AUTOC_KX4_SUPP;
629 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
630 autoc |= IXGBE_AUTOC_KX_SUPP;
631 if (autoc != curr_autoc)
632 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
635 /* Setup and restart the link based on the new values in
636 * ixgbe_hw This will write the AUTOC register based on the new
639 return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
644 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
645 * @hw: pointer to hardware structure
646 * @speed: new link speed
647 * @autoneg_wait_to_complete: true if waiting is needed to complete
649 * Sets the link speed in the AUTOC register in the MAC and restarts link.
651 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
652 ixgbe_link_speed speed,
653 bool autoneg_wait_to_complete)
657 /* Setup the PHY according to input speed */
658 status = hw->phy.ops.setup_link_speed(hw, speed,
659 autoneg_wait_to_complete);
661 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
667 * ixgbe_reset_hw_82598 - Performs hardware reset
668 * @hw: pointer to hardware structure
670 * Resets the hardware by resetting the transmit and receive units, masks and
671 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
674 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
684 /* Call adapter stop to disable tx/rx and clear interrupts */
685 status = hw->mac.ops.stop_adapter(hw);
690 * Power up the Atlas Tx lanes if they are currently powered down.
691 * Atlas Tx lanes are powered down for MAC loopback tests, but
692 * they are not automatically restored on reset.
694 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
695 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
696 /* Enable Tx Atlas so packets can be transmitted again */
697 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
699 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
700 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
703 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
705 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
706 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
709 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
711 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
712 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
715 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
717 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
718 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
723 if (hw->phy.reset_disable == false) {
724 /* PHY ops must be identified and initialized prior to reset */
726 /* Init PHY and function pointers, perform SFP setup */
727 phy_status = hw->phy.ops.init(hw);
728 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
730 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
733 hw->phy.ops.reset(hw);
738 * Issue global reset to the MAC. This needs to be a SW reset.
739 * If link reset is used, it might reset the MAC when mng is using it
741 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
742 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
743 IXGBE_WRITE_FLUSH(hw);
744 usleep_range(1000, 1200);
746 /* Poll for reset bit to self-clear indicating reset is complete */
747 for (i = 0; i < 10; i++) {
748 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
749 if (!(ctrl & IXGBE_CTRL_RST))
753 if (ctrl & IXGBE_CTRL_RST) {
754 status = IXGBE_ERR_RESET_FAILED;
755 hw_dbg(hw, "Reset polling failed to complete.\n");
761 * Double resets are required for recovery from certain error
762 * conditions. Between resets, it is necessary to stall to allow time
763 * for any pending HW events to complete.
765 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
766 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
770 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
771 gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6));
772 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
775 * Store the original AUTOC value if it has not been
776 * stored off yet. Otherwise restore the stored original
777 * AUTOC value since the reset operation sets back to deaults.
779 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
780 if (hw->mac.orig_link_settings_stored == false) {
781 hw->mac.orig_autoc = autoc;
782 hw->mac.orig_link_settings_stored = true;
783 } else if (autoc != hw->mac.orig_autoc) {
784 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
787 /* Store the permanent mac address */
788 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
791 * Store MAC address from RAR0, clear receive address registers, and
792 * clear the multicast table
794 hw->mac.ops.init_rx_addrs(hw);
803 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
804 * @hw: pointer to hardware struct
805 * @rar: receive address register index to associate with a VMDq index
806 * @vmdq: VMDq set index
808 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
811 u32 rar_entries = hw->mac.num_rar_entries;
813 /* Make sure we are using a valid rar index range */
814 if (rar >= rar_entries) {
815 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
816 return IXGBE_ERR_INVALID_ARGUMENT;
819 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
820 rar_high &= ~IXGBE_RAH_VIND_MASK;
821 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
822 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
827 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
828 * @hw: pointer to hardware struct
829 * @rar: receive address register index to associate with a VMDq index
830 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
832 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
835 u32 rar_entries = hw->mac.num_rar_entries;
838 /* Make sure we are using a valid rar index range */
839 if (rar >= rar_entries) {
840 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
841 return IXGBE_ERR_INVALID_ARGUMENT;
844 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
845 if (rar_high & IXGBE_RAH_VIND_MASK) {
846 rar_high &= ~IXGBE_RAH_VIND_MASK;
847 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
854 * ixgbe_set_vfta_82598 - Set VLAN filter table
855 * @hw: pointer to hardware structure
856 * @vlan: VLAN id to write to VLAN filter
857 * @vind: VMDq output index that maps queue to VLAN id in VFTA
858 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
859 * @vlvf_bypass: boolean flag - unused
861 * Turn on/off specified VLAN in the VLAN filter table.
863 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
864 bool vlan_on, bool vlvf_bypass)
872 return IXGBE_ERR_PARAM;
874 /* Determine 32-bit word position in array */
875 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
877 /* Determine the location of the (VMD) queue index */
878 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
879 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
881 /* Set the nibble for VMD queue index */
882 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
883 bits &= (~(0x0F << bitindex));
884 bits |= (vind << bitindex);
885 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
887 /* Determine the location of the bit for this VLAN id */
888 bitindex = vlan & 0x1F; /* lower five bits */
890 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
892 /* Turn on this VLAN id */
893 bits |= BIT(bitindex);
895 /* Turn off this VLAN id */
896 bits &= ~BIT(bitindex);
897 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
903 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
904 * @hw: pointer to hardware structure
906 * Clears the VLAN filer table, and the VMDq index associated with the filter
908 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
913 for (offset = 0; offset < hw->mac.vft_size; offset++)
914 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
916 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
917 for (offset = 0; offset < hw->mac.vft_size; offset++)
918 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
925 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
926 * @hw: pointer to hardware structure
927 * @reg: analog register to read
930 * Performs read operation to Atlas analog register specified.
932 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
936 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
937 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
938 IXGBE_WRITE_FLUSH(hw);
940 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
941 *val = (u8)atlas_ctl;
947 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
948 * @hw: pointer to hardware structure
949 * @reg: atlas register to write
950 * @val: value to write
952 * Performs write operation to Atlas analog register specified.
954 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
958 atlas_ctl = (reg << 8) | val;
959 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
960 IXGBE_WRITE_FLUSH(hw);
967 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
968 * @hw: pointer to hardware structure
969 * @dev_addr: address to read from
970 * @byte_offset: byte offset to read from dev_addr
971 * @eeprom_data: value read
973 * Performs 8 byte read operation to SFP module's data over I2C interface.
975 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
976 u8 byte_offset, u8 *eeprom_data)
985 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
986 gssr = IXGBE_GSSR_PHY1_SM;
988 gssr = IXGBE_GSSR_PHY0_SM;
990 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
991 return IXGBE_ERR_SWFW_SYNC;
993 if (hw->phy.type == ixgbe_phy_nl) {
995 * phy SDA/SCL registers are at addresses 0xC30A to
996 * 0xC30D. These registers are used to talk to the SFP+
997 * module's EEPROM through the SDA/SCL (I2C) interface.
999 sfp_addr = (dev_addr << 8) + byte_offset;
1000 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1001 hw->phy.ops.write_reg_mdi(hw,
1002 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1007 for (i = 0; i < 100; i++) {
1008 hw->phy.ops.read_reg_mdi(hw,
1009 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1012 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1013 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1015 usleep_range(10000, 20000);
1018 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1019 hw_dbg(hw, "EEPROM read did not pass.\n");
1020 status = IXGBE_ERR_SFP_NOT_PRESENT;
1025 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1026 MDIO_MMD_PMAPMD, &sfp_data);
1028 *eeprom_data = (u8)(sfp_data >> 8);
1030 status = IXGBE_ERR_PHY;
1034 hw->mac.ops.release_swfw_sync(hw, gssr);
1039 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1040 * @hw: pointer to hardware structure
1041 * @byte_offset: EEPROM byte offset to read
1042 * @eeprom_data: value read
1044 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1046 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1049 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1050 byte_offset, eeprom_data);
1054 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1055 * @hw: pointer to hardware structure
1056 * @byte_offset: byte offset at address 0xA2
1057 * @eeprom_data: value read
1059 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1061 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1064 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1065 byte_offset, sff8472_data);
1069 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1071 * @hw: pointer to the HW structure
1073 * Calls common function and corrects issue with some single port devices
1074 * that enable LAN1 but not LAN0.
1076 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1078 struct ixgbe_bus_info *bus = &hw->bus;
1082 ixgbe_set_lan_id_multi_port_pcie(hw);
1084 /* check if LAN0 is disabled */
1085 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1086 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1088 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1090 /* if LAN0 is completely disabled force function to 0 */
1091 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1092 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1093 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1101 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1102 * @hw: pointer to hardware structure
1103 * @num_pb: number of packet buffers to allocate
1104 * @headroom: reserve n KB of headroom
1105 * @strategy: packet buffer allocation strategy
1107 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1108 u32 headroom, int strategy)
1110 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1116 /* Setup Rx packet buffer sizes */
1118 case PBA_STRATEGY_WEIGHTED:
1119 /* Setup the first four at 80KB */
1120 rxpktsize = IXGBE_RXPBSIZE_80KB;
1122 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1123 /* Setup the last four at 48KB...don't re-init i */
1124 rxpktsize = IXGBE_RXPBSIZE_48KB;
1126 case PBA_STRATEGY_EQUAL:
1128 /* Divide the remaining Rx packet buffer evenly among the TCs */
1129 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1130 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1134 /* Setup Tx packet buffer sizes */
1135 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1136 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1139 static const struct ixgbe_mac_operations mac_ops_82598 = {
1140 .init_hw = &ixgbe_init_hw_generic,
1141 .reset_hw = &ixgbe_reset_hw_82598,
1142 .start_hw = &ixgbe_start_hw_82598,
1143 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1144 .get_media_type = &ixgbe_get_media_type_82598,
1145 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1146 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1147 .stop_adapter = &ixgbe_stop_adapter_generic,
1148 .get_bus_info = &ixgbe_get_bus_info_generic,
1149 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
1150 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1151 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1152 .setup_link = &ixgbe_setup_mac_link_82598,
1153 .set_rxpba = &ixgbe_set_rxpba_82598,
1154 .check_link = &ixgbe_check_mac_link_82598,
1155 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1156 .led_on = &ixgbe_led_on_generic,
1157 .led_off = &ixgbe_led_off_generic,
1158 .init_led_link_act = ixgbe_init_led_link_act_generic,
1159 .blink_led_start = &ixgbe_blink_led_start_generic,
1160 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1161 .set_rar = &ixgbe_set_rar_generic,
1162 .clear_rar = &ixgbe_clear_rar_generic,
1163 .set_vmdq = &ixgbe_set_vmdq_82598,
1164 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1165 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1166 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1167 .enable_mc = &ixgbe_enable_mc_generic,
1168 .disable_mc = &ixgbe_disable_mc_generic,
1169 .clear_vfta = &ixgbe_clear_vfta_82598,
1170 .set_vfta = &ixgbe_set_vfta_82598,
1171 .fc_enable = &ixgbe_fc_enable_82598,
1172 .setup_fc = ixgbe_setup_fc_generic,
1173 .fc_autoneg = ixgbe_fc_autoneg,
1174 .set_fw_drv_ver = NULL,
1175 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1176 .release_swfw_sync = &ixgbe_release_swfw_sync,
1177 .init_swfw_sync = NULL,
1178 .get_thermal_sensor_data = NULL,
1179 .init_thermal_sensor_thresh = NULL,
1180 .prot_autoc_read = &prot_autoc_read_generic,
1181 .prot_autoc_write = &prot_autoc_write_generic,
1182 .enable_rx = &ixgbe_enable_rx_generic,
1183 .disable_rx = &ixgbe_disable_rx_generic,
1186 static const struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1187 .init_params = &ixgbe_init_eeprom_params_generic,
1188 .read = &ixgbe_read_eerd_generic,
1189 .write = &ixgbe_write_eeprom_generic,
1190 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
1191 .read_buffer = &ixgbe_read_eerd_buffer_generic,
1192 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
1193 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1194 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1197 static const struct ixgbe_phy_operations phy_ops_82598 = {
1198 .identify = &ixgbe_identify_phy_generic,
1199 .identify_sfp = &ixgbe_identify_module_generic,
1200 .init = &ixgbe_init_phy_ops_82598,
1201 .reset = &ixgbe_reset_phy_generic,
1202 .read_reg = &ixgbe_read_phy_reg_generic,
1203 .write_reg = &ixgbe_write_phy_reg_generic,
1204 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
1205 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
1206 .setup_link = &ixgbe_setup_phy_link_generic,
1207 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1208 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
1209 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1210 .check_overtemp = &ixgbe_tn_check_overtemp,
1213 const struct ixgbe_info ixgbe_82598_info = {
1214 .mac = ixgbe_mac_82598EB,
1215 .get_invariants = &ixgbe_get_invariants_82598,
1216 .mac_ops = &mac_ops_82598,
1217 .eeprom_ops = &eeprom_ops_82598,
1218 .phy_ops = &phy_ops_82598,
1219 .mvals = ixgbe_mvals_8259X,