1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2008 Intel Corporation. */
5 * Shared functions for accessing and configuring the adapter
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/pci_ids.h>
14 #include <linux/etherdevice.h>
16 /* Local function prototypes */
18 static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
20 static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
22 static void ixgb_get_bus_info(struct ixgb_hw *hw);
24 static bool ixgb_link_reset(struct ixgb_hw *hw);
26 static void ixgb_optics_reset(struct ixgb_hw *hw);
28 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
30 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
32 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
34 static void ixgb_clear_vfta(struct ixgb_hw *hw);
36 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
38 static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
43 static bool ixgb_setup_fc(struct ixgb_hw *hw);
45 static bool mac_addr_valid(u8 *mac_addr);
47 static u32 ixgb_mac_reset(struct ixgb_hw *hw)
51 ctrl_reg = IXGB_CTRL0_RST |
52 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
56 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
61 /* Workaround for 82597EX reset errata */
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
67 /* Delay a few ms just to allow the reset to complete */
68 msleep(IXGB_DELAY_AFTER_RESET);
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
71 /* Make sure the self-clearing global reset bit did self clear */
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
75 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) {
76 ctrl_reg = /* Enable interrupt from XFP and SerDes */
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
83 ixgb_optics_reset_bcm(hw);
86 if (hw->phy_type == ixgb_phy_type_txn17401)
87 ixgb_optics_reset(hw);
92 /******************************************************************************
93 * Reset the transmit and receive units; mask and clear all interrupts.
95 * hw - Struct containing variables accessed by shared code
96 *****************************************************************************/
98 ixgb_adapter_stop(struct ixgb_hw *hw)
104 /* If we are stopped or resetting exit gracefully and wait to be
105 * started again before accessing the hardware.
107 if (hw->adapter_stopped) {
108 pr_debug("Exiting because the adapter is already stopped!!!\n");
112 /* Set the Adapter Stopped flag so other driver functions stop
113 * touching the Hardware.
115 hw->adapter_stopped = true;
117 /* Clear interrupt mask to stop board from generating interrupts */
118 pr_debug("Masking off all interrupts\n");
119 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
121 /* Disable the Transmit and Receive units. Then delay to allow
122 * any pending transactions to complete before we hit the MAC with
125 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
126 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
127 IXGB_WRITE_FLUSH(hw);
128 msleep(IXGB_DELAY_BEFORE_RESET);
130 /* Issue a global reset to the MAC. This will reset the chip's
131 * transmit, receive, DMA, and link units. It will not effect
132 * the current PCI configuration. The global reset bit is self-
133 * clearing, and should clear within a microsecond.
135 pr_debug("Issuing a global reset to MAC\n");
137 ctrl_reg = ixgb_mac_reset(hw);
139 /* Clear interrupt mask to stop board from generating interrupts */
140 pr_debug("Masking off all interrupts\n");
141 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
143 /* Clear any pending interrupt events. */
144 IXGB_READ_REG(hw, ICR);
146 return ctrl_reg & IXGB_CTRL0_RST;
150 /******************************************************************************
151 * Identifies the vendor of the optics module on the adapter. The SR adapters
152 * support two different types of XPAK optics, so it is necessary to determine
153 * which optics are present before applying any optics-specific workarounds.
155 * hw - Struct containing variables accessed by shared code.
157 * Returns: the vendor of the XPAK optics module.
158 *****************************************************************************/
159 static ixgb_xpak_vendor
160 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
164 ixgb_xpak_vendor xpak_vendor;
168 /* Read the first few bytes of the vendor string from the XPAK NVR
169 * registers. These are standard XENPAK/XPAK registers, so all XPAK
170 * devices should implement them. */
171 for (i = 0; i < 5; i++) {
172 vendor_name[i] = ixgb_read_phy_reg(hw,
173 MDIO_PMA_PMD_XPAK_VENDOR_NAME
174 + i, IXGB_PHY_ADDRESS,
178 /* Determine the actual vendor */
179 if (vendor_name[0] == 'I' &&
180 vendor_name[1] == 'N' &&
181 vendor_name[2] == 'T' &&
182 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
183 xpak_vendor = ixgb_xpak_vendor_intel;
185 xpak_vendor = ixgb_xpak_vendor_infineon;
191 /******************************************************************************
192 * Determine the physical layer module on the adapter.
194 * hw - Struct containing variables accessed by shared code. The device_id
195 * field must be (correctly) populated before calling this routine.
197 * Returns: the phy type of the adapter.
198 *****************************************************************************/
200 ixgb_identify_phy(struct ixgb_hw *hw)
202 ixgb_phy_type phy_type;
203 ixgb_xpak_vendor xpak_vendor;
207 /* Infer the transceiver/phy type from the device id */
208 switch (hw->device_id) {
209 case IXGB_DEVICE_ID_82597EX:
210 pr_debug("Identified TXN17401 optics\n");
211 phy_type = ixgb_phy_type_txn17401;
214 case IXGB_DEVICE_ID_82597EX_SR:
215 /* The SR adapters carry two different types of XPAK optics
216 * modules; read the vendor identifier to determine the exact
218 xpak_vendor = ixgb_identify_xpak_vendor(hw);
219 if (xpak_vendor == ixgb_xpak_vendor_intel) {
220 pr_debug("Identified TXN17201 optics\n");
221 phy_type = ixgb_phy_type_txn17201;
223 pr_debug("Identified G6005 optics\n");
224 phy_type = ixgb_phy_type_g6005;
227 case IXGB_DEVICE_ID_82597EX_LR:
228 pr_debug("Identified G6104 optics\n");
229 phy_type = ixgb_phy_type_g6104;
231 case IXGB_DEVICE_ID_82597EX_CX4:
232 pr_debug("Identified CX4\n");
233 xpak_vendor = ixgb_identify_xpak_vendor(hw);
234 if (xpak_vendor == ixgb_xpak_vendor_intel) {
235 pr_debug("Identified TXN17201 optics\n");
236 phy_type = ixgb_phy_type_txn17201;
238 pr_debug("Identified G6005 optics\n");
239 phy_type = ixgb_phy_type_g6005;
243 pr_debug("Unknown physical layer module\n");
244 phy_type = ixgb_phy_type_unknown;
248 /* update phy type for sun specific board */
249 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN)
250 phy_type = ixgb_phy_type_bcm;
255 /******************************************************************************
256 * Performs basic configuration of the adapter.
258 * hw - Struct containing variables accessed by shared code
260 * Resets the controller.
261 * Reads and validates the EEPROM.
262 * Initializes the receive address registers.
263 * Initializes the multicast table.
264 * Clears all on-chip counters.
265 * Calls routine to setup flow control settings.
266 * Leaves the transmit and receive units disabled and uninitialized.
269 * true if successful,
270 * false if unrecoverable problems were encountered.
271 *****************************************************************************/
273 ixgb_init_hw(struct ixgb_hw *hw)
280 /* Issue a global reset to the MAC. This will reset the chip's
281 * transmit, receive, DMA, and link units. It will not effect
282 * the current PCI configuration. The global reset bit is self-
283 * clearing, and should clear within a microsecond.
285 pr_debug("Issuing a global reset to MAC\n");
289 pr_debug("Issuing an EE reset to MAC\n");
291 /* Workaround for 82597EX reset errata */
292 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
294 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
297 /* Delay a few ms just to allow the reset to complete */
298 msleep(IXGB_DELAY_AFTER_EE_RESET);
300 if (!ixgb_get_eeprom_data(hw))
303 /* Use the device id to determine the type of phy/transceiver. */
304 hw->device_id = ixgb_get_ee_device_id(hw);
305 hw->phy_type = ixgb_identify_phy(hw);
307 /* Setup the receive addresses.
308 * Receive Address Registers (RARs 0 - 15).
310 ixgb_init_rx_addrs(hw);
313 * Check that a valid MAC address has been set.
314 * If it is not valid, we fail hardware init.
316 if (!mac_addr_valid(hw->curr_mac_addr)) {
317 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
321 /* tell the routines in this file they can access hardware again */
322 hw->adapter_stopped = false;
324 /* Fill in the bus_info structure */
325 ixgb_get_bus_info(hw);
327 /* Zero out the Multicast HASH table */
328 pr_debug("Zeroing the MTA\n");
329 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
330 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
332 /* Zero out the VLAN Filter Table Array */
335 /* Zero all of the hardware counters */
336 ixgb_clear_hw_cntrs(hw);
338 /* Call a subroutine to setup flow control. */
339 status = ixgb_setup_fc(hw);
341 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
342 ixgb_check_for_link(hw);
347 /******************************************************************************
348 * Initializes receive address filters.
350 * hw - Struct containing variables accessed by shared code
352 * Places the MAC address in receive address register 0 and clears the rest
353 * of the receive address registers. Clears the multicast table. Assumes
354 * the receiver is in reset when the routine is called.
355 *****************************************************************************/
357 ixgb_init_rx_addrs(struct ixgb_hw *hw)
364 * If the current mac address is valid, assume it is a software override
365 * to the permanent address.
366 * Otherwise, use the permanent address from the eeprom.
368 if (!mac_addr_valid(hw->curr_mac_addr)) {
370 /* Get the MAC address from the eeprom for later reference */
371 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
373 pr_debug("Keeping Permanent MAC Addr = %pM\n",
377 /* Setup the receive address. */
378 pr_debug("Overriding MAC Address in RAR[0]\n");
379 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
381 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
384 /* Zero out the other 15 receive addresses. */
385 pr_debug("Clearing RAR[1-15]\n");
386 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
387 /* Write high reg first to disable the AV bit first */
388 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
389 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
393 /******************************************************************************
394 * Updates the MAC's list of multicast addresses.
396 * hw - Struct containing variables accessed by shared code
397 * mc_addr_list - the list of new multicast addresses
398 * mc_addr_count - number of addresses
399 * pad - number of bytes between addresses in the list
401 * The given list replaces any existing list. Clears the last 15 receive
402 * address registers and the multicast table. Uses receive address registers
403 * for the first 15 multicast addresses, and hashes the rest into the
405 *****************************************************************************/
407 ixgb_mc_addr_list_update(struct ixgb_hw *hw,
414 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
419 /* Set the new number of MC addresses that we are being requested to use. */
420 hw->num_mc_addrs = mc_addr_count;
422 /* Clear RAR[1-15] */
423 pr_debug("Clearing RAR[1-15]\n");
424 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
425 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
426 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
430 pr_debug("Clearing MTA\n");
431 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
432 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
434 /* Add the new addresses */
436 for (i = 0; i < mc_addr_count; i++) {
437 pr_debug("Adding the multicast addresses:\n");
438 pr_debug("MC Addr #%d = %pM\n", i, mca);
440 /* Place this multicast address in the RAR if there is room, *
441 * else put it in the MTA
443 if (rar_used_count < IXGB_RAR_ENTRIES) {
444 ixgb_rar_set(hw, mca, rar_used_count);
445 pr_debug("Added a multicast address to RAR[%d]\n", i);
448 hash_value = ixgb_hash_mc_addr(hw, mca);
450 pr_debug("Hash value = 0x%03X\n", hash_value);
452 ixgb_mta_set(hw, hash_value);
455 mca += ETH_ALEN + pad;
458 pr_debug("MC Update Complete\n");
461 /******************************************************************************
462 * Hashes an address to determine its location in the multicast table
464 * hw - Struct containing variables accessed by shared code
465 * mc_addr - the multicast address to hash
469 *****************************************************************************/
471 ixgb_hash_mc_addr(struct ixgb_hw *hw,
478 /* The portion of the address that is used for the hash table is
479 * determined by the mc_filter_type setting.
481 switch (hw->mc_filter_type) {
482 /* [0] [1] [2] [3] [4] [5]
484 * LSB MSB - According to H/W docs */
486 /* [47:36] i.e. 0x563 for above example address */
488 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
490 case 1: /* [46:35] i.e. 0xAC6 for above example address */
492 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
494 case 2: /* [45:34] i.e. 0x5D8 for above example address */
496 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
498 case 3: /* [43:32] i.e. 0x634 for above example address */
499 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
502 /* Invalid mc_filter_type, what should we do? */
503 pr_debug("MC filter type param set incorrectly\n");
512 /******************************************************************************
513 * Sets the bit in the multicast table corresponding to the hash value.
515 * hw - Struct containing variables accessed by shared code
516 * hash_value - Multicast address hash value
517 *****************************************************************************/
519 ixgb_mta_set(struct ixgb_hw *hw,
522 u32 hash_bit, hash_reg;
525 /* The MTA is a register array of 128 32-bit registers.
526 * It is treated like an array of 4096 bits. We want to set
527 * bit BitArray[hash_value]. So we figure out what register
528 * the bit is in, read it, OR in the new bit, then write
529 * back the new value. The register is determined by the
530 * upper 7 bits of the hash value and the bit within that
531 * register are determined by the lower 5 bits of the value.
533 hash_reg = (hash_value >> 5) & 0x7F;
534 hash_bit = hash_value & 0x1F;
536 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
538 mta_reg |= (1 << hash_bit);
540 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
543 /******************************************************************************
544 * Puts an ethernet address into a receive address register.
546 * hw - Struct containing variables accessed by shared code
547 * addr - Address to put into receive address register
548 * index - Receive address register to write
549 *****************************************************************************/
551 ixgb_rar_set(struct ixgb_hw *hw,
555 u32 rar_low, rar_high;
559 /* HW expects these in little endian so we reverse the byte order
560 * from network order (big endian) to little endian
562 rar_low = ((u32) addr[0] |
563 ((u32)addr[1] << 8) |
564 ((u32)addr[2] << 16) |
565 ((u32)addr[3] << 24));
567 rar_high = ((u32) addr[4] |
568 ((u32)addr[5] << 8) |
571 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
572 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
575 /******************************************************************************
576 * Writes a value to the specified offset in the VLAN filter table.
578 * hw - Struct containing variables accessed by shared code
579 * offset - Offset in VLAN filer table to write
580 * value - Value to write into VLAN filter table
581 *****************************************************************************/
583 ixgb_write_vfta(struct ixgb_hw *hw,
587 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
590 /******************************************************************************
591 * Clears the VLAN filer table
593 * hw - Struct containing variables accessed by shared code
594 *****************************************************************************/
596 ixgb_clear_vfta(struct ixgb_hw *hw)
600 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
601 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
604 /******************************************************************************
605 * Configures the flow control settings based on SW configuration.
607 * hw - Struct containing variables accessed by shared code
608 *****************************************************************************/
611 ixgb_setup_fc(struct ixgb_hw *hw)
614 u32 pap_reg = 0; /* by default, assume no pause time */
619 /* Get the current control reg 0 settings */
620 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
622 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
623 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
625 /* The possible values of the "flow_control" parameter are:
626 * 0: Flow control is completely disabled
627 * 1: Rx flow control is enabled (we can receive pause frames
628 * but not send pause frames).
629 * 2: Tx flow control is enabled (we can send pause frames
630 * but we do not support receiving pause frames).
631 * 3: Both Rx and TX flow control (symmetric) are enabled.
634 switch (hw->fc.type) {
635 case ixgb_fc_none: /* 0 */
636 /* Set CMDC bit to disable Rx Flow control */
637 ctrl_reg |= (IXGB_CTRL0_CMDC);
639 case ixgb_fc_rx_pause: /* 1 */
640 /* RX Flow control is enabled, and TX Flow control is
643 ctrl_reg |= (IXGB_CTRL0_RPE);
645 case ixgb_fc_tx_pause: /* 2 */
646 /* TX Flow control is enabled, and RX Flow control is
647 * disabled, by a software over-ride.
649 ctrl_reg |= (IXGB_CTRL0_TPE);
650 pap_reg = hw->fc.pause_time;
652 case ixgb_fc_full: /* 3 */
653 /* Flow control (both RX and TX) is enabled by a software
656 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
657 pap_reg = hw->fc.pause_time;
660 /* We should never get here. The value should be 0-3. */
661 pr_debug("Flow control param set incorrectly\n");
666 /* Write the new settings */
667 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
670 IXGB_WRITE_REG(hw, PAP, pap_reg);
672 /* Set the flow control receive threshold registers. Normally,
673 * these registers will be set to a default threshold that may be
674 * adjusted later by the driver's runtime code. However, if the
675 * ability to transmit pause frames in not enabled, then these
676 * registers will be set to 0.
678 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
679 IXGB_WRITE_REG(hw, FCRTL, 0);
680 IXGB_WRITE_REG(hw, FCRTH, 0);
682 /* We need to set up the Receive Threshold high and low water
683 * marks as well as (optionally) enabling the transmission of XON
685 if (hw->fc.send_xon) {
686 IXGB_WRITE_REG(hw, FCRTL,
687 (hw->fc.low_water | IXGB_FCRTL_XONE));
689 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
691 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
696 /******************************************************************************
697 * Reads a word from a device over the Management Data Interface (MDI) bus.
698 * This interface is used to manage Physical layer devices.
700 * hw - Struct containing variables accessed by hw code
701 * reg_address - Offset of device register being read.
702 * phy_address - Address of device on MDI.
704 * Returns: Data word (16 bits) from MDI device.
706 * The 82597EX has support for several MDI access methods. This routine
707 * uses the new protocol MDI Single Command and Address Operation.
708 * This requires that first an address cycle command is sent, followed by a
710 *****************************************************************************/
712 ixgb_read_phy_reg(struct ixgb_hw *hw,
721 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
722 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
723 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
725 /* Setup and write the address cycle command */
726 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
727 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
728 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
729 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
731 IXGB_WRITE_REG(hw, MSCA, command);
733 /**************************************************************
734 ** Check every 10 usec to see if the address cycle completed
735 ** The COMMAND bit will clear when the operation is complete.
736 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
737 ** from the CPU Write to the Ready bit assertion.
738 **************************************************************/
740 for (i = 0; i < 10; i++)
744 command = IXGB_READ_REG(hw, MSCA);
746 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
750 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
752 /* Address cycle complete, setup and write the read command */
753 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
754 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
755 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
756 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
758 IXGB_WRITE_REG(hw, MSCA, command);
760 /**************************************************************
761 ** Check every 10 usec to see if the read command completed
762 ** The COMMAND bit will clear when the operation is complete.
763 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
764 ** from the CPU Write to the Ready bit assertion.
765 **************************************************************/
767 for (i = 0; i < 10; i++)
771 command = IXGB_READ_REG(hw, MSCA);
773 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
777 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
779 /* Operation is complete, get the data from the MDIO Read/Write Data
780 * register and return.
782 data = IXGB_READ_REG(hw, MSRWD);
783 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
787 /******************************************************************************
788 * Writes a word to a device over the Management Data Interface (MDI) bus.
789 * This interface is used to manage Physical layer devices.
791 * hw - Struct containing variables accessed by hw code
792 * reg_address - Offset of device register being read.
793 * phy_address - Address of device on MDI.
794 * device_type - Also known as the Device ID or DID.
795 * data - 16-bit value to be written
799 * The 82597EX has support for several MDI access methods. This routine
800 * uses the new protocol MDI Single Command and Address Operation.
801 * This requires that first an address cycle command is sent, followed by a
803 *****************************************************************************/
805 ixgb_write_phy_reg(struct ixgb_hw *hw,
814 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
815 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
816 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
818 /* Put the data in the MDIO Read/Write Data register */
819 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
821 /* Setup and write the address cycle command */
822 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
823 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
824 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
825 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
827 IXGB_WRITE_REG(hw, MSCA, command);
829 /**************************************************************
830 ** Check every 10 usec to see if the address cycle completed
831 ** The COMMAND bit will clear when the operation is complete.
832 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
833 ** from the CPU Write to the Ready bit assertion.
834 **************************************************************/
836 for (i = 0; i < 10; i++)
840 command = IXGB_READ_REG(hw, MSCA);
842 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
846 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
848 /* Address cycle complete, setup and write the write command */
849 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
850 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
851 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
852 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
854 IXGB_WRITE_REG(hw, MSCA, command);
856 /**************************************************************
857 ** Check every 10 usec to see if the read command completed
858 ** The COMMAND bit will clear when the operation is complete.
859 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
860 ** from the CPU Write to the Ready bit assertion.
861 **************************************************************/
863 for (i = 0; i < 10; i++)
867 command = IXGB_READ_REG(hw, MSCA);
869 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
873 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
875 /* Operation is complete, return. */
878 /******************************************************************************
879 * Checks to see if the link status of the hardware has changed.
881 * hw - Struct containing variables accessed by hw code
883 * Called by any function that needs to check the link status of the adapter.
884 *****************************************************************************/
886 ixgb_check_for_link(struct ixgb_hw *hw)
893 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
894 status_reg = IXGB_READ_REG(hw, STATUS);
896 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
897 (status_reg & IXGB_STATUS_LU)) {
899 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
900 (status_reg & IXGB_STATUS_LU)) {
901 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
902 hw->link_up = ixgb_link_reset(hw);
905 * 82597EX errata. Since the lane deskew problem may prevent
906 * link, reset the link before reporting link down.
908 hw->link_up = ixgb_link_reset(hw);
910 /* Anything else for 10 Gig?? */
913 /******************************************************************************
914 * Check for a bad link condition that may have occurred.
915 * The indication is that the RFC / LFC registers may be incrementing
916 * continually. A full adapter reset is required to recover.
918 * hw - Struct containing variables accessed by hw code
920 * Called by any function that needs to check the link status of the adapter.
921 *****************************************************************************/
922 bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
925 bool bad_link_returncode = false;
927 if (hw->phy_type == ixgb_phy_type_txn17401) {
928 newLFC = IXGB_READ_REG(hw, LFC);
929 newRFC = IXGB_READ_REG(hw, RFC);
930 if ((hw->lastLFC + 250 < newLFC)
931 || (hw->lastRFC + 250 < newRFC)) {
932 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
933 bad_link_returncode = true;
935 hw->lastLFC = newLFC;
936 hw->lastRFC = newRFC;
939 return bad_link_returncode;
942 /******************************************************************************
943 * Clears all hardware statistics counters.
945 * hw - Struct containing variables accessed by shared code
946 *****************************************************************************/
948 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
952 /* if we are stopped or resetting exit gracefully */
953 if (hw->adapter_stopped) {
954 pr_debug("Exiting because the adapter is stopped!!!\n");
958 IXGB_READ_REG(hw, TPRL);
959 IXGB_READ_REG(hw, TPRH);
960 IXGB_READ_REG(hw, GPRCL);
961 IXGB_READ_REG(hw, GPRCH);
962 IXGB_READ_REG(hw, BPRCL);
963 IXGB_READ_REG(hw, BPRCH);
964 IXGB_READ_REG(hw, MPRCL);
965 IXGB_READ_REG(hw, MPRCH);
966 IXGB_READ_REG(hw, UPRCL);
967 IXGB_READ_REG(hw, UPRCH);
968 IXGB_READ_REG(hw, VPRCL);
969 IXGB_READ_REG(hw, VPRCH);
970 IXGB_READ_REG(hw, JPRCL);
971 IXGB_READ_REG(hw, JPRCH);
972 IXGB_READ_REG(hw, GORCL);
973 IXGB_READ_REG(hw, GORCH);
974 IXGB_READ_REG(hw, TORL);
975 IXGB_READ_REG(hw, TORH);
976 IXGB_READ_REG(hw, RNBC);
977 IXGB_READ_REG(hw, RUC);
978 IXGB_READ_REG(hw, ROC);
979 IXGB_READ_REG(hw, RLEC);
980 IXGB_READ_REG(hw, CRCERRS);
981 IXGB_READ_REG(hw, ICBC);
982 IXGB_READ_REG(hw, ECBC);
983 IXGB_READ_REG(hw, MPC);
984 IXGB_READ_REG(hw, TPTL);
985 IXGB_READ_REG(hw, TPTH);
986 IXGB_READ_REG(hw, GPTCL);
987 IXGB_READ_REG(hw, GPTCH);
988 IXGB_READ_REG(hw, BPTCL);
989 IXGB_READ_REG(hw, BPTCH);
990 IXGB_READ_REG(hw, MPTCL);
991 IXGB_READ_REG(hw, MPTCH);
992 IXGB_READ_REG(hw, UPTCL);
993 IXGB_READ_REG(hw, UPTCH);
994 IXGB_READ_REG(hw, VPTCL);
995 IXGB_READ_REG(hw, VPTCH);
996 IXGB_READ_REG(hw, JPTCL);
997 IXGB_READ_REG(hw, JPTCH);
998 IXGB_READ_REG(hw, GOTCL);
999 IXGB_READ_REG(hw, GOTCH);
1000 IXGB_READ_REG(hw, TOTL);
1001 IXGB_READ_REG(hw, TOTH);
1002 IXGB_READ_REG(hw, DC);
1003 IXGB_READ_REG(hw, PLT64C);
1004 IXGB_READ_REG(hw, TSCTC);
1005 IXGB_READ_REG(hw, TSCTFC);
1006 IXGB_READ_REG(hw, IBIC);
1007 IXGB_READ_REG(hw, RFC);
1008 IXGB_READ_REG(hw, LFC);
1009 IXGB_READ_REG(hw, PFRC);
1010 IXGB_READ_REG(hw, PFTC);
1011 IXGB_READ_REG(hw, MCFRC);
1012 IXGB_READ_REG(hw, MCFTC);
1013 IXGB_READ_REG(hw, XONRXC);
1014 IXGB_READ_REG(hw, XONTXC);
1015 IXGB_READ_REG(hw, XOFFRXC);
1016 IXGB_READ_REG(hw, XOFFTXC);
1017 IXGB_READ_REG(hw, RJC);
1020 /******************************************************************************
1021 * Turns on the software controllable LED
1023 * hw - Struct containing variables accessed by shared code
1024 *****************************************************************************/
1026 ixgb_led_on(struct ixgb_hw *hw)
1028 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1030 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1031 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1032 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1035 /******************************************************************************
1036 * Turns off the software controllable LED
1038 * hw - Struct containing variables accessed by shared code
1039 *****************************************************************************/
1041 ixgb_led_off(struct ixgb_hw *hw)
1043 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1045 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1046 ctrl0_reg |= IXGB_CTRL0_SDP0;
1047 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1050 /******************************************************************************
1051 * Gets the current PCI bus type, speed, and width of the hardware
1053 * hw - Struct containing variables accessed by shared code
1054 *****************************************************************************/
1056 ixgb_get_bus_info(struct ixgb_hw *hw)
1060 status_reg = IXGB_READ_REG(hw, STATUS);
1062 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1063 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1065 if (hw->bus.type == ixgb_bus_type_pci) {
1066 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1067 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1069 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1070 case IXGB_STATUS_PCIX_SPD_66:
1071 hw->bus.speed = ixgb_bus_speed_66;
1073 case IXGB_STATUS_PCIX_SPD_100:
1074 hw->bus.speed = ixgb_bus_speed_100;
1076 case IXGB_STATUS_PCIX_SPD_133:
1077 hw->bus.speed = ixgb_bus_speed_133;
1080 hw->bus.speed = ixgb_bus_speed_reserved;
1085 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1086 ixgb_bus_width_64 : ixgb_bus_width_32;
1089 /******************************************************************************
1090 * Tests a MAC address to ensure it is a valid Individual Address
1092 * mac_addr - pointer to MAC address.
1094 *****************************************************************************/
1096 mac_addr_valid(u8 *mac_addr)
1098 bool is_valid = true;
1101 /* Make sure it is not a multicast address */
1102 if (is_multicast_ether_addr(mac_addr)) {
1103 pr_debug("MAC address is multicast\n");
1106 /* Not a broadcast address */
1107 else if (is_broadcast_ether_addr(mac_addr)) {
1108 pr_debug("MAC address is broadcast\n");
1111 /* Reject the zero address */
1112 else if (is_zero_ether_addr(mac_addr)) {
1113 pr_debug("MAC address is all zeros\n");
1119 /******************************************************************************
1120 * Resets the 10GbE link. Waits the settle time and returns the state of
1123 * hw - Struct containing variables accessed by shared code
1124 *****************************************************************************/
1126 ixgb_link_reset(struct ixgb_hw *hw)
1128 bool link_status = false;
1129 u8 wait_retries = MAX_RESET_ITERATIONS;
1130 u8 lrst_retries = MAX_RESET_ITERATIONS;
1133 /* Reset the link */
1134 IXGB_WRITE_REG(hw, CTRL0,
1135 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1137 /* Wait for link-up and lane re-alignment */
1139 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1141 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1142 && (IXGB_READ_REG(hw, XPCSS) &
1143 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1144 } while (!link_status && --wait_retries);
1146 } while (!link_status && --lrst_retries);
1151 /******************************************************************************
1152 * Resets the 10GbE optics module.
1154 * hw - Struct containing variables accessed by shared code
1155 *****************************************************************************/
1157 ixgb_optics_reset(struct ixgb_hw *hw)
1159 if (hw->phy_type == ixgb_phy_type_txn17401) {
1160 ixgb_write_phy_reg(hw,
1166 ixgb_read_phy_reg(hw, MDIO_CTRL1, IXGB_PHY_ADDRESS, MDIO_MMD_PMAPMD);
1170 /******************************************************************************
1171 * Resets the 10GbE optics module for Sun variant NIC.
1173 * hw - Struct containing variables accessed by shared code
1174 *****************************************************************************/
1176 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1177 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1178 #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1179 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1180 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1181 #define IXGB_SUN_PHY_ADDRESS 0x0000
1182 #define IXGB_SUN_PHY_RESET_DELAY 305
1185 ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1187 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1188 ctrl &= ~IXGB_CTRL0_SDP2;
1189 ctrl |= IXGB_CTRL0_SDP3;
1190 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1191 IXGB_WRITE_FLUSH(hw);
1193 /* SerDes needs extra delay */
1194 msleep(IXGB_SUN_PHY_RESET_DELAY);
1196 /* Broadcom 7408L configuration */
1197 /* Reference clock config */
1198 ixgb_write_phy_reg(hw,
1199 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1200 IXGB_SUN_PHY_ADDRESS,
1201 IXGB_BCM8704_USER_DEV3_ADDR,
1202 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1203 /* we must read the registers twice */
1204 ixgb_read_phy_reg(hw,
1205 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1206 IXGB_SUN_PHY_ADDRESS,
1207 IXGB_BCM8704_USER_DEV3_ADDR);
1208 ixgb_read_phy_reg(hw,
1209 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1210 IXGB_SUN_PHY_ADDRESS,
1211 IXGB_BCM8704_USER_DEV3_ADDR);
1213 ixgb_write_phy_reg(hw,
1214 IXGB_BCM8704_USER_CTRL_REG,
1215 IXGB_SUN_PHY_ADDRESS,
1216 IXGB_BCM8704_USER_DEV3_ADDR,
1217 IXGB_BCM8704_USER_CTRL_REG_VAL);
1218 ixgb_read_phy_reg(hw,
1219 IXGB_BCM8704_USER_CTRL_REG,
1220 IXGB_SUN_PHY_ADDRESS,
1221 IXGB_BCM8704_USER_DEV3_ADDR);
1222 ixgb_read_phy_reg(hw,
1223 IXGB_BCM8704_USER_CTRL_REG,
1224 IXGB_SUN_PHY_ADDRESS,
1225 IXGB_BCM8704_USER_DEV3_ADDR);
1227 /* SerDes needs extra delay */
1228 msleep(IXGB_SUN_PHY_RESET_DELAY);