1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
4 #ifndef _IGC_DEFINES_H_
5 #define _IGC_DEFINES_H_
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
8 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
9 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
11 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
13 /* Definitions for power management and wakeup registers */
15 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
17 /* Wake Up Filter Control */
18 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
19 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
20 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
21 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
22 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
24 #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
27 #define IGC_WUS_EX 0x00000004 /* Directed Exact */
28 #define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */
29 #define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */
30 #define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */
31 #define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */
33 /* Packet types that are enabled for wake packet delivery */
34 #define WAKE_PKT_WUS ( \
41 /* Wake Up Packet Length */
42 #define IGC_WUPL_MASK 0x00000FFF
44 /* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
45 #define IGC_WUPM_BYTES 128
47 /* Loop limit on how long we wait for auto-negotiation to complete */
48 #define COPPER_LINK_UP_LIMIT 10
49 #define PHY_AUTO_NEG_LIMIT 45
51 /* Number of 100 microseconds we wait for PCI Express master disable */
52 #define MASTER_DISABLE_TIMEOUT 800
53 /*Blocks new Master requests */
54 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
55 /* Status of Master requests. */
56 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
59 * Number of high/low register pairs in the RAR. The RAR (Receive Address
60 * Registers) holds the directed and multicast addresses that we monitor.
61 * Technically, we have 16 spots. However, we reserve one of these spots
62 * (RAR[15]) for our directed address used by controllers with
63 * manageability enabled, allowing us room for 15 multicast addresses.
65 #define IGC_RAH_RAH_MASK 0x0000FFFF
66 #define IGC_RAH_ASEL_MASK 0x00030000
67 #define IGC_RAH_ASEL_SRC_ADDR BIT(16)
68 #define IGC_RAH_QSEL_MASK 0x000C0000
69 #define IGC_RAH_QSEL_SHIFT 18
70 #define IGC_RAH_QSEL_ENABLE BIT(28)
71 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
73 #define IGC_RAL_MAC_ADDR_LEN 4
74 #define IGC_RAH_MAC_ADDR_LEN 2
80 #define IGC_ERR_CONFIG 3
81 #define IGC_ERR_PARAM 4
82 #define IGC_ERR_MAC_INIT 5
83 #define IGC_ERR_RESET 9
84 #define IGC_ERR_MASTER_REQUESTS_PENDING 10
85 #define IGC_ERR_BLK_PHY_RESET 12
86 #define IGC_ERR_SWFW_SYNC 13
89 #define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */
91 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
92 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
93 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */
94 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
96 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
97 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
99 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
100 #define MAX_JUMBO_FRAME_SIZE 0x2600
103 #define IGC_PBA_34K 0x0022
105 /* SW Semaphore Register */
106 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
107 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
109 /* SWFW_SYNC Definitions */
110 #define IGC_SWFW_EEP_SM 0x1
111 #define IGC_SWFW_PHY0_SM 0x2
113 /* Autoneg Advertisement Register */
114 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
115 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
116 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
117 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
118 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
119 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
121 /* Link Partner Ability Register (Base Page) */
122 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
123 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
125 /* 1000BASE-T Control Register */
126 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
127 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
128 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
130 /* 1000BASE-T Status Register */
131 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
132 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
134 /* PHY GPY 211 registers */
135 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */
136 #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */
137 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
138 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */
141 /* Number of milliseconds for NVM auto read done after MAC reset. */
142 #define AUTO_READ_DONE_TIMEOUT 10
143 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
144 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */
145 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */
146 /* NVM Addressing bits based on type 0=small, 1=large */
147 #define IGC_EECD_ADDR_BITS 0x00000400
148 #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
149 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
150 #define IGC_EECD_SIZE_EX_SHIFT 11
151 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
152 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/
153 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */
154 #define IGC_FLUDONE_ATTEMPTS 20000
155 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
157 /* Offset to data in NVM read/write registers */
158 #define IGC_NVM_RW_REG_DATA 16
159 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
160 #define IGC_NVM_RW_REG_START 1 /* Start operation */
161 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
162 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */
164 /* NVM Word Offsets */
165 #define NVM_CHECKSUM_REG 0x003F
167 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
168 #define NVM_SUM 0xBABA
169 #define NVM_WORD_SIZE_BASE_SHIFT 6
171 /* Collision related configuration parameters */
172 #define IGC_COLLISION_THRESHOLD 15
173 #define IGC_CT_SHIFT 4
174 #define IGC_COLLISION_DISTANCE 63
175 #define IGC_COLD_SHIFT 12
178 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
179 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
180 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
181 #define IGC_STATUS_FUNC_SHIFT 2
182 #define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */
183 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */
184 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
185 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
186 #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */
189 #define SPEED_100 100
190 #define SPEED_1000 1000
191 #define SPEED_2500 2500
192 #define HALF_DUPLEX 1
193 #define FULL_DUPLEX 2
195 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
196 #define ADVERTISE_10_HALF 0x0001
197 #define ADVERTISE_10_FULL 0x0002
198 #define ADVERTISE_100_HALF 0x0004
199 #define ADVERTISE_100_FULL 0x0008
200 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
201 #define ADVERTISE_1000_FULL 0x0020
202 #define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */
203 #define ADVERTISE_2500_FULL 0x0080
205 #define IGC_ALL_SPEED_DUPLEX_2500 ( \
206 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
207 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
209 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500
211 /* Interrupt Cause Read */
212 #define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
213 #define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
214 #define IGC_ICR_LSC BIT(2) /* Link Status Change */
215 #define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
216 #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
217 #define IGC_ICR_RXO BIT(6) /* Rx overrun */
218 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
219 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */
220 #define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
222 /* If this bit asserted, the driver should claim the interrupt */
223 #define IGC_ICR_INT_ASSERTED BIT(31)
225 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
227 #define IMS_ENABLE_MASK ( \
234 /* Interrupt Mask Set */
235 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
236 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
237 #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
238 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
239 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
240 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
241 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
242 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */
244 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
245 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
247 /* Interrupt Cause Set */
248 #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */
249 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */
251 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
252 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
253 #define IGC_IVAR_VALID 0x80
254 #define IGC_GPIE_NSICR 0x00000001
255 #define IGC_GPIE_MSIX_MODE 0x00000010
256 #define IGC_GPIE_EIAME 0x40000000
257 #define IGC_GPIE_PBA 0x80000000
259 /* Receive Descriptor bit definitions */
260 #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */
262 /* Transmit Descriptor bit definitions */
263 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
264 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
265 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
266 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
267 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */
268 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */
269 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
270 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
271 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */
272 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */
273 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */
274 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
275 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
277 /* IPSec Encrypt Enable */
278 #define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
279 #define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
281 #define IGC_ADVTXD_TSN_CNTX_FIRST 0x00000080
283 /* Transmit Control */
284 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
285 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */
286 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
287 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */
288 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
289 #define IGC_TCTL_MULR 0x10000000 /* Multiple request support */
291 /* Flow Control Constants */
292 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
293 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
294 #define FLOW_CONTROL_TYPE 0x8808
295 /* Enable XON frame transmission */
296 #define IGC_FCRTL_XONE 0x80000000
298 /* Management Control */
299 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
300 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
302 /* Receive Control */
303 #define IGC_RCTL_RST 0x00000001 /* Software reset */
304 #define IGC_RCTL_EN 0x00000002 /* enable */
305 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */
306 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
307 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
308 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */
309 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
310 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
312 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
313 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
315 /* Split Replication Receive Control */
316 #define IGC_SRRCTL_TIMESTAMP 0x40000000
317 #define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14)
318 #define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17)
320 /* Receive Descriptor bit definitions */
321 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
322 #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */
323 #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
324 #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
326 /* Advanced Receive Descriptor bit definitions */
327 #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
329 #define IGC_RXDEXT_STATERR_L4E 0x20000000
330 #define IGC_RXDEXT_STATERR_IPE 0x40000000
331 #define IGC_RXDEXT_STATERR_RXE 0x80000000
333 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
334 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000
335 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
336 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000
337 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
339 /* Header split receive */
340 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000
341 #define IGC_RFCTL_LEF 0x00040000
343 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
345 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */
346 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
347 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
348 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
349 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
351 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
352 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
353 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
355 #define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */
357 #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
358 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
360 /* Time Sync Interrupt Causes */
361 #define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
362 #define IGC_TSICR_TXTS BIT(1) /* Transmit Timestamp. */
363 #define IGC_TSICR_TT0 BIT(3) /* Target Time 0 Trigger. */
364 #define IGC_TSICR_TT1 BIT(4) /* Target Time 1 Trigger. */
365 #define IGC_TSICR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
366 #define IGC_TSICR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */
368 #define IGC_TSICR_INTERRUPTS IGC_TSICR_TXTS
370 #define IGC_FTQF_VF_BP 0x00008000
371 #define IGC_FTQF_1588_TIME_STAMP 0x08000000
372 #define IGC_FTQF_MASK 0xF0000000
373 #define IGC_FTQF_MASK_PROTO_BP 0x10000000
375 /* Time Sync Receive Control bit definitions */
376 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
377 #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00
378 #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02
379 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
380 #define IGC_TSYNCRXCTL_TYPE_ALL 0x08
381 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
382 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
383 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
384 #define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 /* Sample RX tstamp in PHY sop */
386 /* Time Sync Receive Configuration */
387 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
388 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
389 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
391 /* Immediate Interrupt Receive */
392 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
393 #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
394 #define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
395 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
397 /* Immediate Interrupt Receive Extended */
398 #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
399 #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
401 /* Time Sync Transmit Control bit definitions */
402 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
403 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
404 #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
405 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
406 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
407 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
408 #define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */
410 /* Transmit Scheduling */
411 #define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
412 #define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008
414 #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
415 #define IGC_TXQCTL_STRICT_CYCLE 0x00000002
416 #define IGC_TXQCTL_STRICT_END 0x00000004
418 /* Receive Checksum Control */
419 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
420 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
422 /* GPY211 - I225 defines */
423 #define GPY_MMD_MASK 0xFFFF0000
424 #define GPY_MMD_SHIFT 16
425 #define GPY_REG_MASK 0x0000FFFF
427 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
429 /* MAC definitions */
430 #define IGC_FACTPS_MNGCG 0x20000000
431 #define IGC_FWSM_MODE_MASK 0xE
432 #define IGC_FWSM_MODE_SHIFT 1
434 /* Management Control */
435 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
436 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
439 #define PHY_REVISION_MASK 0xFFFFFFF0
440 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
441 #define IGC_GEN_POLL_TIMEOUT 1920
443 /* PHY Control Register */
444 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
445 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
446 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
447 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
448 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
449 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
450 #define MII_CR_SPEED_1000 0x0040
451 #define MII_CR_SPEED_100 0x2000
452 #define MII_CR_SPEED_10 0x0000
454 /* PHY Status Register */
455 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
456 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
457 #define IGC_PHY_RST_COMP 0x0100 /* Internal PHY reset completion */
459 /* PHY 1000 MII Register/Bit Definitions */
460 /* PHY Registers defined by IEEE */
461 #define PHY_CONTROL 0x00 /* Control Register */
462 #define PHY_STATUS 0x01 /* Status Register */
463 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
464 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
465 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
466 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
467 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
468 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
470 /* Bit definitions for valid PHY IDs. I = Integrated E = External */
471 #define I225_I_PHY_ID 0x67C9DC00
474 #define IGC_MDIC_DATA_MASK 0x0000FFFF
475 #define IGC_MDIC_REG_MASK 0x001F0000
476 #define IGC_MDIC_REG_SHIFT 16
477 #define IGC_MDIC_PHY_MASK 0x03E00000
478 #define IGC_MDIC_PHY_SHIFT 21
479 #define IGC_MDIC_OP_WRITE 0x04000000
480 #define IGC_MDIC_OP_READ 0x08000000
481 #define IGC_MDIC_READY 0x10000000
482 #define IGC_MDIC_INT_EN 0x20000000
483 #define IGC_MDIC_ERROR 0x40000000
485 #define IGC_N0_QUEUE -1
487 #define IGC_MAX_MAC_HDR_LEN 127
488 #define IGC_MAX_NETWORK_HDR_LEN 511
490 #define IGC_VLANPQF_QSEL(_n, q_idx) ((q_idx) << ((_n) * 4))
491 #define IGC_VLANPQF_VALID(_n) (0x1 << (3 + (_n) * 4))
492 #define IGC_VLANPQF_QUEUE_MASK 0x03
494 #define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
495 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */
496 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet Type of TCP */
497 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
499 /* Maximum size of the MTA register table in all supported adapters */
500 #define MAX_MTA_REG 128
503 #define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */
504 #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
505 #define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
506 #define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
507 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
508 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
509 #define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
510 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
513 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
514 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */
515 #define IGC_TW_SYSTEM_1000_MASK 0x000000FF
516 /* Minimum time for 100BASE-T where no data will be transmit following move out
517 * of EEE LPI Tx state
519 #define IGC_TW_SYSTEM_100_MASK 0x0000FF00
520 #define IGC_TW_SYSTEM_100_SHIFT 8
521 #define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
522 #define IGC_DMACR_DMACTHR_MASK 0x00FF0000
523 #define IGC_DMACR_DMACTHR_SHIFT 16
524 /* Reg val to set scale to 1024 nsec */
525 #define IGC_LTRMINV_SCALE_1024 2
526 /* Reg val to set scale to 32768 nsec */
527 #define IGC_LTRMINV_SCALE_32768 3
528 /* Reg val to set scale to 1024 nsec */
529 #define IGC_LTRMAXV_SCALE_1024 2
530 /* Reg val to set scale to 32768 nsec */
531 #define IGC_LTRMAXV_SCALE_32768 3
532 #define IGC_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */
533 #define IGC_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */
534 #define IGC_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
535 #define IGC_LTRMINV_SCALE_SHIFT 10
536 #define IGC_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
537 #define IGC_LTRMAXV_SCALE_SHIFT 10
539 #endif /* _IGC_DEFINES_H_ */