1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
69 * SYSTIM is converted to real time using a timecounter. As
70 * timecounter_cyc2time() allows old timestamps, the timecounter
71 * needs to be updated at least once per half of the SYSTIM interval.
72 * Scheduling of delayed work is not very accurate, so we aim for 8
73 * minutes to be sure the actual interval is shorter than 9.16 minutes.
76 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 8)
77 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
78 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
79 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
80 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
81 #define IGB_NBITS_82580 40
83 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
85 /* SYSTIM read access for the 82576 */
86 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
88 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
89 struct e1000_hw *hw = &igb->hw;
93 lo = rd32(E1000_SYSTIML);
94 hi = rd32(E1000_SYSTIMH);
96 val = ((u64) hi) << 32;
102 /* SYSTIM read access for the 82580 */
103 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
105 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
106 struct e1000_hw *hw = &igb->hw;
110 /* The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
115 lo = rd32(E1000_SYSTIML);
116 hi = rd32(E1000_SYSTIMH);
118 val = ((u64) hi) << 32;
124 /* SYSTIM read access for I210/I211 */
125 static void igb_ptp_read_i210(struct igb_adapter *adapter,
126 struct timespec64 *ts)
128 struct e1000_hw *hw = &adapter->hw;
131 /* The timestamp latches on lowest register read. For I210/I211, the
132 * lowest register is SYSTIMR. Since we only need to provide nanosecond
133 * resolution, we can ignore it.
136 nsec = rd32(E1000_SYSTIML);
137 sec = rd32(E1000_SYSTIMH);
143 static void igb_ptp_write_i210(struct igb_adapter *adapter,
144 const struct timespec64 *ts)
146 struct e1000_hw *hw = &adapter->hw;
148 /* Writing the SYSTIMR register is not necessary as it only provides
149 * sub-nanosecond resolution.
151 wr32(E1000_SYSTIML, ts->tv_nsec);
152 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
156 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
157 * @adapter: board private structure
158 * @hwtstamps: timestamp structure to update
159 * @systim: unsigned 64bit system time value.
161 * We need to convert the system time value stored in the RX/TXSTMP registers
162 * into a hwtstamp which can be used by the upper level timestamping functions.
164 * The 'tmreg_lock' spinlock is used to protect the consistency of the
165 * system time value. This is needed because reading the 64 bit time
166 * value involves reading two (or three) 32 bit registers. The first
167 * read latches the value. Ditto for writing.
169 * In addition, here have extended the system time with an overflow
170 * counter in software.
172 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
173 struct skb_shared_hwtstamps *hwtstamps,
179 switch (adapter->hw.mac.type) {
184 spin_lock_irqsave(&adapter->tmreg_lock, flags);
186 ns = timecounter_cyc2time(&adapter->tc, systim);
188 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
190 memset(hwtstamps, 0, sizeof(*hwtstamps));
191 hwtstamps->hwtstamp = ns_to_ktime(ns);
195 memset(hwtstamps, 0, sizeof(*hwtstamps));
196 /* Upper 32 bits contain s, lower 32 bits contain ns. */
197 hwtstamps->hwtstamp = ktime_set(systim >> 32,
198 systim & 0xFFFFFFFF);
205 /* PTP clock operations */
206 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
208 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
210 struct e1000_hw *hw = &igb->hw;
221 rate = div_u64(rate, 1953125);
223 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
230 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
235 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
237 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
239 struct e1000_hw *hw = &igb->hw;
250 rate = div_u64(rate, 1953125);
252 inca = rate & INCVALUE_MASK;
256 wr32(E1000_TIMINCA, inca);
261 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
263 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
267 spin_lock_irqsave(&igb->tmreg_lock, flags);
268 timecounter_adjtime(&igb->tc, delta);
269 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
274 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
276 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
279 struct timespec64 now, then = ns_to_timespec64(delta);
281 spin_lock_irqsave(&igb->tmreg_lock, flags);
283 igb_ptp_read_i210(igb, &now);
284 now = timespec64_add(now, then);
285 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
287 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
292 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
293 struct timespec64 *ts)
295 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
300 spin_lock_irqsave(&igb->tmreg_lock, flags);
302 ns = timecounter_read(&igb->tc);
304 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
306 *ts = ns_to_timespec64(ns);
311 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
312 struct timespec64 *ts)
314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
318 spin_lock_irqsave(&igb->tmreg_lock, flags);
320 igb_ptp_read_i210(igb, ts);
322 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
327 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
328 const struct timespec64 *ts)
330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
335 ns = timespec64_to_ns(ts);
337 spin_lock_irqsave(&igb->tmreg_lock, flags);
339 timecounter_init(&igb->tc, &igb->cc, ns);
341 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
346 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
347 const struct timespec64 *ts)
349 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
353 spin_lock_irqsave(&igb->tmreg_lock, flags);
355 igb_ptp_write_i210(igb, ts);
357 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
362 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
364 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
365 static const u32 mask[IGB_N_SDP] = {
368 E1000_CTRL_EXT_SDP2_DIR,
369 E1000_CTRL_EXT_SDP3_DIR,
378 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
380 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
381 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
383 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
384 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
386 static const u32 ts_sdp_en[IGB_N_SDP] = {
387 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
389 struct e1000_hw *hw = &igb->hw;
390 u32 ctrl, ctrl_ext, tssdp = 0;
392 ctrl = rd32(E1000_CTRL);
393 ctrl_ext = rd32(E1000_CTRL_EXT);
394 tssdp = rd32(E1000_TSSDP);
396 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
398 /* Make sure this pin is not enabled as an output. */
399 tssdp &= ~ts_sdp_en[pin];
402 tssdp &= ~AUX1_SEL_SDP3;
403 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
405 tssdp &= ~AUX0_SEL_SDP3;
406 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
409 wr32(E1000_TSSDP, tssdp);
410 wr32(E1000_CTRL, ctrl);
411 wr32(E1000_CTRL_EXT, ctrl_ext);
414 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
416 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
417 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
419 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
420 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
422 static const u32 ts_sdp_en[IGB_N_SDP] = {
423 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
425 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
426 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
427 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
429 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
430 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
431 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
433 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
434 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
435 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
437 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
438 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
439 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
441 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
442 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
443 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
445 struct e1000_hw *hw = &igb->hw;
446 u32 ctrl, ctrl_ext, tssdp = 0;
448 ctrl = rd32(E1000_CTRL);
449 ctrl_ext = rd32(E1000_CTRL_EXT);
450 tssdp = rd32(E1000_TSSDP);
452 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
454 /* Make sure this pin is not enabled as an input. */
455 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
456 tssdp &= ~AUX0_TS_SDP_EN;
458 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
459 tssdp &= ~AUX1_TS_SDP_EN;
461 tssdp &= ~ts_sdp_sel_clr[pin];
464 tssdp |= ts_sdp_sel_fc1[pin];
466 tssdp |= ts_sdp_sel_fc0[pin];
469 tssdp |= ts_sdp_sel_tt1[pin];
471 tssdp |= ts_sdp_sel_tt0[pin];
473 tssdp |= ts_sdp_en[pin];
475 wr32(E1000_TSSDP, tssdp);
476 wr32(E1000_CTRL, ctrl);
477 wr32(E1000_CTRL_EXT, ctrl_ext);
480 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
481 struct ptp_clock_request *rq, int on)
483 struct igb_adapter *igb =
484 container_of(ptp, struct igb_adapter, ptp_caps);
485 struct e1000_hw *hw = &igb->hw;
486 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
488 struct timespec64 ts;
489 int use_freq = 0, pin = -1;
493 case PTP_CLK_REQ_EXTTS:
495 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
500 if (rq->extts.index == 1) {
501 tsauxc_mask = TSAUXC_EN_TS1;
502 tsim_mask = TSINTR_AUTT1;
504 tsauxc_mask = TSAUXC_EN_TS0;
505 tsim_mask = TSINTR_AUTT0;
507 spin_lock_irqsave(&igb->tmreg_lock, flags);
508 tsauxc = rd32(E1000_TSAUXC);
509 tsim = rd32(E1000_TSIM);
511 igb_pin_extts(igb, rq->extts.index, pin);
512 tsauxc |= tsauxc_mask;
515 tsauxc &= ~tsauxc_mask;
518 wr32(E1000_TSAUXC, tsauxc);
519 wr32(E1000_TSIM, tsim);
520 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
523 case PTP_CLK_REQ_PEROUT:
525 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
530 ts.tv_sec = rq->perout.period.sec;
531 ts.tv_nsec = rq->perout.period.nsec;
532 ns = timespec64_to_ns(&ts);
534 if (on && ns <= 70000000LL) {
539 ts = ns_to_timespec64(ns);
540 if (rq->perout.index == 1) {
542 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
545 tsauxc_mask = TSAUXC_EN_TT1;
546 tsim_mask = TSINTR_TT1;
548 trgttiml = E1000_TRGTTIML1;
549 trgttimh = E1000_TRGTTIMH1;
550 freqout = E1000_FREQOUT1;
553 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
556 tsauxc_mask = TSAUXC_EN_TT0;
557 tsim_mask = TSINTR_TT0;
559 trgttiml = E1000_TRGTTIML0;
560 trgttimh = E1000_TRGTTIMH0;
561 freqout = E1000_FREQOUT0;
563 spin_lock_irqsave(&igb->tmreg_lock, flags);
564 tsauxc = rd32(E1000_TSAUXC);
565 tsim = rd32(E1000_TSIM);
566 if (rq->perout.index == 1) {
567 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
570 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
574 int i = rq->perout.index;
575 igb_pin_perout(igb, i, pin, use_freq);
576 igb->perout[i].start.tv_sec = rq->perout.start.sec;
577 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
578 igb->perout[i].period.tv_sec = ts.tv_sec;
579 igb->perout[i].period.tv_nsec = ts.tv_nsec;
580 wr32(trgttimh, rq->perout.start.sec);
581 wr32(trgttiml, rq->perout.start.nsec);
584 tsauxc |= tsauxc_mask;
587 wr32(E1000_TSAUXC, tsauxc);
588 wr32(E1000_TSIM, tsim);
589 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
592 case PTP_CLK_REQ_PPS:
593 spin_lock_irqsave(&igb->tmreg_lock, flags);
594 tsim = rd32(E1000_TSIM);
596 tsim |= TSINTR_SYS_WRAP;
598 tsim &= ~TSINTR_SYS_WRAP;
599 wr32(E1000_TSIM, tsim);
600 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
607 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
608 struct ptp_clock_request *rq, int on)
613 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
614 enum ptp_pin_function func, unsigned int chan)
629 * @work: pointer to work struct
631 * This work function polls the TSYNCTXCTL valid bit to determine when a
632 * timestamp has been taken for the current stored skb.
634 static void igb_ptp_tx_work(struct work_struct *work)
636 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
638 struct e1000_hw *hw = &adapter->hw;
641 if (!adapter->ptp_tx_skb)
644 if (time_is_before_jiffies(adapter->ptp_tx_start +
645 IGB_PTP_TX_TIMEOUT)) {
646 dev_kfree_skb_any(adapter->ptp_tx_skb);
647 adapter->ptp_tx_skb = NULL;
648 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
649 adapter->tx_hwtstamp_timeouts++;
650 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
654 tsynctxctl = rd32(E1000_TSYNCTXCTL);
655 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
656 igb_ptp_tx_hwtstamp(adapter);
658 /* reschedule to check later */
659 schedule_work(&adapter->ptp_tx_work);
662 static void igb_ptp_overflow_check(struct work_struct *work)
664 struct igb_adapter *igb =
665 container_of(work, struct igb_adapter, ptp_overflow_work.work);
666 struct timespec64 ts;
668 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
670 pr_debug("igb overflow check at %lld.%09lu\n",
671 (long long) ts.tv_sec, ts.tv_nsec);
673 schedule_delayed_work(&igb->ptp_overflow_work,
674 IGB_SYSTIM_OVERFLOW_PERIOD);
678 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
679 * @adapter: private network adapter structure
681 * This watchdog task is scheduled to detect error case where hardware has
682 * dropped an Rx packet that was timestamped when the ring is full. The
683 * particular error is rare but leaves the device in a state unable to timestamp
684 * any future packets.
686 void igb_ptp_rx_hang(struct igb_adapter *adapter)
688 struct e1000_hw *hw = &adapter->hw;
689 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
690 unsigned long rx_event;
692 if (hw->mac.type != e1000_82576)
695 /* If we don't have a valid timestamp in the registers, just update the
696 * timeout counter and exit
698 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
699 adapter->last_rx_ptp_check = jiffies;
703 /* Determine the most recent watchdog or rx_timestamp event */
704 rx_event = adapter->last_rx_ptp_check;
705 if (time_after(adapter->last_rx_timestamp, rx_event))
706 rx_event = adapter->last_rx_timestamp;
708 /* Only need to read the high RXSTMP register to clear the lock */
709 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
711 adapter->last_rx_ptp_check = jiffies;
712 adapter->rx_hwtstamp_cleared++;
713 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
718 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
719 * @adapter: Board private structure.
721 * If we were asked to do hardware stamping and such a time stamp is
722 * available, then it must have been for this skb here because we only
723 * allow only one such packet into the queue.
725 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
727 struct e1000_hw *hw = &adapter->hw;
728 struct skb_shared_hwtstamps shhwtstamps;
731 regval = rd32(E1000_TXSTMPL);
732 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
734 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
735 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
736 dev_kfree_skb_any(adapter->ptp_tx_skb);
737 adapter->ptp_tx_skb = NULL;
738 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
742 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
743 * @q_vector: Pointer to interrupt specific structure
744 * @va: Pointer to address containing Rx buffer
745 * @skb: Buffer containing timestamp and packet
747 * This function is meant to retrieve a timestamp from the first buffer of an
748 * incoming frame. The value is stored in little endian format starting on
751 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
755 __le64 *regval = (__le64 *)va;
757 /* The timestamp is recorded in little endian format.
759 * Field: Reserved Reserved SYSTIML SYSTIMH
761 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
762 le64_to_cpu(regval[1]));
766 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
767 * @q_vector: Pointer to interrupt specific structure
768 * @skb: Buffer containing timestamp and packet
770 * This function is meant to retrieve a timestamp from the internal registers
771 * of the adapter and store it in the skb.
773 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
776 struct igb_adapter *adapter = q_vector->adapter;
777 struct e1000_hw *hw = &adapter->hw;
780 /* If this bit is set, then the RX registers contain the time stamp. No
781 * other packet will be time stamped until we read these registers, so
782 * read the registers to make them available again. Because only one
783 * packet can be time stamped at a time, we know that the register
784 * values must belong to this one here and therefore we don't need to
785 * compare any of the additional attributes stored for it.
787 * If nothing went wrong, then it should have a shared tx_flags that we
788 * can turn into a skb_shared_hwtstamps.
790 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
793 regval = rd32(E1000_RXSTMPL);
794 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
796 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
798 /* Update the last_rx_timestamp timer in order to enable watchdog check
799 * for error case of latched timestamp on a dropped packet.
801 adapter->last_rx_timestamp = jiffies;
805 * igb_ptp_get_ts_config - get hardware time stamping config
809 * Get the hwtstamp_config settings to return to the user. Rather than attempt
810 * to deconstruct the settings from the registers, just return a shadow copy
811 * of the last known settings.
813 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
815 struct igb_adapter *adapter = netdev_priv(netdev);
816 struct hwtstamp_config *config = &adapter->tstamp_config;
818 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
823 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
824 * @adapter: networking device structure
825 * @config: hwtstamp configuration
827 * Outgoing time stamping can be enabled and disabled. Play nice and
828 * disable it when requested, although it shouldn't case any overhead
829 * when no packet needs it. At most one packet in the queue may be
830 * marked for time stamping, otherwise it would be impossible to tell
831 * for sure to which packet the hardware time stamp belongs.
833 * Incoming time stamping has to be configured via the hardware
834 * filters. Not all combinations are supported, in particular event
835 * type has to be specified. Matching the kind of event packet is
836 * not supported, with the exception of "all V2 events regardless of
839 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
840 struct hwtstamp_config *config)
842 struct e1000_hw *hw = &adapter->hw;
843 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
844 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
845 u32 tsync_rx_cfg = 0;
850 /* reserved for future extensions */
854 switch (config->tx_type) {
855 case HWTSTAMP_TX_OFF:
863 switch (config->rx_filter) {
864 case HWTSTAMP_FILTER_NONE:
867 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
868 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
869 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
872 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
873 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
874 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
877 case HWTSTAMP_FILTER_PTP_V2_EVENT:
878 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
879 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
880 case HWTSTAMP_FILTER_PTP_V2_SYNC:
881 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
882 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
883 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
884 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
885 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
886 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
887 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
891 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
892 case HWTSTAMP_FILTER_ALL:
893 /* 82576 cannot timestamp all packets, which it needs to do to
894 * support both V1 Sync and Delay_Req messages
896 if (hw->mac.type != e1000_82576) {
897 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
898 config->rx_filter = HWTSTAMP_FILTER_ALL;
903 config->rx_filter = HWTSTAMP_FILTER_NONE;
907 if (hw->mac.type == e1000_82575) {
908 if (tsync_rx_ctl | tsync_tx_ctl)
913 /* Per-packet timestamping only works if all packets are
914 * timestamped, so enable timestamping in all packets as
915 * long as one Rx filter was configured.
917 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
918 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
919 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
920 config->rx_filter = HWTSTAMP_FILTER_ALL;
924 if ((hw->mac.type == e1000_i210) ||
925 (hw->mac.type == e1000_i211)) {
926 regval = rd32(E1000_RXPBS);
927 regval |= E1000_RXPBS_CFG_TS_EN;
928 wr32(E1000_RXPBS, regval);
932 /* enable/disable TX */
933 regval = rd32(E1000_TSYNCTXCTL);
934 regval &= ~E1000_TSYNCTXCTL_ENABLED;
935 regval |= tsync_tx_ctl;
936 wr32(E1000_TSYNCTXCTL, regval);
938 /* enable/disable RX */
939 regval = rd32(E1000_TSYNCRXCTL);
940 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
941 regval |= tsync_rx_ctl;
942 wr32(E1000_TSYNCRXCTL, regval);
944 /* define which PTP packets are time stamped */
945 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
947 /* define ethertype filter for timestamped packets */
950 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
951 E1000_ETQF_1588 | /* enable timestamping */
952 ETH_P_1588)); /* 1588 eth protocol type */
954 wr32(E1000_ETQF(3), 0);
956 /* L4 Queue Filter[3]: filter by destination port and protocol */
958 u32 ftqf = (IPPROTO_UDP /* UDP */
959 | E1000_FTQF_VF_BP /* VF not compared */
960 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
961 | E1000_FTQF_MASK); /* mask all inputs */
962 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
964 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
965 wr32(E1000_IMIREXT(3),
966 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
967 if (hw->mac.type == e1000_82576) {
968 /* enable source port check */
969 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
970 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
972 wr32(E1000_FTQF(3), ftqf);
974 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
978 /* clear TX/RX time stamp registers, just to be sure */
979 regval = rd32(E1000_TXSTMPL);
980 regval = rd32(E1000_TXSTMPH);
981 regval = rd32(E1000_RXSTMPL);
982 regval = rd32(E1000_RXSTMPH);
988 * igb_ptp_set_ts_config - set hardware time stamping config
993 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
995 struct igb_adapter *adapter = netdev_priv(netdev);
996 struct hwtstamp_config config;
999 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1002 err = igb_ptp_set_timestamp_mode(adapter, &config);
1006 /* save these settings for future reference */
1007 memcpy(&adapter->tstamp_config, &config,
1008 sizeof(adapter->tstamp_config));
1010 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1014 void igb_ptp_init(struct igb_adapter *adapter)
1016 struct e1000_hw *hw = &adapter->hw;
1017 struct net_device *netdev = adapter->netdev;
1020 switch (hw->mac.type) {
1022 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1023 adapter->ptp_caps.owner = THIS_MODULE;
1024 adapter->ptp_caps.max_adj = 999999881;
1025 adapter->ptp_caps.n_ext_ts = 0;
1026 adapter->ptp_caps.pps = 0;
1027 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1028 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1029 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1030 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1031 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1032 adapter->cc.read = igb_ptp_read_82576;
1033 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1034 adapter->cc.mult = 1;
1035 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1036 /* Dial the nominal frequency. */
1037 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1042 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1043 adapter->ptp_caps.owner = THIS_MODULE;
1044 adapter->ptp_caps.max_adj = 62499999;
1045 adapter->ptp_caps.n_ext_ts = 0;
1046 adapter->ptp_caps.pps = 0;
1047 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1048 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1049 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1050 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1051 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1052 adapter->cc.read = igb_ptp_read_82580;
1053 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1054 adapter->cc.mult = 1;
1055 adapter->cc.shift = 0;
1056 /* Enable the timer functions by clearing bit 31. */
1057 wr32(E1000_TSAUXC, 0x0);
1061 for (i = 0; i < IGB_N_SDP; i++) {
1062 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1064 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1066 ppd->func = PTP_PF_NONE;
1068 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1069 adapter->ptp_caps.owner = THIS_MODULE;
1070 adapter->ptp_caps.max_adj = 62499999;
1071 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1072 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1073 adapter->ptp_caps.n_pins = IGB_N_SDP;
1074 adapter->ptp_caps.pps = 1;
1075 adapter->ptp_caps.pin_config = adapter->sdp_config;
1076 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1077 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1078 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1079 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1080 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1081 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1082 /* Enable the timer functions by clearing bit 31. */
1083 wr32(E1000_TSAUXC, 0x0);
1086 adapter->ptp_clock = NULL;
1092 spin_lock_init(&adapter->tmreg_lock);
1093 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1095 /* Initialize the clock and overflow work for devices that need it. */
1096 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1097 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1099 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
1101 timecounter_init(&adapter->tc, &adapter->cc,
1102 ktime_to_ns(ktime_get_real()));
1104 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1105 igb_ptp_overflow_check);
1107 schedule_delayed_work(&adapter->ptp_overflow_work,
1108 IGB_SYSTIM_OVERFLOW_PERIOD);
1111 /* Initialize the time sync interrupts for devices that support it. */
1112 if (hw->mac.type >= e1000_82580) {
1113 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1114 wr32(E1000_IMS, E1000_IMS_TS);
1117 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1118 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1120 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1121 &adapter->pdev->dev);
1122 if (IS_ERR(adapter->ptp_clock)) {
1123 adapter->ptp_clock = NULL;
1124 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1126 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1127 adapter->netdev->name);
1128 adapter->flags |= IGB_FLAG_PTP;
1133 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1134 * @adapter: Board private structure.
1136 * This function stops the PTP support and cancels the delayed work.
1138 void igb_ptp_stop(struct igb_adapter *adapter)
1140 switch (adapter->hw.mac.type) {
1145 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1149 /* No delayed work to cancel. */
1155 cancel_work_sync(&adapter->ptp_tx_work);
1156 if (adapter->ptp_tx_skb) {
1157 dev_kfree_skb_any(adapter->ptp_tx_skb);
1158 adapter->ptp_tx_skb = NULL;
1159 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1162 if (adapter->ptp_clock) {
1163 ptp_clock_unregister(adapter->ptp_clock);
1164 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1165 adapter->netdev->name);
1166 adapter->flags &= ~IGB_FLAG_PTP;
1171 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1172 * @adapter: Board private structure.
1174 * This function handles the reset work required to re-enable the PTP device.
1176 void igb_ptp_reset(struct igb_adapter *adapter)
1178 struct e1000_hw *hw = &adapter->hw;
1179 unsigned long flags;
1181 if (!(adapter->flags & IGB_FLAG_PTP))
1184 /* reset the tstamp_config */
1185 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1187 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1189 switch (adapter->hw.mac.type) {
1191 /* Dial the nominal frequency. */
1192 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1199 wr32(E1000_TSAUXC, 0x0);
1200 wr32(E1000_TSSDP, 0x0);
1201 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1202 wr32(E1000_IMS, E1000_IMS_TS);
1205 /* No work to do. */
1209 /* Re-initialize the timer. */
1210 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1211 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1213 igb_ptp_write_i210(adapter, &ts);
1215 timecounter_init(&adapter->tc, &adapter->cc,
1216 ktime_to_ns(ktime_get_real()));
1219 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);