1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
69 * SYSTIM is converted to real time using a timecounter. As
70 * timecounter_cyc2time() allows old timestamps, the timecounter
71 * needs to be updated at least once per half of the SYSTIM interval.
72 * Scheduling of delayed work is not very accurate, so we aim for 8
73 * minutes to be sure the actual interval is shorter than 9.16 minutes.
76 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 8)
77 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
78 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
79 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
80 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
81 #define IGB_NBITS_82580 40
83 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
85 /* SYSTIM read access for the 82576 */
86 static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
88 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
89 struct e1000_hw *hw = &igb->hw;
93 lo = rd32(E1000_SYSTIML);
94 hi = rd32(E1000_SYSTIMH);
96 val = ((u64) hi) << 32;
102 /* SYSTIM read access for the 82580 */
103 static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
105 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
106 struct e1000_hw *hw = &igb->hw;
110 /* The timestamp latches on lowest register read. For the 82580
111 * the lowest register is SYSTIMR instead of SYSTIML. However we only
112 * need to provide nanosecond resolution, so we just ignore it.
115 lo = rd32(E1000_SYSTIML);
116 hi = rd32(E1000_SYSTIMH);
118 val = ((u64) hi) << 32;
124 /* SYSTIM read access for I210/I211 */
125 static void igb_ptp_read_i210(struct igb_adapter *adapter,
126 struct timespec64 *ts)
128 struct e1000_hw *hw = &adapter->hw;
131 /* The timestamp latches on lowest register read. For I210/I211, the
132 * lowest register is SYSTIMR. Since we only need to provide nanosecond
133 * resolution, we can ignore it.
136 nsec = rd32(E1000_SYSTIML);
137 sec = rd32(E1000_SYSTIMH);
143 static void igb_ptp_write_i210(struct igb_adapter *adapter,
144 const struct timespec64 *ts)
146 struct e1000_hw *hw = &adapter->hw;
148 /* Writing the SYSTIMR register is not necessary as it only provides
149 * sub-nanosecond resolution.
151 wr32(E1000_SYSTIML, ts->tv_nsec);
152 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
156 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
157 * @adapter: board private structure
158 * @hwtstamps: timestamp structure to update
159 * @systim: unsigned 64bit system time value.
161 * We need to convert the system time value stored in the RX/TXSTMP registers
162 * into a hwtstamp which can be used by the upper level timestamping functions.
164 * The 'tmreg_lock' spinlock is used to protect the consistency of the
165 * system time value. This is needed because reading the 64 bit time
166 * value involves reading two (or three) 32 bit registers. The first
167 * read latches the value. Ditto for writing.
169 * In addition, here have extended the system time with an overflow
170 * counter in software.
172 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
173 struct skb_shared_hwtstamps *hwtstamps,
179 switch (adapter->hw.mac.type) {
184 spin_lock_irqsave(&adapter->tmreg_lock, flags);
186 ns = timecounter_cyc2time(&adapter->tc, systim);
188 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
190 memset(hwtstamps, 0, sizeof(*hwtstamps));
191 hwtstamps->hwtstamp = ns_to_ktime(ns);
195 memset(hwtstamps, 0, sizeof(*hwtstamps));
196 /* Upper 32 bits contain s, lower 32 bits contain ns. */
197 hwtstamps->hwtstamp = ktime_set(systim >> 32,
198 systim & 0xFFFFFFFF);
205 /* PTP clock operations */
206 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
208 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
210 struct e1000_hw *hw = &igb->hw;
221 rate = div_u64(rate, 1953125);
223 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
230 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
235 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
237 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
239 struct e1000_hw *hw = &igb->hw;
244 if (scaled_ppm < 0) {
246 scaled_ppm = -scaled_ppm;
250 rate = div_u64(rate, 15625);
252 inca = rate & INCVALUE_MASK;
256 wr32(E1000_TIMINCA, inca);
261 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
263 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
267 spin_lock_irqsave(&igb->tmreg_lock, flags);
268 timecounter_adjtime(&igb->tc, delta);
269 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
274 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
276 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
279 struct timespec64 now, then = ns_to_timespec64(delta);
281 spin_lock_irqsave(&igb->tmreg_lock, flags);
283 igb_ptp_read_i210(igb, &now);
284 now = timespec64_add(now, then);
285 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
287 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
292 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
293 struct timespec64 *ts)
295 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
300 spin_lock_irqsave(&igb->tmreg_lock, flags);
302 ns = timecounter_read(&igb->tc);
304 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
306 *ts = ns_to_timespec64(ns);
311 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
312 struct timespec64 *ts)
314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
318 spin_lock_irqsave(&igb->tmreg_lock, flags);
320 igb_ptp_read_i210(igb, ts);
322 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
327 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
328 const struct timespec64 *ts)
330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
335 ns = timespec64_to_ns(ts);
337 spin_lock_irqsave(&igb->tmreg_lock, flags);
339 timecounter_init(&igb->tc, &igb->cc, ns);
341 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
346 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
347 const struct timespec64 *ts)
349 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
353 spin_lock_irqsave(&igb->tmreg_lock, flags);
355 igb_ptp_write_i210(igb, ts);
357 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
362 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
364 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
365 static const u32 mask[IGB_N_SDP] = {
368 E1000_CTRL_EXT_SDP2_DIR,
369 E1000_CTRL_EXT_SDP3_DIR,
378 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
380 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
381 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
383 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
384 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
386 static const u32 ts_sdp_en[IGB_N_SDP] = {
387 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
389 struct e1000_hw *hw = &igb->hw;
390 u32 ctrl, ctrl_ext, tssdp = 0;
392 ctrl = rd32(E1000_CTRL);
393 ctrl_ext = rd32(E1000_CTRL_EXT);
394 tssdp = rd32(E1000_TSSDP);
396 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
398 /* Make sure this pin is not enabled as an output. */
399 tssdp &= ~ts_sdp_en[pin];
402 tssdp &= ~AUX1_SEL_SDP3;
403 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
405 tssdp &= ~AUX0_SEL_SDP3;
406 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
409 wr32(E1000_TSSDP, tssdp);
410 wr32(E1000_CTRL, ctrl);
411 wr32(E1000_CTRL_EXT, ctrl_ext);
414 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
416 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
417 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
419 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
420 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
422 static const u32 ts_sdp_en[IGB_N_SDP] = {
423 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
425 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
426 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
427 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
429 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
430 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
431 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
433 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
434 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
435 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
437 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
438 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
439 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
441 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
442 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
443 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
445 struct e1000_hw *hw = &igb->hw;
446 u32 ctrl, ctrl_ext, tssdp = 0;
448 ctrl = rd32(E1000_CTRL);
449 ctrl_ext = rd32(E1000_CTRL_EXT);
450 tssdp = rd32(E1000_TSSDP);
452 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
454 /* Make sure this pin is not enabled as an input. */
455 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
456 tssdp &= ~AUX0_TS_SDP_EN;
458 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
459 tssdp &= ~AUX1_TS_SDP_EN;
461 tssdp &= ~ts_sdp_sel_clr[pin];
464 tssdp |= ts_sdp_sel_fc1[pin];
466 tssdp |= ts_sdp_sel_fc0[pin];
469 tssdp |= ts_sdp_sel_tt1[pin];
471 tssdp |= ts_sdp_sel_tt0[pin];
473 tssdp |= ts_sdp_en[pin];
475 wr32(E1000_TSSDP, tssdp);
476 wr32(E1000_CTRL, ctrl);
477 wr32(E1000_CTRL_EXT, ctrl_ext);
480 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
481 struct ptp_clock_request *rq, int on)
483 struct igb_adapter *igb =
484 container_of(ptp, struct igb_adapter, ptp_caps);
485 struct e1000_hw *hw = &igb->hw;
486 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
488 struct timespec64 ts;
489 int use_freq = 0, pin = -1;
493 case PTP_CLK_REQ_EXTTS:
495 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
500 if (rq->extts.index == 1) {
501 tsauxc_mask = TSAUXC_EN_TS1;
502 tsim_mask = TSINTR_AUTT1;
504 tsauxc_mask = TSAUXC_EN_TS0;
505 tsim_mask = TSINTR_AUTT0;
507 spin_lock_irqsave(&igb->tmreg_lock, flags);
508 tsauxc = rd32(E1000_TSAUXC);
509 tsim = rd32(E1000_TSIM);
511 igb_pin_extts(igb, rq->extts.index, pin);
512 tsauxc |= tsauxc_mask;
515 tsauxc &= ~tsauxc_mask;
518 wr32(E1000_TSAUXC, tsauxc);
519 wr32(E1000_TSIM, tsim);
520 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
523 case PTP_CLK_REQ_PEROUT:
525 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
530 ts.tv_sec = rq->perout.period.sec;
531 ts.tv_nsec = rq->perout.period.nsec;
532 ns = timespec64_to_ns(&ts);
534 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
535 (ns == 250000000LL) || (ns == 500000000LL))) {
540 ts = ns_to_timespec64(ns);
541 if (rq->perout.index == 1) {
543 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
546 tsauxc_mask = TSAUXC_EN_TT1;
547 tsim_mask = TSINTR_TT1;
549 trgttiml = E1000_TRGTTIML1;
550 trgttimh = E1000_TRGTTIMH1;
551 freqout = E1000_FREQOUT1;
554 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
557 tsauxc_mask = TSAUXC_EN_TT0;
558 tsim_mask = TSINTR_TT0;
560 trgttiml = E1000_TRGTTIML0;
561 trgttimh = E1000_TRGTTIMH0;
562 freqout = E1000_FREQOUT0;
564 spin_lock_irqsave(&igb->tmreg_lock, flags);
565 tsauxc = rd32(E1000_TSAUXC);
566 tsim = rd32(E1000_TSIM);
567 if (rq->perout.index == 1) {
568 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
571 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
575 int i = rq->perout.index;
576 igb_pin_perout(igb, i, pin, use_freq);
577 igb->perout[i].start.tv_sec = rq->perout.start.sec;
578 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
579 igb->perout[i].period.tv_sec = ts.tv_sec;
580 igb->perout[i].period.tv_nsec = ts.tv_nsec;
581 wr32(trgttimh, rq->perout.start.sec);
582 wr32(trgttiml, rq->perout.start.nsec);
585 tsauxc |= tsauxc_mask;
588 wr32(E1000_TSAUXC, tsauxc);
589 wr32(E1000_TSIM, tsim);
590 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
593 case PTP_CLK_REQ_PPS:
594 spin_lock_irqsave(&igb->tmreg_lock, flags);
595 tsim = rd32(E1000_TSIM);
597 tsim |= TSINTR_SYS_WRAP;
599 tsim &= ~TSINTR_SYS_WRAP;
600 igb->pps_sys_wrap_on = !!on;
601 wr32(E1000_TSIM, tsim);
602 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
609 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
610 struct ptp_clock_request *rq, int on)
615 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
616 enum ptp_pin_function func, unsigned int chan)
631 * @work: pointer to work struct
633 * This work function polls the TSYNCTXCTL valid bit to determine when a
634 * timestamp has been taken for the current stored skb.
636 static void igb_ptp_tx_work(struct work_struct *work)
638 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
640 struct e1000_hw *hw = &adapter->hw;
643 if (!adapter->ptp_tx_skb)
646 if (time_is_before_jiffies(adapter->ptp_tx_start +
647 IGB_PTP_TX_TIMEOUT)) {
648 dev_kfree_skb_any(adapter->ptp_tx_skb);
649 adapter->ptp_tx_skb = NULL;
650 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
651 adapter->tx_hwtstamp_timeouts++;
652 /* Clear the tx valid bit in TSYNCTXCTL register to enable
656 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
660 tsynctxctl = rd32(E1000_TSYNCTXCTL);
661 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
662 igb_ptp_tx_hwtstamp(adapter);
664 /* reschedule to check later */
665 schedule_work(&adapter->ptp_tx_work);
668 static void igb_ptp_overflow_check(struct work_struct *work)
670 struct igb_adapter *igb =
671 container_of(work, struct igb_adapter, ptp_overflow_work.work);
672 struct timespec64 ts;
674 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
676 pr_debug("igb overflow check at %lld.%09lu\n",
677 (long long) ts.tv_sec, ts.tv_nsec);
679 schedule_delayed_work(&igb->ptp_overflow_work,
680 IGB_SYSTIM_OVERFLOW_PERIOD);
684 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
685 * @adapter: private network adapter structure
687 * This watchdog task is scheduled to detect error case where hardware has
688 * dropped an Rx packet that was timestamped when the ring is full. The
689 * particular error is rare but leaves the device in a state unable to timestamp
690 * any future packets.
692 void igb_ptp_rx_hang(struct igb_adapter *adapter)
694 struct e1000_hw *hw = &adapter->hw;
695 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
696 unsigned long rx_event;
698 /* Other hardware uses per-packet timestamps */
699 if (hw->mac.type != e1000_82576)
702 /* If we don't have a valid timestamp in the registers, just update the
703 * timeout counter and exit
705 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
706 adapter->last_rx_ptp_check = jiffies;
710 /* Determine the most recent watchdog or rx_timestamp event */
711 rx_event = adapter->last_rx_ptp_check;
712 if (time_after(adapter->last_rx_timestamp, rx_event))
713 rx_event = adapter->last_rx_timestamp;
715 /* Only need to read the high RXSTMP register to clear the lock */
716 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
718 adapter->last_rx_ptp_check = jiffies;
719 adapter->rx_hwtstamp_cleared++;
720 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
725 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
726 * @adapter: private network adapter structure
728 void igb_ptp_tx_hang(struct igb_adapter *adapter)
730 struct e1000_hw *hw = &adapter->hw;
731 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
734 if (!adapter->ptp_tx_skb)
737 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
740 /* If we haven't received a timestamp within the timeout, it is
741 * reasonable to assume that it will never occur, so we can unlock the
742 * timestamp bit when this occurs.
745 cancel_work_sync(&adapter->ptp_tx_work);
746 dev_kfree_skb_any(adapter->ptp_tx_skb);
747 adapter->ptp_tx_skb = NULL;
748 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
749 adapter->tx_hwtstamp_timeouts++;
750 /* Clear the tx valid bit in TSYNCTXCTL register to enable
754 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
759 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
760 * @adapter: Board private structure.
762 * If we were asked to do hardware stamping and such a time stamp is
763 * available, then it must have been for this skb here because we only
764 * allow only one such packet into the queue.
766 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
768 struct sk_buff *skb = adapter->ptp_tx_skb;
769 struct e1000_hw *hw = &adapter->hw;
770 struct skb_shared_hwtstamps shhwtstamps;
774 regval = rd32(E1000_TXSTMPL);
775 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
777 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
778 /* adjust timestamp for the TX latency based on link speed */
779 if (adapter->hw.mac.type == e1000_i210) {
780 switch (adapter->link_speed) {
782 adjust = IGB_I210_TX_LATENCY_10;
785 adjust = IGB_I210_TX_LATENCY_100;
788 adjust = IGB_I210_TX_LATENCY_1000;
793 shhwtstamps.hwtstamp =
794 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
796 /* Clear the lock early before calling skb_tstamp_tx so that
797 * applications are not woken up before the lock bit is clear. We use
798 * a copy of the skb pointer to ensure other threads can't change it
799 * while we're notifying the stack.
801 adapter->ptp_tx_skb = NULL;
802 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
804 /* Notify the stack and free the skb after we've unlocked */
805 skb_tstamp_tx(skb, &shhwtstamps);
806 dev_kfree_skb_any(skb);
810 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
811 * @q_vector: Pointer to interrupt specific structure
812 * @va: Pointer to address containing Rx buffer
813 * @skb: Buffer containing timestamp and packet
815 * This function is meant to retrieve a timestamp from the first buffer of an
816 * incoming frame. The value is stored in little endian format starting on
819 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
822 __le64 *regval = (__le64 *)va;
823 struct igb_adapter *adapter = q_vector->adapter;
826 /* The timestamp is recorded in little endian format.
828 * Field: Reserved Reserved SYSTIML SYSTIMH
830 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
831 le64_to_cpu(regval[1]));
833 /* adjust timestamp for the RX latency based on link speed */
834 if (adapter->hw.mac.type == e1000_i210) {
835 switch (adapter->link_speed) {
837 adjust = IGB_I210_RX_LATENCY_10;
840 adjust = IGB_I210_RX_LATENCY_100;
843 adjust = IGB_I210_RX_LATENCY_1000;
847 skb_hwtstamps(skb)->hwtstamp =
848 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
852 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
853 * @q_vector: Pointer to interrupt specific structure
854 * @skb: Buffer containing timestamp and packet
856 * This function is meant to retrieve a timestamp from the internal registers
857 * of the adapter and store it in the skb.
859 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
862 struct igb_adapter *adapter = q_vector->adapter;
863 struct e1000_hw *hw = &adapter->hw;
867 /* If this bit is set, then the RX registers contain the time stamp. No
868 * other packet will be time stamped until we read these registers, so
869 * read the registers to make them available again. Because only one
870 * packet can be time stamped at a time, we know that the register
871 * values must belong to this one here and therefore we don't need to
872 * compare any of the additional attributes stored for it.
874 * If nothing went wrong, then it should have a shared tx_flags that we
875 * can turn into a skb_shared_hwtstamps.
877 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
880 regval = rd32(E1000_RXSTMPL);
881 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
883 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
885 /* adjust timestamp for the RX latency based on link speed */
886 if (adapter->hw.mac.type == e1000_i210) {
887 switch (adapter->link_speed) {
889 adjust = IGB_I210_RX_LATENCY_10;
892 adjust = IGB_I210_RX_LATENCY_100;
895 adjust = IGB_I210_RX_LATENCY_1000;
899 skb_hwtstamps(skb)->hwtstamp =
900 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
902 /* Update the last_rx_timestamp timer in order to enable watchdog check
903 * for error case of latched timestamp on a dropped packet.
905 adapter->last_rx_timestamp = jiffies;
909 * igb_ptp_get_ts_config - get hardware time stamping config
913 * Get the hwtstamp_config settings to return to the user. Rather than attempt
914 * to deconstruct the settings from the registers, just return a shadow copy
915 * of the last known settings.
917 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
919 struct igb_adapter *adapter = netdev_priv(netdev);
920 struct hwtstamp_config *config = &adapter->tstamp_config;
922 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
927 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
928 * @adapter: networking device structure
929 * @config: hwtstamp configuration
931 * Outgoing time stamping can be enabled and disabled. Play nice and
932 * disable it when requested, although it shouldn't case any overhead
933 * when no packet needs it. At most one packet in the queue may be
934 * marked for time stamping, otherwise it would be impossible to tell
935 * for sure to which packet the hardware time stamp belongs.
937 * Incoming time stamping has to be configured via the hardware
938 * filters. Not all combinations are supported, in particular event
939 * type has to be specified. Matching the kind of event packet is
940 * not supported, with the exception of "all V2 events regardless of
943 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
944 struct hwtstamp_config *config)
946 struct e1000_hw *hw = &adapter->hw;
947 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
948 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
949 u32 tsync_rx_cfg = 0;
954 /* reserved for future extensions */
958 switch (config->tx_type) {
959 case HWTSTAMP_TX_OFF:
967 switch (config->rx_filter) {
968 case HWTSTAMP_FILTER_NONE:
971 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
972 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
973 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
976 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
977 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
978 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
981 case HWTSTAMP_FILTER_PTP_V2_EVENT:
982 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
983 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
984 case HWTSTAMP_FILTER_PTP_V2_SYNC:
985 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
986 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
987 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
988 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
989 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
990 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
991 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
995 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
996 case HWTSTAMP_FILTER_NTP_ALL:
997 case HWTSTAMP_FILTER_ALL:
998 /* 82576 cannot timestamp all packets, which it needs to do to
999 * support both V1 Sync and Delay_Req messages
1001 if (hw->mac.type != e1000_82576) {
1002 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1003 config->rx_filter = HWTSTAMP_FILTER_ALL;
1008 config->rx_filter = HWTSTAMP_FILTER_NONE;
1012 if (hw->mac.type == e1000_82575) {
1013 if (tsync_rx_ctl | tsync_tx_ctl)
1018 /* Per-packet timestamping only works if all packets are
1019 * timestamped, so enable timestamping in all packets as
1020 * long as one Rx filter was configured.
1022 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1023 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1024 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1025 config->rx_filter = HWTSTAMP_FILTER_ALL;
1029 if ((hw->mac.type == e1000_i210) ||
1030 (hw->mac.type == e1000_i211)) {
1031 regval = rd32(E1000_RXPBS);
1032 regval |= E1000_RXPBS_CFG_TS_EN;
1033 wr32(E1000_RXPBS, regval);
1037 /* enable/disable TX */
1038 regval = rd32(E1000_TSYNCTXCTL);
1039 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1040 regval |= tsync_tx_ctl;
1041 wr32(E1000_TSYNCTXCTL, regval);
1043 /* enable/disable RX */
1044 regval = rd32(E1000_TSYNCRXCTL);
1045 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1046 regval |= tsync_rx_ctl;
1047 wr32(E1000_TSYNCRXCTL, regval);
1049 /* define which PTP packets are time stamped */
1050 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1052 /* define ethertype filter for timestamped packets */
1054 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1055 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1056 E1000_ETQF_1588 | /* enable timestamping */
1057 ETH_P_1588)); /* 1588 eth protocol type */
1059 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1061 /* L4 Queue Filter[3]: filter by destination port and protocol */
1063 u32 ftqf = (IPPROTO_UDP /* UDP */
1064 | E1000_FTQF_VF_BP /* VF not compared */
1065 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1066 | E1000_FTQF_MASK); /* mask all inputs */
1067 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1069 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1070 wr32(E1000_IMIREXT(3),
1071 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1072 if (hw->mac.type == e1000_82576) {
1073 /* enable source port check */
1074 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1075 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1077 wr32(E1000_FTQF(3), ftqf);
1079 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1083 /* clear TX/RX time stamp registers, just to be sure */
1084 regval = rd32(E1000_TXSTMPL);
1085 regval = rd32(E1000_TXSTMPH);
1086 regval = rd32(E1000_RXSTMPL);
1087 regval = rd32(E1000_RXSTMPH);
1093 * igb_ptp_set_ts_config - set hardware time stamping config
1098 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1100 struct igb_adapter *adapter = netdev_priv(netdev);
1101 struct hwtstamp_config config;
1104 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1107 err = igb_ptp_set_timestamp_mode(adapter, &config);
1111 /* save these settings for future reference */
1112 memcpy(&adapter->tstamp_config, &config,
1113 sizeof(adapter->tstamp_config));
1115 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1120 * igb_ptp_init - Initialize PTP functionality
1121 * @adapter: Board private structure
1123 * This function is called at device probe to initialize the PTP
1126 void igb_ptp_init(struct igb_adapter *adapter)
1128 struct e1000_hw *hw = &adapter->hw;
1129 struct net_device *netdev = adapter->netdev;
1132 switch (hw->mac.type) {
1134 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1135 adapter->ptp_caps.owner = THIS_MODULE;
1136 adapter->ptp_caps.max_adj = 999999881;
1137 adapter->ptp_caps.n_ext_ts = 0;
1138 adapter->ptp_caps.pps = 0;
1139 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1140 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1141 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1142 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1143 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1144 adapter->cc.read = igb_ptp_read_82576;
1145 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1146 adapter->cc.mult = 1;
1147 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1148 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1153 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1154 adapter->ptp_caps.owner = THIS_MODULE;
1155 adapter->ptp_caps.max_adj = 62499999;
1156 adapter->ptp_caps.n_ext_ts = 0;
1157 adapter->ptp_caps.pps = 0;
1158 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1159 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1160 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1161 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1162 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1163 adapter->cc.read = igb_ptp_read_82580;
1164 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1165 adapter->cc.mult = 1;
1166 adapter->cc.shift = 0;
1167 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1171 for (i = 0; i < IGB_N_SDP; i++) {
1172 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1174 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1176 ppd->func = PTP_PF_NONE;
1178 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1179 adapter->ptp_caps.owner = THIS_MODULE;
1180 adapter->ptp_caps.max_adj = 62499999;
1181 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1182 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1183 adapter->ptp_caps.n_pins = IGB_N_SDP;
1184 adapter->ptp_caps.pps = 1;
1185 adapter->ptp_caps.pin_config = adapter->sdp_config;
1186 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1187 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1188 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1189 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1190 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1191 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1194 adapter->ptp_clock = NULL;
1198 spin_lock_init(&adapter->tmreg_lock);
1199 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1201 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1202 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1203 igb_ptp_overflow_check);
1205 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1206 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1208 igb_ptp_reset(adapter);
1210 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1211 &adapter->pdev->dev);
1212 if (IS_ERR(adapter->ptp_clock)) {
1213 adapter->ptp_clock = NULL;
1214 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1215 } else if (adapter->ptp_clock) {
1216 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1217 adapter->netdev->name);
1218 adapter->ptp_flags |= IGB_PTP_ENABLED;
1223 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1224 * @adapter: Board private structure
1226 * This function stops the overflow check work and PTP Tx timestamp work, and
1227 * will prepare the device for OS suspend.
1229 void igb_ptp_suspend(struct igb_adapter *adapter)
1231 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1234 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1235 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1237 cancel_work_sync(&adapter->ptp_tx_work);
1238 if (adapter->ptp_tx_skb) {
1239 dev_kfree_skb_any(adapter->ptp_tx_skb);
1240 adapter->ptp_tx_skb = NULL;
1241 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1246 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1247 * @adapter: Board private structure.
1249 * This function stops the PTP support and cancels the delayed work.
1251 void igb_ptp_stop(struct igb_adapter *adapter)
1253 igb_ptp_suspend(adapter);
1255 if (adapter->ptp_clock) {
1256 ptp_clock_unregister(adapter->ptp_clock);
1257 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1258 adapter->netdev->name);
1259 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1264 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1265 * @adapter: Board private structure.
1267 * This function handles the reset work required to re-enable the PTP device.
1269 void igb_ptp_reset(struct igb_adapter *adapter)
1271 struct e1000_hw *hw = &adapter->hw;
1272 unsigned long flags;
1274 /* reset the tstamp_config */
1275 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1277 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1279 switch (adapter->hw.mac.type) {
1281 /* Dial the nominal frequency. */
1282 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1289 wr32(E1000_TSAUXC, 0x0);
1290 wr32(E1000_TSSDP, 0x0);
1293 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1294 wr32(E1000_IMS, E1000_IMS_TS);
1297 /* No work to do. */
1301 /* Re-initialize the timer. */
1302 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1303 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1305 igb_ptp_write_i210(adapter, &ts);
1307 timecounter_init(&adapter->tc, &adapter->cc,
1308 ktime_to_ns(ktime_get_real()));
1311 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1315 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1316 schedule_delayed_work(&adapter->ptp_overflow_work,
1317 IGB_SYSTIM_OVERFLOW_PERIOD);