1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 /* ethtool support for igb */
26 #include <linux/vmalloc.h>
27 #include <linux/netdevice.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/if_ether.h>
32 #include <linux/ethtool.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/highmem.h>
37 #include <linux/mdio.h>
42 char stat_string[ETH_GSTRING_LEN];
47 #define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
52 static const struct igb_stats igb_gstrings_stats[] = {
53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
96 #define IGB_NETDEV_STAT(_net_stat) { \
97 .stat_string = __stringify(_net_stat), \
98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
101 static const struct igb_stats igb_gstrings_net_stats[] = {
102 IGB_NETDEV_STAT(rx_errors),
103 IGB_NETDEV_STAT(tx_errors),
104 IGB_NETDEV_STAT(tx_dropped),
105 IGB_NETDEV_STAT(rx_length_errors),
106 IGB_NETDEV_STAT(rx_over_errors),
107 IGB_NETDEV_STAT(rx_frame_errors),
108 IGB_NETDEV_STAT(rx_fifo_errors),
109 IGB_NETDEV_STAT(tx_fifo_errors),
110 IGB_NETDEV_STAT(tx_heartbeat_errors)
113 #define IGB_GLOBAL_STATS_LEN \
114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
115 #define IGB_NETDEV_STATS_LEN \
116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
117 #define IGB_RX_QUEUE_STATS_LEN \
118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
122 #define IGB_QUEUE_STATS_LEN \
123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
124 IGB_RX_QUEUE_STATS_LEN) + \
125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
126 IGB_TX_QUEUE_STATS_LEN))
127 #define IGB_STATS_LEN \
128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
130 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
131 "Register test (offline)", "Eeprom test (offline)",
132 "Interrupt test (offline)", "Loopback test (offline)",
133 "Link test (on/offline)"
135 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
137 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
139 struct igb_adapter *adapter = netdev_priv(netdev);
140 struct e1000_hw *hw = &adapter->hw;
141 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
142 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
146 status = pm_runtime_suspended(&adapter->pdev->dev) ?
147 0 : rd32(E1000_STATUS);
148 if (hw->phy.media_type == e1000_media_type_copper) {
150 ecmd->supported = (SUPPORTED_10baseT_Half |
151 SUPPORTED_10baseT_Full |
152 SUPPORTED_100baseT_Half |
153 SUPPORTED_100baseT_Full |
154 SUPPORTED_1000baseT_Full|
158 ecmd->advertising = ADVERTISED_TP;
160 if (hw->mac.autoneg == 1) {
161 ecmd->advertising |= ADVERTISED_Autoneg;
162 /* the e1000 autoneg seems to match ethtool nicely */
163 ecmd->advertising |= hw->phy.autoneg_advertised;
166 ecmd->port = PORT_TP;
167 ecmd->phy_address = hw->phy.addr;
168 ecmd->transceiver = XCVR_INTERNAL;
170 ecmd->supported = (SUPPORTED_FIBRE |
171 SUPPORTED_1000baseKX_Full |
174 ecmd->advertising = (ADVERTISED_FIBRE |
175 ADVERTISED_1000baseKX_Full);
176 if (hw->mac.type == e1000_i354) {
177 if ((hw->device_id ==
178 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
179 !(status & E1000_STATUS_2P5_SKU_OVER)) {
180 ecmd->supported |= SUPPORTED_2500baseX_Full;
182 ~SUPPORTED_1000baseKX_Full;
183 ecmd->advertising |= ADVERTISED_2500baseX_Full;
185 ~ADVERTISED_1000baseKX_Full;
188 if (eth_flags->e100_base_fx) {
189 ecmd->supported |= SUPPORTED_100baseT_Full;
190 ecmd->advertising |= ADVERTISED_100baseT_Full;
192 if (hw->mac.autoneg == 1)
193 ecmd->advertising |= ADVERTISED_Autoneg;
195 ecmd->port = PORT_FIBRE;
196 ecmd->transceiver = XCVR_EXTERNAL;
198 if (hw->mac.autoneg != 1)
199 ecmd->advertising &= ~(ADVERTISED_Pause |
200 ADVERTISED_Asym_Pause);
202 switch (hw->fc.requested_mode) {
204 ecmd->advertising |= ADVERTISED_Pause;
206 case e1000_fc_rx_pause:
207 ecmd->advertising |= (ADVERTISED_Pause |
208 ADVERTISED_Asym_Pause);
210 case e1000_fc_tx_pause:
211 ecmd->advertising |= ADVERTISED_Asym_Pause;
214 ecmd->advertising &= ~(ADVERTISED_Pause |
215 ADVERTISED_Asym_Pause);
217 if (status & E1000_STATUS_LU) {
218 if ((status & E1000_STATUS_2P5_SKU) &&
219 !(status & E1000_STATUS_2P5_SKU_OVER)) {
221 } else if (status & E1000_STATUS_SPEED_1000) {
223 } else if (status & E1000_STATUS_SPEED_100) {
228 if ((status & E1000_STATUS_FD) ||
229 hw->phy.media_type != e1000_media_type_copper)
230 ecmd->duplex = DUPLEX_FULL;
232 ecmd->duplex = DUPLEX_HALF;
234 speed = SPEED_UNKNOWN;
235 ecmd->duplex = DUPLEX_UNKNOWN;
237 ethtool_cmd_speed_set(ecmd, speed);
238 if ((hw->phy.media_type == e1000_media_type_fiber) ||
240 ecmd->autoneg = AUTONEG_ENABLE;
242 ecmd->autoneg = AUTONEG_DISABLE;
244 /* MDI-X => 2; MDI =>1; Invalid =>0 */
245 if (hw->phy.media_type == e1000_media_type_copper)
246 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
249 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
251 if (hw->phy.mdix == AUTO_ALL_MODES)
252 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
254 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
259 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
261 struct igb_adapter *adapter = netdev_priv(netdev);
262 struct e1000_hw *hw = &adapter->hw;
264 /* When SoL/IDER sessions are active, autoneg/speed/duplex
267 if (igb_check_reset_block(hw)) {
268 dev_err(&adapter->pdev->dev,
269 "Cannot change link characteristics when SoL/IDER is active.\n");
273 /* MDI setting is only allowed when autoneg enabled because
274 * some hardware doesn't allow MDI setting when speed or
277 if (ecmd->eth_tp_mdix_ctrl) {
278 if (hw->phy.media_type != e1000_media_type_copper)
281 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
282 (ecmd->autoneg != AUTONEG_ENABLE)) {
283 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
288 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
289 usleep_range(1000, 2000);
291 if (ecmd->autoneg == AUTONEG_ENABLE) {
293 if (hw->phy.media_type == e1000_media_type_fiber) {
294 hw->phy.autoneg_advertised = ecmd->advertising |
297 switch (adapter->link_speed) {
299 hw->phy.autoneg_advertised =
300 ADVERTISED_2500baseX_Full;
303 hw->phy.autoneg_advertised =
304 ADVERTISED_1000baseT_Full;
307 hw->phy.autoneg_advertised =
308 ADVERTISED_100baseT_Full;
314 hw->phy.autoneg_advertised = ecmd->advertising |
318 ecmd->advertising = hw->phy.autoneg_advertised;
319 if (adapter->fc_autoneg)
320 hw->fc.requested_mode = e1000_fc_default;
322 u32 speed = ethtool_cmd_speed(ecmd);
323 /* calling this overrides forced MDI setting */
324 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
325 clear_bit(__IGB_RESETTING, &adapter->state);
330 /* MDI-X => 2; MDI => 1; Auto => 3 */
331 if (ecmd->eth_tp_mdix_ctrl) {
332 /* fix up the value for auto (3 => 0) as zero is mapped
335 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
336 hw->phy.mdix = AUTO_ALL_MODES;
338 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
342 if (netif_running(adapter->netdev)) {
348 clear_bit(__IGB_RESETTING, &adapter->state);
352 static u32 igb_get_link(struct net_device *netdev)
354 struct igb_adapter *adapter = netdev_priv(netdev);
355 struct e1000_mac_info *mac = &adapter->hw.mac;
357 /* If the link is not reported up to netdev, interrupts are disabled,
358 * and so the physical link state may have changed since we last
359 * looked. Set get_link_status to make sure that the true link
360 * state is interrogated, rather than pulling a cached and possibly
361 * stale link state from the driver.
363 if (!netif_carrier_ok(netdev))
364 mac->get_link_status = 1;
366 return igb_has_link(adapter);
369 static void igb_get_pauseparam(struct net_device *netdev,
370 struct ethtool_pauseparam *pause)
372 struct igb_adapter *adapter = netdev_priv(netdev);
373 struct e1000_hw *hw = &adapter->hw;
376 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
378 if (hw->fc.current_mode == e1000_fc_rx_pause)
380 else if (hw->fc.current_mode == e1000_fc_tx_pause)
382 else if (hw->fc.current_mode == e1000_fc_full) {
388 static int igb_set_pauseparam(struct net_device *netdev,
389 struct ethtool_pauseparam *pause)
391 struct igb_adapter *adapter = netdev_priv(netdev);
392 struct e1000_hw *hw = &adapter->hw;
395 /* 100basefx does not support setting link flow control */
396 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
399 adapter->fc_autoneg = pause->autoneg;
401 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
402 usleep_range(1000, 2000);
404 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
405 hw->fc.requested_mode = e1000_fc_default;
406 if (netif_running(adapter->netdev)) {
413 if (pause->rx_pause && pause->tx_pause)
414 hw->fc.requested_mode = e1000_fc_full;
415 else if (pause->rx_pause && !pause->tx_pause)
416 hw->fc.requested_mode = e1000_fc_rx_pause;
417 else if (!pause->rx_pause && pause->tx_pause)
418 hw->fc.requested_mode = e1000_fc_tx_pause;
419 else if (!pause->rx_pause && !pause->tx_pause)
420 hw->fc.requested_mode = e1000_fc_none;
422 hw->fc.current_mode = hw->fc.requested_mode;
424 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
425 igb_force_mac_fc(hw) : igb_setup_link(hw));
428 clear_bit(__IGB_RESETTING, &adapter->state);
432 static u32 igb_get_msglevel(struct net_device *netdev)
434 struct igb_adapter *adapter = netdev_priv(netdev);
435 return adapter->msg_enable;
438 static void igb_set_msglevel(struct net_device *netdev, u32 data)
440 struct igb_adapter *adapter = netdev_priv(netdev);
441 adapter->msg_enable = data;
444 static int igb_get_regs_len(struct net_device *netdev)
446 #define IGB_REGS_LEN 739
447 return IGB_REGS_LEN * sizeof(u32);
450 static void igb_get_regs(struct net_device *netdev,
451 struct ethtool_regs *regs, void *p)
453 struct igb_adapter *adapter = netdev_priv(netdev);
454 struct e1000_hw *hw = &adapter->hw;
458 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
460 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
462 /* General Registers */
463 regs_buff[0] = rd32(E1000_CTRL);
464 regs_buff[1] = rd32(E1000_STATUS);
465 regs_buff[2] = rd32(E1000_CTRL_EXT);
466 regs_buff[3] = rd32(E1000_MDIC);
467 regs_buff[4] = rd32(E1000_SCTL);
468 regs_buff[5] = rd32(E1000_CONNSW);
469 regs_buff[6] = rd32(E1000_VET);
470 regs_buff[7] = rd32(E1000_LEDCTL);
471 regs_buff[8] = rd32(E1000_PBA);
472 regs_buff[9] = rd32(E1000_PBS);
473 regs_buff[10] = rd32(E1000_FRTIMER);
474 regs_buff[11] = rd32(E1000_TCPTIMER);
477 regs_buff[12] = rd32(E1000_EECD);
480 /* Reading EICS for EICR because they read the
481 * same but EICS does not clear on read
483 regs_buff[13] = rd32(E1000_EICS);
484 regs_buff[14] = rd32(E1000_EICS);
485 regs_buff[15] = rd32(E1000_EIMS);
486 regs_buff[16] = rd32(E1000_EIMC);
487 regs_buff[17] = rd32(E1000_EIAC);
488 regs_buff[18] = rd32(E1000_EIAM);
489 /* Reading ICS for ICR because they read the
490 * same but ICS does not clear on read
492 regs_buff[19] = rd32(E1000_ICS);
493 regs_buff[20] = rd32(E1000_ICS);
494 regs_buff[21] = rd32(E1000_IMS);
495 regs_buff[22] = rd32(E1000_IMC);
496 regs_buff[23] = rd32(E1000_IAC);
497 regs_buff[24] = rd32(E1000_IAM);
498 regs_buff[25] = rd32(E1000_IMIRVP);
501 regs_buff[26] = rd32(E1000_FCAL);
502 regs_buff[27] = rd32(E1000_FCAH);
503 regs_buff[28] = rd32(E1000_FCTTV);
504 regs_buff[29] = rd32(E1000_FCRTL);
505 regs_buff[30] = rd32(E1000_FCRTH);
506 regs_buff[31] = rd32(E1000_FCRTV);
509 regs_buff[32] = rd32(E1000_RCTL);
510 regs_buff[33] = rd32(E1000_RXCSUM);
511 regs_buff[34] = rd32(E1000_RLPML);
512 regs_buff[35] = rd32(E1000_RFCTL);
513 regs_buff[36] = rd32(E1000_MRQC);
514 regs_buff[37] = rd32(E1000_VT_CTL);
517 regs_buff[38] = rd32(E1000_TCTL);
518 regs_buff[39] = rd32(E1000_TCTL_EXT);
519 regs_buff[40] = rd32(E1000_TIPG);
520 regs_buff[41] = rd32(E1000_DTXCTL);
523 regs_buff[42] = rd32(E1000_WUC);
524 regs_buff[43] = rd32(E1000_WUFC);
525 regs_buff[44] = rd32(E1000_WUS);
526 regs_buff[45] = rd32(E1000_IPAV);
527 regs_buff[46] = rd32(E1000_WUPL);
530 regs_buff[47] = rd32(E1000_PCS_CFG0);
531 regs_buff[48] = rd32(E1000_PCS_LCTL);
532 regs_buff[49] = rd32(E1000_PCS_LSTAT);
533 regs_buff[50] = rd32(E1000_PCS_ANADV);
534 regs_buff[51] = rd32(E1000_PCS_LPAB);
535 regs_buff[52] = rd32(E1000_PCS_NPTX);
536 regs_buff[53] = rd32(E1000_PCS_LPABNP);
539 regs_buff[54] = adapter->stats.crcerrs;
540 regs_buff[55] = adapter->stats.algnerrc;
541 regs_buff[56] = adapter->stats.symerrs;
542 regs_buff[57] = adapter->stats.rxerrc;
543 regs_buff[58] = adapter->stats.mpc;
544 regs_buff[59] = adapter->stats.scc;
545 regs_buff[60] = adapter->stats.ecol;
546 regs_buff[61] = adapter->stats.mcc;
547 regs_buff[62] = adapter->stats.latecol;
548 regs_buff[63] = adapter->stats.colc;
549 regs_buff[64] = adapter->stats.dc;
550 regs_buff[65] = adapter->stats.tncrs;
551 regs_buff[66] = adapter->stats.sec;
552 regs_buff[67] = adapter->stats.htdpmc;
553 regs_buff[68] = adapter->stats.rlec;
554 regs_buff[69] = adapter->stats.xonrxc;
555 regs_buff[70] = adapter->stats.xontxc;
556 regs_buff[71] = adapter->stats.xoffrxc;
557 regs_buff[72] = adapter->stats.xofftxc;
558 regs_buff[73] = adapter->stats.fcruc;
559 regs_buff[74] = adapter->stats.prc64;
560 regs_buff[75] = adapter->stats.prc127;
561 regs_buff[76] = adapter->stats.prc255;
562 regs_buff[77] = adapter->stats.prc511;
563 regs_buff[78] = adapter->stats.prc1023;
564 regs_buff[79] = adapter->stats.prc1522;
565 regs_buff[80] = adapter->stats.gprc;
566 regs_buff[81] = adapter->stats.bprc;
567 regs_buff[82] = adapter->stats.mprc;
568 regs_buff[83] = adapter->stats.gptc;
569 regs_buff[84] = adapter->stats.gorc;
570 regs_buff[86] = adapter->stats.gotc;
571 regs_buff[88] = adapter->stats.rnbc;
572 regs_buff[89] = adapter->stats.ruc;
573 regs_buff[90] = adapter->stats.rfc;
574 regs_buff[91] = adapter->stats.roc;
575 regs_buff[92] = adapter->stats.rjc;
576 regs_buff[93] = adapter->stats.mgprc;
577 regs_buff[94] = adapter->stats.mgpdc;
578 regs_buff[95] = adapter->stats.mgptc;
579 regs_buff[96] = adapter->stats.tor;
580 regs_buff[98] = adapter->stats.tot;
581 regs_buff[100] = adapter->stats.tpr;
582 regs_buff[101] = adapter->stats.tpt;
583 regs_buff[102] = adapter->stats.ptc64;
584 regs_buff[103] = adapter->stats.ptc127;
585 regs_buff[104] = adapter->stats.ptc255;
586 regs_buff[105] = adapter->stats.ptc511;
587 regs_buff[106] = adapter->stats.ptc1023;
588 regs_buff[107] = adapter->stats.ptc1522;
589 regs_buff[108] = adapter->stats.mptc;
590 regs_buff[109] = adapter->stats.bptc;
591 regs_buff[110] = adapter->stats.tsctc;
592 regs_buff[111] = adapter->stats.iac;
593 regs_buff[112] = adapter->stats.rpthc;
594 regs_buff[113] = adapter->stats.hgptc;
595 regs_buff[114] = adapter->stats.hgorc;
596 regs_buff[116] = adapter->stats.hgotc;
597 regs_buff[118] = adapter->stats.lenerrs;
598 regs_buff[119] = adapter->stats.scvpc;
599 regs_buff[120] = adapter->stats.hrmpc;
601 for (i = 0; i < 4; i++)
602 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
603 for (i = 0; i < 4; i++)
604 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
605 for (i = 0; i < 4; i++)
606 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
607 for (i = 0; i < 4; i++)
608 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
609 for (i = 0; i < 4; i++)
610 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
611 for (i = 0; i < 4; i++)
612 regs_buff[141 + i] = rd32(E1000_RDH(i));
613 for (i = 0; i < 4; i++)
614 regs_buff[145 + i] = rd32(E1000_RDT(i));
615 for (i = 0; i < 4; i++)
616 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
618 for (i = 0; i < 10; i++)
619 regs_buff[153 + i] = rd32(E1000_EITR(i));
620 for (i = 0; i < 8; i++)
621 regs_buff[163 + i] = rd32(E1000_IMIR(i));
622 for (i = 0; i < 8; i++)
623 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
624 for (i = 0; i < 16; i++)
625 regs_buff[179 + i] = rd32(E1000_RAL(i));
626 for (i = 0; i < 16; i++)
627 regs_buff[195 + i] = rd32(E1000_RAH(i));
629 for (i = 0; i < 4; i++)
630 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
631 for (i = 0; i < 4; i++)
632 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
633 for (i = 0; i < 4; i++)
634 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
635 for (i = 0; i < 4; i++)
636 regs_buff[223 + i] = rd32(E1000_TDH(i));
637 for (i = 0; i < 4; i++)
638 regs_buff[227 + i] = rd32(E1000_TDT(i));
639 for (i = 0; i < 4; i++)
640 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
641 for (i = 0; i < 4; i++)
642 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
643 for (i = 0; i < 4; i++)
644 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
645 for (i = 0; i < 4; i++)
646 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
648 for (i = 0; i < 4; i++)
649 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
650 for (i = 0; i < 4; i++)
651 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
652 for (i = 0; i < 32; i++)
653 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
654 for (i = 0; i < 128; i++)
655 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
656 for (i = 0; i < 128; i++)
657 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
658 for (i = 0; i < 4; i++)
659 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
661 regs_buff[547] = rd32(E1000_TDFH);
662 regs_buff[548] = rd32(E1000_TDFT);
663 regs_buff[549] = rd32(E1000_TDFHS);
664 regs_buff[550] = rd32(E1000_TDFPC);
666 if (hw->mac.type > e1000_82580) {
667 regs_buff[551] = adapter->stats.o2bgptc;
668 regs_buff[552] = adapter->stats.b2ospc;
669 regs_buff[553] = adapter->stats.o2bspc;
670 regs_buff[554] = adapter->stats.b2ogprc;
673 if (hw->mac.type != e1000_82576)
675 for (i = 0; i < 12; i++)
676 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
677 for (i = 0; i < 4; i++)
678 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
679 for (i = 0; i < 12; i++)
680 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
681 for (i = 0; i < 12; i++)
682 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
683 for (i = 0; i < 12; i++)
684 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
685 for (i = 0; i < 12; i++)
686 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
687 for (i = 0; i < 12; i++)
688 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
689 for (i = 0; i < 12; i++)
690 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
692 for (i = 0; i < 12; i++)
693 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
694 for (i = 0; i < 12; i++)
695 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
696 for (i = 0; i < 12; i++)
697 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
698 for (i = 0; i < 12; i++)
699 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
700 for (i = 0; i < 12; i++)
701 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
702 for (i = 0; i < 12; i++)
703 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
704 for (i = 0; i < 12; i++)
705 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
706 for (i = 0; i < 12; i++)
707 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
710 static int igb_get_eeprom_len(struct net_device *netdev)
712 struct igb_adapter *adapter = netdev_priv(netdev);
713 return adapter->hw.nvm.word_size * 2;
716 static int igb_get_eeprom(struct net_device *netdev,
717 struct ethtool_eeprom *eeprom, u8 *bytes)
719 struct igb_adapter *adapter = netdev_priv(netdev);
720 struct e1000_hw *hw = &adapter->hw;
722 int first_word, last_word;
726 if (eeprom->len == 0)
729 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
731 first_word = eeprom->offset >> 1;
732 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
734 eeprom_buff = kmalloc(sizeof(u16) *
735 (last_word - first_word + 1), GFP_KERNEL);
739 if (hw->nvm.type == e1000_nvm_eeprom_spi)
740 ret_val = hw->nvm.ops.read(hw, first_word,
741 last_word - first_word + 1,
744 for (i = 0; i < last_word - first_word + 1; i++) {
745 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
752 /* Device's eeprom is always little-endian, word addressable */
753 for (i = 0; i < last_word - first_word + 1; i++)
754 le16_to_cpus(&eeprom_buff[i]);
756 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
763 static int igb_set_eeprom(struct net_device *netdev,
764 struct ethtool_eeprom *eeprom, u8 *bytes)
766 struct igb_adapter *adapter = netdev_priv(netdev);
767 struct e1000_hw *hw = &adapter->hw;
770 int max_len, first_word, last_word, ret_val = 0;
773 if (eeprom->len == 0)
776 if ((hw->mac.type >= e1000_i210) &&
777 !igb_get_flash_presence_i210(hw)) {
781 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
784 max_len = hw->nvm.word_size * 2;
786 first_word = eeprom->offset >> 1;
787 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
788 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
792 ptr = (void *)eeprom_buff;
794 if (eeprom->offset & 1) {
795 /* need read/modify/write of first changed EEPROM word
796 * only the second byte of the word is being modified
798 ret_val = hw->nvm.ops.read(hw, first_word, 1,
802 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
803 /* need read/modify/write of last changed EEPROM word
804 * only the first byte of the word is being modified
806 ret_val = hw->nvm.ops.read(hw, last_word, 1,
807 &eeprom_buff[last_word - first_word]);
810 /* Device's eeprom is always little-endian, word addressable */
811 for (i = 0; i < last_word - first_word + 1; i++)
812 le16_to_cpus(&eeprom_buff[i]);
814 memcpy(ptr, bytes, eeprom->len);
816 for (i = 0; i < last_word - first_word + 1; i++)
817 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
819 ret_val = hw->nvm.ops.write(hw, first_word,
820 last_word - first_word + 1, eeprom_buff);
822 /* Update the checksum if nvm write succeeded */
824 hw->nvm.ops.update(hw);
826 igb_set_fw_version(adapter);
831 static void igb_get_drvinfo(struct net_device *netdev,
832 struct ethtool_drvinfo *drvinfo)
834 struct igb_adapter *adapter = netdev_priv(netdev);
836 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
837 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
839 /* EEPROM image version # is reported as firmware version # for
842 strlcpy(drvinfo->fw_version, adapter->fw_version,
843 sizeof(drvinfo->fw_version));
844 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
845 sizeof(drvinfo->bus_info));
848 static void igb_get_ringparam(struct net_device *netdev,
849 struct ethtool_ringparam *ring)
851 struct igb_adapter *adapter = netdev_priv(netdev);
853 ring->rx_max_pending = IGB_MAX_RXD;
854 ring->tx_max_pending = IGB_MAX_TXD;
855 ring->rx_pending = adapter->rx_ring_count;
856 ring->tx_pending = adapter->tx_ring_count;
859 static int igb_set_ringparam(struct net_device *netdev,
860 struct ethtool_ringparam *ring)
862 struct igb_adapter *adapter = netdev_priv(netdev);
863 struct igb_ring *temp_ring;
865 u16 new_rx_count, new_tx_count;
867 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
870 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
871 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
872 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
874 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
875 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
876 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
878 if ((new_tx_count == adapter->tx_ring_count) &&
879 (new_rx_count == adapter->rx_ring_count)) {
884 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
885 usleep_range(1000, 2000);
887 if (!netif_running(adapter->netdev)) {
888 for (i = 0; i < adapter->num_tx_queues; i++)
889 adapter->tx_ring[i]->count = new_tx_count;
890 for (i = 0; i < adapter->num_rx_queues; i++)
891 adapter->rx_ring[i]->count = new_rx_count;
892 adapter->tx_ring_count = new_tx_count;
893 adapter->rx_ring_count = new_rx_count;
897 if (adapter->num_tx_queues > adapter->num_rx_queues)
898 temp_ring = vmalloc(adapter->num_tx_queues *
899 sizeof(struct igb_ring));
901 temp_ring = vmalloc(adapter->num_rx_queues *
902 sizeof(struct igb_ring));
911 /* We can't just free everything and then setup again,
912 * because the ISRs in MSI-X mode get passed pointers
913 * to the Tx and Rx ring structs.
915 if (new_tx_count != adapter->tx_ring_count) {
916 for (i = 0; i < adapter->num_tx_queues; i++) {
917 memcpy(&temp_ring[i], adapter->tx_ring[i],
918 sizeof(struct igb_ring));
920 temp_ring[i].count = new_tx_count;
921 err = igb_setup_tx_resources(&temp_ring[i]);
925 igb_free_tx_resources(&temp_ring[i]);
931 for (i = 0; i < adapter->num_tx_queues; i++) {
932 igb_free_tx_resources(adapter->tx_ring[i]);
934 memcpy(adapter->tx_ring[i], &temp_ring[i],
935 sizeof(struct igb_ring));
938 adapter->tx_ring_count = new_tx_count;
941 if (new_rx_count != adapter->rx_ring_count) {
942 for (i = 0; i < adapter->num_rx_queues; i++) {
943 memcpy(&temp_ring[i], adapter->rx_ring[i],
944 sizeof(struct igb_ring));
946 temp_ring[i].count = new_rx_count;
947 err = igb_setup_rx_resources(&temp_ring[i]);
951 igb_free_rx_resources(&temp_ring[i]);
958 for (i = 0; i < adapter->num_rx_queues; i++) {
959 igb_free_rx_resources(adapter->rx_ring[i]);
961 memcpy(adapter->rx_ring[i], &temp_ring[i],
962 sizeof(struct igb_ring));
965 adapter->rx_ring_count = new_rx_count;
971 clear_bit(__IGB_RESETTING, &adapter->state);
975 /* ethtool register test data */
976 struct igb_reg_test {
985 /* In the hardware, registers are laid out either singly, in arrays
986 * spaced 0x100 bytes apart, or in contiguous tables. We assume
987 * most tests take place on arrays or single registers (handled
988 * as a single-element array) and special-case the tables.
989 * Table tests are always pattern tests.
991 * We also make provision for some required setup steps by specifying
992 * registers to be written without any read-back testing.
995 #define PATTERN_TEST 1
996 #define SET_READ_TEST 2
997 #define WRITE_NO_TEST 3
998 #define TABLE32_TEST 4
999 #define TABLE64_TEST_LO 5
1000 #define TABLE64_TEST_HI 6
1003 static struct igb_reg_test reg_test_i210[] = {
1004 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1005 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1006 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1007 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1008 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1009 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1010 /* RDH is read-only for i210, only test RDT. */
1011 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1012 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1013 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1014 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1015 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1016 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1017 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1018 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1019 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1020 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1021 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1022 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1023 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1024 0xFFFFFFFF, 0xFFFFFFFF },
1025 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1026 0x900FFFFF, 0xFFFFFFFF },
1027 { E1000_MTA, 0, 128, TABLE32_TEST,
1028 0xFFFFFFFF, 0xFFFFFFFF },
1033 static struct igb_reg_test reg_test_i350[] = {
1034 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1035 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1036 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1037 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1038 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1039 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1040 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1041 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1042 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1043 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1044 /* RDH is read-only for i350, only test RDT. */
1045 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1046 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1047 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1048 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1049 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1050 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1051 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1052 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1053 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1054 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1055 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1056 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1057 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1058 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1059 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1060 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1061 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1062 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1063 0xFFFFFFFF, 0xFFFFFFFF },
1064 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1065 0xC3FFFFFF, 0xFFFFFFFF },
1066 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1067 0xFFFFFFFF, 0xFFFFFFFF },
1068 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1069 0xC3FFFFFF, 0xFFFFFFFF },
1070 { E1000_MTA, 0, 128, TABLE32_TEST,
1071 0xFFFFFFFF, 0xFFFFFFFF },
1075 /* 82580 reg test */
1076 static struct igb_reg_test reg_test_82580[] = {
1077 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1078 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1079 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1080 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1081 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1082 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1083 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1084 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1085 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1086 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1087 /* RDH is read-only for 82580, only test RDT. */
1088 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1089 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1090 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1091 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1092 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1093 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1094 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1095 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1096 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1097 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1099 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1100 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1101 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1102 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1103 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1104 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1105 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1106 0xFFFFFFFF, 0xFFFFFFFF },
1107 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1108 0x83FFFFFF, 0xFFFFFFFF },
1109 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1110 0xFFFFFFFF, 0xFFFFFFFF },
1111 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1112 0x83FFFFFF, 0xFFFFFFFF },
1113 { E1000_MTA, 0, 128, TABLE32_TEST,
1114 0xFFFFFFFF, 0xFFFFFFFF },
1118 /* 82576 reg test */
1119 static struct igb_reg_test reg_test_82576[] = {
1120 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1121 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1122 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1123 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1124 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1125 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1126 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1127 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1128 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1130 /* Enable all RX queues before testing. */
1131 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1132 E1000_RXDCTL_QUEUE_ENABLE },
1133 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1134 E1000_RXDCTL_QUEUE_ENABLE },
1135 /* RDH is read-only for 82576, only test RDT. */
1136 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1137 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1138 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1139 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1140 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1141 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1142 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1143 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1144 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1145 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1146 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1147 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1149 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1150 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1151 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1152 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1153 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1154 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1155 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1156 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1157 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1161 /* 82575 register test */
1162 static struct igb_reg_test reg_test_82575[] = {
1163 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1164 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1165 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1166 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1168 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1169 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1170 /* Enable all four RX queues before testing. */
1171 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1172 E1000_RXDCTL_QUEUE_ENABLE },
1173 /* RDH is read-only for 82575, only test RDT. */
1174 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1175 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1176 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1177 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1178 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1179 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1180 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1182 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1183 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1184 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1185 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1186 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1187 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1188 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1189 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1193 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1194 int reg, u32 mask, u32 write)
1196 struct e1000_hw *hw = &adapter->hw;
1198 static const u32 _test[] = {
1199 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1200 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1201 wr32(reg, (_test[pat] & write));
1202 val = rd32(reg) & mask;
1203 if (val != (_test[pat] & write & mask)) {
1204 dev_err(&adapter->pdev->dev,
1205 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1206 reg, val, (_test[pat] & write & mask));
1215 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1216 int reg, u32 mask, u32 write)
1218 struct e1000_hw *hw = &adapter->hw;
1221 wr32(reg, write & mask);
1223 if ((write & mask) != (val & mask)) {
1224 dev_err(&adapter->pdev->dev,
1225 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1226 reg, (val & mask), (write & mask));
1234 #define REG_PATTERN_TEST(reg, mask, write) \
1236 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1240 #define REG_SET_AND_CHECK(reg, mask, write) \
1242 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1246 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1248 struct e1000_hw *hw = &adapter->hw;
1249 struct igb_reg_test *test;
1250 u32 value, before, after;
1253 switch (adapter->hw.mac.type) {
1256 test = reg_test_i350;
1257 toggle = 0x7FEFF3FF;
1261 test = reg_test_i210;
1262 toggle = 0x7FEFF3FF;
1265 test = reg_test_82580;
1266 toggle = 0x7FEFF3FF;
1269 test = reg_test_82576;
1270 toggle = 0x7FFFF3FF;
1273 test = reg_test_82575;
1274 toggle = 0x7FFFF3FF;
1278 /* Because the status register is such a special case,
1279 * we handle it separately from the rest of the register
1280 * tests. Some bits are read-only, some toggle, and some
1281 * are writable on newer MACs.
1283 before = rd32(E1000_STATUS);
1284 value = (rd32(E1000_STATUS) & toggle);
1285 wr32(E1000_STATUS, toggle);
1286 after = rd32(E1000_STATUS) & toggle;
1287 if (value != after) {
1288 dev_err(&adapter->pdev->dev,
1289 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1294 /* restore previous status */
1295 wr32(E1000_STATUS, before);
1297 /* Perform the remainder of the register test, looping through
1298 * the test table until we either fail or reach the null entry.
1301 for (i = 0; i < test->array_len; i++) {
1302 switch (test->test_type) {
1304 REG_PATTERN_TEST(test->reg +
1305 (i * test->reg_offset),
1310 REG_SET_AND_CHECK(test->reg +
1311 (i * test->reg_offset),
1317 (adapter->hw.hw_addr + test->reg)
1318 + (i * test->reg_offset));
1321 REG_PATTERN_TEST(test->reg + (i * 4),
1325 case TABLE64_TEST_LO:
1326 REG_PATTERN_TEST(test->reg + (i * 8),
1330 case TABLE64_TEST_HI:
1331 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1344 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1346 struct e1000_hw *hw = &adapter->hw;
1350 /* Validate eeprom on all parts but flashless */
1351 switch (hw->mac.type) {
1354 if (igb_get_flash_presence_i210(hw)) {
1355 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1360 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1368 static irqreturn_t igb_test_intr(int irq, void *data)
1370 struct igb_adapter *adapter = (struct igb_adapter *) data;
1371 struct e1000_hw *hw = &adapter->hw;
1373 adapter->test_icr |= rd32(E1000_ICR);
1378 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1380 struct e1000_hw *hw = &adapter->hw;
1381 struct net_device *netdev = adapter->netdev;
1382 u32 mask, ics_mask, i = 0, shared_int = true;
1383 u32 irq = adapter->pdev->irq;
1387 /* Hook up test interrupt handler just for this test */
1388 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1389 if (request_irq(adapter->msix_entries[0].vector,
1390 igb_test_intr, 0, netdev->name, adapter)) {
1394 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1396 if (request_irq(irq,
1397 igb_test_intr, 0, netdev->name, adapter)) {
1401 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1402 netdev->name, adapter)) {
1404 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1405 netdev->name, adapter)) {
1409 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1410 (shared_int ? "shared" : "unshared"));
1412 /* Disable all the interrupts */
1413 wr32(E1000_IMC, ~0);
1415 usleep_range(10000, 11000);
1417 /* Define all writable bits for ICS */
1418 switch (hw->mac.type) {
1420 ics_mask = 0x37F47EDD;
1423 ics_mask = 0x77D4FBFD;
1426 ics_mask = 0x77DCFED5;
1432 ics_mask = 0x77DCFED5;
1435 ics_mask = 0x7FFFFFFF;
1439 /* Test each interrupt */
1440 for (; i < 31; i++) {
1441 /* Interrupt to test */
1444 if (!(mask & ics_mask))
1448 /* Disable the interrupt to be reported in
1449 * the cause register and then force the same
1450 * interrupt and see if one gets posted. If
1451 * an interrupt was posted to the bus, the
1454 adapter->test_icr = 0;
1456 /* Flush any pending interrupts */
1457 wr32(E1000_ICR, ~0);
1459 wr32(E1000_IMC, mask);
1460 wr32(E1000_ICS, mask);
1462 usleep_range(10000, 11000);
1464 if (adapter->test_icr & mask) {
1470 /* Enable the interrupt to be reported in
1471 * the cause register and then force the same
1472 * interrupt and see if one gets posted. If
1473 * an interrupt was not posted to the bus, the
1476 adapter->test_icr = 0;
1478 /* Flush any pending interrupts */
1479 wr32(E1000_ICR, ~0);
1481 wr32(E1000_IMS, mask);
1482 wr32(E1000_ICS, mask);
1484 usleep_range(10000, 11000);
1486 if (!(adapter->test_icr & mask)) {
1492 /* Disable the other interrupts to be reported in
1493 * the cause register and then force the other
1494 * interrupts and see if any get posted. If
1495 * an interrupt was posted to the bus, the
1498 adapter->test_icr = 0;
1500 /* Flush any pending interrupts */
1501 wr32(E1000_ICR, ~0);
1503 wr32(E1000_IMC, ~mask);
1504 wr32(E1000_ICS, ~mask);
1506 usleep_range(10000, 11000);
1508 if (adapter->test_icr & mask) {
1515 /* Disable all the interrupts */
1516 wr32(E1000_IMC, ~0);
1518 usleep_range(10000, 11000);
1520 /* Unhook test interrupt handler */
1521 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1522 free_irq(adapter->msix_entries[0].vector, adapter);
1524 free_irq(irq, adapter);
1529 static void igb_free_desc_rings(struct igb_adapter *adapter)
1531 igb_free_tx_resources(&adapter->test_tx_ring);
1532 igb_free_rx_resources(&adapter->test_rx_ring);
1535 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1537 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1538 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1539 struct e1000_hw *hw = &adapter->hw;
1542 /* Setup Tx descriptor ring and Tx buffers */
1543 tx_ring->count = IGB_DEFAULT_TXD;
1544 tx_ring->dev = &adapter->pdev->dev;
1545 tx_ring->netdev = adapter->netdev;
1546 tx_ring->reg_idx = adapter->vfs_allocated_count;
1548 if (igb_setup_tx_resources(tx_ring)) {
1553 igb_setup_tctl(adapter);
1554 igb_configure_tx_ring(adapter, tx_ring);
1556 /* Setup Rx descriptor ring and Rx buffers */
1557 rx_ring->count = IGB_DEFAULT_RXD;
1558 rx_ring->dev = &adapter->pdev->dev;
1559 rx_ring->netdev = adapter->netdev;
1560 rx_ring->reg_idx = adapter->vfs_allocated_count;
1562 if (igb_setup_rx_resources(rx_ring)) {
1567 /* set the default queue to queue 0 of PF */
1568 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1570 /* enable receive ring */
1571 igb_setup_rctl(adapter);
1572 igb_configure_rx_ring(adapter, rx_ring);
1574 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1579 igb_free_desc_rings(adapter);
1583 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1585 struct e1000_hw *hw = &adapter->hw;
1587 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1588 igb_write_phy_reg(hw, 29, 0x001F);
1589 igb_write_phy_reg(hw, 30, 0x8FFC);
1590 igb_write_phy_reg(hw, 29, 0x001A);
1591 igb_write_phy_reg(hw, 30, 0x8FF0);
1594 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1596 struct e1000_hw *hw = &adapter->hw;
1599 hw->mac.autoneg = false;
1601 if (hw->phy.type == e1000_phy_m88) {
1602 if (hw->phy.id != I210_I_PHY_ID) {
1603 /* Auto-MDI/MDIX Off */
1604 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1605 /* reset to update Auto-MDI/MDIX */
1606 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1608 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1610 /* force 1000, set loopback */
1611 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1612 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1614 } else if (hw->phy.type == e1000_phy_82580) {
1615 /* enable MII loopback */
1616 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1619 /* add small delay to avoid loopback test failure */
1622 /* force 1000, set loopback */
1623 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1625 /* Now set up the MAC to the same speed/duplex as the PHY. */
1626 ctrl_reg = rd32(E1000_CTRL);
1627 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1628 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1629 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1630 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1631 E1000_CTRL_FD | /* Force Duplex to FULL */
1632 E1000_CTRL_SLU); /* Set link up enable bit */
1634 if (hw->phy.type == e1000_phy_m88)
1635 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1637 wr32(E1000_CTRL, ctrl_reg);
1639 /* Disable the receiver on the PHY so when a cable is plugged in, the
1640 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1642 if (hw->phy.type == e1000_phy_m88)
1643 igb_phy_disable_receiver(adapter);
1649 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1651 return igb_integrated_phy_loopback(adapter);
1654 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1656 struct e1000_hw *hw = &adapter->hw;
1659 reg = rd32(E1000_CTRL_EXT);
1661 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1662 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1663 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1664 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1665 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1666 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1667 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1668 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1669 /* Enable DH89xxCC MPHY for near end loopback */
1670 reg = rd32(E1000_MPHY_ADDR_CTL);
1671 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1672 E1000_MPHY_PCS_CLK_REG_OFFSET;
1673 wr32(E1000_MPHY_ADDR_CTL, reg);
1675 reg = rd32(E1000_MPHY_DATA);
1676 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1677 wr32(E1000_MPHY_DATA, reg);
1680 reg = rd32(E1000_RCTL);
1681 reg |= E1000_RCTL_LBM_TCVR;
1682 wr32(E1000_RCTL, reg);
1684 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1686 reg = rd32(E1000_CTRL);
1687 reg &= ~(E1000_CTRL_RFCE |
1690 reg |= E1000_CTRL_SLU |
1692 wr32(E1000_CTRL, reg);
1694 /* Unset switch control to serdes energy detect */
1695 reg = rd32(E1000_CONNSW);
1696 reg &= ~E1000_CONNSW_ENRGSRC;
1697 wr32(E1000_CONNSW, reg);
1699 /* Unset sigdetect for SERDES loopback on
1700 * 82580 and newer devices.
1702 if (hw->mac.type >= e1000_82580) {
1703 reg = rd32(E1000_PCS_CFG0);
1704 reg |= E1000_PCS_CFG_IGN_SD;
1705 wr32(E1000_PCS_CFG0, reg);
1708 /* Set PCS register for forced speed */
1709 reg = rd32(E1000_PCS_LCTL);
1710 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1711 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1712 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1713 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1714 E1000_PCS_LCTL_FSD | /* Force Speed */
1715 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1716 wr32(E1000_PCS_LCTL, reg);
1721 return igb_set_phy_loopback(adapter);
1724 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1726 struct e1000_hw *hw = &adapter->hw;
1730 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1731 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1732 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1733 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1734 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1737 /* Disable near end loopback on DH89xxCC */
1738 reg = rd32(E1000_MPHY_ADDR_CTL);
1739 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1740 E1000_MPHY_PCS_CLK_REG_OFFSET;
1741 wr32(E1000_MPHY_ADDR_CTL, reg);
1743 reg = rd32(E1000_MPHY_DATA);
1744 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1745 wr32(E1000_MPHY_DATA, reg);
1748 rctl = rd32(E1000_RCTL);
1749 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1750 wr32(E1000_RCTL, rctl);
1752 hw->mac.autoneg = true;
1753 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1754 if (phy_reg & MII_CR_LOOPBACK) {
1755 phy_reg &= ~MII_CR_LOOPBACK;
1756 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1757 igb_phy_sw_reset(hw);
1761 static void igb_create_lbtest_frame(struct sk_buff *skb,
1762 unsigned int frame_size)
1764 memset(skb->data, 0xFF, frame_size);
1766 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1767 memset(&skb->data[frame_size + 10], 0xBE, 1);
1768 memset(&skb->data[frame_size + 12], 0xAF, 1);
1771 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1772 unsigned int frame_size)
1774 unsigned char *data;
1779 data = kmap(rx_buffer->page);
1781 if (data[3] != 0xFF ||
1782 data[frame_size + 10] != 0xBE ||
1783 data[frame_size + 12] != 0xAF)
1786 kunmap(rx_buffer->page);
1791 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1792 struct igb_ring *tx_ring,
1795 union e1000_adv_rx_desc *rx_desc;
1796 struct igb_rx_buffer *rx_buffer_info;
1797 struct igb_tx_buffer *tx_buffer_info;
1798 u16 rx_ntc, tx_ntc, count = 0;
1800 /* initialize next to clean and descriptor values */
1801 rx_ntc = rx_ring->next_to_clean;
1802 tx_ntc = tx_ring->next_to_clean;
1803 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1805 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1806 /* check Rx buffer */
1807 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1809 /* sync Rx buffer for CPU read */
1810 dma_sync_single_for_cpu(rx_ring->dev,
1811 rx_buffer_info->dma,
1815 /* verify contents of skb */
1816 if (igb_check_lbtest_frame(rx_buffer_info, size))
1819 /* sync Rx buffer for device write */
1820 dma_sync_single_for_device(rx_ring->dev,
1821 rx_buffer_info->dma,
1825 /* unmap buffer on Tx side */
1826 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1827 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1829 /* increment Rx/Tx next to clean counters */
1831 if (rx_ntc == rx_ring->count)
1834 if (tx_ntc == tx_ring->count)
1837 /* fetch next descriptor */
1838 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1841 netdev_tx_reset_queue(txring_txq(tx_ring));
1843 /* re-map buffers to ring, store next to clean values */
1844 igb_alloc_rx_buffers(rx_ring, count);
1845 rx_ring->next_to_clean = rx_ntc;
1846 tx_ring->next_to_clean = tx_ntc;
1851 static int igb_run_loopback_test(struct igb_adapter *adapter)
1853 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1854 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1855 u16 i, j, lc, good_cnt;
1857 unsigned int size = IGB_RX_HDR_LEN;
1858 netdev_tx_t tx_ret_val;
1859 struct sk_buff *skb;
1861 /* allocate test skb */
1862 skb = alloc_skb(size, GFP_KERNEL);
1866 /* place data into test skb */
1867 igb_create_lbtest_frame(skb, size);
1870 /* Calculate the loop count based on the largest descriptor ring
1871 * The idea is to wrap the largest ring a number of times using 64
1872 * send/receive pairs during each loop
1875 if (rx_ring->count <= tx_ring->count)
1876 lc = ((tx_ring->count / 64) * 2) + 1;
1878 lc = ((rx_ring->count / 64) * 2) + 1;
1880 for (j = 0; j <= lc; j++) { /* loop count loop */
1881 /* reset count of good packets */
1884 /* place 64 packets on the transmit queue*/
1885 for (i = 0; i < 64; i++) {
1887 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1888 if (tx_ret_val == NETDEV_TX_OK)
1892 if (good_cnt != 64) {
1897 /* allow 200 milliseconds for packets to go from Tx to Rx */
1900 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1901 if (good_cnt != 64) {
1905 } /* end loop count loop */
1907 /* free the original skb */
1913 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1915 /* PHY loopback cannot be performed if SoL/IDER
1916 * sessions are active
1918 if (igb_check_reset_block(&adapter->hw)) {
1919 dev_err(&adapter->pdev->dev,
1920 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1925 if (adapter->hw.mac.type == e1000_i354) {
1926 dev_info(&adapter->pdev->dev,
1927 "Loopback test not supported on i354.\n");
1931 *data = igb_setup_desc_rings(adapter);
1934 *data = igb_setup_loopback_test(adapter);
1937 *data = igb_run_loopback_test(adapter);
1938 igb_loopback_cleanup(adapter);
1941 igb_free_desc_rings(adapter);
1946 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1948 struct e1000_hw *hw = &adapter->hw;
1950 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1953 hw->mac.serdes_has_link = false;
1955 /* On some blade server designs, link establishment
1956 * could take as long as 2-3 minutes
1959 hw->mac.ops.check_for_link(&adapter->hw);
1960 if (hw->mac.serdes_has_link)
1963 } while (i++ < 3750);
1967 hw->mac.ops.check_for_link(&adapter->hw);
1968 if (hw->mac.autoneg)
1971 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1977 static void igb_diag_test(struct net_device *netdev,
1978 struct ethtool_test *eth_test, u64 *data)
1980 struct igb_adapter *adapter = netdev_priv(netdev);
1981 u16 autoneg_advertised;
1982 u8 forced_speed_duplex, autoneg;
1983 bool if_running = netif_running(netdev);
1985 set_bit(__IGB_TESTING, &adapter->state);
1987 /* can't do offline tests on media switching devices */
1988 if (adapter->hw.dev_spec._82575.mas_capable)
1989 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
1990 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1993 /* save speed, duplex, autoneg settings */
1994 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1995 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1996 autoneg = adapter->hw.mac.autoneg;
1998 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2000 /* power up link for link test */
2001 igb_power_up_link(adapter);
2003 /* Link test performed before hardware reset so autoneg doesn't
2004 * interfere with test result
2006 if (igb_link_test(adapter, &data[4]))
2007 eth_test->flags |= ETH_TEST_FL_FAILED;
2010 /* indicate we're in test mode */
2015 if (igb_reg_test(adapter, &data[0]))
2016 eth_test->flags |= ETH_TEST_FL_FAILED;
2019 if (igb_eeprom_test(adapter, &data[1]))
2020 eth_test->flags |= ETH_TEST_FL_FAILED;
2023 if (igb_intr_test(adapter, &data[2]))
2024 eth_test->flags |= ETH_TEST_FL_FAILED;
2027 /* power up link for loopback test */
2028 igb_power_up_link(adapter);
2029 if (igb_loopback_test(adapter, &data[3]))
2030 eth_test->flags |= ETH_TEST_FL_FAILED;
2032 /* restore speed, duplex, autoneg settings */
2033 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2034 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2035 adapter->hw.mac.autoneg = autoneg;
2037 /* force this routine to wait until autoneg complete/timeout */
2038 adapter->hw.phy.autoneg_wait_to_complete = true;
2040 adapter->hw.phy.autoneg_wait_to_complete = false;
2042 clear_bit(__IGB_TESTING, &adapter->state);
2046 dev_info(&adapter->pdev->dev, "online testing starting\n");
2048 /* PHY is powered down when interface is down */
2049 if (if_running && igb_link_test(adapter, &data[4]))
2050 eth_test->flags |= ETH_TEST_FL_FAILED;
2054 /* Online tests aren't run; pass by default */
2060 clear_bit(__IGB_TESTING, &adapter->state);
2062 msleep_interruptible(4 * 1000);
2065 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2067 struct igb_adapter *adapter = netdev_priv(netdev);
2071 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2074 wol->supported = WAKE_UCAST | WAKE_MCAST |
2075 WAKE_BCAST | WAKE_MAGIC |
2078 /* apply any specific unsupported masks here */
2079 switch (adapter->hw.device_id) {
2084 if (adapter->wol & E1000_WUFC_EX)
2085 wol->wolopts |= WAKE_UCAST;
2086 if (adapter->wol & E1000_WUFC_MC)
2087 wol->wolopts |= WAKE_MCAST;
2088 if (adapter->wol & E1000_WUFC_BC)
2089 wol->wolopts |= WAKE_BCAST;
2090 if (adapter->wol & E1000_WUFC_MAG)
2091 wol->wolopts |= WAKE_MAGIC;
2092 if (adapter->wol & E1000_WUFC_LNKC)
2093 wol->wolopts |= WAKE_PHY;
2096 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2098 struct igb_adapter *adapter = netdev_priv(netdev);
2100 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2103 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2104 return wol->wolopts ? -EOPNOTSUPP : 0;
2106 /* these settings will always override what we currently have */
2109 if (wol->wolopts & WAKE_UCAST)
2110 adapter->wol |= E1000_WUFC_EX;
2111 if (wol->wolopts & WAKE_MCAST)
2112 adapter->wol |= E1000_WUFC_MC;
2113 if (wol->wolopts & WAKE_BCAST)
2114 adapter->wol |= E1000_WUFC_BC;
2115 if (wol->wolopts & WAKE_MAGIC)
2116 adapter->wol |= E1000_WUFC_MAG;
2117 if (wol->wolopts & WAKE_PHY)
2118 adapter->wol |= E1000_WUFC_LNKC;
2119 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2124 /* bit defines for adapter->led_status */
2125 #define IGB_LED_ON 0
2127 static int igb_set_phys_id(struct net_device *netdev,
2128 enum ethtool_phys_id_state state)
2130 struct igb_adapter *adapter = netdev_priv(netdev);
2131 struct e1000_hw *hw = &adapter->hw;
2134 case ETHTOOL_ID_ACTIVE:
2140 case ETHTOOL_ID_OFF:
2143 case ETHTOOL_ID_INACTIVE:
2145 clear_bit(IGB_LED_ON, &adapter->led_status);
2146 igb_cleanup_led(hw);
2153 static int igb_set_coalesce(struct net_device *netdev,
2154 struct ethtool_coalesce *ec)
2156 struct igb_adapter *adapter = netdev_priv(netdev);
2159 if (ec->rx_max_coalesced_frames ||
2160 ec->rx_coalesce_usecs_irq ||
2161 ec->rx_max_coalesced_frames_irq ||
2162 ec->tx_max_coalesced_frames ||
2163 ec->tx_coalesce_usecs_irq ||
2164 ec->stats_block_coalesce_usecs ||
2165 ec->use_adaptive_rx_coalesce ||
2166 ec->use_adaptive_tx_coalesce ||
2168 ec->rx_coalesce_usecs_low ||
2169 ec->rx_max_coalesced_frames_low ||
2170 ec->tx_coalesce_usecs_low ||
2171 ec->tx_max_coalesced_frames_low ||
2172 ec->pkt_rate_high ||
2173 ec->rx_coalesce_usecs_high ||
2174 ec->rx_max_coalesced_frames_high ||
2175 ec->tx_coalesce_usecs_high ||
2176 ec->tx_max_coalesced_frames_high ||
2177 ec->rate_sample_interval)
2180 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2181 ((ec->rx_coalesce_usecs > 3) &&
2182 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2183 (ec->rx_coalesce_usecs == 2))
2186 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2187 ((ec->tx_coalesce_usecs > 3) &&
2188 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2189 (ec->tx_coalesce_usecs == 2))
2192 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2195 /* If ITR is disabled, disable DMAC */
2196 if (ec->rx_coalesce_usecs == 0) {
2197 if (adapter->flags & IGB_FLAG_DMAC)
2198 adapter->flags &= ~IGB_FLAG_DMAC;
2201 /* convert to rate of irq's per second */
2202 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2203 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2205 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2207 /* convert to rate of irq's per second */
2208 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2209 adapter->tx_itr_setting = adapter->rx_itr_setting;
2210 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2211 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2213 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2215 for (i = 0; i < adapter->num_q_vectors; i++) {
2216 struct igb_q_vector *q_vector = adapter->q_vector[i];
2217 q_vector->tx.work_limit = adapter->tx_work_limit;
2218 if (q_vector->rx.ring)
2219 q_vector->itr_val = adapter->rx_itr_setting;
2221 q_vector->itr_val = adapter->tx_itr_setting;
2222 if (q_vector->itr_val && q_vector->itr_val <= 3)
2223 q_vector->itr_val = IGB_START_ITR;
2224 q_vector->set_itr = 1;
2230 static int igb_get_coalesce(struct net_device *netdev,
2231 struct ethtool_coalesce *ec)
2233 struct igb_adapter *adapter = netdev_priv(netdev);
2235 if (adapter->rx_itr_setting <= 3)
2236 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2238 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2240 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2241 if (adapter->tx_itr_setting <= 3)
2242 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2244 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2250 static int igb_nway_reset(struct net_device *netdev)
2252 struct igb_adapter *adapter = netdev_priv(netdev);
2253 if (netif_running(netdev))
2254 igb_reinit_locked(adapter);
2258 static int igb_get_sset_count(struct net_device *netdev, int sset)
2262 return IGB_STATS_LEN;
2264 return IGB_TEST_LEN;
2270 static void igb_get_ethtool_stats(struct net_device *netdev,
2271 struct ethtool_stats *stats, u64 *data)
2273 struct igb_adapter *adapter = netdev_priv(netdev);
2274 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2276 struct igb_ring *ring;
2280 spin_lock(&adapter->stats64_lock);
2281 igb_update_stats(adapter, net_stats);
2283 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2284 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2285 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2286 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2288 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2289 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2290 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2291 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2293 for (j = 0; j < adapter->num_tx_queues; j++) {
2296 ring = adapter->tx_ring[j];
2298 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2299 data[i] = ring->tx_stats.packets;
2300 data[i+1] = ring->tx_stats.bytes;
2301 data[i+2] = ring->tx_stats.restart_queue;
2302 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2304 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2305 restart2 = ring->tx_stats.restart_queue2;
2306 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2307 data[i+2] += restart2;
2309 i += IGB_TX_QUEUE_STATS_LEN;
2311 for (j = 0; j < adapter->num_rx_queues; j++) {
2312 ring = adapter->rx_ring[j];
2314 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2315 data[i] = ring->rx_stats.packets;
2316 data[i+1] = ring->rx_stats.bytes;
2317 data[i+2] = ring->rx_stats.drops;
2318 data[i+3] = ring->rx_stats.csum_err;
2319 data[i+4] = ring->rx_stats.alloc_failed;
2320 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2321 i += IGB_RX_QUEUE_STATS_LEN;
2323 spin_unlock(&adapter->stats64_lock);
2326 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2328 struct igb_adapter *adapter = netdev_priv(netdev);
2332 switch (stringset) {
2334 memcpy(data, *igb_gstrings_test,
2335 IGB_TEST_LEN*ETH_GSTRING_LEN);
2338 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2339 memcpy(p, igb_gstrings_stats[i].stat_string,
2341 p += ETH_GSTRING_LEN;
2343 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2344 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2346 p += ETH_GSTRING_LEN;
2348 for (i = 0; i < adapter->num_tx_queues; i++) {
2349 sprintf(p, "tx_queue_%u_packets", i);
2350 p += ETH_GSTRING_LEN;
2351 sprintf(p, "tx_queue_%u_bytes", i);
2352 p += ETH_GSTRING_LEN;
2353 sprintf(p, "tx_queue_%u_restart", i);
2354 p += ETH_GSTRING_LEN;
2356 for (i = 0; i < adapter->num_rx_queues; i++) {
2357 sprintf(p, "rx_queue_%u_packets", i);
2358 p += ETH_GSTRING_LEN;
2359 sprintf(p, "rx_queue_%u_bytes", i);
2360 p += ETH_GSTRING_LEN;
2361 sprintf(p, "rx_queue_%u_drops", i);
2362 p += ETH_GSTRING_LEN;
2363 sprintf(p, "rx_queue_%u_csum_err", i);
2364 p += ETH_GSTRING_LEN;
2365 sprintf(p, "rx_queue_%u_alloc_failed", i);
2366 p += ETH_GSTRING_LEN;
2368 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2373 static int igb_get_ts_info(struct net_device *dev,
2374 struct ethtool_ts_info *info)
2376 struct igb_adapter *adapter = netdev_priv(dev);
2378 if (adapter->ptp_clock)
2379 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2381 info->phc_index = -1;
2383 switch (adapter->hw.mac.type) {
2385 info->so_timestamping =
2386 SOF_TIMESTAMPING_TX_SOFTWARE |
2387 SOF_TIMESTAMPING_RX_SOFTWARE |
2388 SOF_TIMESTAMPING_SOFTWARE;
2396 info->so_timestamping =
2397 SOF_TIMESTAMPING_TX_SOFTWARE |
2398 SOF_TIMESTAMPING_RX_SOFTWARE |
2399 SOF_TIMESTAMPING_SOFTWARE |
2400 SOF_TIMESTAMPING_TX_HARDWARE |
2401 SOF_TIMESTAMPING_RX_HARDWARE |
2402 SOF_TIMESTAMPING_RAW_HARDWARE;
2405 (1 << HWTSTAMP_TX_OFF) |
2406 (1 << HWTSTAMP_TX_ON);
2408 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
2410 /* 82576 does not support timestamping all packets. */
2411 if (adapter->hw.mac.type >= e1000_82580)
2412 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2415 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2416 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2417 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2425 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2426 struct ethtool_rxnfc *cmd)
2430 /* Report default options for RSS on igb */
2431 switch (cmd->flow_type) {
2433 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2437 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2440 case AH_ESP_V4_FLOW:
2444 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2447 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2450 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2451 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2454 case AH_ESP_V6_FLOW:
2458 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2467 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2470 struct igb_adapter *adapter = netdev_priv(dev);
2471 int ret = -EOPNOTSUPP;
2474 case ETHTOOL_GRXRINGS:
2475 cmd->data = adapter->num_rx_queues;
2479 ret = igb_get_rss_hash_opts(adapter, cmd);
2488 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2489 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2490 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2491 struct ethtool_rxnfc *nfc)
2493 u32 flags = adapter->flags;
2495 /* RSS does not support anything other than hashing
2496 * to queues on src and dst IPs and ports
2498 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2499 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2502 switch (nfc->flow_type) {
2505 if (!(nfc->data & RXH_IP_SRC) ||
2506 !(nfc->data & RXH_IP_DST) ||
2507 !(nfc->data & RXH_L4_B_0_1) ||
2508 !(nfc->data & RXH_L4_B_2_3))
2512 if (!(nfc->data & RXH_IP_SRC) ||
2513 !(nfc->data & RXH_IP_DST))
2515 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2517 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2519 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2520 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2527 if (!(nfc->data & RXH_IP_SRC) ||
2528 !(nfc->data & RXH_IP_DST))
2530 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2532 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2534 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2535 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2541 case AH_ESP_V4_FLOW:
2545 case AH_ESP_V6_FLOW:
2549 if (!(nfc->data & RXH_IP_SRC) ||
2550 !(nfc->data & RXH_IP_DST) ||
2551 (nfc->data & RXH_L4_B_0_1) ||
2552 (nfc->data & RXH_L4_B_2_3))
2559 /* if we changed something we need to update flags */
2560 if (flags != adapter->flags) {
2561 struct e1000_hw *hw = &adapter->hw;
2562 u32 mrqc = rd32(E1000_MRQC);
2564 if ((flags & UDP_RSS_FLAGS) &&
2565 !(adapter->flags & UDP_RSS_FLAGS))
2566 dev_err(&adapter->pdev->dev,
2567 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2569 adapter->flags = flags;
2571 /* Perform hash on these packet types */
2572 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2573 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2574 E1000_MRQC_RSS_FIELD_IPV6 |
2575 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2577 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2578 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2580 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2581 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2583 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2584 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2586 wr32(E1000_MRQC, mrqc);
2592 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2594 struct igb_adapter *adapter = netdev_priv(dev);
2595 int ret = -EOPNOTSUPP;
2599 ret = igb_set_rss_hash_opt(adapter, cmd);
2608 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2610 struct igb_adapter *adapter = netdev_priv(netdev);
2611 struct e1000_hw *hw = &adapter->hw;
2615 if ((hw->mac.type < e1000_i350) ||
2616 (hw->phy.media_type != e1000_media_type_copper))
2619 edata->supported = (SUPPORTED_1000baseT_Full |
2620 SUPPORTED_100baseT_Full);
2621 if (!hw->dev_spec._82575.eee_disable)
2623 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
2625 /* The IPCNFG and EEER registers are not supported on I354. */
2626 if (hw->mac.type == e1000_i354) {
2627 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
2631 eeer = rd32(E1000_EEER);
2633 /* EEE status on negotiated link */
2634 if (eeer & E1000_EEER_EEE_NEG)
2635 edata->eee_active = true;
2637 if (eeer & E1000_EEER_TX_LPI_EN)
2638 edata->tx_lpi_enabled = true;
2641 /* EEE Link Partner Advertised */
2642 switch (hw->mac.type) {
2644 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2649 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2654 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
2655 E1000_EEE_LP_ADV_DEV_I210,
2660 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2667 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2669 if ((hw->mac.type == e1000_i354) &&
2670 (edata->eee_enabled))
2671 edata->tx_lpi_enabled = true;
2673 /* Report correct negotiated EEE status for devices that
2674 * wrongly report EEE at half-duplex
2676 if (adapter->link_duplex == HALF_DUPLEX) {
2677 edata->eee_enabled = false;
2678 edata->eee_active = false;
2679 edata->tx_lpi_enabled = false;
2680 edata->advertised &= ~edata->advertised;
2686 static int igb_set_eee(struct net_device *netdev,
2687 struct ethtool_eee *edata)
2689 struct igb_adapter *adapter = netdev_priv(netdev);
2690 struct e1000_hw *hw = &adapter->hw;
2691 struct ethtool_eee eee_curr;
2692 bool adv1g_eee = true, adv100m_eee = true;
2695 if ((hw->mac.type < e1000_i350) ||
2696 (hw->phy.media_type != e1000_media_type_copper))
2699 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
2701 ret_val = igb_get_eee(netdev, &eee_curr);
2705 if (eee_curr.eee_enabled) {
2706 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2707 dev_err(&adapter->pdev->dev,
2708 "Setting EEE tx-lpi is not supported\n");
2712 /* Tx LPI timer is not implemented currently */
2713 if (edata->tx_lpi_timer) {
2714 dev_err(&adapter->pdev->dev,
2715 "Setting EEE Tx LPI timer is not supported\n");
2719 if (!edata->advertised || (edata->advertised &
2720 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
2721 dev_err(&adapter->pdev->dev,
2722 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
2725 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
2726 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
2728 } else if (!edata->eee_enabled) {
2729 dev_err(&adapter->pdev->dev,
2730 "Setting EEE options are not supported with EEE disabled\n");
2734 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
2735 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2736 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2737 adapter->flags |= IGB_FLAG_EEE;
2740 if (netif_running(netdev))
2741 igb_reinit_locked(adapter);
2746 if (hw->mac.type == e1000_i354)
2747 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
2749 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
2752 dev_err(&adapter->pdev->dev,
2753 "Problem setting EEE advertisement options\n");
2760 static int igb_get_module_info(struct net_device *netdev,
2761 struct ethtool_modinfo *modinfo)
2763 struct igb_adapter *adapter = netdev_priv(netdev);
2764 struct e1000_hw *hw = &adapter->hw;
2766 u16 sff8472_rev, addr_mode;
2767 bool page_swap = false;
2769 if ((hw->phy.media_type == e1000_media_type_copper) ||
2770 (hw->phy.media_type == e1000_media_type_unknown))
2773 /* Check whether we support SFF-8472 or not */
2774 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2778 /* addressing mode is not supported */
2779 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2783 /* addressing mode is not supported */
2784 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2785 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2789 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2790 /* We have an SFP, but it does not support SFF-8472 */
2791 modinfo->type = ETH_MODULE_SFF_8079;
2792 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2794 /* We have an SFP which supports a revision of SFF-8472 */
2795 modinfo->type = ETH_MODULE_SFF_8472;
2796 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2802 static int igb_get_module_eeprom(struct net_device *netdev,
2803 struct ethtool_eeprom *ee, u8 *data)
2805 struct igb_adapter *adapter = netdev_priv(netdev);
2806 struct e1000_hw *hw = &adapter->hw;
2809 u16 first_word, last_word;
2815 first_word = ee->offset >> 1;
2816 last_word = (ee->offset + ee->len - 1) >> 1;
2818 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2823 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2824 for (i = 0; i < last_word - first_word + 1; i++) {
2825 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2827 /* Error occurred while reading module */
2832 be16_to_cpus(&dataword[i]);
2835 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2841 static int igb_ethtool_begin(struct net_device *netdev)
2843 struct igb_adapter *adapter = netdev_priv(netdev);
2844 pm_runtime_get_sync(&adapter->pdev->dev);
2848 static void igb_ethtool_complete(struct net_device *netdev)
2850 struct igb_adapter *adapter = netdev_priv(netdev);
2851 pm_runtime_put(&adapter->pdev->dev);
2854 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
2856 return IGB_RETA_SIZE;
2859 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2862 struct igb_adapter *adapter = netdev_priv(netdev);
2866 *hfunc = ETH_RSS_HASH_TOP;
2869 for (i = 0; i < IGB_RETA_SIZE; i++)
2870 indir[i] = adapter->rss_indir_tbl[i];
2875 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
2877 struct e1000_hw *hw = &adapter->hw;
2878 u32 reg = E1000_RETA(0);
2882 switch (hw->mac.type) {
2887 /* 82576 supports 2 RSS queues for SR-IOV */
2888 if (adapter->vfs_allocated_count)
2895 while (i < IGB_RETA_SIZE) {
2899 for (j = 3; j >= 0; j--) {
2901 val |= adapter->rss_indir_tbl[i + j];
2904 wr32(reg, val << shift);
2910 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
2911 const u8 *key, const u8 hfunc)
2913 struct igb_adapter *adapter = netdev_priv(netdev);
2914 struct e1000_hw *hw = &adapter->hw;
2918 /* We do not allow change in unsupported parameters */
2920 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
2925 num_queues = adapter->rss_queues;
2927 switch (hw->mac.type) {
2929 /* 82576 supports 2 RSS queues for SR-IOV */
2930 if (adapter->vfs_allocated_count)
2937 /* Verify user input. */
2938 for (i = 0; i < IGB_RETA_SIZE; i++)
2939 if (indir[i] >= num_queues)
2943 for (i = 0; i < IGB_RETA_SIZE; i++)
2944 adapter->rss_indir_tbl[i] = indir[i];
2946 igb_write_rss_indir_tbl(adapter);
2951 static unsigned int igb_max_channels(struct igb_adapter *adapter)
2953 struct e1000_hw *hw = &adapter->hw;
2954 unsigned int max_combined = 0;
2956 switch (hw->mac.type) {
2958 max_combined = IGB_MAX_RX_QUEUES_I211;
2962 max_combined = IGB_MAX_RX_QUEUES_82575;
2965 if (!!adapter->vfs_allocated_count) {
2971 if (!!adapter->vfs_allocated_count) {
2979 max_combined = IGB_MAX_RX_QUEUES;
2983 return max_combined;
2986 static void igb_get_channels(struct net_device *netdev,
2987 struct ethtool_channels *ch)
2989 struct igb_adapter *adapter = netdev_priv(netdev);
2991 /* Report maximum channels */
2992 ch->max_combined = igb_max_channels(adapter);
2994 /* Report info for other vector */
2995 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2996 ch->max_other = NON_Q_VECTORS;
2997 ch->other_count = NON_Q_VECTORS;
3000 ch->combined_count = adapter->rss_queues;
3003 static int igb_set_channels(struct net_device *netdev,
3004 struct ethtool_channels *ch)
3006 struct igb_adapter *adapter = netdev_priv(netdev);
3007 unsigned int count = ch->combined_count;
3008 unsigned int max_combined = 0;
3010 /* Verify they are not requesting separate vectors */
3011 if (!count || ch->rx_count || ch->tx_count)
3014 /* Verify other_count is valid and has not been changed */
3015 if (ch->other_count != NON_Q_VECTORS)
3018 /* Verify the number of channels doesn't exceed hw limits */
3019 max_combined = igb_max_channels(adapter);
3020 if (count > max_combined)
3023 if (count != adapter->rss_queues) {
3024 adapter->rss_queues = count;
3025 igb_set_flag_queue_pairs(adapter, max_combined);
3027 /* Hardware has to reinitialize queues and interrupts to
3028 * match the new configuration.
3030 return igb_reinit_queues(adapter);
3036 static const struct ethtool_ops igb_ethtool_ops = {
3037 .get_settings = igb_get_settings,
3038 .set_settings = igb_set_settings,
3039 .get_drvinfo = igb_get_drvinfo,
3040 .get_regs_len = igb_get_regs_len,
3041 .get_regs = igb_get_regs,
3042 .get_wol = igb_get_wol,
3043 .set_wol = igb_set_wol,
3044 .get_msglevel = igb_get_msglevel,
3045 .set_msglevel = igb_set_msglevel,
3046 .nway_reset = igb_nway_reset,
3047 .get_link = igb_get_link,
3048 .get_eeprom_len = igb_get_eeprom_len,
3049 .get_eeprom = igb_get_eeprom,
3050 .set_eeprom = igb_set_eeprom,
3051 .get_ringparam = igb_get_ringparam,
3052 .set_ringparam = igb_set_ringparam,
3053 .get_pauseparam = igb_get_pauseparam,
3054 .set_pauseparam = igb_set_pauseparam,
3055 .self_test = igb_diag_test,
3056 .get_strings = igb_get_strings,
3057 .set_phys_id = igb_set_phys_id,
3058 .get_sset_count = igb_get_sset_count,
3059 .get_ethtool_stats = igb_get_ethtool_stats,
3060 .get_coalesce = igb_get_coalesce,
3061 .set_coalesce = igb_set_coalesce,
3062 .get_ts_info = igb_get_ts_info,
3063 .get_rxnfc = igb_get_rxnfc,
3064 .set_rxnfc = igb_set_rxnfc,
3065 .get_eee = igb_get_eee,
3066 .set_eee = igb_set_eee,
3067 .get_module_info = igb_get_module_info,
3068 .get_module_eeprom = igb_get_module_eeprom,
3069 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3070 .get_rxfh = igb_get_rxfh,
3071 .set_rxfh = igb_set_rxfh,
3072 .get_channels = igb_get_channels,
3073 .set_channels = igb_set_channels,
3074 .begin = igb_ethtool_begin,
3075 .complete = igb_ethtool_complete,
3078 void igb_set_ethtool_ops(struct net_device *netdev)
3080 netdev->ethtool_ops = &igb_ethtool_ops;